Memory structure and method of forming a memory structure
By designing a memory structure in which the floating gate spans the active region and covers its surface, and controlling the gate to surround the floating gate in multiple directions, the problem of low coupling coefficient in Nor Flash memory is solved, improving read and write speed and simplifying process steps.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (BEIJING) CORP
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-23
AI Technical Summary
The coupling coefficients between the floating gate and control gate, as well as between the active region and the floating gate, in existing Nor Flash memories are small, resulting in unstable read and write speeds.
Design a memory structure in which a floating gate spans the active region and covers its surface, a control gate spans the floating gate along both the first and second directions, and the control gate completely surrounds the sidewalls of the floating gate. The coupling coefficient is increased by forming the floating gate directly on the substrate and the control gate on the isolation layer.
The coupling coefficient of the memory structure was increased, the read and write speeds were improved, and the process steps were simplified, reducing the difficulty of the process.
Smart Images
Figure CN122269697A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a memory structure and a method for forming the memory structure. Background Technology
[0002] In recent years, electronic devices have trended towards multi-functionality, making memory, which plays a crucial role in electronic devices, one of the main research and development areas. Nor Flash memory is an electronic component with powerful storage capabilities, consisting of active regions, floating gates, and control gates. Read and write speeds are one of the important key parameters for evaluating memory performance.
[0003] The coupling coefficient between the floating gate and the control gate, as well as the coupling coefficient between the active region and the floating gate, are important parameters affecting the read and write speed of Nor Flash memory. Current common processes simply superimpose the floating gate and the control gate, apply voltage to the control gate, and use the control gate to write, read, or erase charges into the floating gate.
[0004] However, current memory still has shortcomings. Summary of the Invention
[0005] The problem addressed by this invention is how to increase the coupling coefficient of the memory structure in order to improve the operating speed of the memory.
[0006] To address the aforementioned problems, the present invention provides a memory structure comprising: a substrate, the substrate including an active region and an isolation region, the isolation region surrounding the active region and the surface of the active region protruding from the surface of the isolation region; a floating gate, the floating gate spanning the active region and covering the surface of the active region; and a control gate located on the floating gate.
[0007] Optionally, it may also include a floating gate oxide layer, the floating gate oxide layer being located between the active region and the floating gate.
[0008] Optionally, the floating gate oxide layer also extends onto the substrate of the isolation region.
[0009] Optionally, it may also include an isolation layer located between the floating gate and the control gate.
[0010] Optionally, the control gate spans the floating gate along both a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other; the isolation layer also extends to the isolation area.
[0011] Optionally, the thickness of the isolation layer extending into the isolation zone is greater than the thickness of the isolation layer between the control gate and the floating gate.
[0012] Optionally, the isolation layer of the isolation region has two first parts and two second parts, in a plane parallel to the substrate surface, the two first parts are located on both sides of the floating gate along a first direction, and the two second parts are located on both sides of the floating gate along a second direction.
[0013] Optionally, the top surfaces of the first and second parts are flush.
[0014] Optionally, the thickness of the first part is greater than the thickness of the second part.
[0015] Optionally, the first part extends along the second direction to be flush with the boundary of the second part.
[0016] Accordingly, the present invention also provides a method for forming a memory structure, comprising: forming a substrate, the substrate comprising: a substrate, the substrate comprising an active region and an isolation region, the isolation region surrounding the active region and the surface of the active region protruding from the surface of the isolation region; forming a floating gate on the active region, the floating gate spanning the active region and covering the surface of the active region; and forming a control gate on the floating gate.
[0017] Optionally, the step of forming the substrate includes: providing an initial substrate; etching the initial substrate to form a transition substrate; and oxidizing the surface of the transition substrate after forming the transition substrate and before forming a floating gate on the active region to form the substrate and a floating gate oxide layer located on the surface of the substrate.
[0018] Optionally, it may further include: forming an isolation layer located between the floating gate and the control gate.
[0019] Optionally, the floating gate oxide layer also extends onto the substrate of the isolation region; the isolation layer is formed after the floating gate is formed and before the control gate is formed.
[0020] Optionally, the isolation layer also extends into the isolation zone.
[0021] Optionally, the step of forming the isolation layer includes: forming an isolation trench in the isolation region, the isolation trench being located on both sides of the floating gate along a first direction; forming an initial isolation layer in the isolation trench and on the substrate; and etching the initial isolation layer to form the isolation layer.
[0022] Optionally, the isolation layer of the isolation region has two first parts and two second parts in a plane parallel to the substrate surface. The two first parts are located on both sides of the floating gate along a first direction, and the two second parts are located on both sides of the floating gate along a second direction, wherein the first direction and the second direction are perpendicular to each other.
[0023] Optionally, the step of forming the control gate includes: forming a control gate material layer on the isolation layer; forming a mask layer on the control gate material layer, wherein the dimension of the mask layer along the second direction is larger than the dimension of the floating gate along the second direction and the projection of the floating gate on the substrate surface is located within the projection range of the mask layer on the substrate surface; and etching the control gate material layer using the mask layer as a mask to form the control gate.
[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0025] In the memory structure of the present invention, the floating gate spans the active region and covers the surface of the active region. The surface of the active region is adjacent to the floating gate, which increases the contact area between the floating gate and the active region, thereby increasing the coupling coefficient of the memory structure and thus improving the read and write speed of the memory structure.
[0026] In an optional embodiment of the present invention, the control gate spans the floating gate along both a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other. The control gate completely surrounds the sidewalls of the floating gate, increasing the coupling coefficient between the control gate and the floating gate, thereby improving the read and write speed of the memory structure.
[0027] In the method for forming the memory structure of the present invention, the floating gate spans the active region and covers the surface of the active region. The surface of the active region is adjacent to the floating gate, increasing the contact area between the floating gate and the active region, thereby increasing the coupling coefficient of the memory structure and improving the read / write speed of the memory structure. Furthermore, after forming the substrate, the floating gate spanning the active region is directly formed on the substrate. The fabrication steps of the floating gate are simple, reducing the process difficulty.
[0028] In an optional embodiment of the present invention, the step of forming the control gate includes: forming a control gate material layer on the isolation layer; forming a mask layer on the control gate material layer, wherein the dimension of the mask layer along the second direction is larger than the dimension of the floating gate along the second direction and the projection of the floating gate onto the substrate surface is within the projection range of the mask layer on the substrate surface; and etching the control gate material layer using the mask layer as a mask to form the control gate. The mask layer is used to define the dimension of the control gate in the second direction. The fact that the dimension of the mask layer along the second direction is larger than the dimension of the floating gate along the second direction and the projection of the floating gate onto the substrate surface is within the projection range of the mask layer on the substrate surface ensures that the control gate etched using the mask layer as a mask completely surrounds the floating gate in both the first and second directions. Attached Figure Description
[0029] Figures 1 to 3 This is a cross-sectional schematic diagram of a prior art memory structure;
[0030] Figures 4 to 27 This is a schematic diagram of the various steps in the formation process of the memory structure according to an embodiment of the present invention. Detailed Implementation
[0031] As can be seen from the background art, the existing memory structures still have shortcomings. The causes of these problems will now be analyzed using an embodiment as an example:
[0032] Please refer to Figures 1 to 3 , Figure 1 yes Figure 2 and Figure 3 Top view, Figure 2 yes Figure 1 A sectional view at position X1X2. Figure 3 yes Figure 1 In a cross-sectional view at position Y1Y2, a memory structure includes: a substrate 100, the substrate 100 including an active region I and an isolation region II, the isolation region II surrounding the active region I; a floating gate 101 located on the active region I; and a control gate 102 located on the floating gate 101.
[0033] The floating gate 101 is located on the active region I, and the control gate 102 is located on the floating gate 101. A voltage is applied to the control gate 102, enabling the writing, reading, and erasing of charges within the floating gate 101. The control gate 102 only surrounds the floating gate 101 in the first direction X, and the contact area between the floating gate 101 and the active region I is small. This results in a low coupling coefficient between the control gate 102 and the floating gate 101, and between the floating gate 101 and the active region I. Consequently, the control gate 102's control over the floating gate 101 and the active region I is weak, leading to unstable memory operating speed.
[0034] To address the aforementioned technical problem, the present invention provides a memory structure comprising: a substrate, the substrate including an active region and an isolation region, the isolation region surrounding the active region and the surface of the active region protruding from the surface of the isolation region; a floating gate, the floating gate spanning the active region and covering the surface of the active region; and a control gate located on the floating gate.
[0035] In the memory of this invention, the floating gate spans the active region and covers its surface. The surface of the active region is adjacent to the floating gate, increasing the contact area between the floating gate and the active region, thereby increasing the coupling coefficient of the memory structure and improving its read / write speed. Furthermore, the control gate spans the floating gate along both a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other. The control gate completely surrounds the sidewalls of the floating gate, increasing the coupling coefficient between the control gate and the floating gate, further increasing the read / write speed of the memory structure.
[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0037] Figures 4 to 27 This is a schematic diagram of the various steps in the formation process of the memory structure according to an embodiment of the present invention.
[0038] Please refer to Figures 4 to 12 A substrate is formed, the substrate comprising: a substrate 202, the substrate 202 including an active region I and an isolation region II, the isolation region II surrounding the active region I and the surface of the active region I protruding from the surface of the isolation region II.
[0039] The steps for forming the substrate include: Figures 4 to 6 As shown, Figure 4 yes Figure 5 and Figure 6 Top view, Figure 5 yes Figure 4 A sectional view at position X1X2. Figure 6 yes Figure 4 A cross-sectional view at position Y1Y2 provides the initial substrate 200;
[0040] like Figures 7 to 9 As shown, Figure 7 yes Figure 8 and Figure 9 Top view, Figure 8 yes Figure 7 A sectional view at position X1X2. Figure 9 yes Figure 7 In the cross-sectional view at position Y1Y2, the initial substrate 200 is etched to form the transition substrate 201;
[0041] like Figures 10 to 12 As shown, Figure 10 yes Figure 11 and Figure 12 Top view, Figure 11 yes Figure 10 A sectional view at position X1X2. Figure 12 yes Figure 10In the cross-sectional view at position Y1Y2, after the transition substrate 201 is formed, the surface of the transition substrate 201 is oxidized to form the substrate 202 and the floating gate oxide layer 203 located on the surface of the substrate 202.
[0042] The purpose of etching the initial substrate 200 is to provide a structural basis for forming the active region I protruding from the isolation region II of the substrate 202.
[0043] The step of etching the initial substrate 200 to form the transition substrate 201 includes: forming a mask layer on the initial substrate 200, the mask layer exposing a portion of the initial substrate 200; and using the mask layer as a mask, etching the initial substrate 200 to form the transition substrate 201.
[0044] The mask layer is used to define the size of the active region I.
[0045] The substrate 202 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Specifically, in some embodiments of the present invention, the substrate 202 is made of silicon.
[0046] The projection shape of the portion of the active region I protruding from the surface of the isolation region II onto the plane perpendicular to the substrate 202 can be any shape, such as square, circular, or trapezoidal. Specifically, in some embodiments of the present invention, the shape of the active region I protruding from the surface of the isolation region II is square.
[0047] The active region I protrudes from the surface of the isolation region II, providing a structural basis for increasing the contact area between the floating gate 204 and the active region I. Specifically, in some embodiments of the present invention, the height 'a' of the active region I protruding from the surface of the isolation region II ranges from 5 angstroms to 100 angstroms.
[0048] Specifically, in some embodiments of the present invention, the floating gate oxide layer 203 further extends onto the substrate 202 of the isolation region II. The function of the floating gate oxide layer 203 is to improve the stability of the memory structure and ensure the reliability of the memory structure.
[0049] The floating gate oxide layer 203 is made of silicon oxide. Specifically, in some embodiments of the present invention, the thickness of the floating gate oxide layer 203 ranges from 50 angstroms to 200 angstroms.
[0050] Please refer to Figures 13 to 15 , Figure 13 yes Figure 14 and Figure 15 Top view, Figure 14 yes Figure 13 A sectional view at position X1X2. Figure 15 yes Figure 13 In the cross-sectional view at position Y1Y2, a floating grid 204 is formed on the active region I, the floating grid 204 spans the active region I and covers the surface of the active region I.
[0051] Specifically, in some embodiments of the present invention, the floating gate 204 covers the surface of the active region I. That is, in both the first direction X and the second direction Y, the floating gate 204 covers the surface of the active region I. The surface of the active region I is adjacent to the floating gate 204, which increases the contact area between the floating gate 204 and the active region I, thereby increasing the coupling coefficient of the memory structure and improving the operating speed of the memory structure.
[0052] The floating gate 204 is made of crystalline silicon; the crystalline silicon includes doped crystalline silicon and undoped crystalline silicon. In some embodiments of the present invention, the floating gate 204 is made of doped crystalline silicon. In other embodiments of the present invention, the floating gate 204 is made of undoped crystalline silicon.
[0053] The method for forming the floating gate 204 includes deposition. A floating gate material layer is directly deposited on the substrate 202 to form the floating gate 204; the fabrication steps are simple and the process is easy.
[0054] Specifically, in some embodiments of the present invention, the thickness c1 of the floating gate 204 ranges from 550 angstroms to 850 angstroms. Specifically, the thickness c1 of the floating gate 204 refers to the thickness of the floating gate 204 located on the active region I.
[0055] The floating gate 204 is used to store electrical charge.
[0056] The floating gate oxide layer 203 is located between the floating gate 204 and the substrate 202, and is used to separate the substrate 202 from the floating gate 204.
[0057] Please refer to Figures 16 to 24 After the floating gate 204 is formed, an isolation layer 207 is formed.
[0058] The steps for forming the isolation layer 207 include: as follows Figures 16 to 18 As shown, Figure 16 yes Figure 17 and Figure 18 Top view, Figure 17 yes Figure 16 A sectional view at position X1X2. Figure 18 yes Figure 16 In the cross-sectional view at position Y1Y2, isolation trenches 205 are formed within the isolation zone II, and the isolation trenches 205 are located on both sides of the floating gate 204 along the first direction X; as shown Figures 19 to 21 As shown, Figure 19 yes Figure 20and Figure 21 Top view, Figure 20 yes Figure 19 A sectional view at position X1X2. Figure 21 yes Figure 19 In a cross-sectional view at position Y1Y2, an initial isolation layer 206 is formed within the isolation trench 205 and on the substrate 202; as shown... Figures 22 to 24 As shown, Figure 22 yes Figure 23 and Figure 24 Top view, Figure 23 yes Figure 22 A sectional view at position X1X2. Figure 24 yes Figure 22 In the cross-sectional view at position Y1Y2, the initial isolation layer 206 is etched to form the isolation layer 207.
[0059] The isolation trench 205 provides a structural basis for forming the isolation layer 207. Specifically, in some embodiments of the present invention, such as... Figures 22 to 24 As shown, the isolation layer located within the isolation trench 205 is the first part A of the isolation layer 207.
[0060] The step of forming the isolation trench 205 includes: forming a mask layer on the floating gate 204, the mask layer exposing a portion of the floating gate 204; using the mask layer as a mask, etching the floating gate 204 and the substrate 202 to form the isolation trench 205 located in the isolation region II.
[0061] The mask layer is used to define the dimensions of the isolation trench 205 along the first direction X and along the second direction Y.
[0062] During the process of forming the isolation trench 205 within the isolation zone II, the method further includes: removing a portion of the floating gate 204 located on the isolation zone II along the second direction Y. Specifically, in some embodiments of the present invention, such as... Figure 18 As shown, after removing a portion of the floating gate 204 located in isolation region II along the second direction Y, the size d1 of the floating gate 204 along the second direction Y ranges from 50 nanometers to 85 nanometers.
[0063] The initial isolation layer 206 is made of a high-dielectric material. The high-dielectric material includes hafnium oxide and silicon nitride, among others.
[0064] The method for forming the initial isolation layer 206 includes deposition.
[0065] Specifically, such as Figures 22 to 24As shown, the isolation layer 207 of the isolation region II has two first parts A and two second parts B in a plane parallel to the surface of the substrate 202. The two first parts A are located on both sides of the floating gate 204 along the first direction X, and the two second parts B are located on both sides of the floating gate 204 along the second direction Y, wherein the first direction X and the second direction Y are perpendicular to each other.
[0066] Specifically, in some embodiments of the present invention, the top surfaces of the first part A and the second part B are flush. The first part A extends along the second direction Y to be flush with the boundary of the second part B.
[0067] Specifically, in some embodiments of the present invention, such as Figure 24 As shown, the thickness b1 of the second part B ranges from 150 angstroms to 300 angstroms. The greater thickness of the second part B increases the distance between the floating gate 204 and the subsequently formed control gate 208, thereby improving the breakdown voltage of the memory structure.
[0068] The isolation layer 207 is also located on the top surface of the floating gate 204 and the sidewall surface of the floating gate 204. Specifically, in some embodiments of the present invention, such as Figure 24 As shown, the thickness b2 of the isolation layer 207 on the top surface and sidewall surface of the floating gate 204 ranges from 50 angstroms to 150 angstroms.
[0069] In some embodiments of the present invention, the step of etching the initial isolation layer 206 to form the isolation layer 207 includes:
[0070] The initial isolation layer 206 is etched to form a transition isolation layer;
[0071] A mask layer is formed on the transition isolation layer, the mask layer exposing the transition isolation layer located on the active region I;
[0072] Using the mask layer as a mask, the transition isolation layer is etched to form the isolation layer 207.
[0073] That is: during the etching of the initial isolation layer 206 to form the transition isolation layer, the etching is a general etching process, and the etching targets all areas of the initial isolation layer 206, resulting in two first portions A and two second portions B located on the isolation region II; during the etching of the transition isolation layer to form the isolation layer 207, the mask layer blocks the first portions A and the second portions B, and the etching targets the transition isolation layer located on top of the floating gate 204, resulting in an isolation layer with a thickness of b2 located on top of the floating gate 204. The thickness of the isolation layer 207 located on top of the floating gate 204 is less than the thickness of the second portions B located on the isolation region II, and the thickness of the second portions B located on the isolation region II is less than the thickness of the first portions A located on the isolation region II.
[0074] In other embodiments of the present invention, the step of etching the initial isolation layer to form the isolation layer further includes: etching the initial isolation layer using a plasma etching method to form the isolation layer. The first portion of the isolation layer, the second portion of the isolation layer, and the isolation layer located on the floating gate are formed simultaneously in the same etching process.
[0075] Please refer to Figures 25 to 27 , Figure 25 yes Figure 26 and Figure 27 Top view, Figure 26 yes Figure 25 A sectional view at position X1X2. Figure 27 yes Figure 25 In the cross-sectional view at position Y1Y2, a control gate 208 is formed on the floating gate 204.
[0076] Specifically, in some embodiments of the present invention, the control gate 208 spans the floating gate 204 along both the first direction X and the second direction Y, wherein the first direction X and the second direction Y are perpendicular to each other. Since the control gate 208 spans the floating gate 204 along both the first direction X and the second direction Y, the control gate 208 completely surrounds the sidewalls of the floating gate 204 in both directions X and Y, increasing the coupling coefficient between the control gate 208 and the floating gate 204, thereby improving the read and write speed of the memory structure.
[0077] The steps of forming the control gate 208 include: forming a control gate material layer on the isolation layer 207; forming a mask layer on the control gate material layer, wherein the dimension of the mask layer along the second direction Y is larger than the dimension of the floating gate 204 along the second direction Y and the projection of the floating gate 204 on the surface of the substrate 202 is located within the projection range of the mask layer on the surface of the substrate 202; and etching the control gate material layer using the mask layer as a mask to form the control gate 208.
[0078] The mask layer is used to define the size of the control gate 208 in the second direction Y. The size of the mask layer in the second direction Y is larger than the size of the floating gate 204 in the second direction Y, and the projection of the floating gate 204 on the surface of the substrate 202 is within the projection range of the mask layer on the surface of the substrate 202. This ensures that the control gate 208 etched with the mask layer as a mask completely surrounds the floating gate 204 in the first direction X and the second direction Y.
[0079] The method for forming the control gate material layer includes deposition.
[0080] The control gate 208 is made of crystalline silicon; the crystalline silicon includes doped crystalline silicon and undoped crystalline silicon. In some embodiments of the present invention, the control gate 208 is made of doped crystalline silicon. In other embodiments of the present invention, the control gate 208 is made of undoped crystalline silicon.
[0081] Specifically, in some embodiments of the present invention, such as Figure 27 As shown, the thickness c2 of the top of the control gate 208 extending above the top of the isolation layer 207 ranges from 900 angstroms to 1500 angstroms.
[0082] Specifically, in some embodiments of the present invention, such as Figure 27 As shown, the dimension d2 of the control gate 208 along the second direction Y ranges from 100 nanometers to 200 nanometers.
[0083] The control gate 208 is used to realize the writing, reading and erasing of charge in the floating gate 204.
[0084] The isolation layer 207 is located between the floating gate 204 and the control gate 208 to ensure the reliability of the memory structure.
[0085] Accordingly, this invention also provides a memory structure, please refer to the following: Figures 25 to 27 The system includes: a substrate 202, the substrate 202 including an active region I and an isolation region II, the isolation region II surrounding the active region I and the surface of the active region I protruding from the surface of the isolation region II; a floating gate 204, the floating gate 204 spanning the active region I and covering the surface of the active region I; and a control gate 208 located on the floating gate 204.
[0086] The memory structure includes a substrate 202, which includes an active region I and an isolation region II, wherein the isolation region II surrounds the active region I and the surface of the active region I protrudes from the surface of the isolation region II.
[0087] The substrate 202 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. Specifically, in some embodiments of the present invention, the substrate 202 is made of silicon.
[0088] The projection shape of the portion of the active region I protruding from the surface of the isolation region II onto the plane perpendicular to the substrate 202 can be any shape, such as square, circular, or trapezoidal. Specifically, in some embodiments of the present invention, the shape of the active region I protruding from the surface of the isolation region II is square.
[0089] The active region I protrudes from the surface of the isolation region II, providing a structural basis for increasing the contact area between the floating gate 204 and the active region I. Specifically, in some embodiments of the present invention, the height 'a' of the active region I protruding from the surface of the isolation region II ranges from 5 angstroms to 100 angstroms.
[0090] The memory structure includes a floating gate oxide layer 203, which is located between the active region I and the floating gate 204.
[0091] Specifically, in some embodiments of the present invention, the floating gate oxide layer 203 further extends onto the substrate 202 of the isolation region II. The function of the floating gate oxide layer 203 is to improve the stability of the memory structure and ensure the reliability of the memory structure.
[0092] The floating gate oxide layer 203 is made of silicon oxide. Specifically, in some embodiments of the present invention, the thickness of the floating gate oxide layer 203 ranges from 50 angstroms to 200 angstroms.
[0093] The memory structure includes a floating gate 204 that spans the active region I and covers the surface of the active region I.
[0094] That is, in both the first direction X and the second direction Y, the floating gate 204 covers the surface of the active region I. The surface of the active region I is adjacent to the floating gate 204, which increases the contact area between the floating gate 204 and the active region I, thereby increasing the coupling coefficient of the memory structure and improving the operating speed of the memory structure.
[0095] The floating gate 204 is made of crystalline silicon; the crystalline silicon includes doped crystalline silicon and undoped crystalline silicon. In some embodiments of the present invention, the floating gate 204 is made of doped crystalline silicon. In other embodiments of the present invention, the floating gate 204 is made of undoped crystalline silicon.
[0096] Specifically, in some embodiments of the present invention, the thickness c1 of the floating gate 204 ranges from 550 angstroms to 850 angstroms. Specifically, the thickness c1 of the floating gate 204 refers to the thickness of the floating gate 204 located on the active region I.
[0097] The memory structure includes an isolation layer 207, which is located between the floating gate 204 and the control gate 208.
[0098] The thickness of the isolation layer 207 extending into isolation zone II is greater than the thickness of the isolation layer 207 between control gate 208 and floating gate 204.
[0099] The thickness b2 of the isolation layer 207 between the control gate 208 and the floating gate 204 ranges from 50 angstroms to 150 angstroms.
[0100] The isolation layer 207 of the isolation region II has two first parts A and two second parts B in a plane parallel to the surface of the substrate 202. The two first parts A are located on both sides of the floating gate 204 along the first direction X, and the two second parts B are located on both sides of the floating gate 204 along the second direction Y.
[0101] The thickness b1 of the second part B ranges from 150 angstroms to 300 angstroms.
[0102] The top surfaces of the first part A and the second part B are flush. The first part A extends along the second direction Y until it is flush with the boundary of the second part B.
[0103] The thickness of the first part A is greater than the thickness of the second part B.
[0104] The material of the isolation layer 207 includes a high-dielectric material. The high-dielectric material includes hafnium oxide and silicon nitride, etc.
[0105] The memory structure includes a control gate 208, which is located on the floating gate 204.
[0106] The control gate 208 spans the floating gate 204 and is located on the sidewall of the floating gate 204. The dimension of the control gate 208 in the second direction Y is larger than the dimension of the floating gate 204 in the second direction Y, and the projection of the floating gate 204 on the surface of the substrate 202 is within the projection range of the control gate 208 on the surface of the substrate 202.
[0107] The control gate 208 is made of crystalline silicon; the crystalline silicon includes doped crystalline silicon and undoped crystalline silicon. In some embodiments of the present invention, the control gate 208 is made of doped crystalline silicon. In other embodiments of the present invention, the control gate 208 is made of undoped crystalline silicon.
[0108] Specifically, in some embodiments of the present invention, such as Figure 27 As shown, the thickness c2 of the top of the control gate 208 extending above the top of the isolation layer 207 ranges from 900 angstroms to 1500 angstroms.
[0109] Specifically, in some embodiments of the present invention, such as Figure 27 As shown, the dimension d2 of the control gate 208 along the second direction Y ranges from 100 nanometers to 200 nanometers.
[0110] In summary, the floating gate 204 spans the active region I and covers its surface. The surface of the active region I is adjacent to the floating gate 204, increasing the contact area between them and thus increasing the coupling coefficient of the memory structure, thereby improving its read / write speed. The control gate 208 spans the floating gate 204 along both the first direction X and the second direction Y, where the first direction X and the second direction Y are perpendicular to each other. The control gate 208 completely surrounds the sidewalls of the floating gate 204, increasing the coupling coefficient between them and further improving the read / write speed of the memory structure. Furthermore, after forming the substrate, the floating gate 204 spanning the active region I is directly formed on the substrate. The fabrication steps of the floating gate 204 are simple, reducing the technological difficulty.
[0111] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A memory structure, characterized in that, include: A substrate, the substrate including an active region and an isolation region, the isolation region surrounding the active region and the surface of the active region protruding from the surface of the isolation region; A floating gate that spans the active region and covers the surface of the active region; A control gate, which is located on the floating gate.
2. The memory structure as described in claim 1, characterized in that, Also includes: A floating gate oxide layer is located between the active region and the floating gate.
3. The memory structure as described in claim 2, characterized in that, The floating gate oxide layer also extends onto the substrate of the isolation region.
4. The memory structure as described in claim 1, characterized in that, Also includes: An isolation layer is located between the floating gate and the control gate.
5. The memory structure as described in claim 4, characterized in that, The control gate spans the floating gate along both a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other; The isolation layer also extends into the isolation zone.
6. The memory structure as described in claim 5, characterized in that, The thickness of the isolation layer extending into the isolation zone is greater than the thickness of the isolation layer between the control gate and the floating gate.
7. The memory structure as described in claim 6, characterized in that, The isolation layer of the isolation region has two first parts and two second parts. In a plane parallel to the substrate surface, the two first parts are located on both sides of the floating gate along a first direction, and the two second parts are located on both sides of the floating gate along a second direction.
8. The memory structure as described in claim 7, characterized in that, The top surfaces of the first and second parts are flush.
9. The memory structure as described in claim 7, characterized in that, The thickness of the first part is greater than the thickness of the second part.
10. The memory structure as described in claim 7, characterized in that, The first part extends along the second direction to be flush with the boundary of the second part.
11. A method for forming a memory structure, characterized in that, include: A substrate is formed, the substrate comprising: a substrate, the substrate including an active region and an isolation region, the isolation region surrounding the active region and the surface of the active region protruding from the surface of the isolation region; A floating grid is formed on the active region, the floating grid spanning the active region and covering the surface of the active region; A control gate is formed on the floating gate.
12. The method for forming a memory structure as described in claim 11, characterized in that, The steps involved in forming the substrate include: Provide initial substrate; The initial substrate is etched to form the transition substrate; After the transition substrate is formed and before the floating gate is formed on the active region, the surface of the transition substrate is oxidized to form the substrate and the floating gate oxide layer located on the surface of the substrate.
13. The method for forming a memory structure as described in claim 12, characterized in that, Also includes: An isolation layer is formed between the floating gate and the control gate.
14. The method for forming a memory structure as described in claim 13, characterized in that, The floating gate oxide layer also extends onto the substrate of the isolation region; The isolation layer is formed after the floating gate is formed and before the control gate is formed.
15. The method for forming a memory structure as described in claim 14, characterized in that, The isolation layer also extends into the isolation zone.
16. The method for forming a memory structure as described in claim 13 or 14, characterized in that, The steps to form the isolation layer include: An isolation trench is formed within the isolation zone, and the isolation trench is located on both sides of the floating grid along the first direction; An initial isolation layer is formed within the isolation trench and on the substrate; The initial isolation layer is etched to form the isolation layer.
17. The method for forming a memory structure as described in claim 16, characterized in that, The isolation layer of the isolation region has two first parts and two second parts in a plane parallel to the substrate surface. The two first parts are located on both sides of the floating gate along a first direction, and the two second parts are located on both sides of the floating gate along a second direction, wherein the first direction and the second direction are perpendicular to each other.
18. The method for forming a memory structure as described in claim 17, characterized in that, The steps for forming the control gate include: A control gate material layer is formed on the isolation layer; A mask layer is formed on the control gate material layer, wherein the dimension of the mask layer along the second direction is larger than the dimension of the floating gate along the second direction, and the projection of the floating gate on the substrate surface is located within the projection range of the mask layer on the substrate surface; Using the mask layer as a mask, the control gate material layer is etched to form the control gate.