Semiconductor device and data storage system including semiconductor device

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a substrate, a stack structure including gate electrodes spaced apart from each other in a vertical direction, and a channel structure extending in the vertical direction through the stack structure in a channel hole. The channel structure includes a channel layer on sidewalls of the channel hole, a resistance switching layer between the sidewalls of the channel hole and the channel layer, a diffusion barrier structure between the sidewalls of the channel hole and the resistance switching layer, an electrolyte layer between the channel hole and the diffusion barrier structure, and an ion storage layer between the channel hole and the electrolyte layer, the resistance switching layer configured to change electrical conductivity based on an electrochemical reaction involving loss or gain of oxygen ions. The diffusion barrier structure includes at least two diffusion barrier layers stacked in sequence.

Description

Technical Field

[0001] An exemplary embodiment of the present invention relates to a semiconductor device and a data storage system including the semiconductor device. Background Technology

[0002] In electronic systems that utilize data storage, there is an increasing need for semiconductor devices capable of storing higher volumes of data. Therefore, methods to increase the data storage capacity of semiconductor devices have been investigated. For example, methods to increase the data storage capacity of semiconductor devices may include manufacturing semiconductor devices comprising memory cells arranged in a three-dimensional arrangement rather than a two-dimensional arrangement. Summary of the Invention

[0003] Some exemplary embodiments of the present invention provide a semiconductor device with improved reliability.

[0004] Some exemplary embodiments of the present invention provide a data storage system including a semiconductor device with improved reliability, the semiconductor device being capable of low-voltage operation.

[0005] According to some exemplary embodiments of the present invention, a semiconductor device is provided, including a substrate, a stacked structure including gate electrodes spaced apart from each other in a vertical direction, and a channel structure in a channel hole and extending through the stacked structure in a vertical direction perpendicular to the upper surface of the substrate. The channel structure includes a channel layer on the sidewall of the channel hole, a switching layer between the sidewall of the channel hole and the channel layer, a diffusion barrier structure between the sidewall of the channel hole and the switching layer, an electrolyte layer between the sidewall of the channel hole and the diffusion barrier structure, and an ion storage layer between the sidewall of the channel hole and the electrolyte layer. The switching layer is configured to change its conductivity based on an electrochemical reaction involving the loss or gain of oxygen ions. The diffusion barrier structure includes at least two diffusion barrier layers sequentially stacked in a direction from the switching layer toward the electrolyte layer.

[0006] According to some exemplary embodiments of the present invention, a semiconductor device is provided, including a substrate, a stacked structure including gate electrodes spaced apart from each other in a vertical direction, and a channel structure extending through the stacked structure in a channel hole in a vertical direction perpendicular to the upper surface of the substrate. The channel structure includes an insulating pillar with a circular cross-section at the center of the channel hole, an ion-providing structure surrounding the outer surface of the insulating pillar, a diffusion-blocking structure surrounding the outer surface of the ion-providing structure, an electrolyte layer surrounding the outer surface of the diffusion-blocking structure, and an ion storage layer surrounding the outer surface of the electrolyte layer. The ion-providing structure includes a first metal oxide and is configured to change conductivity based on an electrochemical reaction involving the loss or gain of oxygen ions. The diffusion-blocking structure includes a second metal oxide, the electrolyte layer includes a third metal oxide, and the ion storage layer includes a fourth metal oxide. The diffusion-blocking structure includes at least two diffusion-blocking layers sequentially stacked between the ion-providing structure and the electrolyte layer, and is configured to reduce the re-diffusion of oxygen ions from the ion storage layer.

[0007] According to some exemplary embodiments of the present invention, a data storage system is provided, including a semiconductor device and a controller. The semiconductor device includes a channel structure in a channel aperture and extending through a gate electrode stacked on a substrate. The controller is electrically connected to the semiconductor device and configured to control the semiconductor device. The channel structure includes an insulating pillar having a circular cross-section at the center of the channel aperture, an ion-providing structure surrounding the outer surface of the insulating pillar, a diffusion-blocking structure surrounding the outer surface of the ion-providing structure, an electrolyte layer surrounding the outer surface of the diffusion-blocking structure, and an ion storage layer surrounding the outer surface of the electrolyte layer. The ion-providing structure includes a first metal oxide and is configured to change conductivity based on an electrochemical reaction involving the loss or gain of oxygen ions. The diffusion-blocking structure includes a second metal oxide, the electrolyte layer includes a third metal oxide, and the ion storage layer includes a fourth metal oxide. The diffusion-blocking structure includes at least two diffusion-blocking layers sequentially stacked between the ion-providing structure and the electrolyte layer, the diffusion-blocking structure being configured to reduce the re-diffusion of oxygen ions from the ion storage layer.

[0008] According to some exemplary embodiments of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a mold structure by alternately stacking an interlayer insulating layer and a sacrificial insulating layer on a semiconductor substrate; forming a channel via through the mold structure; forming an ion storage layer and an electrolyte layer in the channel via; and forming a diffusion barrier structure by sequentially stacking a plurality of diffusion barrier layers on the electrolyte layer.

[0009] According to some exemplary embodiments of the present invention, in a method of manufacturing a semiconductor device, in forming a diffusion barrier structure, each of a plurality of diffusion barrier layers comprises a metal oxide, and each of the plurality of diffusion barrier layers comprises oxygen of different concentrations. Attached Figure Description

[0010] The above and other aspects, features and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A These are schematic plan views of semiconductor devices according to some example embodiments;

[0012] Figure 1B yes Figure 1A A magnified view of a portion of a semiconductor device;

[0013] Figure 2 These are schematic cross-sectional views of a semiconductor device according to some example embodiments;

[0014] Figure 3A This is a partial enlarged view of a semiconductor device according to some example embodiments;

[0015] Figure 3B It is shown Figure 3A A graph showing the characteristics of the diffusion barrier layer in a semiconductor device;

[0016] Figure 4 It is a graph showing the characteristics based on the thickness of the metal oxide;

[0017] Figures 5A to 5C Show Figure 3A Ion movement and current flow during programming, reading and erasing operations of semiconductor devices;

[0018] Figures 6A to 17 These are partial enlarged views of semiconductor devices according to some exemplary embodiments and graphs showing the characteristics of the diffusion barrier layer of the semiconductor device according to each of some exemplary embodiments.

[0019] Figure 18 It shows the manufacturing process. Figure 2 A flowchart of a method for manufacturing semiconductor devices;

[0020] Figure 19 This is a schematic diagram illustrating a data storage system including semiconductor devices according to some example embodiments; and

[0021] Figure 20 This is a schematic perspective view of a data storage system including semiconductor devices according to some example embodiments. Detailed Implementation

[0022] In the following description, some exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following, unless indicated by reference numerals, terms such as “top,” “upper,” “upper surface,” “above,” “bottom,” “lower,” “lower surface,” “below,” and “side surface” are to be understood as referring to the drawings.

[0023] Figure 1A This is a schematic plan view of a semiconductor device according to some example implementations. Figure 1B yes Figure 1A A magnified view of part "A" of the semiconductor device. Figure 2 It is a schematic cross-sectional view of a semiconductor device according to some example embodiments, taken along line I-I'. Figure 3A This is an enlarged view of part "B" of a semiconductor device according to some example embodiments. Figure 3B It is shown Figure 3A A graph showing the characteristics of semiconductor devices. Figure 4 It is a graph showing the degree of ion diffusion based on the thickness of the diffusion barrier layer.

[0024] refer to Figures 1A to 4 The semiconductor device 100 may include a source structure SS comprising a semiconductor substrate 101 and a first horizontal conductive layer 102 and a second horizontal conductive layer 104 on the semiconductor substrate 101, a gate electrode 130 stacked on the semiconductor substrate 101, an interlayer insulating layer 120 stacked alternately with the gate electrode 130 on the semiconductor substrate 101, a channel structure CH (the channel structure CH includes a channel layer 140) configured to pass through a first stack structure GS1 and a second stack structure GS2 of the gate electrode 130, an upper isolation region US passing through a portion of the second stack structure GS2, an isolation region MS extending through the first stack structure GS1 and the second stack structure GS2, a contact plug 170 on the channel structure CH, and a cell region insulating layer 192 covering the channel structure CH.

[0025] In the semiconductor device 100, a single memory cell string can be configured relative to each channel structure CH, and multiple memory cell strings can be arranged in columns and rows in the X and Y directions.

[0026] Semiconductor substrate 101 may have an upper surface extending in both the X and Y directions. Semiconductor substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Semiconductor substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. However, the exemplary embodiments are not limited thereto.

[0027] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be stacked and disposed on the upper surface of the semiconductor substrate 101. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 (source layers) can form a source structure SS together with the semiconductor substrate 101. The source structure SS can be used as a common source line of the semiconductor device 100. The first horizontal conductive layer 102 can be directly connected to the channel layer 140 at the periphery of the channel layer 140. The first horizontal conductive layer 102 can extend partially along the channel layer 140 in the Z direction to contact the channel layer 140.

[0028] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise semiconductor materials, and may include, for example, polysilicon. However, the exemplary embodiments are not limited thereto. In this case, at least the first horizontal conductive layer 102 may be a layer doped with impurities having the same conductivity type as the semiconductor substrate 101, and the second horizontal conductive layer 104 may be a doped layer or an intrinsic semiconductor layer comprising impurities diffused from the first horizontal conductive layer 102. However, the material of the second horizontal conductive layer 104 is not limited to semiconductor materials, and in some exemplary embodiments may be replaced by an insulating layer. In some exemplary embodiments, an insulating layer having a relatively small thickness may be interposed between the upper surface of the first horizontal conductive layer 102 and the lower surface of the second horizontal conductive layer 104.

[0029] Gate electrodes 130 may be vertically spaced and stacked on semiconductor substrate 101 to form a first stacked structure GS1 and a second stacked structure GS2. Gate electrodes 130 may include a lower gate electrode forming the gate of a ground select transistor, a memory gate electrode forming a plurality of memory cells, and an upper gate electrode 130U forming the gate of a string select transistor. The number of memory gate electrodes forming memory cells may be determined according to the capacity of semiconductor device 100. In some example embodiments, each of the number of upper gate electrodes and the number of lower gate electrodes may be one, two, or more, and may have the same or different structure as the memory gate electrodes. In some example embodiments, gate electrodes 130 may further include gate electrodes 130 disposed above the upper gate electrode 130U and / or below the lower gate electrode, the gate electrodes 130 forming an erase transistor for an erase operation utilizing the gate-induced drain leakage current (GIDL) phenomenon. Furthermore, some gate electrodes 130, such as those adjacent to the upper or lower gate electrodes, may be dummy gate electrodes.

[0030] The gate electrode 130 may include a metallic material, such as tungsten (W). However, the exemplary embodiments are not limited thereto. In some exemplary embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In some exemplary embodiments, the gate electrode 130 may further include a diffusion barrier 158. For example, the diffusion barrier 158 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. However, the exemplary embodiments are not limited thereto.

[0031] Interlayer insulating layers 120 may be disposed between gate electrodes 130. In the same manner as gate electrodes 130, interlayer insulating layers 120 may also be configured to be spaced apart from each other in a direction perpendicular to the upper surface of semiconductor substrate 101. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride. However, the exemplary embodiments are not limited thereto.

[0032] In the interlayer insulation layer 120, the intermediate insulation layer 125 between the stacked structures GS1 and GS2 and the uppermost interlayer insulation layer 121 may have a thickness greater than that of the other interlayer insulation layers 120, but the example implementation is not limited thereto.

[0033] The channel structures CH can each form individual memory cell strings and can be arranged in rows and columns on the semiconductor substrate 101, spaced apart from each other. The channel structures CH can be configured to form a lattice pattern on the XY plane or have a zigzag shape in one direction. The channel structures CH can have a pillar shape filling the channel vias and can have sloping side surfaces, such that the width of the channel structures CH narrows as the distance from the semiconductor substrate 101 decreases according to the aspect ratio. Figure 3A As shown, in addition to the channel layer 140, each of the channel structures CH may also include a resistance switching layer 143, a diffusion barrier structure 150, an electrolyte layer 145 and an ion storage layer 147 on the outer surface of the channel layer 140, and may further include a buried insulating layer 160 inside the channel layer 140 and a channel pad 165 on the upper end of the channel structure CH.

[0034] The multilayer material layers forming the channel structure CH can have a structure in which oxygen ions are diffused, and can include metal oxides, preferably transition metal oxides.

[0035] The buried insulating layer 160 can be configured as an insulating post at the center O of the channel hole. The buried insulating layer 160 can have a circular cross-section in the XY plane and can be formed of an insulating material such as silicon oxide, silicon nitride, etc. However, the example embodiment is not limited thereto.

[0036] The channel layer 140 may have an annular shape surrounding the buried insulating layer 160 therein. However, in some example embodiments, the buried insulating layer 160 may be omitted, and the channel layer 140 may have a cylindrical shape, such as a cylinder filling a channel hole. The channel layer 140 may include a metal-oxide-semiconductor or a silicon semiconductor. For example, the channel layer 140 may include WO4. x It may be one of IGZO, IZO, ZnO, ZTO, InO, PCMO, TiO2, or one of polycrystalline silicon (poly-Si) and crystalline silicon (c-Si). However, the example embodiments are not limited thereto.

[0037] The channel layer 140 may be a layer that is not doped with conductive impurities such as P-type or N-type impurities during the manufacturing process. That is, the channel layer 140 may be a layer that is not intentionally doped with conductive impurities. However, in some example embodiments, the channel layer 140 may further include N-type impurities diffused from the upper region and / or the lower region and the source structure SS. For example, when the gate electrode 130 includes an erase gate electrode forming an erase transistor, the N-type impurities may be further included in a region parallel to the erase gate electrode. The channel layer 140 may have a first thickness t1, and may have a substantially uniform thickness from the upper portion to the lower portion of the channel layer 140.

[0038] A resistor switching layer 143 may be disposed between the gate electrode 130 and the channel layer 140. The resistor switching layer 143 may be configured to cover the outer and bottom surfaces of the channel layer 140, and in a plan view may have an annular shape surrounding the outer surface of the channel layer 140. The resistor switching layer 143 may include a metal oxide, and may include a transition metal oxide, such as WO3. z However, the example implementation is not limited thereto. The resistance switching layer 143 may include a material that exhibits a significant change in conductivity due to an electrochemical reaction caused by the loss of oxygen ions in the metal oxide, and the resistance value may change due to the change in conductivity caused by the loss or gain of oxygen ions, thereby allowing current flow together with the channel layer 140.

[0039] The resistance switching layer 143 comprises a material with a high ion diffusion coefficient to facilitate the loss and gain of oxygen ions, and the second thickness t2 of the resistance switching layer 143 may be substantially the same as the first thickness t1 of the channel layer 140.

[0040] The diffusion barrier structure 150 may be disposed along the outer surface of the resistor switching layer 143. In a plan view, the diffusion barrier structure 150 may be formed in an annular shape surrounding the outer surface of the resistor switching layer 143. The diffusion barrier structure 150 may include a metal oxide, and preferably, may include a transition metal oxide, such as WO3. x HfOy AlO x At least one of the following. However, the example implementation is not limited thereto. The diffusion barrier structure 150 may have a total third thickness t3, and the third thickness t3 may be less than the first thickness t1 of the channel layer 140, but may be greater than 1 / 2 of the first thickness t1. For example, the third thickness t3 may be 0.6 to 0.8 times the first thickness t1, but the example implementation is not limited thereto.

[0041] The diffusion barrier structure 150 can have a total ion diffusion coefficient significantly lower than that of the resistive switching layer 143 and the ion storage layer 147, and can reduce and / or prevent oxygen ions stored in the ion storage layer 147 from re-diffusing into the resistive switching layer 143, thereby improving data retention efficiency. Furthermore, the diffusion barrier structure 150 can include a material having a degree of ionization lower than that of the electrolyte layer 145. In this case, the degree of ionization can be defined not as the ease of ion formation in solution, but as the ease of ion formation when a voltage is applied.

[0042] Multiple diffusion barrier layers 156, 154, ..., 152 may be sequentially configured in the diffusion barrier structure 150. The term "sequentially configured" can be understood as being configured from the top to the bottom of the channel aperture, while simultaneously covering the outer and bottom surfaces of the previous diffusion barrier layers 156, 154, ..., 152. The multiple diffusion barrier layers 156, 154, ..., 152 in the diffusion barrier structure 150 may include at least three stacked layers, and the diffusion barrier layers 156, 154, ..., 152 may include the same material, but the inventive concept is not limited thereto.

[0043] The plurality of diffusion barrier layers 156, 154, ... and 152 may include tungsten oxide. However, the example implementation is not limited thereto. When the resistor switching layer 143 also includes tungsten oxide, the plurality of diffusion barrier layers 156, 154, ... and 152 may have a higher oxygen concentration than the oxygen concentration of the resistor switching layer 143.

[0044] Multiple diffusion barrier layers 156, 154, ... and 152 can all contain HfO y However, the example implementation is not limited thereto. Multiple diffusion barrier layers 156, 154, ..., 152 can suppress the movement of oxygen ions at the interfaces between the diffusion barrier layers 156, 154, ..., 152, thereby limiting and / or preventing oxygen ions from re-diffusing from the ion storage layer 147 to the resistance switching layer 143. The multiple diffusion barrier layers 156, 154, ..., 152 can have substantially the same thickness t3c, t3b, ..., t3a (…). Figure 3B (ta in the example), but the example implementation is not limited to this.

[0045] The ion diffusion coefficient and thickness of the multiple diffusion barrier layers 156, 154, ... and 152 forming the diffusion barrier structure 150 can be controlled to achieve an improved degree of ion diffusion, thereby causing a diffusion prevention effect.

[0046] In transition metal oxides, the degree of ionization can change as the concentration of the oxygen component varies, and therefore the ion diffusion coefficients may differ from one another. Specifically, within the group of metal oxides comprising the same metallic material, it is understood that the ion diffusion coefficient can decrease with increasing oxygen concentration.

[0047] Figure 4 The graph shows the degree of ion diffusion based on the thickness of the transition metal oxide. Figure 4 In the graph, the X-axis represents the number of voltage pulses, and the Y-axis represents the normalized conductivity. Figure 4 In this study, the thickness of the diffusion barrier structure 150 was varied to 2.5 nm, 5 nm, and 7.5 nm, and the normalized conductivity was calculated for each thickness. It can be understood that a higher normalized conductivity indicates a greater degree of ion diffusion.

[0048] according to Figure 4 When the number of voltage pulses is less than or equal to the desired (and / or alternatively, predetermined) number of voltage pulses, the conductivity with respect to thickness can exhibit a substantially linear trend. However, when the number of voltage pulses is greater than the desired (and / or alternatively, predetermined) number of voltage pulses, the conductivity with respect to a larger thickness can exhibit a relatively linear change, and the conductivity with respect to a smaller thickness can deviate from this linearity, exhibiting a more rapid change in the conductivity trend. This deviation from linearity can indicate that the normalized conductivity is more unpredictable, thereby allowing for the inference of potential memory loss due to rapid diffusion.

[0049] The diffusion barrier structure 150 can be optimized to allow oxygen ions to tunnel to the ion storage layer 147, thus making it difficult to increase the thickness of the diffusion barrier structure 150. Furthermore, in a channel aperture with finite dimensions, the thickness of the diffusion barrier structure 150 cannot be increased indefinitely. Therefore, the thickness and material of the diffusion barrier structure 150 can be controlled such that multiple diffusion barrier layers 156, 154, ..., 152 can be stacked in multiple layers to reduce (and / or minimize) ion re-diffusion, resulting in an effect similar to that of a single diffusion barrier structure 150 with a thickness greater than a third thickness t3. At the interfaces between the diffusion barrier layers 156, 154, ..., 152, oxygen ions may be unable to move to the diffusion barrier layers 156, 154, ..., 152 in contact with them due to interface resistance.

[0050] exist Figure 3A and Figure 3BIn this context, it can be understood that even when the multiple diffusion barrier layers 156, 154, ... and 152 of the diffusion barrier structure 150 have the same thickness t3c, t3b, ... and t3a and comprise the same material and therefore have the same ion diffusion coefficient Da, the re-diffusion of oxygen ions is sufficiently reduced and / or prevented due to the suppression of oxygen ion movement at the interface between the diffusion barrier layers 156, 154, ... and 152.

[0051] The electrolyte layer 145 can be disposed on the diffusion barrier structure 150 to cover the outer surface and bottom surface of the diffusion barrier structure 150.

[0052] Electrolyte layer 145 comprises metal oxides and may include transition metal oxides, such as HfO. x ZrO x Materials such as YSZ and Ta2O5 can be used. The electrolyte layer 145 may include materials with a higher ionization tendency than the diffusion barrier structure 150. While the individual layers of the diffusion barrier structure 150 may include hafnium oxide, the electrolyte layer 145 may include tantalum oxide, but the inventive concept is not limited thereto. The electrolyte layer 145 may also include hafnium oxide when the individual layers of the diffusion barrier structure 150 include hafnium oxide. However, the oxygen concentration of the electrolyte layer 145 may be lower than that of the diffusion barrier structure 150. The fourth thickness t4 of the electrolyte layer 145 may be substantially the same as the first thickness t1 of the channel layer 140.

[0053] The ion storage layer 147 can be configured to cover both the outer and bottom surfaces of the electrolyte layer 145. The ion storage layer 147 may include a metal oxide, and may include transition metal oxides, such as WO3. x GdO x MoO y Ta2O5, Al2O3, TiO x HfO x SiO x The ion storage layer 147 can perform the same function as the charge trapping layer, where data of the memory cells is stored by acquiring and storing oxygen ions generated in the resistance switching layer 143. The ion storage layer 147 may include a material with a higher ion diffusion coefficient to facilitate the loss and acquisition of oxygen ions. However, when both the ion storage layer 147 and the resistance switching layer 143 comprise tungsten oxide, the oxygen concentration of the ion storage layer 147 can be higher than that of the resistance switching layer 143. Therefore, the ion diffusion coefficient of the ion storage layer 147 can be less than that of the resistance switching layer 143. The fifth thickness t5 of the ion storage layer 147 can be substantially the same as the first thickness t1 of the channel layer 140.

[0054] like Figure 1BAs shown, when viewed in the XY plane, each of the channel structures CH can have a buried insulating layer 160 at the center O of the channel aperture. As an insulating pillar structure with a circular or elliptical cross-section positioned relative to the center O of the channel structure CH, an annular channel layer 140 can be configured to surround the side surface of the buried insulating layer 160, and an annular resistance switching layer 143 can be configured to surround the outer surface of the annular channel layer 140. The layers of the diffusion barrier structure 150 are sequentially configured to have annular shapes, and an annular electrolyte layer 145 can be configured to surround the outer surface of the diffusion barrier structure 150, i.e., the outer surface of the outermost diffusion barrier layer 156. An annular ion storage layer 147 can be configured to surround the outer surface of the electrolyte layer 145 and contact the outer surface of the channel aperture. Therefore, from the channel layer 140 to the ion storage layer 147, all layers can have a concentric ring shape with a center O and can be configured to have increasing radii.

[0055] The channel structure CH may include a first channel structure CH1 and a second channel structure CH2 passing through the stacked structures GS1 and GS2 respectively, and may include a curved portion between the first channel structure CH1 and the second channel structure CH2.

[0056] Between the first channel structure CH1 and the second channel structure CH2, the channel layer 140, the resistance switching layer 143, the diffusion barrier structure 150, the electrolyte layer 145 and the ion storage layer 147 can be connected to each other, and the channel pad 165 can be provided only on the upper end of the second channel structure CH2.

[0057] The upper isolation region US can extend in the X direction between adjacent isolation regions MS in the Y direction. The upper isolation region US can be configured to pass through a portion of the upper gate electrode 130U (including the uppermost gate electrode 130U) within the gate electrode 130. According to some example embodiments, the number of upper gate electrodes 130U isolated by the upper isolation region US can be varied in various ways. The upper isolation region US can be configured to intersect a portion of the channel structure CH. The upper isolation region US can have a desired (and / or alternatively, predetermined) width in the Y direction and can extend in the X direction while intersecting multiple channel structures CH arranged in a zigzag matrix pattern. Therefore, when multiple channel structures CH are arranged with the same separation distance, the upper isolation region US can extend while simultaneously intersecting two consecutive rows of channel structures CH. The upper isolation region US can be recessed into a portion of the channel structure CH opposite the upper ends of two rows of channel structures CH, thus allowing a portion of the channel structure CH to be removed. The upper isolation region US may not extend through the center of the channel structure CH, and may be configured such that at least half of the channel structure CH remains on its upper surface; however, the example implementation is not limited thereto. The channel structure CH recessed therein by the upper isolation region US may be an effective channel structure that is essentially used as a memory cell, rather than a dummy channel structure. The upper isolation region US may include an upper isolation insulating layer 103. The upper isolation insulating layer 103 may include an insulating material, and may include, for example, silicon oxide, silicon nitride, or silicon nitride. However, the example implementation is not limited thereto.

[0058] The isolation region MS can extend in the X direction through the gate electrode 130, the interlayer insulating layer 120, and the first horizontal conductive layer 102 and the second horizontal conductive layer 104, and can be connected to the semiconductor substrate 101. For example... Figure 1A As shown, the isolation regions MS can be configured to be parallel to each other. The isolation regions MS can isolate the gate electrodes 130 from each other in the Y direction. Due to the high aspect ratio, the isolation regions MS can have a width that decreases toward the semiconductor substrate 101. The isolation regions MS may include an isolation insulating layer disposed in a trench. The isolation insulating layer may include an insulating material, such as silicon oxide, silicon nitride, or silicon nitride. However, the example embodiment is not limited thereto.

[0059] Contact plug 170 may be disposed on the channel structure CH. Contact plug 170 may have a cylindrical shape and may have sloped side surfaces such that the width of contact plug 170 decreases toward the semiconductor substrate 101 according to the aspect ratio. Contact plug 170 can electrically connect the channel structure CH to an upper interconnect structure such as a bit line. Contact plug 170 may be formed of a conductive material and may include at least one of, for example, tungsten (W), aluminum (Al), and copper (Cu). However, the exemplary embodiments are not limited thereto.

[0060] The cell region insulating layer 192 may have a multi-layer structure and may be configured to cover the gate electrode 130 and the isolation regions MS and US, as well as the channel structure CH. Each of the cell region insulating layers 192 may be formed of an insulating material and may include at least one of, for example, silicon oxide, silicon nitride, and silicon nitride. However, the example embodiments are not limited thereto.

[0061] In the following text, reference will be made to Figures 5A to 5C The operation of a semiconductor device 100, including a memory cell, is described.

[0062] Figure 5A These are state diagrams during programming operations of semiconductor devices according to some exemplary embodiments of the present invention. Figure 5B This is a state diagram during a readout operation of a semiconductor device according to some example embodiments, and Figure 5C This is a state diagram during the erase operation of a semiconductor device according to some example embodiments.

[0063] The region corresponding to the gate electrode 130 of each channel structure CH can be a single memory cell transistor, which can be operated by a word line signal applied from the gate electrode 130, and the current flowing between the source structure SS, which can be the source, and the channel pad 165, which can be the drain, can flow through the channel pad 165 toward the bit line BL, thus the state of the memory cell can be identified.

[0064] exist Figure 5A In the middle, when gate electrode 130 is selected and programming voltage V is applied pgm At that time, through programming voltage V pgm Under positive (+) voltage, the metal oxide of the resistive switching layer 143 can be decomposed by an electrochemical reaction. Therefore, oxygen ions can tunnel through the diffusion barrier structure 150 and the electrolyte layer 145, and subsequently diffuse into the ion storage layer 147. This movement (diffusion) of oxygen ions increases the concentration of oxygen ions in the ion storage layer 147 and decreases the concentration of oxygen ions in the resistive switching layer 143, thereby maintaining a state with a large number of oxygen vacancies in the transition metal oxide of the resistive switching layer 143. When oxygen ions accumulate as charge carriers in the ion storage layer 147, data can be considered to be stored (programmed) in the corresponding memory cells.

[0065] When in Figure 5B When performing a read operation, the read voltage V can be... read A positive voltage is applied to the gate electrode 130 of the programmed memory cell.

[0066] Reading voltage V readDuring a read operation applied to the gate electrode 130 of a programmed memory cell, current (indicated by the arrow) can flow from the source structure SS to the channel pad 165, which may be the drain. Therefore, current based on the programmed data can flow to the bit line BL through the channel pad 165, which may be the drain. In this case, the current can flow along the channel layer 140 and then along the resistance switching layer 143, which has lower resistance due to oxygen vacancies in the corresponding memory cell. Therefore, a read operation can include current flowing along the channel layer 140 and the resistance switching layer 143 opposite the gate electrode 130 of the programmed memory cell.

[0067] like Figure 5C As shown, when an erase operation is performed, an erase voltage Vera (negative (-) voltage) can be applied to the gate electrode 130 (word line). The erase voltage Vera allows oxygen ions in the ion storage layer 147 to move (diffuse) towards the channel layer 140 due to repulsive forces, and the oxygen ions can pass through the electrolyte layer 145 and the diffusion barrier structure 150, and can rearrange into oxygen vacancies in the resistor switching layer 143. Therefore, oxygen vacancies can be removed by the acquisition of oxygen ions, and thus the oxygen vacancies in the resistor switching layer 143 can be (significantly) reduced, thereby increasing the resistance value again. This increase in the resistance value of the resistor switching layer 143 allows the current flowing from the source structure SS to the channel pad 165 to continue flowing along the channel layer 140, rather than along the resistor switching layer 143 on the memory cell. Therefore, it can be considered that the oxygen ions accumulated in the ion storage layer 147 are removed to perform the erase operation. In some example embodiments, the current path in the channel structure CH during a read operation may be different from the current path during an erase operation. In other words, it can be understood that the current path can be bypassed during the read operation. Therefore, the resistor switching layer 143 and the channel layer 140 can be used together as a current path, serving as an ion-providing structure.

[0068] Semiconductor device 100 can be defined as an electrochemical random access memory (ECRAM) that stores data via an electrochemical reaction. To ensure that the programmed state is maintained for an extended period, retention efficiency can be ensured in the ECRAM. Diffusion barrier structure 150 may include multiple diffusion barrier layers 156, 154, ..., 152 to reduce and / or prevent the re-diffusion of oxygen ions accumulated in the ion storage layer 147 in the programmed state through the electrolyte layer 145 and diffusion barrier structure 150.

[0069] In the following text, reference will be made to Figures 6A to 17 Describe an example implementation method.

[0070] Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16 and Figure 17 It corresponds to Figure 3A A magnified view of a portion of the image.

[0071] Figure 6B , 7B 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B can be corresponding to Figure 3B The graphs show the characteristics of the diffusion barrier structure 150 in each semiconductor device. Each graph may include the ion diffusion coefficient f(D) and thickness f(t) of each of the diffusion barrier layers 156, 154, ... and 152.

[0072] refer to Figure 6A and Figure 6B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100a can be with Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers 156, 154, ... and 152 sequentially stacked on the channel layer 140 may include different materials. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the example embodiments are not limited thereto.

[0073] The multiple diffusion barrier layers 156, 154, ..., 152 may comprise materials having a smaller ion diffusion coefficient f(D) between the electrolyte layer 145 and the resistance switching layer 143 as the distance from the electrolyte layer 145 increases. For example, they may comprise metal oxides containing the same metal, and the oxygen concentration in the metal oxide may increase as the distance from the resistance switching layer 143 decreases. For example, when hafnium oxide is included, the oxygen concentration in the compound may increase as the distance from the resistance switching layer 143 decreases. Metal oxides with different oxygen concentrations can result in different ion diffusion coefficients f(D) in the diffusion barrier layers 156, 154, ..., 152, thereby further enhancing the blocking of ion diffusion at the interfaces between the diffusion barrier layers 156, 154, ..., 152. Even in this case, the thickness f(t) of the diffusion barrier layers 156, 154, ..., 152 may be the same.

[0074] refer to Figure 7A and Figure 7B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100b can be connected with... Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers 156, 154, ... and 152 sequentially stacked on the channel layer 140 may include different materials. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the example embodiments are not limited thereto.

[0075] The multiple diffusion barrier layers 156, 154, ..., 152 may comprise materials having a larger ion diffusion coefficient f(D) between the electrolyte layer 145 and the resistance switching layer 143 as the distance from the electrolyte layer 145 increases. For example, they may comprise metal oxides containing the same metal, and the oxygen concentration in the metal oxide may decrease as the distance from the resistance switching layer 143 decreases. For example, when hafnium oxide is included, the oxygen concentration in the compound may decrease as the distance from the resistance switching layer 143 decreases. Metal oxides with different oxygen concentrations can result in different ion diffusion coefficients f(D) in the diffusion barrier layers 156, 154, ..., 152, thereby further enhancing the barrier to ion diffusion at the interface between the diffusion barrier layers. Even in this case, the thickness f(t) of the diffusion barrier layers 156, 154, ..., 152 may be the same.

[0076] refer to Figure 8A and Figure 8B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100c can be with Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers 156, 154, ... and 152 sequentially stacked on the channel layer 140 may include different materials. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the exemplary embodiments may not be limited to this.

[0077] Multiple diffusion barrier layers 156, 154, ..., 152 may comprise materials having a smaller ion diffusion coefficient f(D) between the electrolyte layer 145 and the resistance switching layer 143 as the distance from the electrolyte layer 145 and the resistance switching layer 143 increases. For example, they may comprise metal oxides containing the same metal, and the metal oxide of the intermediate diffusion barrier layer may have a higher oxygen concentration. For example, when hafnium oxide is included, the oxygen concentration in the compound may increase with increasing distance from the electrolyte layer 145 and the resistance switching layer 143. Metal oxides with different oxygen concentrations may result in different ion diffusion coefficients f(D) in the diffusion barrier layers 156, 154, ..., 152, thereby further enhancing the blocking of ion diffusion at the interface between the diffusion barrier layers 156, 154, ..., 152. Even in this case, the thickness f(t) of the diffusion barrier layers 156, 154, ..., 152 may be the same.

[0078] refer to Figure 9A and Figure 9B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100d can be with Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers 156, 154, ... and 152 sequentially stacked on the channel layer 140 may include different materials. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the exemplary embodiments may not be limited to this.

[0079] The multiple diffusion barrier layers 156, 154, ..., 152 may comprise materials having a larger ion diffusion coefficient f(D) between the electrolyte layer 145 and the resistance switching layer 143 as the distance from the electrolyte layer 145 and the resistance switching layer 143 increases. For example, they may comprise metal oxides containing the same metal, and the metal oxide of the intermediate diffusion barrier layer may have a lower oxygen concentration. For example, when hafnium oxide is included, the oxygen concentration in the compound may decrease with increasing distance from the electrolyte layer 145 and the resistance switching layer 143. Metal oxides with different oxygen concentrations can result in different ion diffusion coefficients f(D) in the diffusion barrier layers 156, 154, ..., 152, thereby further enhancing the blocking of ion diffusion at the interface between the diffusion barrier layers 156, 154, ..., 152. Even in this case, the thickness f(t) of the diffusion barrier layers 156, 154, ..., 152 may be the same.

[0080] refer to Figure 10A and Figure 10B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100e can be with Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers 156, 154, ... and 152 sequentially stacked on the channel layer 140 may include the same material. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the exemplary embodiments may not be limited to this.

[0081] Multiple diffusion barrier layers 156, 154, ..., 152 may have different thicknesses f(t) between the electrolyte layer 145 and the resistance switching layer 143. The thickness of the multiple diffusion barrier layers 156, 154, ..., 152 may decrease with increasing distance from the electrolyte layer 145. For example... Figure 4 As shown, each of the diffusion barrier layers 156, 154, ... and 152 can have varying electrical conductivity as the thickness changes, thus altering the degree of oxygen ion diffusion and thereby further enhancing the barrier to ion diffusion at the interfaces between the diffusion barrier layers 156, 154, ... and 152.

[0082] refer to Figure 11A and Figure 11B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100f can be with Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers 156, 154, ... and 152 sequentially stacked on the channel layer 140 may include the same material. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the exemplary embodiments may not be limited to this.

[0083] Multiple diffusion barrier layers 156, 154, ..., 152 may have different thicknesses f(t) between the electrolyte layer 145 and the resistance switching layer 143. The multiple diffusion barrier layers 156, 154, ..., 152 may have increasing thicknesses f(t) with increasing distance from the electrolyte layer 145. For example... Figure 4 As shown, each of the diffusion barrier layers 156, 154, ... and 152 can have a varying conductivity as the thickness f(t) changes, thus altering the degree of oxygen ion diffusion and thereby further enhancing the barrier to ion diffusion at the interface between the diffusion barrier layers 156, 154, ... and 152.

[0084] refer to Figure 12A and Figure 12B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100g can be combined with... Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers sequentially stacked on the channel layer 140 may include the same material. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the exemplary embodiments may not be limited to this.

[0085] Multiple diffusion barrier layers 156, 154, ..., 152 may have different thicknesses f(t) between the electrolyte layer 145 and the resistance switching layer 143. As the distance from the electrolyte layer 145 and the resistance switching layer 143 increases, the multiple diffusion barrier layers 156, 154, ..., 152 may have decreasing thicknesses f(t), allowing the intermediate diffusion barrier layer to have an even smaller thickness f(t). When the thickness f(t) varies, each of the diffusion barrier layers 156, 154, ..., 152 may have varying conductivity, thus altering the degree of oxygen ion diffusion and further enhancing the barrier to ion diffusion at the interface between the diffusion barrier layers 156, 154, ..., 152.

[0086] refer to Figure 13A and Figure 13B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100h can be combined with... Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers sequentially stacked on the channel layer 140 may include the same material. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of them, as a transition metal oxide. However, the exemplary embodiments may not be limited to this.

[0087] Multiple diffusion barrier layers 156, 154, ..., 152 may have different thicknesses f(t) between the electrolyte layer 145 and the resistance switching layer 143. As the distance from the electrolyte layer 145 and the resistance switching layer 143 increases, the multiple diffusion barrier layers 156, 154, ..., 152 may have increasing thicknesses f(t), allowing the intermediate diffusion barrier layer to have a larger thickness f(t). When the thickness f(t) varies, each of the diffusion barrier layers 156, 154, ..., 152 may have varying conductivity, thus altering the degree of oxygen ion diffusion and further enhancing the barrier to ion diffusion at the interface between the diffusion barrier layers 156, 154, ..., 152.

[0088] refer to Figure 14A and Figure 14B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100i can be with Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers 156, 154, ... and 152 sequentially stacked on the channel layer 140 may include different materials. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of the following, as a transition metal oxide. However, the example embodiments are not limited to this. The plurality of diffusion barrier layers 156, 154, ... and 152 may include materials having a larger ion diffusion coefficient f(D) between the electrolyte layer 145 and the resistance switching layer 143 as the distance from the electrolyte layer 145 increases. For example, metal oxides comprising the same metal may be included, and the metal oxides configured to be closer to the resistance switching layer 143 may have a lower oxygen concentration. For example, when hafnium oxide is included, the oxygen concentration in the compound may decrease as the distance from the electrolyte layer 145 increases. Metal oxides with different oxygen concentrations may result in different ion diffusion coefficients f(D) in the diffusion barrier layers 156, 154, ... and 152, thereby further enhancing the blocking of ion diffusion at the interface between the diffusion barrier layers 156, 154, ... and 152.

[0089] Multiple diffusion barrier layers 156, 154, ..., 152 may have different thicknesses f(t) between the electrolyte layer 145 and the resistance switching layer 143. The thickness f(t) of the multiple diffusion barrier layers 156, 154, ..., 152 may decrease as the distance from the electrolyte layer 145 increases. As the thickness f(t) varies, each of the diffusion barrier layers 156, 154, ..., 152 may have a varying conductivity, thus altering the degree of oxygen ion diffusion and further enhancing the barrier to ion diffusion at the interface between the diffusion barrier layers 156, 154, ..., 152.

[0090] As described, the thickness f(t) and ion diffusion coefficient f(D) of the multiple diffusion barrier layers 156, 154, ... and 152 forming the stacked structure can both be controlled, thereby achieving improved diffusion prevention efficiency.

[0091] refer to Figure 15A and Figure 15B In addition to the diffusion barrier structure 150 of the channel structure CH, the semiconductor device 100j can be with Figures 1A to 3A The semiconductor device is the same. Specifically, the diffusion barrier structure 150 may include a plurality of diffusion barrier layers 156, 154, ... and 152, and the plurality of diffusion barrier layers sequentially stacked on the channel layer 140 may include different materials. Each of the plurality of diffusion barrier layers 156, 154, ... and 152 may include a metal oxide and may include WO3. x HfO y and AlO x At least one of the following, as a transition metal oxide. However, the example embodiments are not limited to this. The plurality of diffusion barrier layers 156, 154, ... and 152 may include materials having a smaller ion diffusion coefficient f(D) between the electrolyte layer 145 and the resistance switching layer 143 as the distance from the electrolyte layer 145 increases. For example, metal oxides comprising the same metal may be included, and the metal oxide configured to be closer to the diffusion barrier layer 152 of the resistance switching layer 143 may have a higher oxygen concentration. For example, when hafnium oxide is included, the oxygen concentration in the compound may increase with increasing distance from the electrolyte layer 145. Metal oxides with different oxygen concentrations may result in different ion diffusion coefficients f(D) in the diffusion barrier layers 156, 154, ... and 152, thereby further enhancing the blocking of ion diffusion at the interface between the diffusion barrier layers 156, 154, ... and 152.

[0092] Multiple diffusion barrier layers 156, 154, ..., 152 may have different thicknesses f(t) between the electrolyte layer 145 and the resistance switching layer 143. The multiple diffusion barrier layers 156, 154, ..., 152 may have increasing thicknesses f(t) with increasing distance from the electrolyte layer 145. As the thickness f(t) varies, each of the diffusion barrier layers 156, 154, ..., 152 may have varying conductivity, thus altering the degree of oxygen ion diffusion and further enhancing the barrier to ion diffusion at the interface between the diffusion barrier layers 156, 154, ..., 152.

[0093] As described, both the thickness f(t) and the ion diffusion coefficient f(D) of the multiple diffusion barrier layers 156, 154, ... and 152 forming the stacked structure can be controlled, thereby achieving improved diffusion prevention efficiency.

[0094] refer to Figure 16 In addition to the resistive switching layer 143 of the channel structure CH, the semiconductor device 100k can be connected with... Figures 1A to 3A The semiconductor device is the same. Specifically, the channel structure CH may include a diffusion barrier structure 150 surrounding the outer and bottom surfaces of the channel layer 140 without a resistance switching layer 143. In this case, the channel layer 140 may include a metal oxide-based semiconductor instead of a silicon-based material. Therefore, oxygen ions in the channel layer itself can be ionized and diffused into the ion storage layer through an electrochemical reaction. Since there is no resistance switching layer, the resistance value of the channel layer may decrease due to the desorption of oxygen ions from the channel layer itself, thereby changing the threshold voltage.

[0095] refer to Figure 17 In addition to the tunneling layers 161 and 163 of the channel structure CH, the semiconductor device 100l can be connected with... Figures 1A to 3A The semiconductor device is the same. Specifically, the channel structure may further include multiple tunneling layers 161 and 163.

[0096] The first tunneling layer 161 can be disposed between the gate electrode 130 and the ion storage layer 147.

[0097] The second tunneling layer 163 can be disposed between the trench layer 140 and the resistance switching layer 143.

[0098] The first tunneling layer 161 and the second tunneling layer 163 may have a thickness less than the first thickness t1 of the channel layer 140, and may have a thickness through which oxygen ions can easily tunnel. The first tunneling layer 161 and the second tunneling layer 163 may comprise silicon oxide (SiO2), silicon nitride (Si3N4), silicon nitride oxide (SiON), or a combination thereof.

[0099] The following describes a method for manufacturing a semiconductor device according to some example embodiments.

[0100] Figure 18 It shows the manufacturing process. Figures 1A to 3B The flowchart illustrates the method for using a semiconductor device.

[0101] refer to Figure 18 The first mode structure and the second mode structure can be formed by alternately stacking the sacrificial insulating layer and the interlayer insulating layer 120 (S100). Specifically, a first horizontal sacrificial layer and a second horizontal conductive layer can be formed on the semiconductor substrate 101 first, then a vertical sacrificial layer can be formed through the first mode structure, and the second mode structure can be formed.

[0102] The sacrificial insulating layer can be achieved through subsequent processes using gate electrode 130 (see...). Figure 3A The sacrificial insulating layer can be formed of a material different from that of the interlayer insulating layer 120, and can be formed of a material that can be etched selectively relative to the interlayer insulating layer 120 under specific etch conditions. For example, the interlayer insulating layer 120 can be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer can be formed of a material different from that of the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. However, the exemplary embodiments are not limited to this.

[0103] Vertical sacrificial layers can be formed in the corresponding Figure 3A In the region of the first channel structure CH1. The vertical sacrificial layer can be formed by forming a lower channel hole through the first structure, then depositing the material included in the vertical sacrificial layer in the lower channel hole and performing a planarization process.

[0104] Subsequently, a channel hole can be formed through the first and second mode structures (S110), and an ion storage layer 147 and an electrolyte layer 145 can be formed in the channel hole (S120).

[0105] A channel hole can be formed by anisotropically etching the first mode structure and the second mode structure using a mask layer. The channel hole can be formed to recess a portion of the semiconductor substrate 101.

[0106] The ion storage layer 147 and the electrolyte layer 145 can be formed by sequentially depositing the ion storage layer 147 and the electrolyte layer 145 in the channel holes. The ion storage layer 147 and the electrolyte layer 145 can be formed to have a uniform (or substantially uniform) thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.

[0107] Subsequently, a diffusion barrier structure 150 (S130) can be formed on the electrolyte layer 145.

[0108] Each of the diffusion barrier layers 156, 154, ... and 152 can be formed by performing an ALD or CVD process simultaneously with oxygen and metal particles having a concentration that satisfies a controlled thickness and ion diffusion coefficient relative to each of the plurality of diffusion barrier layers 156, 154, ... and 152.

[0109] As described, each of the diffusion barrier layers 156, 154, ... and 152 can be formed by a deposition process, thereby creating an interface between the diffusion barrier layers 156, 154, ... and 152.

[0110] Subsequently, a resistance switching layer 143 and a channel layer 140 can be formed on the diffusion barrier structure 150 (S140). The resistance switching layer 143 can be formed by performing an ALD or CVD process to form a metal oxide with a desired (and / or alternatively, predetermined) thickness. The channel layer 140 can be formed on the resistance switching layer 143. The channel layer 140 can be formed by depositing a metal oxide semiconductor or by depositing a silicon semiconductor.

[0111] Subsequently, this can be achieved by forming an insulating pillar with a buried insulating layer 160 at the center of the channel hole in the channel layer 140 and forming a channel pad 165 on its upper part. Figure 3A The channel structure is described in S150. A channel pad 165 can be formed by depositing a conductive material on the channel layer 140 while filling the space on the buried insulating layer 160 at the upper end of the channel hole. The channel pad 165 can be formed of a conductive material and can have a different crystallinity than that of the channel layer 140. For example, the channel pad can be formed of polysilicon. Subsequently, a chemical mechanical polishing (CMP) process can be performed from the polysilicon until the upper surface of the uppermost interlayer insulating layer 121 is exposed.

[0112] Subsequently, an opening can be formed through the first and second mode structures, a first horizontal conductive layer 102 can be formed, and then a tunnel portion can be formed by removing the sacrificial insulating layer (S160). A sacrificial spacer layer can be formed in the opening, an etch-back process can be performed to expose the horizontal sacrificial layer, and the horizontal sacrificial layer can be removed from the exposed area. The first horizontal conductive layer 102 can be formed by depositing conductive material in the area from which the horizontal sacrificial layer has been removed, and then the sacrificial spacer layer can be removed from the opening. Through this process, a source structure SS including a semiconductor substrate 101 and the first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be formed.

[0113] The sacrificial insulating layer can be selectively removed relative to the interlayer insulating layer 120, for example, using wet etching. Therefore, multiple channel portions can be formed between the interlayer insulating layers 120. The gate electrode 130 can be formed by filling the channel portions with a conductive material, and an isolation region MS can be formed by filling the openings. Then, an upper interconnect structure including contact plugs 170 can be formed to create... Figure 3A Semiconductor devices.

[0114] Figure 19 This is a schematic diagram illustrating a data storage system including semiconductor devices according to some example embodiments.

[0115] refer to Figure 19 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including a single semiconductor device 1100 or multiple semiconductor devices 1100, or an electronic device including such a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including a single semiconductor device 1100 or multiple semiconductor devices 1100.

[0116] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, the above-mentioned reference. Figures 1A to 17 The ECRAM memory device described herein. Semiconductor device 1100 may include a first semiconductor structure 1100F and a second semiconductor structure 1100S on the first semiconductor structure 1100F. In some example embodiments, the first semiconductor structure 1100F may be disposed adjacent to the second semiconductor structure 1100S. The first semiconductor structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second semiconductor structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0117] In the second semiconductor structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In some example embodiments, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified in various ways.

[0118] In some example implementations, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of a memory cell transistor MCT, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0119] In some example implementations, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used for an erase operation to erase data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0120] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the interior of the first semiconductor structure 1100F to the second semiconductor structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the interior of the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0121] In the first semiconductor structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the interior of the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0122] The controller 1200 may include a processor 1210, an ECRAM controller 1220, and a host interface 1230. In some example embodiments, the data storage system 1000 may include multiple semiconductor devices 1100. In this case, the controller 1200 may control the multiple semiconductor devices 1100.

[0123] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to desired (and / or alternatively, predetermined) firmware and can access semiconductor device 1100 by controlling ECRAM controller 1220. ECRAM controller 1220 may include controller interface 1221 for handling communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted via controller interface 1221. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0124] Figure 20 This is a schematic perspective view of a data storage system including semiconductor devices according to some example embodiments.

[0125] refer to Figure 20 A data storage system 2000 according to some example embodiments of the present disclosure may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the main substrate 2001.

[0126] The main substrate 2001 may include a connector 2006, which includes multiple pins for connection to an external host. The number and arrangement of the multiple pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some example embodiments, the data storage system 2000 may communicate with the external host via one of the following interfaces: Universal Flash Memory (UFS), PCI-Express, Serial Advanced Technology Attachment (SATA), M-Phy for Universal Serial Bus (USB), etc. However, the example embodiments are not limited to this. In some example embodiments, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0127] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0128] DRAM 2004 can be a buffer memory used to mitigate the speed difference between semiconductor package 2003 (data storage space) and an external host. DRAM 2004 included in data storage system 2000 can also operate as a type of cache memory and can provide space for temporary data storage during control operations on semiconductor package 2003. When DRAM 2004 is included in data storage system 2000, controller 2002 may further include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0129] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 to each other, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0130] The package substrate 2100 may be a printed circuit board including a package top pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to... Figure 19 The input / output pads 1101. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include the above-referenced... Figures 1A to 17 The semiconductor device described.

[0131] In some example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 and the package top pads 2130 to each other. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and may be electrically connected to the package top pads 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including a through-silicon via (TSV) instead of the connection structure 2400 using a bonding wire method.

[0132] In some example implementations, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example implementations, the controller 2002 and the semiconductor chip 2200 (e.g., the bottommost 2200) may be mounted on an interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via interconnects formed on the interposer substrate.

[0133] According to some example implementations, the threshold voltage of the memory cell can be changed when desorbing or acquiring ions, and thus the semiconductor device can store or read data, allowing the semiconductor device to operate with a low gate voltage.

[0134] In this configuration, multiple diffusion barrier layers can be formed to (significantly) limit and / or prevent ion diffusion between the diffusion barrier layers, thereby reducing and / or preventing data loss due to ion re-diffusion. Therefore, the memory device can have improved retention characteristics without significant data loss.

[0135] One or more of the elements disclosed above may include or be implemented in processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0136] While some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

[0137] This application claims priority to Korean Patent Application No. 10-2024-0192843, filed on December 20, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Substrate; A stacked structure including gate electrodes spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; as well as A channel structure, within channel holes and extending through the stacked structure in the vertical direction. The channel structure includes: The channel layer is located on the sidewall of the channel opening. A resistance switching layer, located between the sidewall of the channel aperture and the channel layer, is configured to alter conductivity based on electrochemical reactions involving the loss or gain of oxygen ions. A diffusion barrier structure is located between the sidewall of the channel aperture and the resistance switching layer. An electrolyte layer, located between the sidewall of the channel orifice and the diffusion barrier structure, and An ion storage layer, located between the sidewall of the channel aperture and the electrolyte layer, and The diffusion barrier structure comprises at least two diffusion barrier layers sequentially stacked in the direction from the resistance switching layer toward the electrolyte layer.

2. The semiconductor device according to claim 1, wherein, The diffusion barrier structure has a set thickness and a set ion diffusion coefficient for each of the at least two diffusion barrier layers, and is configured to reduce the re-diffusion of oxygen ions from the ion storage layer.

3. The semiconductor device according to claim 2, wherein, The at least two diffusion barrier layers have the same thickness.

4. The semiconductor device according to claim 3, wherein, The ion diffusion coefficients of each of the at least two diffusion barrier layers are different from each other.

5. The semiconductor device according to claim 3, wherein, Each of the at least two diffusion barrier layers comprises a metal oxide. The at least two diffusion barrier layers comprise the same metallic material, and The at least two diffusion barrier layers comprise oxygen of different concentrations.

6. The semiconductor device according to claim 2, wherein, The at least two diffusion barrier layers have the same ion diffusion coefficient, and The thickness of each of the at least two diffusion barrier layers is different.

7. The semiconductor device according to claim 6, wherein, The thickness of each of the at least two diffusion barrier layers increases from the electrolyte layer to the resistance switching layer.

8. The semiconductor device according to claim 2, wherein, The at least two diffusion barrier layers have different ion diffusion coefficients and different thicknesses.

9. The semiconductor device according to claim 2, wherein, The at least two diffusion barrier layers have the same ion diffusion coefficient and the same thickness.

10. The semiconductor device according to claim 1, wherein, The thickness of the diffusion barrier structure is less than the thickness of the channel layer.

11. The semiconductor device according to claim 1, wherein, The channel structure further includes: An insulating post is located at the center of the channel hole. A first tunneling layer, between the stacked structure and the ion storage layer, and The second tunneling layer is located between the trench layer and the resistance switching layer.

12. The semiconductor device according to claim 1, wherein, The channel layer comprises silicon. The resistance switching layer comprises tungsten oxide. The diffusion barrier structure includes hafnium oxide. The electrolyte layer comprises tantalum oxide, and The ion storage layer comprises tungsten oxide.

13. The semiconductor device according to claim 12, wherein, The oxygen concentration in the resistance switching layer is lower than that in the ion storage layer.

14. A semiconductor device, comprising: Substrate; A stacked structure including gate electrodes spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; as well as A channel structure, within channel holes and extending through the stacked structure in the vertical direction. The channel structure includes: An insulating post with a circular cross-section is located at the center of the channel hole. An ion-providing structure surrounds the outer surface of the insulating pillar, the ion-providing structure comprising a first metal oxide, and the ion-providing structure being configured to alter conductivity based on an electrochemical reaction involving the loss or gain of oxygen ions. A diffusion-blocking structure, providing an outer surface around the ions, the diffusion-blocking structure comprising a second metal oxide. An electrolyte layer, surrounding the outer surface of the diffusion barrier structure, the electrolyte layer comprising a third metal oxide, and An ion storage layer, surrounding the outer surface of the electrolyte layer, the ion storage layer comprising a fourth metal oxide, and The diffusion barrier structure includes at least two diffusion barrier layers sequentially stacked between the ion providing structure and the electrolyte layer, the diffusion barrier structure being configured to reduce the re-diffusion of the oxygen ions from the ion storage layer.

15. The semiconductor device according to claim 14, wherein, The thickness of the diffusion barrier structure is less than the thickness of the electrolyte layer.

16. The semiconductor device according to claim 15, wherein, The at least two diffusion barrier layers of the diffusion barrier structure have the same thickness and different ion diffusion coefficients.

17. The semiconductor device according to claim 15, wherein, The at least two diffusion barrier layers of the diffusion barrier structure comprise the same metallic material and contain different concentrations of oxygen.

18. The semiconductor device according to claim 15, wherein, The ions provide a structure including tungsten oxide. The diffusion barrier structure includes hafnium oxide. The electrolyte layer comprises tantalum oxide, and The ion storage layer comprises tungsten oxide.

19. A data storage system, comprising: A semiconductor device includes a channel structure in a channel hole and extending through a gate electrode stacked on a substrate; as well as A controller, electrically connected to the semiconductor device, is configured to control the semiconductor device. The channel structure includes: An insulating post with a circular cross-section is located at the center of the channel hole. An ion-providing structure, surrounding the outer surface of the insulating pillar, comprises a first metal oxide and is configured to alter conductivity based on an electrochemical reaction involving the loss or gain of oxygen ions. A diffusion-blocking structure, providing an outer surface around the ions, the diffusion-blocking structure comprising a second metal oxide. An electrolyte layer, surrounding the outer surface of the diffusion barrier structure, the electrolyte layer comprising a third metal oxide, and An ion storage layer, surrounding the outer surface of the electrolyte layer, comprising a fourth metal oxide. The diffusion barrier structure includes at least two diffusion barrier layers sequentially stacked between the ion providing structure and the electrolyte layer, the diffusion barrier structure being configured to reduce the re-diffusion of the oxygen ions from the ion storage layer.

20. The data storage system according to claim 19, wherein, The ion provides a structure including: A channel layer surrounding the insulating pillar, the channel layer comprising silicon, and A resistance switching layer surrounds the outer surface of the channel layer, the resistance switching layer comprising the first metal oxide. The oxygen ions in the resistive switching layer are configured to be lost or gained in response to the voltage of each of the gate electrodes.

Images