Buried nanogated ferroelectric 3D NAND structure and method of making the same

Abstract

The application relates to a buried nanometer grid ferroelectric 3D NAND structure and a preparation method thereof, and belongs to the memory device field.The buried nanometer grid ferroelectric 3D NAND structure comprises a substrate, a stack structure is arranged on the substrate, the stack structure comprises a plurality of first insulating medium layers and FeFET storage structures which are alternately stacked, a plurality of through holes are arranged through the stack structure, a first gate medium layer and a center channel layer are sequentially arranged on the side wall of each through hole, and a center insulating medium layer is filled in the center channel layer; the FeFET storage structure comprises a nanometer grid layer, the outer side of the nanometer grid layer is embedded into a gate word line metal, the FeFET storage structure is vertically arranged with the first gate medium layer of the channel side wall, a metal layer and a ferroelectric material layer are sequentially arranged in the direction from the first gate medium layer to the outside of the through hole, and the nanometer grid layer is in contact with the ferroelectric material layer. The application guarantees long-term stable storage of information and realizes low-power-consumption and high-density storage.

Description

Technical Field

[0001] This invention relates to the field of storage devices, and more particularly to an embedded nanogate ferroelectric 3D NAND structure and its fabrication method. Background Technology

[0002] With the rapid development of mobile terminals, artificial intelligence, and big data applications, more stringent requirements have been placed on the storage density and power consumption of memory chips. Traditional planar ferroelectric memories (FeFETs) are limited by their cell structure and face fundamental bottlenecks when integrating them towards higher density and lower power consumption, making it difficult to meet the needs of future high-capacity storage applications.

[0003] Currently, the industry is exploring high-density, low-power ferroelectric memory solutions mainly through two technical paths: One approach involves the miniaturization of planar FeFETs. This method continues the traditional CMOS process, aiming to reduce the feature size of cells through advancements in photolithography to improve integration density. However, as cell sizes enter the nanoscale, the dual constraints of physical limitations and economic efficiency become increasingly prominent. Short-channel effects lead to increased leakage current and threshold voltage drift, severely impacting device reliability. More critically, the area of ​​the storage capacitor in a planar structure directly determines the data retention capability. To maintain sufficient charge storage, the cell area cannot be reduced proportionally, resulting in extremely limited improvements in storage density and failing to overcome the bottleneck of two-dimensional planar miniaturization.

[0004] Secondly, there is the introduction of a vertically stacked three-dimensional architecture. Drawing on the successful experience of 3D NAND flash memory, the industry has attempted to integrate FeFET cells into a three-dimensional structure of vertical channels or vertical gates, aiming to achieve higher storage density per unit area through multi-layer stacking. However, this approach faces severe process and physical challenges in practical applications. Electrically, since the coercive field strength of ferroelectric materials is an intrinsic property, achieving reliable polarization reversal of the ferroelectric material layer within a high aspect ratio vertical channel requires ensuring high uniformity in ferroelectric film thickness, interface quality, and electric field distribution. This makes it difficult to effectively reduce the actual operating voltage, hindering the realization of low-power characteristics. In terms of process, depositing uniformly thick, high-quality ferroelectric films within high aspect ratio channel holes or trenches presents significant technical difficulties. Traditional atomic layer deposition processes still have unsatisfactory control over film consistency at the bottom and sidewalls of deep holes. Process deviations easily lead to dispersion in ferroelectric performance, manifesting as a smaller storage window, reduced durability, and decreased retention characteristics. This makes achieving high-density and low-power three-dimensional ferroelectric memories a major technical and cost hurdle.

[0005] Therefore, developing a device structure and fabrication method that can fundamentally resolve the contradiction between three-dimensional integration and low-voltage operation has become an urgent need to realize the next generation of high-density, ultra-low-power storage technology. Summary of the Invention

[0006] The present invention aims to provide an embedded nano-gate ferroelectric 3D NAND structure and its preparation method to overcome the shortcomings of the prior art. The technical problem to be solved by the present invention is achieved through the following technical solution.

[0007] According to a first aspect of this application, a buried nano-gate ferroelectric 3D NAND structure is provided. Includes a substrate, A stacked structure is disposed on the substrate, the stacked structure comprising a plurality of first insulating dielectric layers and a FeFET memory structure stacked in an alternating manner; A plurality of through holes are provided through the stacked structure, and a first gate dielectric layer and a central channel layer are sequentially provided on the sidewall of each through hole, and a central insulating dielectric layer is filled in the central channel layer; The FeFET memory structure includes a nanogate layer, the outer side of which is embedded in the gate line metal. The FeFET memory structure is perpendicular to the first gate dielectric layer of the channel sidewall. A metal layer and a ferroelectric material layer are sequentially disposed along the first gate dielectric layer toward the outside of the via. The nanogate layer is in contact with the ferroelectric material layer. A second insulating dielectric layer is disposed between the gate line metal and the ferroelectric material layer.

[0008] Preferably, the nanogrid layer is selected from graphene, ALD metal layer or composite layer of graphene and ALD metal, and has a thickness of 1-5 nanometers. Preferably, the ferroelectric material layer is selected from HfO2-based materials or perovskite-type materials.

[0009] Preferably, the gate line metal interconnect is made of tungsten, titanium, titanium nitride, polycrystalline silicon, or an alloy of the above materials.

[0010] According to a second aspect of this application, a method for fabricating the above-mentioned embedded nano-gate ferroelectric 3D NAND structure is provided, comprising the following steps: Step 1: After depositing a sacrificial layer on the substrate, several periodic stacked structures are vertically deposited. The periodic stacked structures include, from bottom to top, a second insulating dielectric layer, a nanogate layer, a second insulating dielectric layer, and a sacrificial layer. Step 2: Etch through-holes, which penetrate the plurality of periodic stacked structures and the bottommost sacrificial layer; Step 3: After depositing a ferroelectric material layer and a metal layer sequentially on the sidewall of the through hole, the through hole is filled with an insulating medium; Step 4: After removing the sacrificial layer to form the first cavity using a selective etching process, selectively etch the ferroelectric material layer and the metal layer in the first cavity to form a separate memory cell; Step 5: Fill the first cavity with the first insulating dielectric layer and perform planarization treatment; Step 6: Using a selective etching process, the nanogate layer and the second insulating dielectric layer are etched back, with the etching stopping at a distance of 10-1000 nanometers from the ferroelectric material layer to form a second cavity; Step 7: The second insulating dielectric layer in the second cavity is etched back using a selective etching process, with the etching stopping at a distance of 5-500 nanometers from the ferroelectric material layer; Step 8: Deposit the grid line metal in the second cavity and perform planarization; Step 9: After selectively removing the insulating medium inside the via, the first gate dielectric layer and the central channel layer are sequentially deposited inside the via, and the central insulating dielectric layer is filled. After planarization, the fabrication of the nano-gate ferroelectric NAND flash memory is completed.

[0011] Preferably, the material of the first insulating dielectric layer is different from the material of the second insulating dielectric layer.

[0012] Preferably, in step 2, the via pattern is defined by photolithography, and then a high aspect ratio via is formed by reactive ion etching based on Cl2 / HBr gas.

[0013] Preferably, in step 3, atomic layer deposition, chemical vapor deposition, magnetron sputtering, or sol-gel method are used to deposit the ferroelectric material layer in a conformal manner.

[0014] Preferably, in step 3, tungsten or titanium nitride is deposited as a barrier layer using chemical vapor deposition or atomic layer deposition, and the metal layer is prepared by combining it with electrochemical copper plating technology; or a titanium or cobalt metal layer is prepared using physical vapor deposition technology.

[0015] Preferably, in step 9, after selectively removing the insulating medium in the through-hole using hot phosphoric acid at 180°C, the first gate dielectric layer is prepared by atomic layer deposition or chemical vapor deposition; the central channel layer is grown by chemical vapor deposition, epitaxial growth, physical vapor deposition or spin coating; and the central insulating dielectric layer is filled by chemical vapor deposition, plasma-enhanced chemical vapor deposition, spin coating or atomic layer deposition.

[0016] According to one embodiment of this application, the beneficial effects of using this ultra-low power buried nano-gate ferroelectric memory structure and its fabrication method are as follows: First, this application significantly reduces the operating voltage and power consumption of ferroelectric field-effect transistors. By introducing a nanogate structure and its electric field focusing effect, the gate electrode size is reduced to the nanometer scale, creating a highly localized strong electric field focusing region in the ferroelectric material layer, effectively amplifying the local electric field intensity. This design breaks through the coercive voltage limit of conventional planar ferroelectrics, enabling efficient polarization switching of ferroelectric materials in a three-dimensional stacked architecture. Only a very small voltage is required to drive ferroelectric domain switching, thereby significantly reducing the voltage and dynamic power consumption required for programming operations.

[0017] Secondly, this application effectively improves gate control efficiency and memory cell isolation performance. By redesigning the traditional word line stacking cycle and integrating nanometer gate control cells, the gate's control over channel charge is significantly enhanced. While achieving ultra-low voltage drive, this structure effectively suppresses electrical crosstalk between adjacent memory cells in vertical stacking, ensuring the accuracy and reliability of data read and write processes.

[0018] Third, this application provides a technological foundation for achieving reliable operation of devices at ultra-low voltages. By developing a highly consistent three-dimensional integration process, combined with high-precision atomic layer deposition, anisotropic etching technology, and a sacrificial layer and multi-step selective filling scheme, the excellent uniformity, consistency, and interface stability of the nanogate structure and ferroelectric functional layer in three-dimensional space are ensured, providing a strong guarantee for the stable performance of the device.

[0019] Finally, this application overcomes the bottlenecks of existing storage technologies in three major dimensions: voltage, power consumption, and storage density. The constructed ultra-low power, high-density three-dimensional ferroelectric memory is particularly suitable for energy-sensitive applications such as artificial intelligence edge computing, IoT terminals, and wearable devices, and strongly promotes the industrialization of next-generation low-power, high-performance storage technologies. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the embedded nano-gate ferroelectric 3D NAND structure in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure after the deposition of the layered structure in step 1 of embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure after etching the through-hole in step 2; Figure 4 This is a schematic diagram of the structure after the ferroelectric material layer is deposited in step 3; Figure 5 This is a schematic diagram of the structure after the metal layer is deposited in step 4; Figure 6 This is a schematic diagram of the structure after the insulating medium is filled into the through hole in step 5; Figure 7This is a schematic diagram of the structure after the sacrificial layer is etched back in step 6; Figure 8 This is a schematic diagram of the structure after selectively etching the ferroelectric material layer and the metal layer in step 7; Figure 9 This is a schematic diagram of the structure after the insulating medium is filled and planarized in step 8; Figure 10 This is a schematic diagram of the structure after etching back the second insulating dielectric layer and the nanogate layer in step 9; Figure 11 This is a schematic diagram of the structure after selectively etching back the second insulating dielectric layer in step 10; Figure 12 This is a schematic diagram of the structure after filling the grid lines with metal in step 11; Figure 13 This is a schematic diagram of the structure after removing the insulating medium filling the through hole in step 12; Figure 14 This is a schematic diagram of the structure after the first gate dielectric layer is grown in step 13; Figure 15 This is a schematic diagram of the structure after the growth center channel layer in step 14; Figure 16 This is a schematic diagram of the structure after the growth center insulating dielectric layer in step 15; Figure 17 a is a schematic diagram showing the effect of applying a 2V programming voltage to the conventional gate on the device's memory window; Figure 17 b is a schematic diagram illustrating the effect of applying a 1.2V programming voltage to a 1nm gate on the device's memory window. Detailed Implementation

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] Example 1

[0024] like Figure 1 As shown, the buried nanogate ferroelectric 3D NAND structure in this embodiment includes a substrate 100, on which a stacked structure is disposed, and on the stacked structure include a plurality of first insulating dielectric layers 111 and a FeFET memory structure stacked in an alternating manner. A plurality of through holes 130 penetrate the stacked structure, and a first gate dielectric layer 223 and a central channel layer 224 are sequentially disposed on the sidewall of each through hole 130, and a central insulating dielectric layer 225 is filled in the central channel layer 224. The FeFET memory structure includes a nanogate layer 212, the outer side of which is embedded in the gate line metal 211. The FeFET memory structure is perpendicular to the first gate dielectric layer 223 of the channel sidewall. A metal layer 222 and a ferroelectric material layer 221 are sequentially disposed along the first gate dielectric layer 223 toward the outside of the via 130. The nanogate layer 212 is in contact with the ferroelectric material layer 221. A second insulating dielectric layer 126 is disposed between the gate line metal 211 and the ferroelectric material layer 221.

[0025] In this embodiment, the substrate 100 may be a single-crystal silicon substrate 100, a silicon-on-insulator (SOI) substrate 100, a silicon-germanium (SiGe) substrate 100, or a compound semiconductor substrate 100 (such as GaAs or InP), used to provide mechanical support and serve as an electrical reference for the bottom layer of the device; its surface flatness, lattice integrity, and thermal stability must meet the requirements of subsequent high-precision thin film deposition and etching processes; in this application, the substrate 100 undertakes the functions of substrate support, heat sink heat dissipation, and bottom electrode lead-out, and forms a physical and electrical isolation interface with the first insulating dielectric layer 111 to prevent leakage current from spreading to the substrate 100 body.

[0026] In this embodiment, the first insulating dielectric layer 111 can be any one of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), phosphorus-doped glass (PSG), boron-doped glass (BSG), or a low dielectric constant medium (such as SiCOH, porous SiO2) or a composite stack thereof; its thickness is in the range of 20–40 nm; the first insulating dielectric layer 111 is located on the substrate 100 and together with the subsequent stacked structure forms a vertical interlayer isolation base; its material selection needs to take into account the etching selectivity ratio with the substrate 100 and the sacrificial layer 121 above, so as to achieve selective removal in subsequent steps; in this application, the composition of the first insulating dielectric layer 111 and the second insulating dielectric layer 126 have distinguishable etching characteristics.

[0027] The nano-gate layer 212 can be graphene, an ALD metal layer (such as TiN, TaN, W), or a composite layer of graphene and ALD metal, with a thickness of 1–5 nm. The nano-gate layer 212 is directly located between the second insulating dielectric layer 125 and the gate line metal 211, and is in physical contact with the ferroelectric material layer 221. Its nanoscale thickness and high aspect ratio structure can generate a significant electric field enhancement effect at the tip / edge when a gate voltage is applied, so that the local electric field intensity can reach several times that of the macroscopic electric field, thereby triggering polarization reversal under conditions far below the intrinsic coercive field of the ferroelectric material. In this application, the nano-gate layer 212 is the core physical carrier for realizing ultra-low voltage operation. Its material selection needs to take into account work function matching (to control the threshold voltage), etching process compatibility, and thermal stability (to withstand subsequent high-temperature processes). For example, graphene has atomic-level thickness and excellent carrier mobility, while the ALD metal layer has good step coverage and conductivity. The combination of the two can take into account both electrical performance and structural robustness.

[0028] The gate word line metal 211 can be tungsten (W), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or an alloy thereof. This gate word line metal 211 is located above the nanogate layer 212 and serves as the input port for the word line potential. It is isolated from the ferroelectric material layer 221 by a second insulating dielectric layer 126 to prevent the word line voltage from being directly applied to the ferroelectric material layer, causing breakdown or irreversible degradation. In this application, the gate word line metal 211 and the nanogate layer 212 constitute a two-stage driving structure of word line-nanogate. The word line voltage is focused by the nanogate layer 212 and then applied to the ferroelectric material layer 221, achieving both voltage reduction and electric field enhancement. Its resistivity and linewidth must meet the 3D NAND word line RC delay requirements to ensure high-speed read / write response.

[0029] The central channel layer 224 can be any one or a combination of polycrystalline silicon, monocrystalline silicon, IGZO, SiGe, MoS2, WSe2, WS2, and MoSe2; it can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxial growth, physical vapor deposition (PVD), or spin coating; the central channel layer 224 covers the inner side of the first gate dielectric layer 223, forming a vertical carrier transport trunk; its conductivity type, doping concentration, and lattice quality determine the on-state current and subthreshold swing of the device; in this application, the central channel layer 224, the first gate dielectric layer 223, and the central insulating dielectric layer 225 form a coaxial channel structure, which is surrounded by the first gate dielectric layer 223, thereby achieving full circumferential electric field modulation under the action of gate voltage, improving gate control efficiency and suppressing short-channel effects.

[0030] The central insulating dielectric layer 225 can be any one of SiO2, SiON, SiONH, SiCN, HfO2, Al2O3, ZrO2, HfZrO, TiO2, SiCOH, high-k dielectric, spin-coated glass, or spin-coated carbon. It is filled into the cavity inside the central channel layer 224 by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or spin coating, and its surface is planarized by chemical mechanical polishing (CMP). The central insulating dielectric layer 225 is used to isolate the central channel layer 224 from other conductive structures in the via 130, preventing leakage and parasitic capacitance formation. Its conformal and compact filling properties directly affect the reliability and yield of the device. In this application, the central insulating dielectric layer 225, the first gate dielectric layer 223, and the central channel layer 224 together form a three-layer coaxial structure of insulation-dielectric-channel, providing electrostatic shielding for the channel and enhancing anti-interference capability.

[0031] The metal layer 222 can be any one or a combination of tungsten (W), titanium (Ti), titanium nitride (TiN), cobalt (Co) or copper (Cu). The metal layer 222 extends outward along the first gate dielectric layer 223 and is located inside the ferroelectric material layer 221, forming a tight interface with the ferroelectric material layer 221. Its function is to: capture and temporarily store the charge generated by channel injection or tunneling in the programming state, forming an additional potential to help maintain the ferroelectric polarization state; and in the reading state, the stored charge shifts the channel threshold voltage, enhancing the storage window. In this application, the metal layer 222 and the ferroelectric material layer 221 constitute a dual storage mechanism, which can improve the data retention time and reduce the risk of fatigue failure of a single ferroelectric material layer, thereby enhancing the device durability. Its thickness is in the range of 5–20 nm.

[0032] The ferroelectric material layer 221 can be an HfO2-based material (such as HfZrO2, HfSiO, HfAlO) or a perovskite-type material (such as PZT, BTO, SBT). The ferroelectric material layer 221 is disposed outside the metal layer 222 and is in direct contact with the nanogate layer 212. Its polarization direction is controlled by the local electric field applied by the nanogate layer 212. The positive electric field drives upward polarization, and the reverse electric field drives downward polarization. The material needs to have good fatigue characteristics, retention characteristics, and interfacial thermodynamic stability with the metal layer 222 and the nanogate layer 212. In this application, the ferroelectric material layer 221 is the physical carrier of information storage. Its residual polarization intensity (Pr) and coercive voltage (Vc) jointly determine the storage window and the lower limit of the operating voltage. HfO2-based materials are an optional system because they are highly compatible with CMOS processes, have controllable film thickness (<10 nm), and have excellent polarization reversibility.

[0033] This embodiment introduces a three-dimensional vertical memory cell architecture with a quadruple coupling of nanogate, ferroelectric, metal layer, and channel. Leveraging its unique highly localized electric field path and multi-level synergistic effect of charge regulation, it achieves efficient polarization switching of ferroelectric materials within a three-dimensional stacked architecture. This design can increase the effective operating electric field strength of the ferroelectric material layer 221 to above its coercive field strength without sacrificing device reliability, thereby significantly reducing the actual programming voltage to below the voltage level required by traditional planar FeFETs. Simultaneously, the 3D stacking technology fundamentally overcomes the density limitations of planar structures.

[0034] By redesigning the traditional word line stacking cycle, nanometer gate control cells are integrated. This structure significantly improves the gate's control over channel charge (i.e., gate control efficiency), allowing a strong electric field sufficient to drive ferroelectric domain switching to be generated with only a very small voltage. This not only drastically reduces the voltage and dynamic power consumption required for programming operations but also effectively suppresses electrical crosstalk between adjacent memory cells in the vertical stacking structure, ensuring the accuracy of data read and write operations.

[0035] This application innovatively introduces the field enhancement mechanism from vacuum field emission into the design of NAND memory structures, achieving an interdisciplinary integration of nanoelectronics and vacuum field emission physics. Through optimized design of the gate geometry, while reducing the gate size, the tip effect is fully utilized to achieve a high concentration of gate charge, thereby significantly improving the programming efficiency of memory cells and effectively reducing power consumption.

[0036] This highly localized strong electric field significantly enhances its control over the underlying channel region: during programming and erasing operations, it enables more efficient polarization reversal of the ferroelectric material, significantly modulates the potential distribution and carrier concentration on the channel surface, and thus causes a wider range of shifts in the device's threshold voltage. This mechanism effectively expands the storage window and improves device performance.

[0037] like Figure 17 a and Figure 17 As shown in Figure b, ferroelectric devices using conventional gates generate a storage window of 0.7V at a programming voltage of 2V; ferroelectric devices using 1nm gates generate a storage window of 1.4V at a programming voltage of 1.2V. These results demonstrate that by utilizing the charge accumulation and electric field enhancement effects of nanogate structures, a localized high-intensity electric field can be formed within the ferroelectric functional layer, thereby significantly reducing the polarization reversal voltage of ferroelectric materials to below their intrinsic coercive voltage, thus lowering the programming voltage and power consumption.

[0038] The buried nanogate ferroelectric 3D NAND structure fabricated in the above embodiments successfully overcomes the technical bottlenecks of existing FeFETs in three major dimensions: operating voltage, power consumption, and storage density. The achieved ultra-low power, high-density three-dimensional ferroelectric memory provides an ideal storage solution for energy-sensitive applications such as AI edge computing, IoT terminals, and wearable devices, powerfully promoting the industrialization of next-generation low-power, high-performance storage technologies.

[0039] Example 2

[0040] like Figures 2 to 17 As shown, the fabrication method of the buried nano-gate ferroelectric 3D NAND structure in this embodiment includes the following steps: Step 1, Stacked Structure Deposition: After depositing the sacrificial layer 121 on the substrate 100 using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), several periodic stacked structures are deposited alternately as needed. Specifically: The periodic stacked structure includes, from bottom to top, a second insulating dielectric layer 126, a nano-gate layer 212, a second insulating dielectric layer 125, and a sacrificial layer 121; The material of the sacrificial layer 121 can be silicon nitride (SiN), amorphous silicon (a-Si), polycrystalline silicon (poly-Si), doped silicon (such as boron or phosphorus doped) or doped oxide (such as silicon phosphide glass PSG, borosilicate glass BSG), with a thickness ranging from 10 to 50 nanometers.

[0041] The material of the second insulating dielectric layer 125 can be silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), low-k dielectric (such as carbon oxide SiCOH, porous silicon dioxide) or high-k dielectric (such as hafnium oxide HfO2, aluminum oxide Al2O3) and their composite stacks (such as SiO2 / SiN stacks), with a thickness ranging from 20 to 40 nanometers.

[0042] The material of the nanogrid layer 212 is: transferred graphene / alone ALD metal layer / or a composite layer of graphene and ALD metal.

[0043] After the periodic stacked structure is deposited, it is annealed at 800-1000℃ to improve the film quality.

[0044] Step 2, Etching Via 130: The via 130 pattern is defined using photolithography, followed by reactive ion etching (RIE) based on Cl2 / HBr gas to form the high aspect ratio via 130 structure. Specifically: A high-performance inductively coupled plasma reactive ion etching (ICP-IR) system was employed, utilizing Cl2 for efficient vertical chemical etching, and HBr to form a protective passivation layer on the sidewalls to suppress lateral etching; finally, Ar was used... + Physical bombardment is used to enhance the reaction and selectively remove the passivation layer at the bottom of the via. This method can successfully fabricate high aspect ratio via 130 structures with steep sidewalls and controllable profiles, and can be used in 3D stacked structures to improve etching accuracy.

[0045] Step 3, Ferroelectric material layer 221 deposition: Atomic layer deposition (ALD) is used to deposit the ferroelectric material layer 221 conformally on the inner wall of the through-hole 130. HfO2-based (e.g., HfZrO2) or perovskite-type (e.g., PZT) materials are preferred. Chemical vapor deposition (CVD), magnetron sputtering, or sol-gel methods can also be used.

[0046] Taking atomic layer deposition (ALD) technology as an example, the specific steps are as follows: Precursor preparation: Place hafnium and zirconium precursors (such as TDMAHf and TDMAZr) and deionized water (H2O) in the vaporizer respectively; Cyclic deposition: The wafer is placed in the ALD reaction chamber and the following steps are performed alternately in a set ratio (e.g., Hf:Zr=1:1): Pulsed Hf precursor, purging; pulsed H2O, purging; pulsed Zr precursor, purging; pulsed H2O, purging; Self-limited growth: Each cycle deposits approximately 0.1 nm of HfO2 or ZrO2 monolayer via self-limited surface reaction; Post-annealing treatment: After deposition, rapid thermal annealing is performed at 400-600°C to induce the amorphous thin film to transform into an orthorhombic crystalline phase with ferroelectricity.

[0047] Step 4, Deposition of metal layer 222: Tungsten (W), titanium nitride (TiN) or other metal layers are deposited on the inner wall of the ferroelectric material layer 221 using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes.

[0048] Taking the most reliable combination of ALD and ECD in complex nanostructures as an example, the specific method is as follows: ALD Deposition Barrier / Seed Layer: Conformal deposition of titanium nitride (TiN) thin layers within trenches and vias 130 using ALD. TiN effectively prevents copper atom diffusion and provides a good conductive substrate.

[0049] Electrochemical copper plating (ECD): The wafer is immersed in an electrolyte containing copper ions as the cathode. After energizing, copper ions are uniformly reduced on the TiN seed layer, filling the interconnect structure from bottom to top, achieving void-free filling.

[0050] Annealing and polishing: Rapid thermal annealing is performed to optimize the grain structure and electrical properties of copper. Finally, chemical mechanical polishing (CMP) is used to remove excess copper from the surface and achieve planarization.

[0051] Step 5, Insulating Dielectric Filling and Planarization: Using high-conformity chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating processes, fill the through-hole 130 with an insulating dielectric material (such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon carbide, hafnium oxide, aluminum oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, low-k dielectrics such as SiCOH, high-k dielectrics, spin-coated dielectric materials, etc.) to form an insulating dielectric layer. Then, chemical mechanical polishing (CMP) is performed to achieve surface planarization.

[0052] The simple steps for chemical mechanical polishing (CMP) surface planarization are as follows: Fixing and Pressuring: Fix the wafer face down on the polishing head and press it onto the rotating polishing pad, applying precise pressure; Chemical and mechanical action: A polishing slurry containing nano-abrasives and chemical reagents is simultaneously delivered to the polishing pad. The chemical action softens the thin film material; the mechanical action removes it through the abrasive particles. Selective removal: Utilizing the selectivity of the process for different materials, the raised parts are removed first to achieve global flattening; Cleaning and drying: After polishing, thoroughly clean the wafer to remove all abrasive and impurities, and then dry it.

[0053] Step 6, Etching back the sacrificial layer 121: The sacrificial layer 121 exposed on the sidewall is etched back using a selective etching process (e.g., dry etching using CHF3 / O2 plasma or wet etching using hot phosphoric acid H3PO4) to form the first cavity 122. The specific steps are as follows: Depending on the material of the sacrificial layer 121, different etching processes are selected: if the sacrificial layer 121 is silicon dioxide, CHF3 / O2 plasma dry etching is used. If the sacrificial layer 121 is silicon nitride, hot phosphoric acid (H3PO4) wet etching is used.

[0054] During the etching process, an etchant is injected to contact and react with the sacrificial layer 121. The lateral etching depth is controlled by utilizing the inherent "self-stopping" characteristic of the etching process itself or by precisely controlled time / endpoint detection. For example, for wet etching: the final boundary of the first cavity 122 is defined by utilizing its inherent uniform isotropic etching characteristics, through precise timing and an etch stop layer with an ultra-high selectivity.

[0055] For the dry etching process: a step-by-step strategy is adopted, first opening the cavity and then expanding it, and isotropic etching is induced by adjusting parameters. Finally, timing or more advanced endpoint detection is used to precisely terminate the lateral etching process. After the sacrificial layer 121 is etched to a certain depth, the space it originally occupied becomes the first cavity 122.

[0056] Step 7: Selectively etch the ferroelectric material layer 221 and the metal layer 222 within the first cavity 122: Discrete memory cells are formed using dry etching (e.g., HBr / Cl2 plasma). Specific steps are as follows: Segmented selective etching: Etching metal layer 222: Using Cl2 / HBr / O2 plasma, selectively etch metal layers 222 such as tungsten / titanium, and use high selectivity to stop it on the ferroelectric material layer below; Etching the ferroelectric material layer: Switch to fluorine-containing chemical gas to selectively etch the HfO2-based ferroelectric material layer, and use its high selectivity to the underlying dielectric to stop the etching; Endpoint detection: Real-time monitoring of specific byproduct concentration changes via optical emission spectroscopy to accurately determine the etching endpoint; Desmearing and cleaning: Wet desmearing and cleaning are used to remove residual masking and byproducts.

[0057] Step 8: Filling and planarizing the first cavity 122 with insulating dielectric: Using high-conformity chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating processes, fill the first cavity 122 with an insulating dielectric (such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon carbide, hafnium oxide, aluminum oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, low-k dielectrics such as SiCOH, high-k dielectrics, spin-coated dielectric materials, etc.) to form the second insulating dielectric layer 126. Subsequently, chemical mechanical polishing (CMP) is performed to achieve surface planarization. The first insulating dielectric layer 111 and the second insulating dielectric layer 126 need to be made of different materials (e.g., the first insulating dielectric layer 111 is silicon nitride, and the second insulating dielectric layer 126 is a doped oxide) to allow for subsequent selective etching.

[0058] The simple steps for chemical mechanical polishing (CMP) surface planarization are as follows: Fixing and Pressuring: Fix the wafer face down on the polishing head and press it onto the rotating polishing pad, applying precise pressure; Chemical and mechanical action: A polishing slurry containing nano-abrasives and chemical reagents is simultaneously delivered to the polishing pad. The chemical action softens the thin film material; the mechanical action removes it through the abrasive particles. Selective removal: Utilizing the selectivity of the process for different materials, the raised parts are removed first to achieve global flattening; Cleaning and drying: After polishing, thoroughly clean the wafer to remove all abrasive and impurities, and then dry it.

[0059] Step 9: Using a selective etching process, the second insulating dielectric layer 125 and the nanogate layer are etched back, with the etching stopping at a distance of 10-1000 nanometers from the ferroelectric material layer, forming the second cavity 123. Specifically: The second cavity 123 is formed by etching back the first insulating dielectric layer 111 except the bottom layer through a selective etching process (e.g., dry etching using CHF3 / O2 plasma or wet etching using hot phosphoric acid H3PO4).

[0060] If the first insulating dielectric layer 111 is silicon dioxide, it is etched using CHF3 / O2 plasma dry etching. If the first insulating dielectric layer 111 is silicon nitride, it is etched using thermal phosphoric acid (H3PO4) wet etching.

[0061] During the etching process, an etchant is injected to contact and react with the first insulating dielectric layer 111. The lateral etching depth is controlled by utilizing the inherent "self-stopping" characteristic of the etching process itself or by precisely controlled time / endpoint detection. For example, for wet etching: the final boundary of the second cavity 123 is defined by utilizing its inherent uniform isotropic etching characteristics, through precise timing and an etching stop layer with ultra-high selectivity.

[0062] For the dry etching process: a step-by-step strategy is adopted, first opening the cavity and then expanding it, and isotropic etching is induced by adjusting parameters. Finally, timing or more advanced endpoint detection is used to precisely terminate the lateral etching process. After the first insulating dielectric layer 111 is etched to a certain depth, the space it originally occupied becomes the second cavity 123.

[0063] Step 10: In the second cavity 123, the second insulating dielectric layer is etched back using a selective etching process (e.g., using CHF3 / O2 plasma dry etching or hot phosphoric acid H3PO4 wet etching), with the etching stopping at a distance of 5-500 nanometers from the ferroelectric material.

[0064] Step 11: Fill the gate line metal 211: Fill the formed second cavity 123 with metal gate material (such as W, Ti / TiN, polycrystalline silicon or its alloy) using atomic layer deposition (ALD) or physical vapor deposition (PVD) technology to form gate line metal 211, and perform CMP planarization again so that the gate line metal 211 wraps the outside of the nanogate layer.

[0065] In this embodiment, atomic layer deposition (ALD) is selected as it is the most reliable method for filling complex cavity structures, enabling pore-free, uniform, and continuous filling. The specific steps are as follows: Pretreatment: Clean the surface of the cavity structure to enhance film adhesion; Cyclic deposition: The wafer is placed in the ALD reaction chamber and a metal precursor (such as WF6 for tungsten) and a reactive gas (such as H2 or Si2H6) are alternately pulsed through it. Self-limiting reaction: Each precursor undergoes a self-limiting reaction with the surface, and only one atomic thin film is deposited per cycle; Thorough purging: After each pulse, thoroughly purge with inert gas to remove residues and prevent gas-phase reactions; Repeated cycle: This cycle is repeated continuously, growing evenly from the cavity sidewalls and bottom towards the center until the cavity is completely filled, forming a seamless grid line metal 211.

[0066] Step 12: Remove the insulating medium filling the through-hole 130: Use hot phosphoric acid (H3PO4, 180℃) to selectively remove the insulating medium inside the through-hole 130. The specific steps are as follows: Preparation and heating: Heat the high-concentration phosphoric acid and keep it at a constant temperature of 180°C; Wet etching: The wafer is immersed in hot phosphoric acid. Phosphoric acid has a much higher etching rate for insulating media such as silicon nitride (Si3N4) than for silicon dioxide (SiO2) or silicon, thus achieving highly selective removal; Time control: By precisely controlling the etching time, it is ensured that the insulating medium inside the through-hole 130 is completely removed, while other material layers are almost unaffected; Cleaning and drying: Thoroughly rinse with deionized water to terminate the reaction and remove residual chemicals, then dry. The entire process utilizes the high selectivity and isotropic properties of wet chemical etching.

[0067] Step 13, Deposition of the first gate dielectric layer 223: Using high conformal chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating processes, an insulating dielectric (such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon carbide, hafnium oxide, aluminum oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, low-k dielectrics such as SiCOH, high-k dielectrics, spin-coated dielectric materials, etc.) is filled into the via 130 to form the first gate dielectric layer 223.

[0068] Taking the atomic layer deposition (ALD) process, which combines high conformability and process reliability, as an example, the specific method is as follows: Pretreatment: Clean the surface of the via 130 to ensure that there are active reaction sites; Pulse A: The first precursor gas is introduced into the reaction chamber, causing it to chemically adsorb a monolayer on the entire inner wall of the through hole 130; Purging A: Inert gas is introduced to purge all residual precursors; Pulse B: The second precursor is introduced and reacts with the first layer of molecules to form a solid insulating medium (such as aluminum oxide). Purging B: Blow away any remaining residues and byproducts again.

[0069] Repeat the above steps until the first gate dielectric layer 223 reaches the target thickness.

[0070] Step 14: Growth of central channel layer 224: Polycrystalline silicon, monocrystalline silicon, oxide semiconductor (such as IGZO), silicon-germanium alloy, and two-dimensional materials (such as molybdenum disulfide, tungsten diselenide, tungsten disulfide, molybdenum diselenide, etc.) channel materials are grown by chemical vapor deposition, epitaxial growth, physical vapor deposition, spin coating, etc., to form central channel layer 224.

[0071] Taking metal-organic chemical vapor deposition (MOCVD) epitaxial growth as an example, the specific steps are as follows: Precursor transport: The organometallic source (such as trimethylgallium for Ga) and hydrides (such as arsine and phosphine) are precisely transported to the reaction chamber via a carrier gas; Surface reaction and growth: The precursor undergoes thermal decomposition and chemical reaction on the heated substrate 100 surface, and high-quality single crystal thin films (such as GaAs and GaN) are epitaxially grown. Thickness and doping control: By precisely controlling the growth time, temperature and gas flow rate, the thickness, composition and electrical doping of the channel material can be precisely controlled.

[0072] Step 15, Filling the central insulating dielectric layer 225 in the via 130: Using high conformal chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating processes, fill the via 130 with an insulating dielectric (such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon carbide, hafnium oxide, aluminum oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, low-k dielectrics such as SiCOH, high-k dielectrics, spin-coated dielectric materials, etc.), and then perform chemical mechanical polishing (CMP) to achieve surface planarization.

[0073] This method combines high-precision thin-film deposition techniques such as atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) with anisotropic etching processes to achieve precise control over the thickness and morphology of the nanogate electrode layer, ensuring its interface quality and electrical performance. Simultaneously, by introducing multi-step etching and selective filling processes, the interfacial characteristics of multilayer functional materials in the three-dimensional structure are effectively optimized, significantly reducing performance fluctuations between different memory cells. This not only directly improves chip yield and reliability but also provides a robust and reliable process guarantee for its large-scale, high-density integration in ultra-large arrays.

[0074] The entire technical solution is designed with high compatibility with existing 3D NAND flash memory manufacturing platforms in mind. The core fabrication steps do not require specialized or expensive dedicated equipment, allowing for rapid implementation and large-scale mass production. This feature significantly reduces the difficulty and cost of technology iteration and production line implementation, making it an efficient and feasible technical path to resolve the current contradiction between energy consumption and density, with broad market application prospects.

[0075] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0076] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0077] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0078] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0079] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0080] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A buried nano-gate ferroelectric 3D NAND structure, characterized in that, Includes a substrate, A stacked structure is disposed on the substrate, the stacked structure comprising a plurality of first insulating dielectric layers and a FeFET memory structure stacked in an alternating manner; A plurality of through holes are provided through the stacked structure, and a first gate dielectric layer and a central channel layer are sequentially provided on the sidewall of each through hole, and a central insulating dielectric layer is filled in the central channel layer; The FeFET memory structure includes a nanogate layer, the outer side of which is embedded in the gate line metal. The FeFET memory structure is perpendicular to the first gate dielectric layer of the channel sidewall. A metal layer and a ferroelectric material layer are sequentially disposed along the first gate dielectric layer toward the outside of the via. The nanogate layer is in contact with the ferroelectric material layer. A second insulating dielectric layer is disposed between the gate line metal and the ferroelectric material layer.

2. The embedded nano-gate ferroelectric 3D NAND structure according to claim 1, characterized in that, The nanogrid layer is selected from graphene, ALD metal layer, or a composite layer of graphene and ALD metal, with a thickness of 1-5 nanometers.

3. The embedded nano-gate ferroelectric 3D NAND structure according to claim 1, characterized in that, The ferroelectric material layer is selected from HfO2-based materials or perovskite-type materials.

4. The embedded nano-gate ferroelectric 3D NAND structure according to claim 3, characterized in that, The gate line metal interconnect is made of tungsten, titanium, titanium nitride, polycrystalline silicon, or an alloy of the above materials.

5. A method for fabricating the buried nano-gate ferroelectric 3D NAND structure as described in claim 1, characterized in that, Includes the following steps: Step 1: After depositing a sacrificial layer on the substrate, several periodic stacked structures are vertically deposited. The periodic stacked structures include, from bottom to top, a second insulating dielectric layer, a nanogate layer, a second insulating dielectric layer, and a sacrificial layer. Step 2: Etch through-holes, which penetrate the plurality of periodic stacked structures and the bottommost sacrificial layer; Step 3: After depositing a ferroelectric material layer and a metal layer sequentially on the sidewall of the through hole, the through hole is filled with an insulating medium; Step 4: After removing the sacrificial layer to form the first cavity using a selective etching process, selectively etch the ferroelectric material layer and the metal layer in the first cavity to form a separate memory cell; Step 5: Fill the first cavity with the first insulating dielectric layer and perform planarization treatment; Step 6: Using a selective etching process, the nanogate layer and the second insulating dielectric layer are etched back, with the etching stopping at a distance of 10-1000 nanometers from the ferroelectric material layer to form a second cavity; Step 7: The second insulating dielectric layer in the second cavity is etched back using a selective etching process, with the etching stopping at a distance of 5-500 nanometers from the ferroelectric material layer; Step 8: Deposit the grid line metal in the second cavity and perform planarization; Step 9: After selectively removing the insulating medium inside the via, the first gate dielectric layer and the central channel layer are sequentially deposited inside the via, and the central insulating dielectric layer is filled. After planarization, the fabrication of the nano-gate ferroelectric NAND flash memory is completed.

6. The method for fabricating the embedded nano-gate ferroelectric 3D NAND structure according to claim 5, characterized in that, The material of the first insulating dielectric layer is different from that of the second insulating dielectric layer.

7. The method for fabricating the embedded nano-gate ferroelectric 3D NAND structure according to claim 5, characterized in that, In step 2, the via pattern is defined by photolithography, and then a high aspect ratio via is formed by reactive ion etching based on Cl2 / HBr gas.

8. The method for fabricating the embedded nano-gate ferroelectric 3D NAND structure according to claim 5, characterized in that, In step 3, a ferroelectric material layer is deposited in a conformal manner using atomic layer deposition, chemical vapor deposition, magnetron sputtering, or sol-gel method.

9. The method for fabricating the embedded nano-gate ferroelectric 3D NAND structure according to claim 5, characterized in that, In step 3, tungsten or titanium nitride is deposited as a barrier layer using chemical vapor deposition or atomic layer deposition, and the metal layer is prepared by combining it with electrochemical copper plating technology; or a titanium or cobalt metal layer is prepared using physical vapor deposition technology.

10. The method for fabricating the buried nano-gate ferroelectric 3D NAND structure according to claim 5, characterized in that, In step 8, after selectively removing the insulating medium in the via with hot phosphoric acid at 180°C, the first gate dielectric layer is prepared by atomic layer deposition or chemical vapor deposition; the central channel layer is grown by chemical vapor deposition, epitaxial growth, physical vapor deposition or spin coating; and the central insulating dielectric layer is filled by chemical vapor deposition, plasma-enhanced chemical vapor deposition, spin coating or atomic layer deposition.

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