Electrical device comprising a capacitor for high voltage applications and method of manufacturing thereof
By using a capacitor structure with a reverse-doped region on a semiconductor substrate, the reliability problem of high-voltage capacitors under polarity is solved, achieving a high capacitance density and reliable capacitor design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MURATA MFG CO LTD
- Filing Date
- 2025-12-22
- Publication Date
- 2026-06-23
AI Technical Summary
Existing high-voltage capacitors are prone to breakdown at lower voltages when operating under one polarity, leading to reliability issues, especially instability under high-frequency AC signals.
A specific semiconductor substrate structure is adopted, including a main region of the first doping type and a reverse doping region of the second doping type. The reverse doping region acts as a minority carrier injection source at the dielectric interface. It is formed by full-wafer doping and partially covers the top surface of the substrate, thereby increasing the generation rate of minority carriers and the charge compensation rate.
It improves the reliability and capacitance density of capacitors under both polarities, reduces early breakdown and dielectric wear, and improves linearity.
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Figure CN122269718A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electrical installations, and more particularly to the field of power electronic devices. More specifically, this invention relates to electrical installations including capacitors for high-voltage applications and methods for manufacturing such electrical installations.
[0002] The present invention is particularly advantageous for implementing decoupling or buffer capacitor elements for high-voltage applications (e.g., above 900 V, and preferably in the range of 1200 V to 2000 V), but such applications are given only as illustrative examples and should not limit the invention. Background Technology
[0003] This invention particularly belongs to the context of electrical devices that include capacitors having high capacitance density and intended for use in high-voltage applications.
[0004] In this context, it is known to use three-dimensional capacitors formed on a embossed semiconductor substrate, with a thick dielectric structure extending on the emboss. On the one hand, using a capacitor formed on a embossed semiconductor substrate allows for an increase in the specific surface area of the capacitor and the achievement of high capacitance density. On the other hand, using a thick dielectric in the capacitor structure allows for reliable withstand of high voltages.
[0005] However, the aforementioned existing capacitors exhibit certain limitations. Electrical tests conducted by the inventors on these capacitors have identified reliability issues. More specifically, such as... Figure 1 As shown, these electrical tests have demonstrated that these capacitors may experience breakdown at lower voltages compared to the opposite polarity when operating under one polarity. This compromises the reliability of the capacitors and necessitates limiting the maximum voltage to ensure reliable operation.
[0006] Therefore, there is a need for capacitors with high capacitance density that can reliably withstand high voltages in both polarities. Summary of the Invention
[0007] The present invention was made in view of the above problems.
[0008] According to one side The present invention provides an electrical device including a capacitor, the electrical device comprising:
[0009] - A bottom electrode structure comprising a semiconductor substrate having upwardly extending, protruding walls.
[0010] - A dielectric structure comprising one or more dielectric layers and conformally extending on protruding walls of a substrate, and
[0011] - A top electrode structure comprising at least one conductive layer and conformally extending over a dielectric structure, wherein the capacitor is formed by a bottom electrode structure and a top electrode structure facing each other and separated by the dielectric structure.
[0012] in:
[0013] - The substrate includes a first region of a first doping type, which extends upward from the bottom surface of the substrate to the top surface of the substrate (opposite to the bottom surface).
[0014] - The substrate includes one or more second regions of a second doping type, wherein the first and second doping types have opposite charge carriers.
[0015] - One or more second regions of the second doping type extend downward from the top surface of the substrate to a given depth of the substrate and extend only partially above the top surface of the substrate, and
[0016] - The dielectric structure extends over a first region of the first doping type and one or more second regions of the second doping type.
[0017] This invention proposes the use of a specific semiconductor substrate to form a three-dimensional capacitor, which allows it to reliably withstand high voltages under both polarities.
[0018] In the proposed solution, the substrate has a primary portion (the first region) of a first doping type and a secondary portion (the second region) of a second doping type. The first and second doping types have opposite charge carriers (e.g., p-doped and n-doped, or n-doped and p-doped).
[0019] More specifically, the second region (hereinafter also referred to as the “reverse-doped region”) is disposed at the top surface of the substrate and extends downward to a specific depth. They only partially cover the top surface of the substrate, such that the dielectric structure extends above both the first region of the first doping type and the second region of the second doping type. These reverse-doped regions allow the capacitor to reliably withstand high voltages under both polarities (which is described in further detail below).
[0020] As previously mentioned, electrical testing has shown that existing capacitors using semiconductor substrates may experience breakdown at lower voltages when operating under one polarity compared to the opposite polarity. The inventors have observed that these capacitors experience breakdown at even lower voltages when the polarity causes the semiconductor substrate to be in depletion mode. When the capacitor operates in this mode with a high-frequency AC signal (e.g., AC voltage or current with frequencies above 1 kHz or even higher than 1 Hz), the generation of minority carriers in the substrate and the drift of those carriers toward the interface with the dielectric (i.e., near the top surface of the substrate) are insufficient to rapidly compensate for the charge on the other electrode. In other words, the establishment of an inversion layer supplied by the minority carriers generated in the substrate is insufficient to rapidly achieve charge compensation at the opposite electrode. This means that a residual electric field caused by the potential applied to the opposite electrode remains in the substrate. The magnitude of this electric field depends on the potential of the opposite electrode and helps to accelerate the minority carriers toward the dielectric. These minority carriers ultimately affect the interface with the dielectric (these carriers are also called “hot carriers”). This leads to accelerated wear of the dielectric and, more critically, triggers capacitor breakdown. If the potential set to the opposite electrode is high enough, the electric field can reach a magnitude of over 70 kV / cm and cause substrate breakdown through ionization.
[0021] In contrast, in the proposed electrical device, a second region of the second doping type in the substrate (i.e., a reverse-doped region) acts as a minority carrier injection source at the interface with the dielectric. This accelerates minority carrier generation and provides faster charge compensation (i.e., improves the kinetics of substrate inversion). This helps limit the magnitude of the electric field in the substrate during transients and reduces the emergence of hot carriers within the substrate. Therefore, it reduces early dielectric wear and ultimately prevents premature capacitor breakdown. The proposed solution provides improved reliability for the capacitor under both polarities. Consequently, the linearity of the capacitor (as a function of capacitance as voltage) is also improved.
[0022] Furthermore, using a substrate with embossed (protruding walls facing each other) allows for an increase in the specific surface area of the capacitor. This results in a high capacitance density.
[0023] For these reasons, the proposed solution provides a capacitor with high capacitance density that can reliably withstand high voltages in both polarities.
[0024] In a specific implementation The second region of the second doping type extends only in the peripheral region of the substrate.
[0025] It should be noted that the central region of the substrate includes a relief formed by protruding walls, while the peripheral region of the substrate does not include a relief formed by protruding walls, but includes a reverse-doped region (the second region). The peripheral region extends to the edge of the electrical device and surrounds the central region including the relief.
[0026] In this configuration, it is preferable that the top electrode structure extends above the peripheral region. Specifically, it is preferable that the edge of the top electrode at least overlaps with the diffusion region into the substrate. Recall that when a PN junction is formed, diffusion regions rich in minority carriers are formed on both sides of the geometric junction. Therefore, it is preferable that these diffusion regions are located in the electric field formed by the capacitor electrodes, or at least in the edge field at the edges of the capacitor electrodes.
[0027] As previously mentioned, the proposed reverse-doped region acts as an injection source of minority carriers in the substrate at the interface with the dielectric, thereby facilitating the formation of an inversion layer that limits the magnitude of the electric field in the substrate, thus reducing the presence of hot carriers and consequently limiting the wear dynamics and early breakdown of the capacitor. In this embodiment, the reverse-doped region is arranged only in the peripheral region of the substrate. This arrangement is advantageous because it significantly increases the injection of minority carriers.
[0028] In a specific implementation The second region of the second doping type extends substantially above the entire highest surface of the substrate.
[0029] Hereinafter, we distinguish between: i) the top surface of the substrate that includes the relief formed by the protruding walls, and ii) the highest surface of the substrate that is substantially flat and does not include the relief formed by the protruding walls. The top surface of the substrate includes the highest surface of the substrate, the side surfaces of the protruding walls, and the lower surface between the protruding walls.
[0030] In this embodiment, the reverse-doped region (the second region) extends substantially above the entire highest surface of the substrate. In other words, the reverse-doped region extends above the top of the protruding wall. Therefore, the reverse-doped region can be formed by performing full-wafer doping on the wafer (without any patterned mask). This is advantageous because the reverse-doped region can be formed without additional photolithography steps and has a smaller impact on the capacitance density of the capacitor. Furthermore, the amount of available minority carriers is larger (i.e., related to the surface of the reverse-doped region) and distributed over the entire area of the capacitor structure. In this respect, the distance that minority carriers drift along the interface is reduced, which reduces the risk of recombination.
[0031] Importantly, it should be noted here that the reverse-doped regions do not extend over the entire top surface of the substrate. The reverse-doped regions do not extend over the entire side surface of the protruding walls (they only extend partially over the side surfaces), and do not extend over the lower surface between the protruding walls. In contrast, the first region of the first doping type does not extend over the highest surface of the substrate, but rather over the side surfaces of the protruding walls and the lower surface between the protruding walls. Assuming the protruding walls form a trench, the reverse-doped regions extend over the top of the protruding walls but not into the bottom of the trench, while the first region of the first doping type extends over the side surfaces and bottom of the trench but not over the highest surface. Thus, the dielectric structure extends over both the first region of the first doping type and the reverse-doped regions.
[0032] In a specific implementation The second region of the second doping type extends to a given depth in the substrate that is equal to or less than 30% of the substrate thickness.
[0033] For example, the given depth into which the second region of the second doping type extends in the substrate includes between 5% and 20% of the total thickness of the substrate.
[0034] This arrangement specifies a particular depth into the substrate where the reverse-doped region extends. This specific depth can be achieved by doping the substrate with a second type of dopant using a tilted implant to form the reverse-doped region. This arrangement is particularly advantageous because it significantly increases the injection of minority carriers at the interface with the dielectric (preventing premature / random breakdown of the capacitor due to faster wear) and further reduces the distance minority carriers drift along the interface.
[0035] In a specific implementation At least one region in the second region of the second doping type is electrically connected only to the bottom electrode structure and electrically insulated from the top electrode structure.
[0036] In this embodiment, all or part of the reverse-doped regions are electrically insulated from other electrical components or structures. In particular, they are insulated from the top electrode.
[0037] This implementation proposes using thermionic diffusion in the reverse-doped region (the second region) to improve minority carrier generation (i.e., without using a reverse-biased source). This is advantageous because it provides particularly low implementation complexity. This helps to provide capacitors capable of withstanding high voltages under both polarities with low implementation complexity.
[0038] In a specific implementation The electrical installation also includes:
[0039] - The first external terminal is electrically connected to the top electrode structure.
[0040] - The second external terminal is electrically connected to the bottom electrode structure.
[0041] - A third external terminal, which is electrically connected to at least one of the second regions of the second doping type.
[0042] In addition to the external terminals connected to the capacitor electrodes, this embodiment also provides external terminals connected to the reverse-doped region (the second region). This allows an external voltage supply to be connected to the reverse-doped region, thereby acting as a reverse bias source. This allows for increased minority carrier injection through the reverse-doped region. The external voltage supply can also be used to dynamically control the reverse bias source.
[0043] Accordingly, the present invention provides a system comprising the proposed electrical device, voltage supply sources connected to a first external terminal and a second external terminal (i.e., connected to capacitor electrodes) of the electrical device, and another voltage supply source connected to a third external terminal (i.e., connected to a reverse doped region) of the electrical device.
[0044] In a specific implementation The electrical device includes only two external terminals respectively connected to the top electrode structure and the bottom electrode structure, and at least one of the second regions of the second doping type is internally connected to the top electrode structure and / or the bottom electrode structure.
[0045] This embodiment proposes using a voltage supply connected to the capacitor electrodes as a reverse bias source. The latter is used to increase minority carrier injection through the reverse doped region and prevent capacitor breakdown. This embodiment provides a capacitor capable of reliably withstanding high voltages in both polarities and is particularly easy to use.
[0046] Accordingly, the present invention provides a system comprising the proposed electrical device and a voltage supply connected to two external terminals of the electrical device.
[0047] In a specific implementation At least one region of the second region of the second doping type is electrically connected to the top electrode structure via a capacitor structure, and is also electrically connected to the bottom electrode structure via another capacitor structure.
[0048] As mentioned above, the use of existing capacitors based on semiconductor substrates with high-frequency alternating current (e.g., frequencies above 1 kHz or even above 1 Hz) leads to reliability issues. The generation of minority carriers in the substrate (i.e., substrate inversion) is insufficient to achieve rapid charge compensation.
[0049] In this embodiment, the voltage supply connected to the capacitor electrodes is used as a reverse bias source to increase minority carrier injection in the substrate through the reverse-doped regions. This embodiment further proposes connecting these second regions to the capacitor electrodes via a capacitor structure. This allows for filtering of low-frequency signals (without using external capacitors) while increasing minority carrier injection for high-frequency signals (i.e., only when necessary).
[0050] Therefore, this implementation helps to provide a capacitor that can withstand high voltages in both polarities and has low implementation complexity.
[0051] In a specific implementation :
[0052] - The capacitor structure that connects the second region of the second doping type to the top electrode structure includes:
[0053] ○ i) a conductive layer of the top electrode structure and ii) a conductive layer electrically connected to the second region of the second doping type, which face each other and are separated by an insulating layer.
[0054] - Another capacitor structure connecting the second region of the second doping type to the bottom electrode structure includes:
[0055] ○ i) a first region of a first doped type of substrate and ii) a conductive layer electrically connected to a second region of the second doped type, which face each other and are separated by a dielectric structure.
[0056] This particular arrangement has the advantages of the above-described implementation and also provides particularly low implementation complexity.
[0057] In a specific implementation The protruding walls of the substrate form one or more trenches.
[0058] This embodiment proposes using a semiconductor substrate with trenches (e.g., zigzag trenches or several linear trenches) to form a three-dimensional capacitor. The use of a trenched semiconductor substrate allows for the use of a thick dielectric layer (e.g., by using wide trenches). This provides a capacitor with high capacitance density and high breakdown voltage.
[0059] In a specific implementation The electrical device (100) is configured to be used when the operating voltage measured between the bottom electrode structure (110) and the top electrode structure (130) exceeds 900 V or 1200 V.
[0060] For example, the proposed electrical device can be used as a decoupling or buffer capacitor element for power electronic devices.
[0061] Accordingly, the present invention provides a system including the proposed electrical device, the electrical device including a capacitor and a voltage supply connected to the capacitor electrodes, wherein the voltage supply operates at a voltage exceeding 900 V or 1200 V.
[0062] According to one side The present invention provides a method for manufacturing an electrical device (100) including a capacitor, the method comprising:
[0063] - Forming a bottom electrode structure including a semiconductor substrate, said substrate comprising:
[0064] ○ The upward-extending surface protrudes from the wall.
[0065] ○ A first region of a first doping type, the first region extending upward from the bottom surface of the substrate to the top surface of the substrate.
[0066] ○ One or more second regions of a second doping type, wherein the first and second doping types have opposite charge carriers, and the second or more second regions of the second doping type extend downward from the top surface of the substrate to a given depth of the substrate and extend only partially above the top surface of the substrate.
[0067] The bottom electrode structure includes:
[0068] ○ The substrate is doped with a dopant of the second doping type to form one or more second regions of the second doping type.
[0069] - Forming a dielectric structure comprising one or more dielectric layers conformally extending on protruding walls of a substrate, the dielectric structure extending over a first region of a first doping type and over one or more second regions of a second doping type.
[0070] - Form a top electrode structure comprising one or more conductive layers and conformally extending over a dielectric structure.
[0071] The proposed manufacturing method can be adapted to obtain any of the electrical devices defined in this disclosure.
[0072] The proposed manufacturing method presents the aforementioned advantages of the proposed electrical device implementation.
[0073] In a specific implementation The bottom electrode structure includes:
[0074] - A mask is formed on a substrate, the mask including at least one opening in a peripheral region of the substrate, the mask covering a central portion of the substrate.
[0075] - The substrate is doped with a second doping type dopant through at least one opening in the mask to form a second region of the second doping type, and
[0076] - Etch the substrate in its central region to form a protruding wall.
[0077] In this embodiment, the reverse doped region is arranged only in the peripheral region of the substrate (i.e., excluding the region of relief formed by protruding walls).
[0078] In a specific implementation The bottom electrode structure includes:
[0079] - Etch the substrate to form protruding walls, and then
[0080] - The substrate is fully doped with a second type of dopant using an ion-based method to form a second region of the second doping type.
[0081] Importantly, it should be noted here that the reverse-doped regions do not extend over the entire top surface of the substrate. They do not extend over the entire side surface of the protrusions (they extend only partially over the side surfaces), and they do not extend over the lower surface between the protrusions. This is due to the fact that they are formed using ion implantation after the protrusions have already been formed. In contrast, the first region of the first doping type does not extend over the highest surface of the substrate, but rather over the side surfaces of the protrusions and the lower surface between the protrusions.
[0082] In a specific implementation The bottom electrode structure includes:
[0083] - By forming a second doped layer on the substrate using full-wafer epitaxy, and then
[0084] - Etch the substrate to form protruding walls and a second region of the second doping type.
[0085] Similarly, in this embodiment, the reverse-doped regions do not extend over the entire top surface of the substrate. They do not extend over the entire side surface of the protrusions (they extend only partially over the side surfaces), and they do not extend over the lower surface between the protrusions. This is due to the fact that these reverse-doped regions are formed by full-wafer epitaxy (without any patterned mask) followed by etching of the substrate to form the protrusions. In contrast, the first region of the first doping type does not extend over the highest surface of the substrate, but rather over the side surfaces of the protrusions and the lower surface between the protrusions. Attached Figure Description
[0086] Referring to the accompanying drawings, other features and advantages of the invention will become apparent from the following description of certain embodiments of the invention, given by way of illustration only and not limitation, in which:
[0087] Figure 1 Experimental results related to standard capacitors (outside the scope of this invention) are shown.
[0088] Figure 2 A cross-sectional view of an electrical device according to an embodiment of the present invention is shown.
[0089] Figures 3A to 3C The steps of a method for manufacturing an electrical device according to an embodiment of the present invention are shown.
[0090] Figures 4A to 4E The diagram illustrates circuits associated with various electrical devices according to embodiments of the present invention, and...
[0091] Figure 5 A cross-sectional view of an electrical device according to an embodiment of the present invention is shown. Detailed Implementation
[0092] The present invention provides an electrical device comprising a capacitor having a high capacitance density, which can reliably withstand high voltages under both polarities.
[0093] This invention is particularly applicable to electrical devices including 3D capacitors formed using a silicon substrate with trenches. The following description of the invention relates to this specific application, which is given by way of illustrative example only. The invention is also applicable to 3D capacitor structures based on other semiconductor substrates and / or other reliefs (e.g., holes or pillars).
[0094] Figure 1 Experimental results related to a standard capacitor are shown.
[0095] The figure is described below to illustrate the inventors' experiments and observations upon which this invention is based. It shows an electrical test performed on an existing capacitor (outside the scope of this invention) formed using a semiconductor substrate with an embossed dielectric structure extending thereon.
[0096] As shown here, these electrical tests demonstrate that these capacitors, when operating in one polarity (polarity B - depletion mode), may experience breakdown at a lower voltage compared to the opposite polarity (polarity A - accumulation mode). The inventors have observed that when the polarity causes the semiconductor substrate to be in depletion mode, the capacitor experiences breakdown at a lower voltage.
[0097] When the capacitor operates in this mode with a high-frequency AC signal (e.g., AC voltage or current with a frequency higher than 1 kHz or even higher than 1 Hz), the generation of minority carriers in the substrate and the drift of those carriers to the interface with the dielectric (i.e., the depletion region) are insufficient to rapidly compensate for the charge on the other electrode. In other words, the establishment of the inversion layer supplied by the minority carriers generated in the substrate is insufficient to rapidly achieve charge compensation on the opposite electrode.
[0098] This means that the residual electric field caused by the potential applied to the opposite electrode remains in the substrate. The magnitude of the electric field depends on the potential of the opposite electrode and helps to accelerate minority carriers toward the dielectric (ionization of the silicon substrate). These minority carriers ultimately affect the interface with the dielectric (these carriers are also called "hot carriers"). This leads to accelerated wear of the dielectric. More critically, this can lead to catastrophic avalanche (i.e., breakdown of the silicon substrate). Leakage in the dielectric layer helps to compensate for the charge. If the potential set to the opposite electrode is high enough, the electric field can reach magnitudes exceeding 70 kV / cm and cause silicon breakdown through ionization.
[0099] Furthermore, this also implies that existing capacitors are inherently nonlinear (regarding capacitance as a function of voltage).
[0100] Below we describe how the present invention allows capacitor breakdown to be prevented by accelerating the generation of minority carriers in the substrate at the interface with the dielectric.
[0101] Figure 2 A cross-sectional view of an electrical device according to an embodiment of the present invention is shown.
[0102] exist Figure 2 In one embodiment, the electrical device 100 includes a capacitor formed of a bottom electrode structure 110, a top electrode structure 130, and a dielectric structure 120 inserted between the bottom electrode structure 110 and the top electrode structure 130.
[0103] Bottom electrode structure 110 This includes silicon substrate 111.
[0104] The substrate 111 includes upwardly extending (relief-forming) facing protruding walls 112. For example, the protruding walls 112 may form one or more trenches (e.g., zigzag-shaped trenches or linear trenches). Therefore, the capacitor of the electrical device 100 is a 3D capacitor. This allows for an increase in the specific area of the capacitor within a given component size and achieves high capacitance density.
[0105] The structure of the proposed substrate 111 represents an important aspect of the present invention and will be described in further detail below.
[0106] Dielectric structure 120It conformally extends over the bottom electrode structure 110 and includes a stack of multiple dielectric layers 121 to 123 (stacked on top of each other in the direction from bottom electrode 110 to top electrode 130). It conformally extends over the protruding wall 112 of the substrate 111.
[0107] For example, dielectric structure 120 includes dielectric layer 121, which includes thermal silicon dioxide extending (i.e. in contact with) silicon substrate 111. Dielectric structure 120 may also include one or more additional dielectric layers 122 to 123 (e.g., one or more silicon nitride layers, one or more silicon oxide layers).
[0108] Top electrode structure 130 Includes a conductive layer 131 (e.g., a polysilicon layer) that conformally extends over the dielectric structure 120.
[0109] like Figure 2 As shown, the top electrode structure 130 fills the aforementioned relief (e.g., trench) formed by the bottom electrode structure 110 and the dielectric structure 120. That is, the top surface of the top electrode structure 130 is located above the top surface of the dielectric structure 120.
[0110] The bottom electrode structure 110 and the top electrode structure 130, which face each other and are separated by the dielectric structure 120, form the capacitor of the proposed electrical device 100.
[0111] Compared to standard capacitors, the proposed solution uses a specific substrate 111 to form a capacitor that reliably withstands high voltages under both polarities. We will now describe the structure of this specific substrate 111 in detail.
[0112] Silicon substrate 111 It includes a first region 113 of a first doping type and one or more second regions 114 of a second doping type.
[0113] In other words, substrate 111 has a primary portion (the first region) of a first doping type and a secondary portion (the second region) of a second doping type. The first doping type and the second doping type have opposite charge carriers. For example, the first region 113 of substrate 111 may be p-doped (e.g., doped with boron), and the second region 114 may be n-doped (e.g., doped with phosphorus).
[0114] The first region 113 of the first doping type extends upward from the bottom surface 111-BS of the substrate 111-BS to the top surface 111-TS of the substrate 111.
[0115] The second region 114 is also referred to as the "reverse doped region". It is disposed at the top surface 111-TS of the substrate 111 and extends downwards to a given depth 111-D of the substrate 111. This depth 111-D can be equal to or less than 30% of the total thickness 111-T of the substrate. For example, the depth 111-D can account for 5% to 20% of the total thickness 111-T.
[0116] The reverse-doped region 114 only partially covers the top surface 111-TS of the substrate 111. Therefore, and as... Figure 2 As shown, dielectric structure 120 extends over both the first region 113 of the first doping type and the reverse doping region 114.
[0117] These reverse-doped regions 114 allow the capacitor to reliably withstand high voltages under both polarities. They act as minority carrier injection sources at the interface with the dielectric (i.e., in the depletion region) to accelerate inversion of the silicon substrate 111. This accelerates charge compensation. This helps limit the magnitude of the electric field in the substrate during transients and reduces the emergence of hot carriers within the substrate. Therefore, it reduces early dielectric wear and ultimately prevents premature breakdown of the capacitor. Thus, the proposed solution provides a capacitor with improved reliability under both polarities. Consequently, the linearity of the capacitor is also improved.
[0118] Reverse doped region 114 It can be achieved according to various arrangements. We refer to... Figure 2 Describe one possible arrangement, and refer to Figures 3A to 3C Describe another possible arrangement.
[0119] First, it should be noted that the silicon substrate 111 may include one or more second regions 114 of the second doping type. On the one hand, it may include a single continuous region of the second doping type. On the other hand, it may include several regions of the second doping type that do not intersect with each other.
[0120] exist Figure 2 In one embodiment, the reverse doped region 114 extends downward from the highest surface 111-HS of the substrate 111 to a given depth 111-D.
[0121] Here, it is important to distinguish the top surface 111-TS of substrate 111 from the highest surface 111-HS of substrate 111. Top surface 111-TS includes a relief formed by protruding walls 112. In other words, top surface 111-TS includes the highest surface 111-HS, the side surfaces 111-SS of protruding walls 112, and the lower surface 111-LS between protruding walls 112. In contrast, the highest surface 111-HS is substantially planar and does not include the relief formed by protruding walls 112.
[0122] In this embodiment, the reverse-doped region 114 extends substantially over the entire highest surface 111-HS (but not the entire top surface 111-TS) of the substrate 111. Therefore, the reverse-doped region 114 can be formed by performing full-wafer doping (without any patterned mask). This is advantageous because the reverse-doped region 114 can be formed without additional photolithography steps and has minimal impact on the high capacitance density of the capacitor.
[0123] For example, the reverse doped region 114 can be formed by: i) etching the substrate 111 to form a protruding wall 112, and then ii) fully doping the substrate 111 with a second doping type dopant using an ion-implementation method. Alternatively, they can also be formed by: i) forming a second doped type layer on the substrate 111 by using full-wafer epitaxy, and then ii) etching the substrate 111 to form the protruding wall 112.
[0124] It should also be noted that the interface between substrate 111 and dielectric structure 120 should be controlled to accelerate minority carrier drift and maximize carrier lifetime at the interface. For this purpose, a substrate 110 with a smooth surface and minimal crystal defects is preferred (this is ensured by annealing at a high temperature >1100°C under hydrogen H2 after etching trenches). To further reduce interface states and traps, a thin dielectric layer 121 of thermally oxidized silicon SiO2 can be formed (through thermal oxidation of substrate 111). This dielectric layer 121 can be annealed to further reduce the density of embedded traps (e.g., at a temperature of 900°C and under nitrogen N2).
[0125] We have already presented Figure 2 This embodiment corresponds to a specific arrangement of the reverse-doped region 114. We will now describe in detail the manufacturing steps of the electrical device 100 according to another embodiment of the present invention.
[0126] Figures 3A to 3C The steps of a method for manufacturing an electrical device according to an embodiment of the present invention are shown.
[0127] The proposed method for manufacturing electrical device 100 includes all or part of the steps described below.
[0128] exist Figure 3A middle The diagram illustrates the steps of forming a mask MA on a substrate 111. The mask MA includes one or more openings in a peripheral region of the substrate 111 and covers a central portion of the substrate 111. The central region of the substrate 111 includes a relief formed by protruding walls 112, while the peripheral region of the substrate 111 does not include a relief formed by protruding walls 112 and surrounds the central region of the substrate 111.
[0129] The figure also illustrates the steps involved in forming the reverse-doped region 114. Here, the reverse-doped region 114 is formed by doping the substrate 111 with a second type of dopant (e.g., an n-type dopant) through an opening in the mask MA. This can be performed, for example, by n-ion implantation. The mask MA is then removed.
[0130] and Figure 2 Compared to the previous implementation, the embodiment of FIG3 defines an arrangement in which the reverse-doped region 114 extends only in the peripheral region of the substrate 111. This is advantageous because it sufficiently increases minority carrier injection while having a negligible effect on the capacitance density of the capacitor. The surface area of the reverse-doped region 114 is small compared to the specific surface area of the capacitor. This is due to the fact that the surface area of the peripheral region of the substrate 111 is small compared to the top surface 111-TS of the substrate 111.
[0131] exist Figure 3B middle The diagram illustrates the steps involved in forming a mask MB on a substrate 111. The mask MB includes openings in a central region of the substrate 111 and covers a peripheral portion of the substrate 111. These openings define reliefs to be formed by protruding walls 112 (e.g., defining one or more grooves to be formed between the protruding walls 112).
[0132] The figure also illustrates the step of forming the protruding wall 112. This can be performed by etching the substrate 111 through an opening in the mask MB. The mask MB is then removed.
[0133] exist Figure 3C middle The diagram illustrates the steps in which the dielectric structure 120 is conformally deposited on the protruding wall 112 of the substrate 111.
[0134] The figure also illustrates the steps involved in forming the top electrode structure 130. Here, the top electrode structure 110 is formed from a conductive layer 131 (e.g., a polysilicon layer) deposited on the dielectric structure 120.
[0135] As shown in the figure, the dielectric structure 120 includes an opening onto the reverse-doped region 114. This opening is (partially or entirely) filled with a conductive material 140 to form an electrical contact C3 with the reverse-doped region 114.
[0136] The electrical contact C3 to the reverse-doped region 114 can be used to connect the reverse-doped region 114 to other components and / or structures, and to define circuitry. For example, the electrical contact C3 can be used to connect the reverse-doped region 114 to the substrate 111 via a metal strip. It can also be used to connect the reverse-doped region 114 to a reverse bias source to increase carrier injection at the interface with the dielectric structure 120.
[0137] We now present a circuit example related to the proposed electrical device 100.
[0138] Figures 4A to 4E Circuits associated with different electrical devices according to embodiments of the present invention are shown.
[0139] Before presenting the various circuits that can be implemented with respect to the proposed electrical device 100, we introduce some symbols. Here, we note that C1 is the first electrical contact connected to the top electrode structure 130, C2 is the second electrical contact connected to the bottom electrode structure 110, and C3 is the third electrical contact connected to the reverse doped region 114.
[0140] Additionally, the electrical device 100 includes a first external terminal T1 connected to a first electrical contact C1 of the top electrode structure 110 and a second external terminal T2 connected to a second electrical contact C2 of the bottom electrode structure 130. In some embodiments, it may include a third external contact T3 connected to a third electrical contact C3 of the reverse-doped region 114. External terminals T1 and T2 will be connected to terminals of a voltage supply, particularly to terminals of a high voltage supply (e.g., exceeding 900 V or in the range of 1200 V to 2000 V).
[0141] exist Figures 4A to 4E as well as Figure 5 In this embodiment, the substrate 110 has a p-doped first region 113 and an n-doped second region 114. A positive potential is applied to terminal T1 (i.e., applied to the top electrode 130), and ground is applied to terminal T2 (i.e., applied to the bottom electrode 110).
[0142] However, the present invention is not limited to these embodiments. An embodiment (not shown) is conceivable in which the substrate 111 has an n-doped first region 113 and a p-doped second region 114, and then the potentials applied to terminals T1 and T2 are reversed (i.e., ground is applied to terminal T1 and a positive potential is applied to terminal T2), and the direction of the diode formed by the pn junction is also reversed.
[0143] Figure 4A and Figure 4B Embodiments of the present invention related to thermionic diffusion are shown.
[0144] As shown in these figures, a pn junction formed at the interface between a first region 113 of a first doping type (e.g., p-doped) and a second region 114 of a second doping type (e.g., n-doped) can be assimilated into a diode.
[0145] It is important to remember that the reverse-doped region 114 extends only partially above the top surface 111-TS of the substrate, such that the dielectric structure 120 extends above both the first region 113 of the first doping type and the second region 114 of the second doping type. This ensures that the diode formed by the pn junction is connected in parallel (rather than in series) with the capacitor.
[0146] exist Figure 4A In this embodiment, the diode formed by the pn junction is connected to the bottom electrode structure 110 only at one end of its ends (i.e., C3 is absent or remains free). And in Figure 4B In one embodiment, the diode is electrically connected to the bottom electrode structure 110 at both ends via a metal strip (i.e., C3 is electrically connected to C2).
[0147] In these embodiments, the reverse-doped regions 114 are electrically insulated from other electrical components or structures. In particular, they are electrically insulated from the top electrode structure 130.
[0148] These implementations propose using thermionic diffusion in the reverse-doped region 114 to enhance minority carrier generation. That is, no reverse bias source is used. This is advantageous because it provides exceptionally low implementation complexity. This helps to provide capacitors with low implementation complexity capable of withstanding high voltages in both polarities.
[0149] Figure 4C An embodiment of the invention related to external injection is shown.
[0150] In this embodiment, an external voltage supply is connected to external terminals T2 and T3. In other words, the external voltage supply is connected to the reverse-doped region 114, which acts as a reverse bias source.
[0151] This allows for increased minority carrier injection through the reverse-doped region 114. This implementation provides a capacitor capable of withstanding high voltages under both polarities. An external voltage supply can also be used to dynamically control the reverse-biased source.
[0152] Figures 4D to 4E An embodiment of the invention related to self-injection is shown.
[0153] In these embodiments, the voltage supply connected to the capacitor electrodes (i.e., connected to external terminals T1 and T2) serves as a reverse bias source. This increases minority carrier injection through the reverse doped region 114.
[0154] In these embodiments, the electrical device 100 includes only two external terminals T1 and T2, which are respectively connected to the top electrode structure 110 and the bottom electrode structure 130. The reverse doped region 114 is internally connected to the top electrode structure 130 and the bottom electrode structure 110 (within the electrical device 100).
[0155] Figure 4D An embodiment in which the voltage divider bridge is implemented is shown. As shown, the reverse doped region 114 is connected to the top electrode structure 130 via a resistor structure (i.e., C1 is connected to C3 via a resistor). And the reverse doped region 114 is connected to the bottom electrode structure 110 via another resistor structure (i.e., C3 is connected to C2 via a resistor).
[0156] Figure 4E An embodiment in which a capacitive voltage divider bridge is implemented is shown. As shown, the reverse-doped region 114 is connected to the top electrode structure 130 via a capacitor structure (i.e., C1 is connected to C3 via a capacitor). The reverse-doped region 114 is also connected to the bottom electrode structure 110 via another capacitor structure (i.e., C3 is connected to C2 via a capacitor). This allows for filtering of low-frequency signals (without using external capacitors) and enables increased minority carrier injection for high-frequency signals (e.g., transient pulses) when such injection is required.
[0157] To further illustrate the proposed solution, we present the following diagram. Figure 4E An example implementation of the method.
[0158] However, before presenting this example implementation, it should be noted that the various circuits described above can be combined. Within the scope of this invention, embodiments are conceivable in which different reverse-doped regions 114 are connected to different circuits.
[0159] For example, some reverse-doped regions 114 may be connected to capacitor electrodes 110 and 130 (i.e., self-implantation), while other reverse-doped regions 114 may be insulated from the top electrode 130 (i.e., hot ion diffusion). Furthermore, the reverse-doped regions 114 may be connected to the top electrode 110 via a resistor and a capacitor, and may be connected to the bottom electrode 130 via another resistor and another capacitor (i.e., self-implantation).
[0160] Figure 5 A cross-sectional view of an electrical device according to an embodiment of the present invention is shown.
[0161] The figure illustrates an implementation in which the voltage supply connected to the capacitor electrodes (i.e., connected to external terminals T1 and T2) is used as a reverse bias source.
[0162] Apart from Figure 2 In addition to the above implementation, the electrical device 100 here also includes an insulating layer 150 (also referred to as a "contact opening layer"). The insulating layer 150 includes openings to i) the top electrode structure 130 and to ii) the conductive layer 140 connected to the reverse doped region 114. For example, the insulating layer 150 is a silicon oxide (SiO2) layer.
[0163] The electrical device 100 also includes a conductive layer 160 in contact with the top electrode structure 130. It also includes a conductive layer 170 in contact with the conductive layer 140 connected to the reverse doped region 114.
[0164] More specifically, Figure 5 An embodiment in which a capacitive voltage divider bridge is implemented is shown. The reverse-doped region 114 is connected to the top electrode structure 130 via a capacitor structure, and is also connected to the bottom electrode structure 110 via another capacitor structure.
[0165] On one hand, the capacitor structure connecting the reverse doped region 114 to the top electrode structure 130 is formed by: i) a conductive layer 131 of the top electrode structure 130, and ii) a conductive layer 170 connected to the reverse doped region 114, which face each other and are separated by an insulating layer 150.
[0166] On the other hand, the capacitor structure connecting the reverse doped region 114 to the bottom electrode structure 110 is formed by: i) a first region 113 of the first doped type of the substrate 111 and ii) a conductive layer 140 electrically connected to the reverse doped region 114, which face each other and are separated by the dielectric structure 120.
[0167] This implementation allows the use of a voltage supply connected to the capacitor electrodes as a reverse bias source. The capacitive voltage divider bridge implemented in this embodiment allows for filtering of low-frequency signals, thereby increasing minority carrier injection for high-frequency signals (i.e., when such injection is required). This implementation thus helps to provide a capacitor capable of withstanding high voltages in both polarities with low implementation complexity.
[0168] Additional variations: Although the present invention has been described above with reference to certain specific embodiments, it will be understood that the present invention is not limited to the particularities of these specific embodiments. Various variations, modifications, and improvements can be made to the above embodiments within the scope of the claims.
[0169] It should be understood that references to directions and positions such as “top” and “bottom”, “highest” and “lowest” in this document refer only to the orientation applicable when the architecture and components are oriented as shown in the accompanying drawings.
Claims
1. An electrical device (100) comprising a capacitor, wherein the capacitor includes: - Bottom electrode structure (110) including a semiconductor substrate (111) having an upwardly extending protruding wall (112). - A dielectric structure (120), said dielectric structure (120) comprising one or more dielectric layers (121-123) and conformally extending on the protruding wall (112) of the substrate (111), and - A top electrode structure (130) comprising at least one conductive layer (131) and conformally extending on the dielectric structure (120), the capacitor being formed by the bottom electrode structure (110) and the top electrode structure (130) facing each other and separated by the dielectric structure (120). in: - The substrate (111) includes a first region (113) of a first doping type, the first region (113) extending upward from the bottom surface (111-BS) of the substrate (111) to the top surface (111-TS) of the substrate (111). - The substrate (111) includes one or more second regions (114) of a second doping type, wherein the first doping type and the second doping type have opposite charge carriers. - One or more second regions (114) of the second doping type extend downward from the top surface (111-TS) of the substrate (111) to a given depth (111-D) of the substrate (111) and extend only partially above the top surface (111-TS) of the substrate (111), and - The dielectric structure (120) extends over a first region (113) of the first doping type and one or more second regions (114) of the second doping type.
2. The electrical device (100) according to claim 1, wherein, The second region (113) of the second doping type extends only in the peripheral region of the substrate (111).
3. The electrical device (100) according to claim 1, wherein, The second region (114) of the second doping type extends substantially over the entire highest surface (111-HS) of the substrate (111).
4. The electrical device (100) according to any one of claims 1 to 3, wherein, The given depth (111-D) of the substrate (111) into which the second region (114) of the second doping type extends is equal to or less than 30% of the thickness (111-T) of the substrate (111).
5. The electrical device (100) according to any one of claims 1 to 4, wherein, At least one region of the second region (114) of the second doping type is electrically connected only to the bottom electrode structure (110) and electrically insulated from the top electrode structure (130).
6. The electrical device (100) according to any one of claims 1 to 5, further comprising: - First external terminal (T1), which is electrically connected to the top electrode structure (130). - Second external terminal (T2), which is electrically connected to the bottom electrode structure (110). - A third external terminal (T3), which is electrically connected to at least one of the second regions (114) of the second doping type.
7. The electrical device (100) according to any one of claims 1 to 5, wherein, The electrical device (100) includes only two external terminals (T1, T2) respectively connected to the top electrode structure (130) and the bottom electrode structure (110), and at least one region of the second region (114) of the second doping type is internally connected to the top electrode structure (130) and / or the bottom electrode structure (110).
8. The electrical device (100) according to claim 7, wherein, At least one of the second regions (114) of the second doping type is electrically connected to the top electrode structure (130) via a capacitor structure, and is also electrically connected to the bottom electrode structure (110) via another capacitor structure.
9. The electrical device (100) according to claim 8, wherein: - The capacitor structure connecting the second region (114) of the second doping type to the top electrode structure (130) includes: ○ i) the conductive layer (131) of the top electrode structure (130) and ii) the conductive layer (170) electrically connected to the second region (114) of the second doping type, which face each other and are separated by an insulating layer (150), - The other capacitor structure connecting the second region (114) of the second doping type to the bottom electrode structure (110) includes: ○ i) the first region (113) of the first doped type of the substrate (111) and ii) the conductive layer (140) electrically connected to the second region (114) of the second doped type, which face each other and are separated by the dielectric structure (120).
10. The electrical device (100) according to any one of claims 1 to 9, wherein, The protruding wall (112) of the substrate (111) forms one or more trenches.
11. The electrical device (100) according to any one of claims 1 to 10, wherein, The electrical device (100) is configured to be used when the operating voltage measured between the bottom electrode structure (110) and the top electrode structure (130) exceeds 900V or 1200V.
12. A method for manufacturing an electrical device (100) including a capacitor, the method comprising: - Forming a bottom electrode structure (110) including a semiconductor substrate (111), the substrate (111) comprising: ○ The upward-extending surface faces the protruding wall (112). ○ A first region (113) of a first doping type, the first region (113) extending upward from the bottom surface (111-BS) of the substrate (111) to the top surface (111-TS) of the substrate (111). ○ One or more second regions (114) of a second doping type, wherein the first doping type and the second doping type have opposite charge carriers, wherein one or more second regions (114) of the second doping type extend downward from the top surface (111-TS) of the substrate (111) to a given depth (111-D) of the substrate (111) and extend only partially above the top surface (111-TS) of the substrate (111). The formation of the bottom electrode structure (110) includes: ○ The substrate (111) is doped with the second type of dopant to form one or more second regions (114) of the second doping type. - A dielectric structure (120) is formed, the dielectric structure (120) comprising one or more dielectric layers (121-123) conformally extending on the protruding wall (112) of the substrate (111), the dielectric structure (120) extending on a first region (113) of the first doping type and on one or more second regions (114) of the second doping type. - A top electrode structure (130) is formed, the top electrode structure (130) comprising one or more conductive layers (131) and conformally extending on the dielectric structure (120).
13. The method according to claim 12, wherein, Forming the bottom electrode structure (110) includes: - A mask (MA) is formed on the substrate (111), the mask (MA) including at least one opening in the peripheral region of the substrate (111), the mask (MA) covering the central portion of the substrate (111). - The substrate (111) is doped with a dopant of the second doping type through at least one opening of the mask (MA) to form a second region (114) of the second doping type, and - Etch the substrate (111) in the central region of the substrate (111) to form the protruding wall (112).
14. The method according to claim 12, wherein, Forming the bottom electrode structure (110) includes: - Etch the substrate (111) to form the protruding wall (112), and then - The substrate (111) is fully doped with a dopant of the second doping type using an ion-based method to form a second region (114) of the second doping type.
15. The method according to claim 12, wherein, Forming the bottom electrode structure (110) includes: - A layer of the second doped type is formed on the substrate (111) by using full-wafer epitaxy, and then - Etch the substrate (111) to form the protruding wall (112) and the second region (114) of the second doping type.