Silicon-based capacitor

Abstract

A silicon-based capacitor is provided. In the silicon-based capacitor, a first conductive connection layer includes a plurality of connection units arranged periodically in a plane, each connection unit includes a first connection part and a second connection part separated from each other, each first connection part is connected to at least one of a plurality of conductive layers through a first connection element penetrating a first interlayer insulating layer, each second connection part is connected to another conductive layer of the plurality of conductive layers through a second connection element penetrating the first interlayer insulating layer, and a lower part of the conductive connection structure interconnects the plurality of first connection parts through a third connection element penetrating a second interlayer insulating layer, and interconnects the plurality of second connection parts through a fourth connection element penetrating the second interlayer insulating layer, and an upper part of the conductive connection structure serves as a capacitor pad area to meet the capacitance density requirement, reduce the capacitor parasitic parameters, and improve the capacitor bandwidth.

Description

Technical Field

[0001] This invention relates to a silicon-based capacitor. Background Technology

[0002] The high-speed interconnection between 5G / 6G and data centers is driving the evolution of high-speed optical modules towards ultra-high transmission rates of 400G / 800G / 1.6T. The operating frequencies of their key circuits cover tens of megahertz (MHz) to hundreds of gigahertz (GHz), placing extremely high demands on the transient response, high-frequency noise suppression, wideband impedance stability, and parasitic parameter control of the power distribution network (PDN). Power supply noise directly affects signal integrity (eye diagram, bit error rate), thus making high-performance wideband capacitors crucial. Summary of the Invention

[0003] At least one embodiment of the present invention provides a silicon-based capacitor that, while meeting capacitance density requirements, reduces capacitor parasitic parameters and increases capacitor bandwidth by shortening the current loop path.

[0004] An embodiment of the present invention provides a silicon-based capacitor, comprising: a silicon substrate having a plurality of structural units, each structural unit including a trench and a platform; a plurality of conductive layers serving as capacitor plates, the plurality of conductive layers being stacked; a first interlayer insulating layer located on the plurality of conductive layers; a first conductive connection layer located on the first interlayer insulating layer; a second interlayer insulating layer located on the first conductive connection layer; and a conductive connection structure located on the second interlayer insulating layer and including at least one second conductive connection layer, wherein the first conductive connection layer includes a plurality of connection units periodically arranged in a plane, each connection unit including a first connection portion and a second connection portion that are separated from each other, each first connection portion being connected to at least one of the plurality of conductive layers by a first connection element penetrating the first interlayer insulating layer, each second connection portion being connected to other conductive layers of the plurality of conductive layers by a second connection element penetrating the first interlayer insulating layer, and the lower part of the conductive connection structure interconnecting the plurality of first connection portions by a third connection element penetrating the second interlayer insulating layer, and interconnecting the plurality of second connection portions by a fourth connection element penetrating the second interlayer insulating layer, and the upper part of the conductive connection structure serving as a capacitor pad area.

[0005] For example, each connecting unit is a rectangular unit, and the first connecting portion and the second connecting portion included in each connecting unit correspond to the central region and the outer boundary region of the rectangular unit, respectively.

[0006] For example, the plurality of first connecting portions are separate from each other, at least some of the plurality of second connecting portions are spaced apart from each other in a first direction, at least some of the plurality of second connecting portions are spaced apart from each other in a second direction, and the first direction and the second direction intersect.

[0007] For example, the plurality of second connecting portions are connected to each other, and the plurality of connected second connecting portions have a plurality of hollow areas, and the plurality of first connecting portions are respectively located in the plurality of hollow areas.

[0008] For example, the first connecting portion and the second connecting portion of each connecting unit are adjacent strips.

[0009] For example, the plurality of first connecting portions are separate from each other, the plurality of second connecting portions are separate from each other, and the plurality of first connecting portions and the plurality of second connecting portions are alternately arranged.

[0010] For example, the plurality of first connecting portions and the plurality of second connecting portions are alternately arranged along a first direction, each first connecting portion extends along a second direction, each second connecting portion extends along a second direction, and the first direction and the second direction intersect.

[0011] For example, the opposite ends of the plurality of first connection portions and the plurality of second connection portions are interconnected respectively.

[0012] For example, the plurality of conductive layers includes an odd-numbered conductive layer and an even-numbered conductive layer, and each first connection portion and each second connection portion are respectively connected to the odd-numbered conductive layer and the even-numbered conductive layer.

[0013] For example, the conductive connection structure includes a single second conductive connection layer, the single second conductive connection layer including mutually separated third connection portions and fourth connection portions, the third connection portions interconnecting multiple first connection portions, and the fourth connection portions interconnecting multiple second connection portions.

[0014] For example, the conductive connection structure includes a plurality of second conductive connection layers, and an intermediate insulating layer is provided between adjacent second conductive connection layers.

[0015] For example, the conductive connection structure includes a lower second conductive connection layer and an upper second conductive connection layer. Each of the plurality of third connecting portions in the lower second conductive connection layer is used to interconnect at least a portion of the plurality of first connecting portions. Each of the plurality of fourth connecting portions in the lower second conductive connection layer is used to interconnect at least a portion of the plurality of second connecting portions. A fifth connecting portion in the upper second conductive connection layer interconnects the plurality of third connecting portions through a fifth connecting element penetrating the intermediate insulating layer. A sixth connecting portion in the upper second conductive connection layer interconnects the plurality of fourth connecting portions through a sixth connecting element penetrating the intermediate insulating layer.

[0016] For example, each connection unit corresponds to at least one structural unit, and the orthographic projections of the first connection element and the second connection element of each connection unit on the silicon substrate fall within the orthographic projections of multiple platforms in the corresponding structural unit on the silicon substrate.

[0017] For example, the multiple structural units are arranged in an array.

[0018] For example, the material of the first conductive connection layer is different from the material of each of the plurality of conductive layers.

[0019] For example, the material of each of the plurality of conductive layers includes polycrystalline silicon or titanium nitride, or the material of one of the plurality of conductive layers includes doped silicon, and the material of the remaining conductive layers includes polycrystalline silicon.

[0020] For example, the material of the first conductive connection layer includes metal, and the material of the conductive connection structure includes metal. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention.

[0022] Figure 1 This is a cross-sectional view of a silicon-based capacitor provided in an embodiment of the present invention.

[0023] Figure 2 A stacked plan view of a silicon-based capacitor 1001 provided for an embodiment of the present invention.

[0024] Figure 3 for Figure 2 The diagram shows a plan view of the first conductive interconnect layer of a silicon-based capacitor.

[0025] Figure 4 for Figure 2The diagram shows a plan view of the lower second conductive connection layer of a silicon-based capacitor.

[0026] Figure 5 for Figure 2 The diagram shows a plan view of the upper second conductive connection layer of the silicon-based capacitor.

[0027] Figure 6 for Figure 2 The diagram shows a plan view of the stacked first conductive connection layer and the upper second conductive connection layer of the silicon-based capacitor.

[0028] Figure 7 for Figure 2 The diagram shows the connection between the first conductive connection layer and multiple conductive layers in a silicon-based capacitor.

[0029] Figure 8A for Figure 2 The diagram shows a plan view of the stack of a first conductive interconnect layer, a first interlayer insulating layer, and a lower second conductive interconnect layer in a silicon-based capacitor.

[0030] Figure 8B for Figure 2 The diagram shows a plan view of the stack of a lower second conductive connection layer, an intermediate insulating layer, and an upper second conductive connection layer in a silicon-based capacitor.

[0031] Figure 9A This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention.

[0032] Figure 9B for Figure 9A A plan view of the stacked first conductive connection layer and the lower second conductive connection layer.

[0033] Figure 9C for Figure 9A A plan view of the stacked lower and upper second conductive connection layers.

[0034] Figure 10 This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention.

[0035] Figure 11 for Figure 10 A plan view of the first conductive interconnect layer in the structure.

[0036] Figure 12 for Figure 10 A plan view of the second conductive interconnect layer.

[0037] Figure 13 This is a plan view of a first conductive connection layer and a first interlayer insulating layer in a silicon-based capacitor provided in another embodiment of the present invention.

[0038] Figure 14 This is a plan view of a stack of a first conductive connection layer, a second interlayer insulating layer, and a second conductive connection layer in a silicon-based capacitor according to another embodiment of the present invention.

[0039] Figure 15 This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention.

[0040] Figure 16 for Figure 15 A plan view of the first conductive interconnect layer in the structure.

[0041] Figure 17 for Figure 15 A plan view of the second conductive interconnect layer.

[0042] Figure 18 This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention.

[0043] Figure 19 for Figure 18 A plan view of the stack of the first conductive connection layer, the second interlayer insulating layer, and the second conductive connection layer.

[0044] Figure 20 This is a cross-sectional view of a silicon-based capacitor provided in an embodiment of the present invention.

[0045] Figure 21 The figure shows the simulation results of the bandwidth of a silicon-based capacitor that includes a first conductive interconnect layer and a single second conductive interconnect layer. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0048] Due to the physical constraints of miniaturization and high-density integration of optical modules, the layout space of printed circuit boards (PCBs) is extremely limited. This places dual requirements on capacitors: on the one hand, they need to have high capacitance density to meet the energy storage needs of chips such as digital signal processors (DSPs), drivers, and transimpedance amplifiers (TIAs); on the other hand, they need to maintain low parasitic parameters and excellent high-frequency characteristics.

[0049] Silicon-based capacitors are fabricated using semiconductor processes, significantly expanding the effective electrode area through three-dimensional designs such as deep trenches and vertical stacking. Furthermore, atomic layer deposition (ALD) technology is used to create a nanoscale uniform dielectric layer, compatible with high-dielectric-constant materials, fundamentally improving capacitance per unit area. Simultaneously, wafer-level integration eliminates the dicing and packaging redundancy of traditional discrete devices, enabling high-capacitance integration in extremely small sizes, significantly saving PCB space, and allowing capacitors to be placed closer to the core power supply area of ​​the chip, further optimizing high-frequency power integrity while improving integration density.

[0050] However, existing silicon-based capacitor technologies still have many technical shortcomings when adapting to the broadband transmission requirements of high-speed optical modules, making it difficult to fully meet practical application needs. For example, existing deep trench silicon capacitors use interleaved stacked multilayer capacitor units, which, while meeting capacitance requirements, suffer from high equivalent series inductance (ESL), resulting in a significant increase in impedance at high frequencies and limited bandwidth, making them unsuitable for ultra-high frequency broadband applications. Another example is the existing technology of simultaneously forming the upper electrodes of silicon capacitors and MIM capacitors on a silicon wafer and connecting them with metal wires to integrate high-capacitance silicon capacitors and low-capacitance metal-insulator-metal (MIM) capacitors into the same device. While this approach effectively expands the overall bandwidth by utilizing the high resonant frequency advantage of MIM capacitors to construct a low-impedance path at high frequencies, it still has specific disadvantages, specifically: First, insufficient performance synergy, with high-capacitance silicon capacitors focusing on medium to low impedance. For frequency energy storage decoupling, MIM capacitors focus on high-frequency and low-parasitic decoupling. After integration without additional wiring, impedance abrupt changes and high-frequency loss superposition are prone to occur, making it difficult to achieve a smooth impedance transition within a wide bandwidth and affecting the stability of broadband signal transmission in high-speed optical modules. Secondly, the process precision requirements are extremely high. The integration method without additional wiring and process steps significantly increases the requirements for silicon substrate flatness, thin film deposition uniformity, and electrode alignment accuracy. Once there is a slight deviation in the process, it is easy to cause abnormal parasitic parameters and increased dispersion of capacitor performance, which in turn increases the difficulty of mass production and affects product consistency.

[0051] Embodiments of the present invention provide a silicon-based capacitor. By designing an interconnect structure containing multiple conductive connection layers, multiple vertically overlapping capacitors are first separated through the bottom conductive connection layer, and then the separated capacitors are merged and connected in parallel or led out to the top layer through other conductive connection layers above. While meeting the capacitance density requirements, the current loop path can be effectively shortened, the parasitic parameters of the capacitor can be reduced, and the capacitor bandwidth can be improved.

[0052] Figure 1 This is a cross-sectional view of a silicon-based capacitor provided in an embodiment of the present invention.

[0053] like Figure 1 As shown, the silicon-based capacitor includes: a silicon substrate 101, a plurality of conductive layers 103 serving as capacitor plates, a first interlayer insulating layer 121, a first conductive connection layer 131, a second interlayer insulating layer 122, and a conductive connection structure 150.

[0054] like Figure 1 As shown, multiple conductive layers 103, which serve as capacitor plates, are stacked to increase capacitance density. Figure 1 Four conductive layers 103 are shown: conductive layer 1031, conductive layer 1032, conductive layer 1033, and conductive layer 1034. For example, conductive layer 1031 can be formed by doping a silicon substrate 101. The remaining conductive layers, namely conductive layers 1032, 1033, and 1034, can be made of polycrystalline silicon. Of course, in other embodiments, the silicon substrate 101 may not be conductive, but rather multiple conductive layers 103 may be disposed on the silicon substrate 101, with each conductive layer 103 made of polycrystalline silicon. That is, the material of each of the multiple conductive layers 103 may include polycrystalline silicon, or the material of one of the multiple conductive layers 103 may include doped silicon, while the materials of the remaining conductive layers 103 may include polycrystalline silicon. In other examples, some or all of the multiple conductive layers 103 may also be formed using titanium nitride, and the present invention does not impose any limitation on the specific materials of the conductive layers.

[0055] like Figure 1 As shown, a dielectric layer 102 is provided between adjacent conductive layers 1031. The dielectric layer 102 can be made of a dielectric material, for example, the dielectric material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the dielectric layer 102 adopts a structure of three stacked silicon oxide-silicon nitride-silicon oxide films. Figure 1Dielectric layers 1021, 1022, and 1023 are shown. Dielectric layer 1021 is located between conductive layers 1031 and 1032, dielectric layer 1022 is located between conductive layers 1032 and 1033, and dielectric layer 1023 is located between conductive layers 1033 and 1034. It should be noted that the number of dielectric layers 102 shown above is only an example, and the number of dielectric layers 102 can be set according to the number of conductive layers 103.

[0056] In one example, an insulating layer (not shown) may be included between the silicon substrate 101 and the conductive layer 1031. This insulating layer may be made of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, but is not limited thereto.

[0057] Further reference Figure 1 The first interlayer insulating layer 121 is located on the plurality of conductive layers 103. Specifically, after the plurality of conductive layers 103 are formed, a first interlayer insulating film can be formed thereon as the first interlayer insulating layer 121, and vias can be formed in the first interlayer insulating film. Conductive material is filled in the vias to form connecting elements, so that the components in the first conductive connecting layer 131 are connected to at least one of the plurality of conductive layers 103 through the connecting elements. The first interlayer insulating layer 121 can be made of an insulating material, for example, the insulating material can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and zirconium oxide, but is not limited thereto.

[0058] like Figure 1 As shown, the first conductive connection layer 131 is located on the first interlayer insulating layer 121.

[0059] like Figure 1 As shown, the second interlayer insulating layer 122 is located on the first conductive connection layer 131. The second interlayer insulating layer 122 may be made of an insulating material, for example, including at least one of silicon oxide, silicon nitride, and silicon oxynitride, but not limited thereto.

[0060] like Figure 1 As shown, the silicon substrate 101 has multiple structural units 1010, each structural unit 1010 including a trench 1011 and a platform 1012. By providing the trench 1011, the capacitor plates can have a larger facing area, thereby increasing the capacitor's capacitance. By providing the platform 1012, connecting elements can be provided at the platform 1012, facilitating the connection of different conductive layers 103.

[0061] like Figure 1 As shown, the conductive connection structure 150 is located on the second interlayer insulating layer 122. (As indicated...) Figure 1As shown, the conductive connection structure 150 may include a plurality of second conductive connection layers 105 (e.g., two second conductive connection layers 105), and an intermediate insulating layer 300 is provided between adjacent second conductive connection layers 105. Each second conductive connection layer 105 may be formed from the same film layer using the same patterning process. The material of each second conductive connection layer 105 in the conductive connection structure 150 may include metal. Providing two second conductive connection layers 105 facilitates the interconnection of multiple discrete portions in the first conductive connection layer 131 and leads them to the top, thereby facilitating connection to pads. Figure 1 As shown, the conductive connection structure 150 may include a lower second conductive connection layer 151 and an upper second conductive connection layer 152. It should be noted that although the conductive connection structure 150 shown here includes multiple second conductive connection layers 105, it is only one example, and in other examples described below, the conductive connection structure 150 may also consist of only a single second conductive connection layer 105.

[0062] Figure 2 A stacked plan view of a silicon-based capacitor 1001 provided for an embodiment of the present invention. Figure 1 It can be regarded as Figure 2 Side sectional view along the X-axis. For clarity, Figure 2 The structure other than the first conductive connection layer 131 and the conductive connection structure 150 (which includes a lower second conductive connection layer 151 and an upper second conductive connection layer 152) is not shown. Figure 1 It shows Figure 2 The membrane structure is not shown in the figure.

[0063] Figure 3 for Figure 2 The diagram shows a plan view of the first conductive interconnect layer of a silicon-based capacitor. Figure 3 The first conductive connection layer 131 is shown. (See diagram.) Figures 1 to 3 As shown, the first conductive connection layer 131 includes a plurality of connection units 1310 periodically arranged in a plane. Each connection unit 1310 includes a first connection portion 1311 and a second connection portion 1312 that are separated from each other. A connection unit 1310 can serve as the smallest unit of the first conductive connection layer 131. Within a single connection unit 1310, the parallel connection of multiple conductive layers serving as capacitor plates is achieved. Correspondingly, the capacitor structure corresponding to the connection unit 1310 can be the smallest capacitor unit. The first connection portion 1311 and the second connection portion 1312 are separate from each other. The first conductive connection layer 131 can be formed from the same film layer using the same patterning process. As an example, the material of the first conductive connection layer 131 can be different from the material of each of the plurality of conductive layers 103. For example, the first conductive connection layer 131 can be made of metal. That is, the material of the first conductive connection layer 131 includes metal. Figure 2 and Figure 3 As shown, the first conductive connection layer 131 includes a plurality of first connection portions 1311 and a plurality of second connection portions 1312.

[0064] As an example, such as Figure 3 As shown, each connecting unit 1310 can be a rectangular unit, and the first connecting portion 1311 and the second connecting portion 1312 included in each connecting unit 1310 can respectively correspond to the central region and the outer boundary region of the rectangular unit. A gap 1315 can be present between the first connecting portion 1311 and the second connecting portion 1312. The gap 1315 can be annular. By setting the gap therebetween, the first connecting portion 1311 and the second connecting portion 1312 can be separated from each other.

[0065] like Figure 3 As shown, multiple second connecting portions 1312 can be connected to each other. That is, the multiple second connecting portions 1312 can be an integral structure. The multiple connected second connecting portions 1312 have multiple hollow areas 1316, and multiple first connecting portions 1311 can be located in the multiple hollow areas 1316 respectively to form separate first connecting portions 1311 and second connecting portions 1312.

[0066] It should be noted that, Figure 3 The shape of the first connecting portion 1311 shown is merely an example, and it can be replaced by other shapes, including but not limited to hexagons, octagons, etc. The present invention does not limit the shape of the first connecting portion 1311, as long as there is a hollow area / gap between it and the second connecting portion 1312.

[0067] As an example, such as Figure 3 As shown, a plurality of first connecting portions 1311 are separate from each other, at least a portion of a plurality of second connecting portions 1312 are spaced apart from each other in the first direction X, at least a portion of a plurality of second connecting portions 1312 are spaced apart from each other in the second direction Y, and the first direction X and the second direction Y intersect.

[0068] In embodiments of the present invention, both the first direction X and the second direction Y are parallel to the reference plane. For example, the first direction X is perpendicular to the second direction Y. The third direction Z is perpendicular to the reference plane. The third direction Z is perpendicular to the first direction X and perpendicular to the second direction Y. For example, the reference plane is the bottom surface of the silicon substrate 101, or the plane containing the top surface of the platform of the silicon substrate 101, or the plane containing the bottom surface of the trench 1011 of the silicon substrate 101. Of course, other suitable surfaces can also be used as the reference plane.

[0069] Figure 4 for Figure 2The diagram shows a plan view of the lower second conductive interconnect layer of a silicon-based capacitor. Figure 4 As shown, the lower second conductive connection layer 151 includes a plurality of third connection portions 1511 and a plurality of fourth connection portions 1512. The lower second conductive connection layer 151 can be formed from the same film layer using the same patterning process.

[0070] like Figure 4 As shown, a plurality of third connecting portions 1511 and a plurality of fourth connecting portions 1512 are alternately arranged along a first direction X, each third connecting portion 1511 extends along a second direction Y, and each fourth connecting portion 1512 extends along a second direction Y, with the first direction X and the second direction Y intersecting.

[0071] Figure 5 for Figure 2 The diagram shows a plan view of the upper second conductive interconnect layer of a silicon-based capacitor. Figure 5 As shown, the upper second conductive connection layer 152 includes a fifth connection portion 1521 and a sixth connection portion 1522. The fifth connection portion 1521 and the sixth connection portion 1522 are separated from each other. The fifth connection portion 1521 and the sixth connection portion 1522 are spaced apart from each other. The upper second conductive connection layer 152 can be formed from the same film layer using the same patterning process.

[0072] Figure 6 for Figure 2 The diagram shows a plan view of the stacked first conductive connection layer and the upper second conductive connection layer of the silicon-based capacitor. Figure 6 The diagram shows the overlap between a plurality of first connection portions 1311 and a plurality of second connection portions 1312 in the first conductive connection layer 131 and a plurality of third connection portions 1511 and a plurality of fourth connection portions 1512 in the upper second conductive connection layer 151.

[0073] Figure 7 for Figure 2 The diagram shows the connection between the first conductive connection layer and multiple conductive layers in a silicon-based capacitor.

[0074] like Figure 1 and Figure 7 As shown, each first connection portion 1311 is connected to at least one conductive layer among the plurality of conductive layers 103 via a first connection element 201 penetrating the first interlayer insulating layer 121, and each second connection portion 1312 is connected to other conductive layers among the plurality of conductive layers 103 via a second connection element 202 penetrating the first interlayer insulating layer 121.

[0075] like Figure 1 and Figure 7As shown, in one example, the plurality of conductive layers 103 may include an odd number of conductive layers (e.g., conductive layers 1031 and 1033) and an even number of conductive layers (e.g., conductive layers 1032 and 1034), and each first connection portion 1311 and each second connection portion 1312 are respectively connected to the odd number of conductive layers (e.g., conductive layers 1031 and 1033) and the even number of conductive layers (e.g., conductive layers 1032 and 1034). Figure 1 As shown, each first connection portion 1311 is connected to an odd-numbered conductive layer (conductive layer 1031 and conductive layer 1033), and each second connection portion 1312 is connected to an even-numbered conductive layer (conductive layer 1032 and conductive layer 1034).

[0076] exist Figure 1 and Figure 7 In the example of the first connecting element 2011 and the first connecting element 2012 shown, each first connecting portion 1311 can be connected to the conductive layer 1031 via the first connecting element 2011 penetrating the first interlayer insulating layer 121, and to the conductive layer 1033 via the first connecting element 2012 penetrating the first interlayer insulating layer 121. For example, a plurality of structural units 1010 can be arranged in an array. The plurality of structural units 1010 can be arranged in an array along a first direction X and a second direction Y. For example, each connecting unit 1310 corresponds to at least one structural unit 1010, and the orthographic projection of the first connecting element 201 and the second connecting element 202 of each connecting unit 1310 on the silicon substrate 101 falls within the orthographic projection of a plurality of platforms 1012 in the corresponding structural unit 1010 on the silicon substrate 101. When dividing the structural unit 1010, the minimum size of the structure in the first conductive connection layer 131 (one connection unit 1310) can be matched. Within the minimum size of the structure in the first conductive connection layer 131 (one connection unit 1310), multiple platforms of the structural unit 1010 can be set accordingly.

[0077] exist Figure 1 and Figure 7 In the example of the second connecting element 2021 and the second connecting element 2022 shown, each second connecting portion 1312 is connected to the conductive layer 1032 via the second connecting element 2021 penetrating the first interlayer insulating layer 121, and is connected to the conductive layer 1034 via the second connecting element 2022 penetrating the first interlayer insulating layer 121.

[0078] In an embodiment of the present invention, the first connecting element 201 and the second connecting element 202 penetrate the first interlayer insulating layer 121, and may also penetrate one or more dielectric layers 102 as needed.

[0079] Figure 7The connecting elements (first connecting element 201 and second connecting element 202) shown are located on platform 1012 of silicon substrate 101. A recess 1011 is formed between adjacent platforms 1012. The placement of the connecting elements (first connecting element 201 and second connecting element 202) is not limited to... Figure 7 As shown.

[0080] It should be noted that the number of conductive layers 103 in the embodiments of the present invention is not limited to... Figure 1 As shown, the number of conductive layers can be set as needed. The number of odd-numbered and even-numbered conductive layers is also not limited. Figure 1 As shown, the configuration can be set as needed. Accordingly, corresponding connecting elements can be set according to the number and connection status of conductive layers 103.

[0081] Figure 8A for Figure 2 The diagram shows a plan view of the stack of a first conductive interconnect layer, a first interlayer insulating layer, and a lower second conductive interconnect layer in a silicon-based capacitor. Figure 8A The diagram shows a first connecting portion 1311 and a second connecting portion 1312 in the first conductive connecting layer 131, a plurality of third connecting portions 1511 and a plurality of fourth connecting portions 1512 in the lower second conductive connecting layer 151, a third connecting element 203, and a fourth connecting element 204. The positions of the third connecting element 203 and the fourth connecting element 204 are not limited to... Figure 8A As shown.

[0082] Figure 8B for Figure 2 The diagram shows a plan view of the stack of a lower second conductive connection layer, an intermediate insulating layer, and an upper second conductive connection layer in a silicon-based capacitor. Figure 8B The diagram shows a plurality of third connecting portions 1511 and a plurality of fourth connecting portions 1512 in the lower second conductive connecting layer 151, a fifth connecting portion 1521 and a sixth connecting portion 1522 in the upper second conductive connecting layer 152, a fifth connecting element 205, and a sixth connecting element 206. It should be noted that in... Figure 8B The shapes of the fifth connecting portion 1521 and the sixth connecting portion 1522 shown are merely examples, and other shapes of two separate portions can be used as the fifth connecting portion 1521 and the sixth connecting portion 1522 respectively.

[0083] like Figure 1 , Figure 8A and Figure 8BAs shown, the lower part of the conductive connection structure 150 (that is, the lower surface of the lower second conductive connection layer 151) interconnects a portion of the plurality of first connection portions 1311 through a third connection element 203 penetrating the second interlayer insulating layer 122, and interconnects a portion of the plurality of second connection portions 1312 through a fourth connection element 204 penetrating the second interlayer insulating layer 122, and the upper part of the conductive connection structure 150 (that is, the upper surface of the upper second conductive connection layer 152) serves as a capacitor pad area.

[0084] like Figure 1 , Figure 2 , Figures 4 to 6 , Figures 8A to 8B As shown, each of the plurality of third connection portions 1511 in the lower second conductive connection layer 151 is used to interconnect a portion of the plurality of first connection portions 1311; each of the plurality of fourth connection portions 1512 in the lower second conductive connection layer 151 is used to interconnect a portion of the plurality of second connection portions 1312; the fifth connection portion 1521 in the upper second conductive connection layer 152 interconnects the plurality of third connection portions 1511 through a fifth connection element 205 penetrating the intermediate insulating layer 300; and the sixth connection portion 1522 in the upper second conductive connection layer 152 interconnects the plurality of fourth connection portions 1512 through a sixth connection element 206 penetrating the intermediate insulating layer 300. Thus, as... Figures 7 to 8B As shown, the discrete first connection portion 1311 and second connection portion 1312 are connected to the fifth connection portion 1521 and the sixth connection portion 1522 respectively via the third connection portion 1511 and the fourth connection portion 1512. Thus, the discrete capacitor units are connected in parallel and led out to the top for easy connection to the pads.

[0085] In general, embodiments of the present invention provide a silicon-based capacitor. The first conductive interconnect layer may include multiple interconnect units, each interconnect unit may include a first interconnect portion and a second interconnect portion that are separated from each other. This facilitates the separation of multiple vertically overlapping capacitors (smallest capacitor units), and the remaining layers combine and connect the discrete capacitor plates in parallel or lead them out to the top layer for connection with pads. This design can effectively shorten the current loop path and reduce capacitor parasitic parameters while meeting capacitance density requirements, thereby improving capacitor bandwidth. In addition, this design does not require additional MIM capacitors, avoiding disadvantages such as insufficient product synergy, easy impedance abrupt changes, high process precision requirements, and poor product consistency.

[0086] Figure 9A This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention. Figure 9B for Figure 9A A plan view of the stacked first conductive connection layer and the lower second conductive connection layer. Figure 9C for Figure 9A A plan view of the stacked lower and upper second conductive connection layers.

[0087] Figures 9A to 9C A silicon-based capacitor 1001-1 is shown. Unlike silicon-based capacitor 1001, in silicon-based capacitor 1001-1, multiple third connection portions 1511 in the lower second conductive connection layer 151 are connected by first connection lines 1513, and multiple fourth connection portions 1512 in the lower second conductive connection layer 151 are connected by second connection lines 1514. That is, the lower second conductive connection layer 151 can be formed by two separate comb-like structures intersecting each other. Thus, in silicon-based capacitor 1001-1, multiple third connection portions 1511 and first connection lines 1513 interconnect all of the multiple first connection portions 1511, and multiple fourth connection portions 1512 and second connection lines 1514 interconnect all of the multiple second connection portions 1512.

[0088] In this case, such as Figure 9A and Figure 9C As shown, the fifth connecting portion 1521 and the sixth connecting portion 1522 in the upper second conductive connection layer 152 can be implemented with a more simplified shape or structure. For example, the fifth connecting portion 1521 and the sixth connecting portion 1522 can be implemented as two separate rectangular portions. However, the present invention is not limited to this, and other shapes can also be used to implement the fifth connecting portion 1521 and the sixth connecting portion 1522 in the second conductive connection layer 152.

[0089] It should be noted that, Figures 1 to 9C Taking the conductive connection structure 150 in the silicon-based capacitor 1001 as an example, which includes two second conductive connection layers 105, in other embodiments, the conductive connection structure 150 may include one or more second conductive connection layers 105, that is, the conductive connection structure 150 may include at least one second conductive connection layer 105.

[0090] Figures 10 to 14 A silicon-based capacitor 1002 is shown. Figure 10 This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention. Figure 11 for Figure 10 A plan view of the first conductive interconnect layer in the structure. Figure 12 for Figure 10 A plan view of the second conductive interconnect layer. Figure 13This is a plan view of a first conductive connection layer and a first interlayer insulating layer in a silicon-based capacitor provided in another embodiment of the present invention. Figure 14 This is a plan view of a stack of a first conductive connection layer, a second interlayer insulating layer, and a second conductive connection layer in a silicon-based capacitor according to another embodiment of the present invention.

[0091] like Figures 10 to 14 As shown, the silicon-based capacitor 1002 includes a first conductive connection layer 131 and a single second conductive connection layer 105.

[0092] like Figure 10 , Figure 11 , Figure 13 and Figure 14 As shown, the first conductive connection layer 131 includes a plurality of connection units 1310, and the first connection portion 1311 and the second connection portion 1312 included in each connection unit 1310 are adjacent strips.

[0093] like Figure 10 , Figure 11 , Figure 13 and Figure 14 As shown, multiple first connecting portions 1311 are separate from each other, multiple second connecting portions 1312 are separate from each other, and multiple first connecting portions 1311 and multiple second connecting portions 1312 are alternately arranged.

[0094] like Figure 10 , Figure 11 , Figure 13 and Figure 14 As shown, a plurality of first connecting portions 1311 and a plurality of second connecting portions 1312 are alternately arranged along a first direction X, each first connecting portion 1311 extends along a second direction Y, and each second connecting portion 1312 extends along a second direction Y, and the first direction X and the second direction Y intersect.

[0095] like Figure 13 As shown, each connecting unit 1310 is a rectangular unit, and the first connecting portion 1311 and the second connecting portion 1312 included in each connecting unit 1310 correspond to the opposite sides of the rectangular unit, respectively. Figure 13 The first connecting element 201 (first connecting element 2011 and first connecting element 2012) is shown. Figure 13The second connecting element 202 (second connecting element 2021 and second connecting element 2022) is shown. The connection method between the first conductive connection layer 131 and the plurality of conductive layers 103 via the first connecting element 201 and the second connecting element 202 is described previously. At the locations where the first connecting element 201 and the second connecting element 202 are provided, the silicon substrate 101 may have corresponding platforms 1012. A recess 1011 is formed between adjacent platforms 1012. The first connecting element 201 and the second connecting element 202 are connecting elements located in vias within the first interlayer insulating layer 121.

[0096] like Figures 10 to 14 As shown, the conductive connection structure 150 in the silicon-based capacitor 1002 includes a single second conductive connection layer 105. The single second conductive connection layer 105 includes a third connection portion 1051 and a fourth connection portion 1052 that are separated from each other. The third connection portion 1051 interconnects a plurality of first connection portions 1311, and the fourth connection portion 1052 interconnects a plurality of second connection portions 1312.

[0097] Figure 14 A third connecting element 203 and a fourth connecting element 204 are shown. A third connecting portion 1051 interconnects a plurality of first connecting portions 1311 via a plurality of third connecting elements 203, and a fourth connecting portion 1052 interconnects a plurality of second connecting portions 1312 via a plurality of fourth connecting elements 204. The third connecting elements 203 and the fourth connecting elements 204 are connecting elements located in vias within the second interlayer insulating layer 122. The lower part of the conductive connection structure 150 (the bottom surface of the second conductive connection layer 105, the bottom surface of the third connection portion 1051, and the bottom surface of the fourth connection portion 1052) interconnects a plurality of first connection portions 1311 through a third connection element 203 penetrating the second interlayer insulating layer 122, and interconnects a plurality of second connection portions 1312 through a fourth connection element 204 penetrating the second interlayer insulating layer 122. The upper part of the conductive connection structure 150 (the top surface of the second conductive connection layer 105, the top surface of the third connection portion 1051, and the top surface of the fourth connection portion 1052) serves as a capacitor pad area.

[0098] In the silicon-based capacitor 1002, the second conductive connection layer 105 serves both as a parallel component (the two opposite poles of the parallel capacitor) and as a lead-out structure (top conductive layer, pad).

[0099] Figures 15 to 18 A silicon-based capacitor 1003 is shown. Figure 15 This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention. Figure 16 for Figure 15 A plan view of the first conductive interconnect layer in the structure. Figure 17 for Figure 15 A plan view of the second conductive interconnect layer.

[0100] Compared to silicon-based capacitor 1002, in silicon-based capacitor 1003, the opposite ends of a plurality of first connection portions 1311 and a plurality of second connection portions 1312 are interconnected respectively. For example... Figure 16 As shown, multiple first connecting portions 1311 are interconnected via first connecting lines 1313. The multiple first connecting portions 1311 and the first connecting lines 1313 are a single integrated structure. Figure 16 As shown, multiple second connecting portions 1312 are interconnected via second connecting lines 1323. The multiple second connecting portions 1312 and the second connecting lines 1323 are an integral structure. The first connecting line 1313 and the second connecting line 1323 are respectively located at opposite ends of the areas occupied by the first connecting portion 1311 and the second connecting portion 1312.

[0101] Compared to silicon-based capacitor 1002, the shapes of the third connection portion 1051 and the fourth connection portion 1052 are adjusted in silicon-based capacitor 1003. In silicon-based capacitor 1003, the shapes of the third connection portion 1051 and the fourth connection portion 1052 are simpler.

[0102] In the silicon-based capacitor 1003, a plurality of first connection portions 1311 in the first conductive connection layer 131 are interconnected, a plurality of second connection portions 1312 are interconnected, and the second conductive connection layer 105 serves as the top conductive layer to provide pad areas.

[0103] Figures 18 to 19 A silicon-based capacitor 1004 is shown. Figure 18 This is a plan view of a silicon-based capacitor stack provided in another embodiment of the present invention. Figure 19 for Figure 18 A plan view of the stack of the first conductive connection layer, the second interlayer insulating layer, and the second conductive connection layer.

[0104] Compared to the silicon-based capacitor 1003, the shapes of the third connection portion 1051 and the fourth connection portion 1052 are adjusted in the silicon-based capacitor 1004.

[0105] It should be noted that the shapes of the third connecting part 1051 and the fourth connecting part 1052 are not limited to those shown in the figure and can be adjusted as needed.

[0106] Figure 20 This is a cross-sectional view of a silicon-based capacitor provided according to an embodiment of the present invention. The silicon-based capacitor includes a first conductive connection layer 131 and a single second conductive connection layer 105. Figure 20 The cross-sectional view shown can be a cross-sectional view of silicon-based capacitor 1002, silicon-based capacitor 1003, or silicon-based capacitor 1004.

[0107] In embodiments of the present invention, when a single second conductive connection layer 105 is used, this second conductive connection layer 105 serves as the top conductive layer. When multiple second conductive connection layers 105 are used, the uppermost second conductive connection layer 105 serves as the top conductive layer.

[0108] In an embodiment of the present invention, the conductive connection structure 150 is used to connect a plurality of first connection portions 1311 in the first conductive connection layer 131 in parallel and / or connect a plurality of second connection portions 1312 in the first conductive connection layer 131 in parallel, and lead them out to the top conductive layer.

[0109] Figure 21 The simulation results are shown for the bandwidth of a silicon-based capacitor including a first conductive interconnect layer 131 and a single second conductive interconnect layer 105.

[0110] like Figure 21 As shown, in the simulation results of a silicon-based capacitor with multiple capacitor plates connected in parallel and including a first conductive connection layer 131 and a single second conductive connection layer 10, the simulated bandwidth of wideband performance reaches up to 200 GHz. Figure 21 In the diagram, the horizontal axis represents frequency, with the unit being GHz. Figure 21 The points on the horizontal axis are shown: 0, 20, 40, 60, 80, 100, 120, 140, 160, 180, and 200; Figure 21 The vertical axis on the left (dB S(1,1)) represents the return loss, in decibels (dB). Figure 21 The following points on the number line on the left vertical axis are shown: -50, -40, -30, -20, -10, and 0; Figure 21 The vertical axis on the right (dBS(2,1)) represents the insertion loss, in decibels (dB). Figure 21 The following points on the number line are shown on the right-hand vertical axis: -1.6, -1.4, -1.2, -1.0, -0.8, -0.6, -0.4, -0.2, and 0.0.

[0111] S(1,1) represents the reflection coefficient of port 1, which is related to the return loss. Return loss measures the degree of signal reflection; the greater the return loss, the lower the reflected power, the better the impedance matching, and the higher the signal transmission quality. S(2,1) represents the forward transmission coefficient, which is related to the insertion loss. Insertion loss reflects the energy loss of the signal during transmission; the closer the insertion loss is to zero, the higher the signal transmission efficiency and the better the performance.

[0112] Depend on Figure 21As shown on the left-hand vertical axis, the silicon-based capacitor provided in the embodiments of the present invention has a return loss of -11.522 dB at point m0 ​​at a frequency (freq) of 200.0 GHz. It still exhibits significant return loss at high frequencies, thus maintaining good matching performance. Figure 21 As can be seen from the vertical axis on the right, the silicon-based capacitor provided in the embodiment of the present invention has an insertion loss of -0.885dB at point m1 at a frequency (freq) of 200.0GHz. It still exhibits extremely low insertion loss at high frequencies, thereby ensuring high transmission efficiency.

[0113] For a silicon-based capacitor with conductive connection structure 150 including multiple second conductive connection layers 105, its broadband properties are not significantly different from those of a silicon-based capacitor with conductive connection structure 150 including a single second conductive connection layer 105 as shown above, and its parasitic parameters are better than those of a silicon-based capacitor with a single second conductive connection layer 105, that is, its parasitic parameters are smaller.

[0114] The silicon-based capacitor provided in the embodiments of the present invention relates to the field of semiconductor technology, specifically to a silicon-based capacitor adapted to broadband signal transmission in high-speed optical modules, and is particularly suitable for broadband decoupling, high-frequency matching and power integrity assurance scenarios of key components such as digital signal processors (DSPs), drivers and transimpedance amplifiers (TIAs) in 400G / 800G / 1.6T high-speed optical modules.

[0115] Where there is no conflict, features of the same embodiment and different embodiments of the present invention can be combined with each other.

[0116] The above are merely exemplary embodiments of the present invention and are not intended to limit the scope of protection of the present invention, which is determined by the appended claims.

Claims

1. A silicon-based capacitor, comprising: A silicon substrate having multiple structural units, each structural unit including trenches and platforms; Multiple conductive layers are used as capacitor plates, and the multiple conductive layers are stacked. The first interlayer insulating layer is located on the plurality of conductive layers; The first conductive connection layer is located on the first interlayer insulating layer; The second interlayer insulating layer is located on the first conductive connection layer; as well as A conductive connection structure is located on the second interlayer insulating layer and includes at least one second conductive connection layer. The first conductive connection layer includes a plurality of connection units periodically arranged in a plane, each connection unit including a first connection portion and a second connection portion that are separated from each other. Each first connection portion is connected to at least one of the plurality of conductive layers via a first connection element penetrating the first interlayer insulation layer, and each second connection portion is connected to the other conductive layers of the plurality of conductive layers via a second connection element penetrating the first interlayer insulation layer. The lower part of the conductive connection structure interconnects multiple first connection portions through a third connection element penetrating the second interlayer insulation layer, and interconnects multiple second connection portions through a fourth connection element penetrating the second interlayer insulation layer, and the upper part of the conductive connection structure serves as a capacitor pad area.

2. The silicon-based capacitor according to claim 1, wherein, Each connecting unit is a rectangular unit, and the first connecting portion and the second connecting portion included in each connecting unit correspond to the central region and the outer boundary region of the rectangular unit, respectively.

3. The silicon-based capacitor according to claim 1, wherein, The plurality of first connecting portions are separate from each other, at least some of the plurality of second connecting portions are spaced apart from each other in a first direction, at least some of the plurality of second connecting portions are spaced apart from each other in a second direction, and the first direction and the second direction intersect.

4. The silicon-based capacitor according to claim 3, wherein, The plurality of second connecting portions are connected to each other, and the plurality of connected second connecting portions have a plurality of hollow areas, and the plurality of first connecting portions are respectively located in the plurality of hollow areas.

5. The silicon-based capacitor according to claim 1, wherein, Each connecting unit comprises a first connecting portion and a second connecting portion arranged in adjacent strips.

6. The silicon-based capacitor according to claim 1, wherein, The plurality of first connecting portions are separate from each other, the plurality of second connecting portions are separate from each other, and the plurality of first connecting portions and the plurality of second connecting portions are alternately arranged.

7. The silicon-based capacitor according to claim 6, wherein, The plurality of first connecting portions and the plurality of second connecting portions are alternately arranged along a first direction, each first connecting portion extends along a second direction, each second connecting portion extends along a second direction, and the first direction and the second direction intersect.

8. The silicon-based capacitor according to claim 6, wherein, The opposite ends of the plurality of first connecting portions and the plurality of second connecting portions are interconnected respectively.

9. The silicon-based capacitor according to any one of claims 1-8, wherein, The plurality of conductive layers includes an odd number of conductive layers and an even number of conductive layers, and, Each first connection portion and each second connection portion are respectively connected to the odd-numbered conductive layer and the even-numbered conductive layer.

10. The silicon-based capacitor according to any one of claims 1, 5-8, wherein, The conductive connection structure includes a single second conductive connection layer, the single second conductive connection layer including a third connection portion and a fourth connection portion that are separated from each other, the third connection portion interconnecting the plurality of first connection portions, and the fourth connection portion interconnecting the plurality of second connection portions.

11. The silicon-based capacitor according to any one of claims 1-4, wherein, The conductive connection structure includes multiple second conductive connection layers, and an intermediate insulating layer is provided between adjacent second conductive connection layers.

12. The silicon-based capacitor according to claim 11, wherein, The conductive connection structure includes a lower second conductive connection layer and an upper second conductive connection layer. Each of the plurality of third connecting portions in the lower second conductive connection layer is used to interconnect at least a portion of the plurality of first connecting portions. Each of the plurality of fourth connecting portions in the lower second conductive connection layer is used to interconnect at least a portion of the plurality of second connecting portions. A fifth connecting portion in the upper second conductive connection layer interconnects the plurality of third connecting portions through a fifth connecting element penetrating the intermediate insulating layer. A sixth connecting portion in the upper second conductive connection layer interconnects the plurality of fourth connecting portions through a sixth connecting element penetrating the intermediate insulating layer.

13. The silicon-based capacitor according to claim 1, wherein, Each connection unit is provided with at least one structural unit, and the orthographic projections of the first connection element and the second connection element of each connection unit on the silicon substrate fall within the orthographic projections of the multiple platforms in the corresponding structural unit on the silicon substrate.

14. The silicon-based capacitor according to any one of claims 1-8, wherein, The multiple structural units are arranged in an array.

15. The silicon-based capacitor according to any one of claims 1-8, wherein, The material of the first conductive connection layer is different from the material of each of the plurality of conductive layers.

16. The silicon-based capacitor according to claim 15, wherein, The material of each of the plurality of conductive layers includes polycrystalline silicon or titanium nitride, or the material of one of the plurality of conductive layers includes doped silicon, and the material of the remaining conductive layers includes polycrystalline silicon.

17. The silicon-based capacitor according to any one of claims 1-8, wherein, The first conductive connection layer is made of metal, and the conductive connection structure is made of metal.

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