Optoelectronic transistor

Abstract

The present invention provides a phototransistor, which includes a first-conductivity-type substrate, a second-conductivity-type base region, and a first-conductivity-type patterned emitter region. The second-conductivity-type base region is disposed in the first-conductivity-type substrate. The first-conductivity-type patterned emitter region has a plurality of emitter sub-regions respectively disposed in the second-conductivity-type base region to increase electron injection paths.

Description

Technical Field

[0001] This invention relates to a phototransistor, and more particularly to a phototransistor that can improve current gain. Background Technology

[0002] A phototransistor is a semiconductor device that converts light signals into electrical signals. Similar to a traditional bipolar junction transistor (BJT), its base can be controlled by both current and light signals. Phototransistors are commonly used in optical detection applications, such as optocouplers and photodetectors.

[0003] The basic structure of a phototransistor is similar to that of a conventional bipolar junction transistor, typically consisting of an NPN or PNP structure. Please refer to [link to relevant documentation]. Figure 1 and Figure 2 This illustrates a conventional NPN structure phototransistor 1, which includes a substrate 10, a base region 20, an emitter region 30, an emitter electrode 40, and a collector electrode 50. Figure 2 So Figure 1 A cross-sectional view of line segment AA. When light shines on the base region 20 of the phototransistor, photons excite electrons, generating electron-hole pairs. These electrons and holes separate under the influence of an electric field and form the base-collector current (I0). BC Due to the electron flow in the base region, the generated electrons mainly flow to the emitter region 30, and the emitter-collector current (I) EC ) increases accordingly. I EC Usually more than I BC The gain is large because most of the photogenerated electrons flow out through the emitter region 30, which is also the gain effect of the phototransistor. Among them, I... EC with I BC With I EC =βx I BC The relationship is that β is the current gain (hFE) of the phototransistor, which is greater than 1 and is usually between tens and hundreds.

[0004] like Figure 3 As shown, it displays the outer contour pattern of the emitter region 30 in a conventional phototransistor 1, typically featuring a simple circular, square, or polygonal outline. This emitter region design limits the current gain that can be achieved, failing to meet the demands of next-generation optoelectronic devices for higher photocurrent gain, higher breakdown voltage, and lower leakage current. Therefore, the industry urgently needs an innovative phototransistor structure to meet the high-efficiency requirements of next-generation phototransistors. Summary of the Invention

[0005] The main objective of this invention is to provide an innovative phototransistor that increases the photocurrent gain, improves voltage resistance, reduces leakage current, and enhances device performance.

[0006] To achieve the above objectives, the present invention provides a phototransistor comprising a first conductivity type substrate, a second conductivity type base region, and a first conductivity type patterned emitter region. The second conductivity type base region is disposed within the first conductivity type substrate. The first conductivity type patterned emitter region has multiple emitter sub-regions respectively disposed within the second conductivity type base region to increase electron injection paths.

[0007] In one embodiment of the phototransistor of the present invention, each emitter sub-region of the first conductive patterned emitter region is a gate-shaped region and is dispersed in the second conductive base region.

[0008] In one embodiment of the phototransistor of the present invention, each emitter sub-region of the first conductive patterned emitter region is arranged in a grid pattern and dispersed in the second conductive base region.

[0009] In one embodiment of the present invention, the phototransistor further includes an emitter electrode electrically connected to a first conductive patterned emitter region.

[0010] In one embodiment of the present invention, the phototransistor includes an emitter electrode comprising an extension portion and an outer ring portion. The outer ring portion is disposed on an edge of a second conductivity type base region, and the extension portion extends from the outer ring portion to a first conductivity type patterned emitter region and is electrically connected to each emitter sub-region of the first conductivity type patterned emitter region.

[0011] In one embodiment of the present invention, the phototransistor has an extension having a hollow ring shape, disposed on the edge of the patterned emitter region relative to the first conductivity type.

[0012] In one embodiment of the phototransistor of the present invention, the first conductivity substrate is a collector.

[0013] The phototransistor in one embodiment of the present invention further includes a collector electrode disposed on one side of a first conductivity substrate.

[0014] In a phototransistor of one embodiment of the present invention, the width (W) of each emitter region E It needs to be greater than 20 micrometers (μm).

[0015] In one embodiment of the phototransistor of the present invention, the width (W) of the second conductivity type base region between adjacent emitter regions B It needs to be greater than 6 micrometers (μm).

[0016] In a phototransistor according to one embodiment of the present invention, the ratio of the area of ​​the second conductivity type base region to the total area of ​​the first conductivity type patterned emitter region must be not less than 0.09.

[0017] To achieve the above objectives, the present invention provides a phototransistor comprising a first substrate, a base region, and a patterned emitter region. The base region is disposed within the substrate. Multiple discontinuous PN junctions are provided between the patterned emitter region and the base region to increase the electron injection path.

[0018] In another embodiment of the phototransistor, each discontinuous PN junction of the patterned emitter region is a gate-shaped structure, which is dispersed in the base region.

[0019] In another embodiment of the phototransistor, the discontinuous PN junctions of the patterned emitter region are arranged in a grid pattern and dispersed in the base region.

[0020] In another embodiment of the present invention, the phototransistor further includes an emitter electrode electrically connected to the patterned emitter region.

[0021] In one embodiment of the present invention, the substrate of the phototransistor is a collector.

[0022] The phototransistor in one embodiment of the present invention further includes a collector electrode disposed on one side of the substrate.

[0023] In one embodiment of the phototransistor of the present invention, the width (W) of the patterned emitter region between each discontinuous PN junction is... E It needs to be greater than 20 micrometers (μm).

[0024] In one embodiment of the phototransistor of the present invention, the width (W) of the base region between each discontinuous PN junction is... B It needs to be greater than 6 micrometers (μm).

[0025] In one embodiment of the present invention, the ratio of the area of ​​the base region to the total area of ​​the patterned emitter region in the phototransistor must be not less than 0.09.

[0026] Other objects of the present invention, as well as the technical means and implementation methods of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description

[0027] Figure 1 This is a top view of a traditional phototransistor;

[0028] Figure 2 for Figure 1 A cross-sectional view of line segment AA in the middle;

[0029] Figure 3This is a schematic diagram of the outer contour of the emitter region in a traditional phototransistor.

[0030] Figure 4 This is a top view schematic diagram of a phototransistor in one embodiment of the present invention;

[0031] Figure 5 for Figure 4 A cross-sectional view of line segment BB in the middle;

[0032] Figure 6 This is a schematic diagram of the outer contour of several gate-type emitter regions in the phototransistor of the present invention;

[0033] Figure 7 This is a schematic diagram of the outer contour of several grid-type emitter regions in the phototransistor of the present invention;

[0034] Figure 8 This is a schematic diagram showing the hFE lifetime test results of the base region versus emitter region in the phototransistor of the present invention under different area ratios;

[0035] Figure 9 This is a top view schematic diagram of a phototransistor according to another embodiment of the present invention; and

[0036] Figure 10 for Figure 9 A cross-sectional view of the CC line segment.

[0037] Explanation of reference numerals in the attached figures

[0038] 1. Phototransistor

[0039] 10 Substrates

[0040] 20 Base region

[0041] 30 radiating region

[0042] 40 Emitter electrode

[0043] 50 Collector Electrode

[0044] 100 phototransistors

[0045] 110 substrate

[0046] 120 Base Region

[0047] 130° radiating zone

[0048] 132 Emitter Region

[0049] 140 Emitter Electrode

[0050] 142 Extension

[0051] 144 Outer Ring Road

[0052] 150 collector electrode

[0053] 160 transparent dielectric layer

[0054] AA section line

[0055] BB profile

[0056] CC section line

[0057] I BC Base collector current

[0058] I EC emitter-collector current

[0059] N First conductivity type

[0060] P Second conductivity type

[0061] W E width

[0062] W B width. Detailed Implementation

[0063] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and accompanying drawings, elements not directly related to this invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0064] This invention relates to a phototransistor, and more particularly, to a phototransistor design that increases photocurrent gain and withstands high voltage. Please refer to both sources. Figure 4 and Figure 5 ,in, Figure 4 This shows a top view schematic diagram of a phototransistor according to one embodiment of the present invention. Figure 5 show Figure 4 A cross-sectional schematic diagram of line segment BB in the middle. The phototransistor 100 has a substrate 110, a base region 120, an emitter region 130, an emitter electrode 140 and a collector electrode 150.

[0065] like Figure 5 As shown, in a specific embodiment, the substrate 110 can be epitaxially formed with a first conductivity type compound semiconductor layer, such as an N-type gallium arsenide (GaAs) layer, and then sulfur (S) or silicon (Si) is used as an N-type dopant for, for example, 10 15 ~10 17 / cm 3Low concentration doping is permitted, but not limited to this. The base region 120 is a second conductivity type compound semiconductor layer disposed in the substrate 110, for example, it can be a p-type gallium arsenide (GaAs) layer, doped with zinc (Zn) or magnesium (Mg) as a p-type dopant to achieve, for example, 10... 17 ~10 19 / cm 3 The emitter region 130 is a first conductivity type compound semiconductor layer disposed in a central region of the light-receiving region 120. The emitter region 130 may be an N-type gallium arsenide (GaAs) layer, which is doped with sulfur (S) or silicon (Si) as an N-type dopant to achieve, for example, a doping concentration of 10. 18 ~10 20 / cm 3 The concentration of heavy doping, but not limited to this.

[0066] In this embodiment, the structure of the phototransistor 100 is based on an NPN bipolar junction transistor. The substrate 110 serves as the collector of the phototransistor 100, the base region 120 serves as the base of the phototransistor 100, and the emitter region 130 serves as the emitter of the phototransistor 100. Furthermore, the emitter electrode 140 serves as the electrode of the emitter region, is disposed on and electrically connected to the emitter region 130. The collector electrode 150 serves as the collector electrode, is disposed on one side of the substrate 110, and is electrically connected to the substrate 110.

[0067] When the surface of the base region 120 is exposed to external light, it can effectively absorb photons to excite electrons, resulting in the generation of electron-hole pairs, which are then separated under the influence of an electric field to form a current. These electron and hole pairs are collected between the base region 120 and the substrate 110, forming the base-collector current (I0). BC On the other hand, due to the electron flow in the base region 120, the emitter-collector current (I) between the emitter region 130 and the substrate 110... EC The current will increase accordingly, thus generating a current gain effect. In another possible embodiment, the structure of the phototransistor 100 of the present invention can also be a PNP bipolar junction transistor. Those skilled in the art can easily extrapolate this after learning about the present invention. The following will only use an NPN bipolar junction transistor as an example to specifically illustrate the relevant technical features of the present invention.

[0068] This invention addresses the problem of poor photocurrent gain efficiency in traditional phototransistors. One of its key technical features is the provision of an innovative emitter structure. For example... Figure 4 and Figure 5The emitter region 130 shown has a patterned outline, forming a patterned emitter region. More specifically, unlike conventional emitter regions which have a complete outline such as a circle or square, the patterned emitter region 130 in the phototransistor of the present invention has multiple emitter sub-regions 132, each emitter sub-region 132 being discontinuously and independently distributed in the base region 120. In this embodiment, since the emitter region 130 is an N-type doped compound semiconductor layer and the base region 120 is a P-type doped compound semiconductor layer, multiple discontinuous PN junctions are formed between each emitter sub-region 132 and the base region 120. The total area of ​​these discontinuous PN junctions is significantly increased compared to the contact area of ​​a conventional emitter region and base region with a complete and continuous outline, thereby increasing the electron injection path. As a result, when illumination is turned on, a base-collector current (I0) is formed between the base region 120 and the substrate 110. BC This results in an emitter-collector current (I) between the emitter region 130 and the substrate 110. EC When the patterned emitter region 130 and base region 120 increase in contact area, the electron injection path between the contact areas will increase significantly, thereby improving the current gain. It should be noted that the phototransistor structure also includes a transparent dielectric layer 160, such as an oxide layer, disposed between the emitter electrode 140 and the base region 120. Besides allowing external light to pass through and be absorbed by the base region 120, it also serves as an electrical isolation layer. Figure 5 As shown. However, for the purpose of clear display and explanation, in Figure 4 The transparent dielectric layer 160 is omitted in the top view; only the positions of the base region 120, emitter region 130, and emitter electrode 140 are shown to clearly show the positional relationship between these three elements.

[0069] Please refer to both together. Figure 6 and Figure 7 It shows a schematic diagram of several patterned emitter regions 130 in the phototransistor of the present invention. Among them, Figure 6 The patterned emitter region 130 is displayed with each emitter sub-region 132 arranged in a grid shape. On the other hand, Figure 7 The patterned emitter region 130 displays emitter sub-regions 132 arranged in a grid pattern. It should be noted that... Figure 6 and Figure 7The patterned outline shown is for illustrative purposes only and is not intended to limit the invention. The patterned outline of the emitter region 130 can be adjusted according to the needs of the device design and current gain. For example, the patterned design of the emitter region 130 may also include multiple emitter sub-regions 132 arranged in concentric rings, or multiple emitter sub-regions 132 arranged in independent island shapes, and the shapes of these independent island shapes can be circular, triangular, or other polygonal. Furthermore, since the contact area between the base region 120 and the patterned emitter region 130 in the phototransistor of the present invention is increased, the depletion region formed at the PN junction between these two interfaces will increase when there is no external light, thereby suppressing the surface leakage current of the phototransistor. On the other hand, as the contact area between the base region 120 and the patterned emitter region 130 increases, the impedance between the base region 120 and the emitter region 130 also increases, thereby increasing the breakdown voltage of the phototransistor.

[0070] Furthermore, considering the limitation of saturation current, the emitter region 130 in the phototransistor of this invention is designed as follows: Figure 6 and Figure 7 The following factors must be considered when designing the pattern: (1) the width of each patterned emitter region 130 (i.e., the width of each emitter region 132, or the width between discontinuous PN junctions, W) E (1) The width of the base region 120 should be greater than 20 micrometers (μm), with 40 micrometers (μm) being preferred. (2) Based on process considerations, the width (W) of the base region 120 between adjacent emitter regions 132 (or between discontinuous PN junctions) should be greater than 20 micrometers (μm), with 40 micrometers (μm) being preferred. B (2) The area of ​​the base region 120 must be greater than 6 micrometers (μm) to avoid "mutual interference" between adjacent emitter regions. This "mutual interference" includes effects such as cross-linking caused by ion diffusion or overlapping depletion regions. (3) The ratio of the area of ​​the base region 120 to the total area of ​​the patterned emitter regions 132 must be no less than 0.09 to avoid hFE (DC current gain) lifetime degradation due to current congestion. Please refer to [link to relevant documentation]. Figure 8 This displays the hFE lifetime test results for different base-to-emitter area ratios in phototransistors. Figure 8 Part (A) shows that when the base-to-emitter area ratio is less than 0.09, current congestion will occur, leading to a decrease in hFE lifetime. On the other hand, Figure 8 Part (B) shows that when the area ratio of the base region to the emitter region is not less than (i.e., greater than or equal to) 0.09, there is no hFE lifetime decay phenomenon.

[0071] For example, if we define α as ΔI C / ΔI EC ≈I C / I ECIt can be deduced that:

[0072] I C = α x I EC (Equation 1)

[0073] Among them, I C This represents the collector current, and Δ represents the increment.

[0074] According to Kirchhoff's Current Law (Circuit Laws):

[0075] I EC = I C + I BC (Equation 2)

[0076] In equation 1, I C Substituting into equation 2, we get:

[0077] I EC = α x I EC + I BC , that is, I BC = (1- α) x I EC (Equation 3)

[0078] According to the definition of β, β(hFE) = I C / I BC (Equation 4)

[0079] Substituting equations 1 and 3 into equation 4, we get:

[0080] β=(αx I EC ) / ((1–α)x I EC Finally, it can be deduced that:

[0081] β=α / (1–α)

[0082] Since α can be approximated as α≈γx aT, where γ is the ratio of the minority carrier current injected from the emitter region to the base region to the total emitter current (emitter injection efficiency), and aT is the ratio of the minority carriers reaching the collector region to the minority carriers injected into the base region (transmission efficiency ratio), we can obtain:

[0083] β≈γx aT / (1-γx aT)

[0084] Taking a square emitter region design with a size of approximately 125 micrometers (μm) as an example, if it is patterned and divided into five parts, the injection efficiency can be increased by about 23%. Based on the above formula, it is estimated that hFE (DC current gain) can be increased by about 0.12% without increasing additional costs.

[0085] Please see Figure 9 and Figure 10 ,in Figure 9 This shows a top view of a phototransistor according to another embodiment of the present invention. Figure 10 Then it will display Figure 9 A cross-sectional view of the CC segment. In this embodiment, the emitter electrode 140 includes an extension 142 and an outer ring 144. The extension 142 extends from the outer ring 144 to the emitter region 130 and is electrically connected to the emitter region 130. To increase the light-receiving area of ​​the base region 120 and avoid excessively blocking the light-receiving area of ​​the base region 120 below the emitter region 130, the extension 142 above the emitter region 130 is designed as a hollow ring, disposed on the edge of each emitter sub-region 132 opposite to the emitter region 130, and electrically connected to each emitter sub-region 132. The hollow ring-shaped extension 142 can substantially reduce the blocking of the light-receiving base region below the emitter region, thereby increasing the base collector current (I0). BC Combined with the effect of patterned emitter regions increasing current gain, the optimal photocurrent gain is achieved through the synergistic effect of the two. In particular, this improvement in current gain not only enhances the performance of optical components but can also be achieved without increasing manufacturing costs, thus satisfying the optimal design of the components.

[0086] The above embodiments are merely illustrative of implementation schemes of the present invention and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of the present invention, and the scope of protection of the present invention should be determined by the claims.

Claims

1. A phototransistor, comprising: A first conductivity type substrate; A second conductivity type base region is disposed in the first conductivity type substrate; and A first conductivity type patterned emitter region has multiple emitter sub-regions respectively disposed in the second conductivity type base region to increase the electron injection path.

2. The phototransistor of claim 1, wherein the emitter sub-region of the first conductivity type patterned emitter region is a gate type and is dispersed in the second conductivity type base region.

3. The phototransistor of claim 1, wherein the emitter region of the first conductivity type patterned emitter region is in the form of a grid and is dispersed in the second conductivity type base region.

4. The phototransistor of claim 1 further comprises an emitter electrode electrically connected to the first conductivity patterned emitter region.

5. The phototransistor of claim 4, wherein the emitter electrode includes an extension and an outer ring, the outer ring being disposed on an edge of the second conductivity base region, the extension extending from the outer ring to the first conductivity patterned emitter region and electrically connected to each of the emitter sub-regions of the first conductivity patterned emitter region.

6. The phototransistor of claim 5, wherein the extension has a hollow ring shape disposed on the edge opposite to the first conductive patterned emitter region.

7. The phototransistor of claim 1, wherein the first conductivity substrate is a collector.

8. The phototransistor of claim 7 further comprises a collector electrode disposed on one side of the first conductivity substrate.

9. The phototransistor of claim 1, wherein the width of each emitter region is greater than 20 micrometers.

10. The phototransistor of claim 1, wherein the width of the second conductivity base region between adjacent emitter regions is greater than 6 micrometers.

11. The phototransistor of claim 1, wherein the ratio of the area of ​​the second conductivity type base region to the total area of ​​the first conductivity type patterned emitter region is not less than 0.

09.

12. A phototransistor, comprising: A substrate; A base region is disposed in the substrate; and A patterned emitter region with multiple discontinuous PN junctions between it and the base region to increase the electron injection path.

13. The phototransistor of claim 12, wherein the discontinuous PN junction of the patterned emitter region is a gate-shaped structure and is distributed in the base region.

14. The phototransistor of claim 12, wherein the discontinuous PN junction of the patterned emitter region is in the form of a grid and is distributed in the base region.

15. The phototransistor of claim 12, further comprising an emitter electrode electrically connected to the patterned emitter region.

16. The phototransistor of claim 12, wherein the substrate is a collector.

17. The phototransistor of claim 16, further comprising a collector electrode disposed on one side of the substrate.

18. The phototransistor of claim 12, wherein the width of the patterned emitter region between each of the discontinuous PN junctions is greater than 20 micrometers.

19. The phototransistor of claim 12, wherein the width of the base region between each of the discontinuous PN junctions is greater than 6 micrometers.

20. The phototransistor of claim 12, wherein the ratio of the area of ​​the base region to the total area of ​​the patterned emitter region is not less than 0.09.

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