image sensor

Abstract

The image sensor may include a semiconductor substrate, an isolation structure in the semiconductor substrate defining a first pixel region and a second pixel region, a transfer gate electrode on the first pixel region, a floating diffusion region in the first pixel region and at the side of the transfer gate electrode, a pixel gate electrode on the second pixel region, a source / drain region in the second pixel region and at the side of the pixel gate electrode, and a connecting conductive pattern on a first surface of the semiconductor substrate connecting the floating diffusion region to the source / drain region. The connecting conductive pattern includes an edge portion adjacent to its outer side surface and a blocking pattern between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0194686, filed on December 23, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some example embodiments relate to an image sensor, and more specifically, to an image sensor with improved electrical and / or optical properties. Background Technology

[0004] An image sensor is, or includes, a device that converts light signals into electrical signals. With the latest developments in the computer and communications industries, there is an increasing demand for high-performance image sensors in a variety of applications, such as digital cameras, camcorders, personal communication systems, gaming consoles, security cameras, miniature cameras for medical applications, and / or robots. Summary of the Invention

[0005] Image sensors are generally classified into charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS) image sensors. CMOS image sensors can operate in a simplified manner, and because the signal processing circuitry of a CMOS image sensor can be integrated on a single chip, the size of products using them can be reduced. Alternatively or additionally, because CMOS image sensors can operate with relatively low power consumption, they can be more easily applied to electronic devices with limited battery capacity. Alternatively or additionally, because CMOS image sensors can be manufactured using existing CMOS manufacturing technologies, their manufacturing costs can be reduced. Alternatively or additionally, due to the increasing resolution of CMOS image sensors, their use is rapidly increasing.

[0006] Some example embodiments provide an image sensor with improved electrical and optical properties.

[0007] According to some example embodiments, an image sensor may include a semiconductor substrate, a PD isolation structure in the semiconductor substrate defining a first pixel region and a second pixel region, a transfer gate electrode on the first pixel region, a floating diffusion region in the first pixel region and at the side of the transfer gate electrode, a pixel gate electrode on the second pixel region, a source / drain region in the second pixel region and at the side of the pixel gate electrode, and a connection conductive pattern on a first surface of the semiconductor substrate connecting the floating diffusion region to the source / drain region, the connection conductive pattern including an edge portion adjacent to the outer surface of the connection conductive pattern, and a blocking pattern between the edge portion of the connection conductive pattern and the first surface of the semiconductor substrate.

[0008] Alternatively or additionally, according to some example embodiments, the image sensor may include a semiconductor substrate, a PD isolation structure in the semiconductor substrate and in a first pixel region and a second pixel region, a first photoelectric conversion element and a second photoelectric conversion element in the first pixel region and the second pixel region, respectively, a first transmission gate electrode in the first pixel region and a first floating diffusion region on the side of the first transmission gate electrode, a second transmission gate electrode in the second pixel region and a second floating diffusion region on the side of the second transmission gate electrode, a plurality of pixel gate electrodes provided in the first pixel region and the second pixel region, and a plurality of source / drain regions provided on the first side and the second side of each of the pixel gate electrodes, a connecting conductive pattern connecting the first floating diffusion region and the second floating diffusion region to the first source / drain region as one of the source / drain regions, the connecting conductive pattern including a first connection portion contacting the first floating diffusion region and the second floating diffusion region, and a second connection portion extending from the first connection portion and contacting the first source / drain region, and a blocking pattern between the bottom surface of the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

[0009] According to some example embodiments, an image sensor may include a semiconductor substrate having a first surface and a second surface opposite to each other; a PD isolation structure defining a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region within the semiconductor substrate; a plurality of photoelectric conversion elements within the first to fourth pixel regions and within the semiconductor substrate; a device isolation layer adjacent to the first surface of the semiconductor substrate and defining a first active portion and a second active portion in each of the first to fourth pixel regions; a plurality of transfer gate electrodes on the first active portion of the first to fourth pixel regions; a plurality of floating diffusion regions in the first active portion and respectively in the first to fourth pixel regions; and a plurality of floating diffusion regions on the second active portion. The first to fourth pixel regions contain multiple pixel transistors, a connecting conductive pattern on a first surface of a semiconductor substrate and in contact with a floating diffusion region in the first to fourth pixel regions and a first source / drain region of one of the pixel transistors, the connecting conductive pattern including an edge portion adjacent to the outer edge surface of the connecting conductive pattern and a pad portion in contact with the floating diffusion region and the first source / drain region, a blocking pattern between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate, multiple color filters on a second surface of the semiconductor substrate corresponding to the pixel regions, a grid structure between the color filters and at least partially overlapping with the PD isolation structure, and multiple microlenses on the multiple color filters.

[0010] Alternatively or additionally, according to some example embodiments, a method of manufacturing an image sensor device is provided, the method comprising: forming a photoelectric conversion element in a substrate; forming an isolation structure in the substrate; forming a transmission gate electrode on the substrate, the transmission gate electrode being at least partially in the photoelectric conversion element; forming a first floating diffusion region in the substrate; conformally forming a spacer insulating layer on an upper surface of the substrate and on an upper surface of the transmission gate electrode; forming a first mask pattern on the spacer insulating layer and defining an opening over a portion of the first floating diffusion region; etching the spacer insulating layer exposed by the first mask pattern; forming a second floating diffusion pattern in the first floating diffusion pattern; conformally forming a conductive layer over the substrate and the spacer insulating layer; forming a second mask pattern over a portion of the conductive layer at least partially over the second floating diffusion region; and etching the spacer insulating pattern while leaving a remaining blocking pattern on the surface of the substrate and adjacent to the second floating diffusion region.

[0011] In some example embodiments, the transmission gate electrode may be formed in the substrate and may also be formed in the photoelectric conversion element.

[0012] In some example embodiments, the depth of the second floating diffusion region may be less than the depth of the first floating diffusion region.

[0013] In some example embodiments, forming the first floating diffusion region may include implanting a dopant into the substrate with a first energy.

[0014] In some exemplary embodiments, forming a second floating diffusion region may include implanting a dopant into the substrate with a second energy less than the first energy. Attached Figure Description

[0015] Figure 1 This is a circuit diagram illustrating a unit pixel of a pixel array according to some example embodiments.

[0016] Figure 2 This is a plan view showing a unit pixel of an image sensor according to some example embodiments.

[0017] Figure 3A It is along Figure 2 The line A-A' is cut to show a cross-sectional view of an image sensor according to some example embodiments.

[0018] Figure 3B It is shown Figure 3A An enlarged cross-sectional view of part "P1".

[0019] Figure 4A It is along Figure 2 The line B-B' is cut to show a cross-sectional view of an image sensor according to some example embodiments.

[0020] Figure 4B It is shown Figure 4A An enlarged cross-sectional view of part "P2".

[0021] Figure 5A and Figure 5C It is along Figure 2 A cross-sectional view taken along line C-C' to illustrate an image sensor according to some example embodiments.

[0022] Figure 5B It is shown Figure 5A An enlarged cross-sectional view of the “P3” section.

[0023] Figure 6A , Figure 6B and Figure 6C It is along Figure 2 A cross-sectional view taken by line D-D' to illustrate an image sensor according to some example embodiments.

[0024] Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a plan view illustrating an image sensor according to some example embodiments.

[0025] Figures 12 to 19 It is along Figure 2 A cross-sectional view taken along line A-A' to illustrate a method of manufacturing an image sensor according to some example embodiments.

[0026] Figure 20 This is a plan view illustrating an image sensor according to some example embodiments.

[0027] Figure 21 This is a schematic plan view of an image sensor according to some example embodiments.

[0028] Figure 22 and Figure 23 It is along Figure 21 A cross-sectional view taken by line I-I' to illustrate an image sensor according to some example embodiments. Detailed Implementation

[0029] Some exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are illustrated.

[0030] Figure 1 This is a circuit diagram illustrating a unit pixel of a pixel array according to some example embodiments.

[0031] Reference Figure 1An image sensor may include multiple unit pixels arranged in a two-dimensional arrangement (e.g., arranged as a two-dimensional array), and each unit pixel PX may be configured to convert an optical signal into an electrical signal.

[0032] A unit pixel PX may include photoelectric conversion circuit 1 and pixel circuit 2.

[0033] The photoelectric conversion circuit 1 may include multiple photoelectric conversion groups 1a, 1b, 1c, and 1d. The photoelectric conversion circuit 1 may include at least 4, 8, or 16 photoelectric conversion groups 1a, 1b, 1c, and 1d. In some example embodiments, the number of photoelectric conversion groups is a power of 2; however, the example embodiments are not limited thereto. Each of the photoelectric conversion groups 1a, 1b, 1c, and 1d may include at least two photoelectric conversion devices (e.g., photodiodes), multiple transmission transistors, and a floating diffusion region. Each of the photoelectric conversion groups 1a, 1b, 1c, and 1d may include 4, 8, or 16 photoelectric conversion devices.

[0034] In some example embodiments, the photoelectric conversion circuit 1 may include a first photoelectric conversion group 1a, a second photoelectric conversion group 1b, a third photoelectric conversion group 1c, and a fourth photoelectric conversion group 1d.

[0035] The first photoelectric conversion group 1a may include a first photodiode PD1, a second photodiode PD2, a first transfer transistor TX1, and a second transfer transistor TX2. The first transfer transistor TX1 and the second transfer transistor TX2 may be configured to transfer the charge accumulated in the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 to the floating diffusion region FD.

[0036] The second photoelectric conversion group 1b may include a third photodiode PD3, a fourth photodiode PD4, a third transfer transistor TX3, and a fourth transfer transistor TX4. The third transfer transistor TX3 and the fourth transfer transistor TX4 may be configured to transfer the charge accumulated in the third photoelectric conversion devices PD3 and PD4 to the floating diffusion region FD. The third photoelectric conversion group 1c may include a fifth photodiode PD5, a sixth photodiode PD6, a fifth transfer transistor TX5, and a sixth transfer transistor TX6. The fifth transfer transistor TX5 and the sixth transfer transistor TX6 may be configured to transfer the charge accumulated in the fifth photoelectric conversion devices PD5 and PD6 to the floating diffusion region FD. The fourth photoelectric conversion group 1d may include a seventh photodiode PD7, an eighth photodiode PD8, a seventh transfer transistor TX7, and an eighth transfer transistor TX8. The seventh transfer transistor TX7 and the eighth transfer transistor TX8 may be configured to transfer the charge accumulated in the seventh photoelectric conversion devices PD7 and PD8 to the floating diffusion region FD.

[0037] In some example embodiments, each of the first transmission transistor TX1 to the eighth transmission transistor TX8 may have the same electrical and / or physical properties; however, the example embodiments are not limited thereto. Alternatively or additionally, in some example embodiments, each of the photodiodes PD1 to PD8 may have the same electrical and / or physical characteristics; however, the example embodiments are not limited thereto.

[0038] The first to fourth photoelectric conversion groups 1a, 1b, 1c, and 1d can be connected together to the floating diffusion region FD. For example, the first transmission transistor TX1 to the eighth transmission transistor TX8 can be connected together to the floating diffusion region FD.

[0039] Each of the first to fourth photoelectric conversion groups 1a, 1b, 1c and 1d is illustrated to include two photodiodes, but the exemplary embodiments are not limited thereto. Each photoelectric conversion group may include four or eight photodiodes, or more than eight photodiodes.

[0040] The transfer gate electrodes of the first transfer transistor TX1 to the eighth transfer transistor TX8 can be controlled by the first charge transfer signal TG1 to the eighth charge transfer signal TG8. As described herein, the transfer gate electrode of each transfer transistor can have a dual vertical gate structure. A dual vertical gate structure can refer to a structure that provides two vertical transfer gates to correspond to a single photodiode. The two vertical transfer gates in a dual vertical gate structure can be applied with the same transfer control signal.

[0041] The floating diffusion region FD can be configured to receive and cumulatively store the charge generated in at least one of the first photodiodes PD1 to the eighth photodiode PD8. The source follower transistor SF can be controlled by the amount of photocharge accumulated in the floating diffusion region FD.

[0042] Pixel circuit 2 may include a reset transistor RX, a source follower transistor SF, a select transistor SX, and a dual-conversion gain transistor DCX. In some example embodiments, each of the unit pixels PX is shown as including four pixel transistors, but the example embodiments are not limited thereto. The number of pixel transistors in each unit pixel PX may vary.

[0043] Specifically, by applying a reset signal RG to the reset gate electrode, the reset transistor RX can reset (e.g., periodically reset) the charge accumulated in the floating diffusion region FD. Specifically, the reset transistor RX may include a source terminal and a drain terminal, the source terminal being connected to either the dual-conversion gain transistor DCX or the floating diffusion region FD, and the drain terminal being connected to the pixel power supply voltage VPIX. If the reset transistor RX and the dual-conversion gain transistor DCX are turned on, the pixel power supply voltage VPIX can be transferred to the floating diffusion region FD. Therefore, the charge accumulated in the floating diffusion region FD can be released to reset the floating diffusion region FD.

[0044] A dual conversion gain transistor (DCX) can be provided between and connected to the floating diffusion region (FD) and the reset transistor (RX). The DCX can change the capacitance of the floating diffusion region (FD) in response to a dual conversion gain control signal (DCG), thereby changing the conversion gain per pixel (PX).

[0045] In detail, during image capture, both low-brightness and high-brightness light can be incident on the pixel array, and the dual-conversion-gain transistor DCX can be turned on in high-brightness mode and turned off in low-brightness mode. Due to the dual-conversion-gain transistor DCX, different conversion gains can be achieved in high-brightness and low-brightness modes.

[0046] If the dual-conversion-gain transistor DCX is turned on, the capacitance of the floating diffusion region FD can increase and the conversion gain can decrease; conversely, if the dual-conversion-gain transistor DCX is turned off, the capacitance of the floating diffusion region FD can decrease and the conversion gain can increase.

[0047] The source follower transistor SF may be, or may include, a source follower buffer amplifier, or be included within a source follower buffer amplifier. The source follower buffer amplifier is configured to generate a source-drain current proportional to the charge of the floating diffusion region FD to be input to the source follower gate electrode. The source follower transistor SF can amplify changes in the potential of the floating diffusion region FD, and the amplified signal can be output to the output line Vout via the select transistor SX. The source follower transistor SF may include a drain terminal and a source terminal, with the drain terminal connected to the pixel power supply voltage VPIX and the source terminal connected to the drain terminal of the select transistor SX.

[0048] The select transistor SX can be used to select a row of unit pixels P to be read during a read operation. When the select transistor SX is turned on by applying the select signal SG to the select gate electrode, the electrical signal output to the source electrode of the source follower transistor SF can be output to the output line Vout.

[0049] Figure 2 This is a plan view showing a unit pixel of an image sensor according to some example embodiments. Figure 3A , Figure 4A , Figure 5A and Figure 6A They are respectively along Figure 2 Cross-sectional views taken along lines A-A', B-B', C-C', and D-D' to illustrate an image sensor according to some example embodiments.

[0050] Figure 3B It is shown Figure 3A An enlarged cross-sectional view of part "P1". Figure 4B It is shown Figure 4A An enlarged cross-sectional view of part "P2". Figure 5B It is shown Figure 5A An enlarged cross-sectional view of the “P3” section. Figure 5C It is along Figure 2 The cross-sectional view taken by line C-C', and Figure 6B and Figure 6C It is along Figure 2 The cross-sectional view taken by line D-D'.

[0051] Reference Figure 2 , Figure 3A , Figure 4A , Figure 5A and Figure 6A An image sensor according to some example embodiments may include a photoelectric conversion circuit layer 10, a pixel circuit layer 20, and an optical transparency layer 30.

[0052] When viewed in a vertical cross-section, the photoelectric conversion circuit layer 10 can be disposed between the pixel circuit layer 20 and the optically transparent layer 30. The photoelectric conversion circuit layer 10 may include a semiconductor substrate 100, a PD isolation structure PIS, a device isolation layer STI, photoelectric conversion elements 110a, 110b, 110c and 110d, transmission gate electrodes TG1, TG2, TG3 and TG4, and floating diffusion regions FD1 and FD2.

[0053] Pixel circuit layer 20 may include pixel circuitry (e.g., MOS transistors such as NMOS and / or PMOS transistors) electrically connected to the floating diffusion regions FD1 and FD2. For example, pixel circuit layer 20 may include a reference... Figure 1 The described reset transistor RX, select transistor SX, dual-conversion gain transistor DCX, and source follower transistor SF, and connected to... Figure 1 The interconnects of pixel circuit 2.

[0054] Specifically, the semiconductor substrate 100 may have a first or front surface 100a and a second or rear surface 100b opposite to each other. The semiconductor substrate 100 may be or may include a substrate comprising a bulk silicon substrate and epitaxial layers, the bulk silicon substrate and epitaxial layers being sequentially stacked and having a first conductivity type (e.g., p-type), and in cases where the bulk silicon substrate is removed during the fabrication of the image sensor, the semiconductor substrate 100 may consist only of p-type epitaxial layers. In some example embodiments, the semiconductor substrate 100 may be or may include a bulk semiconductor substrate comprising a well of a first conductivity type.

[0055] The semiconductor substrate 100 may include a plurality of pixel regions PR1, PR2, PR3 and PR4 defined by the PD isolation structure PIS. The pixel regions PR1, PR2, PR3 and PR4 may be arranged on a first direction D1 and a second direction D2 that are not parallel to each other, or arranged in a matrix shape.

[0056] The pixel region may include a first pixel region PR1, a second pixel region PR2, a third pixel region PR3, and a fourth pixel region PR4. The first pixel region PR1 and the second pixel region PR2 may be arranged adjacent to each other in a first direction D1, and the first pixel region PR1 and the third pixel region PR3 may be arranged adjacent to each other in a second direction D2. The second pixel region PR2 and the fourth pixel region PR4 may be adjacent to each other in the second direction D2, and the second pixel region PR2 and the third pixel region PR3 may be arranged diagonally. Here, the first direction D1 and the second direction D2 may be parallel to the first surface 100a of the semiconductor substrate 100, and may not be parallel to each other; for example, they may intersect at an angle such as 90 degrees. The third direction D3 may be perpendicular to the first surface 100a of the semiconductor substrate 100.

[0057] The first pixel area PR1 to the fourth pixel area PR4 can constitute a single pixel group GPX. In some example embodiments, each pixel group GPX is shown as including four pixel areas, but the example embodiments are not limited to this. For example, the pixel group GPX can consist of 6, 8, 9, or 16 pixel areas.

[0058] When viewed in a planar view, each of the first pixel regions PR1 to PR4 can be surrounded by a PD isolation structure PIS. Each of the first pixel regions PR1 to PR4 can be defined by a pair of first portions Pa extending in a first direction D1 and a pair of second portions Pb extending in a second direction D2. In some example embodiments, the PD isolation structure PIS may include a pair of third portions Pc in each of the first pixel regions PR1 to PR4. The third portions Pc may extend from the first portions Pa in the second direction D2 or from the second portions Pb in the first direction D1, and may be spaced apart from each other.

[0059] In some example embodiments, the PD isolation structure PIS can be provided to penetrate the semiconductor substrate 100. Specifically, the PD isolation structure PIS can have a length in a direction perpendicular to the top surface of the semiconductor substrate 100 (e.g., third direction D3), and the length of the PD isolation structure PIS can be substantially equal to the vertical thickness of the semiconductor substrate 100. In some example embodiments, the PD isolation structure PIS can extend vertically from a first surface 100a of the semiconductor substrate 100 toward a second surface 100b, and can be spaced apart from the second surface 100b of the semiconductor substrate 100.

[0060] In some example embodiments, the PD isolation structure PIS may include a pad insulating pattern 111, a gap filling pattern 113, and a cap insulating pattern 115. The gap filling pattern 113 may be provided as a portion perpendicularly penetrating the semiconductor substrate 100, and the pad insulating pattern 111 may be provided between the gap filling pattern 113 and the semiconductor substrate 100. The cap insulating pattern 115 may be disposed on the gap filling pattern 113. The pad insulating pattern 111 and the cap insulating pattern 115 may be formed of or include at least one of silicon oxide, silicon oxynitride, or silicon nitride. The gap filling pattern 113 may include an undoped polysilicon layer and / or a doped polysilicon layer. The gap filling pattern 113 may include an air gap or may define a void. The cap insulating pattern 115 of the PD isolation structure PIS may be formed of or include the same insulating material as the device isolation layer STI, and in this case, there may be no visible or observable boundary or interface between the cap insulating pattern 115 and the device isolation layer STI.

[0061] In some example embodiments, in each of the first pixel regions PR1 to the fourth pixel regions PR4, a first photoelectric conversion element 110a and a second photoelectric conversion element 110b can be provided in the semiconductor substrate 100. Light incident from the outside can be converted into electrical signals in the first photoelectric conversion element 110a and the second photoelectric conversion element 110b.

[0062] The first photoelectric conversion element 110a and the second photoelectric conversion element 110b can be impurity regions doped with impurities to have a second conductivity type (e.g., n-type) different from the first conductivity type of the semiconductor substrate 100. In some example embodiments, the first photoelectric conversion element 110a and the second photoelectric conversion element 110b can be counter-doped with impurities of the first conductivity type at a much lower concentration than the impurities of the second conductivity type; the example embodiments are not limited thereto. The semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion element 110a and the second photoelectric conversion element 110b can constitute a pair of photodiodes. For example, the junction used as a photodiode can be formed from the semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion element 110a or the second photoelectric conversion element 110b. When light is incident on the first photoelectric conversion element 110a and the second photoelectric conversion element 110b constituting the photodiode, photocharge can be generated and accumulated proportionally to the intensity of the incident light.

[0063] In each of the first pixel regions PR1 to the fourth pixel region PR4, the electrical signals output from the first photoelectric conversion element 110a and the second photoelectric conversion element 110b may have a phase difference, and in some cases may be digital signals and / or analog signals. The image sensor can be configured to measure the distance to a target object based on the phase difference between the electrical signals output from the paired photoelectric conversion elements (e.g., the first photoelectric conversion element 110a and the second photoelectric conversion element 110b), to check whether the target object is in focus or to what extent it is out of focus, and to perform corrections based on the results of the check, such as automatically correcting the focus of the image sensor.

[0064] Each of the first photoelectric conversion element 110a and the second photoelectric conversion element 110b may have a first width in a first direction D1 and a first length in a second direction D2 that is greater than the first width. In some exemplary embodiments, the first length may be approximately twice the first width.

[0065] The first photoelectric conversion element 110a and the second photoelectric conversion element 110b can be spaced apart from each other in the first direction D1, with the third portion Pc of the PD isolation structure PIS inserted between them. The third portion Pc of the PD isolation structure PIS can be configured to physically reflect incident light at the edge portions of each of the first pixel areas PR1 to the fourth pixel areas PR4, and thus, crosstalk between the first photoelectric conversion element 110a and the second photoelectric conversion element 110b can be reduced.

[0066] In each of the first pixel regions PR1 to the fourth pixel region PR4, the device isolation layer STI may be disposed adjacent to the first surface 100a of the semiconductor substrate 100. The bottom surface of the device isolation layer STI may be spaced apart from the first photoelectric conversion element 110a and the second photoelectric conversion element 110b.

[0067] In some example embodiments, the device isolation layer STI may define a first active portion ACT1 and a second active portion ACT2 in each of the first pixel regions PR1 to PR4. The first active portion ACT1 and the second active portion ACT2 may be portions of the semiconductor substrate 100. When viewed in a plan view, the first active portion ACT1 and the second active portion ACT2 may overlap with one of the photoelectric conversion elements 110a and 110b. For example, a pair of first active portions ACT1 and a pair of second active portions ACT2 may be provided in each of the pixel regions PR1 to PR4, but the example embodiments are not limited thereto.

[0068] The first active portion ACT1 and the second active portion ACT2 may be spaced apart from each other in the second direction D2 by a device isolation layer STI, and may have different sizes and shapes. The first active portion ACT1 may have a "T" shape, but the example embodiment is not limited thereto; for example, the first active portion ACT1 may have various polygonal shapes (e.g., rectangular and / or quadrilateral shapes). The second active portion ACT2 may have a major axis in the second direction D2 and a minor axis in the first direction D1. Each of the second active portions ACT2 may have a second length, which, when measured in the second direction D2, is less than the first length of the first photoelectric conversion element 110a or the second photoelectric conversion element 110b.

[0069] The first active portion ACT1 and the second active portion ACT2 of the third pixel region PR3 and the fourth pixel region PR4, as well as the first active portion ACT1 and the second active portion ACT2 of the first pixel region PR1 and the second pixel region PR2, can be arranged in a mirror-symmetric manner (e.g., around a symmetry axis extending in the first direction D1).

[0070] A device isolation layer (STI) can be provided in a trench, which is formed by recessing a first surface 100a of the semiconductor substrate 100. The device isolation layer (STI) can be formed of an insulating material.

[0071] As an example, see reference Figure 3B , Figure 4B and Figure 5BThe device isolation layer STI may include a pad oxide layer 101 and a pad nitride layer 103, and a gap-filling oxide layer 105 filling the trench. The pad oxide layer 101 and the pad nitride layer 103 are formed to conformally cover the surface of the trench, and the gap-filling oxide layer 105 is covered by the pad oxide layer 101 and the pad nitride layer 103. The gap-filling oxide layer 105 may include at least one of, for example, a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0072] The first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be disposed in each of the first pixel regions PR1 to the fourth pixel regions PR4. Each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be disposed on the first active portion ACT1. The first transfer gate electrode TG1 and the second transfer gate electrode TG2 may include portions disposed in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. A gate insulating layer may be inserted between the first transfer gate electrode TG1 and the second transfer gate electrode TG2 and the semiconductor substrate 100. An insulating spacer SP may be disposed on the opposite side surface of each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2.

[0073] In some example embodiments, each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may have a dual vertical gate electrode structure, wherein two vertical portions extend into the semiconductor substrate 100. In some example embodiments, the shape and position of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be varied.

[0074] In each of the first pixel regions PR1 to the fourth pixel regions PR4, a first floating diffusion region FD1 may be provided in the portion of the first active portion ACT1 near the first transfer gate electrode TG1. A second floating diffusion region FD2 may be provided in the portion of the first active portion ACT1 near the second transfer gate electrode TG2.

[0075] The first floating diffusion region FD1 and the second floating diffusion region FD2 can be formed by doping (e.g., implanting a dopant of a second conductivity type different from that of the semiconductor substrate 100). For example, the first floating diffusion region FD1 and the second floating diffusion region FD2 can be n-type doped regions. In some example embodiments, the implantation energy of the dopant implanted into the first floating diffusion region FD1 can be less than the implantation energy of the dopant implanted into the second floating diffusion region FD2.

[0076] Each of the first floating diffusion region FD1 and the second floating diffusion region FD2 may include a first doped region FDa and a second doped region FDb in the first doped region FDa, and the doping concentration in the second doped region FDb may be higher than the doping concentration in the first doped region FDa.

[0077] In each of the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be respectively disposed on the second active portion ACT2. In each of the first pixel region PR1, the second pixel region PR2, and the fourth pixel region PR4, the first pixel gate electrode PG1 may overlap or at least partially overlap with the first photoelectric conversion element 110a, and the second pixel gate electrode PG2 may overlap or at least partially overlap with the second photoelectric conversion element 110b.

[0078] In the third pixel region PR3, the pixel gate electrode PG can be disposed on the second active portion ACT2. In the third pixel region PR3, the pixel gate electrode PG can be longer than the first pixel gate electrode PG1 and the second pixel gate electrode PG2 in the first direction D1. For example, the pixel gate electrode PG can intersect with the second active portion ACT2 in the third pixel region PR3. The pixel gate electrode PG can partially overlap or at least partially overlap with the first photoelectric conversion element 110a and the second photoelectric conversion element 110b in the third pixel region PR3.

[0079] The first source / drain region SD1 can be provided in the second active portion ACT2 and is provided at the side of the first pixel gate electrode PG1, the second pixel gate electrode PG2, and the pixel gate electrode PG, and the second source / drain region SD2 can be provided in the second active portion ACT2 and is provided at the opposite side of the first pixel gate electrode PG1, the second pixel gate electrode PG2, and the pixel gate electrode PG.

[0080] In each of the first pixel regions PR1 to the fourth pixel regions PR4, the first pixel gate electrode PG1, the second pixel gate electrode PG2, and the pixel gate electrode PG can constitute the previously referenced Figure 1 The pixel transistors described are (e.g., reset transistor RX, source follower transistor SF, dual conversion gain transistor DCX, and select transistor SX).

[0081] In some example embodiments, the first pixel gate electrode PG1 in the first pixel region PR1 can be provided as a reference. Figure 1 The description of the selected gate electrode, and the pixel gate electrode PG in the third pixel region PR3 can be provided as a reference. Figure 1The source follower gate electrode is described. The first pixel gate electrode PG1 in the fourth pixel region PR4 can be provided as a reference. Figure 1 The dual-conversion gate electrode is described. The second pixel gate electrode PG2 in the fourth pixel region PR4 can be provided as a reference. Figure 1 The reset gate electrode is described. The functions of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 in the first pixel region PR1 to the fourth pixel region PR4 can be changed differently.

[0082] The insulating spacer SP can be placed on the opposite side surfaces of the first pixel gate electrode PG1 and the second pixel gate electrode PG2.

[0083] Furthermore, in each of the first pixel regions PR1 to the fourth pixel region PR4, a ground impurity region GR can be provided between the first photoelectric conversion element 110a and the second photoelectric conversion element 110b. The ground impurity region GR can also be provided between the third portions Pc of the PD isolation structure PIS. The ground impurity region GR can be formed by an injection process (e.g., implanting a dopant of the same first conductivity type as the semiconductor substrate 100).

[0084] In some example embodiments, the connecting conductive pattern ICP can be disposed on a first surface 100a of the semiconductor substrate 100 and can be jointly connected to a first floating diffusion region FD1 and a second floating diffusion region FD2 provided in the first pixel regions PR1 to the fourth pixel regions PR4. In some example embodiments, the connecting conductive pattern ICP can be connected to a first source / drain region SD1 of the pixel transistor, the first source / drain region SD1 being provided in at least two of the first pixel regions PR1 to the fourth pixel regions PR4. In some example embodiments, the connecting conductive pattern ICP can be connected to the first source / drain region SD1, the first source / drain region SD1 being provided at the side of the first pixel gate electrode PG1 in the fourth pixel region PR4. For example, the connecting conductive pattern ICP can... Figure 1 The dual-conversion-gain transistor DCX is electrically connected to both the first floating diffusion region FD1 and the second floating diffusion region FD2.

[0085] The interconnected conductive pattern ICP can be formed from a conductive material. The interconnected conductive pattern ICP can be formed from monocrystalline silicon and / or polycrystalline silicon, which is doped with or otherwise incorporated with a dopant of a second conductivity type. Furthermore, the interconnected conductive pattern ICP can be formed from or include at least one of a metallic material (e.g., one or more of tungsten, titanium, tantalum, and cobalt). The concentration of the second conductivity type dopant in the interconnected conductive pattern ICP can be higher than the doping concentration in the second doped region FDb of the first floating diffusion region FD1 and the second floating diffusion region FD2, for example, by several orders of magnitude.

[0086] The conductive pattern ICP can have a first thickness on the first surface 100a of the semiconductor substrate 100, and each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 can have a second thickness on the first surface 100a of the semiconductor substrate 100. Here, the second thickness can be greater than the first thickness.

[0087] In detail, the connecting conductive pattern ICP may include an edge portion EP adjacent to the outer side surface of the connecting conductive pattern ICP and a pad portion PP that contacts the first floating diffusion region FD1, the second floating diffusion region FD2, and the first source / drain region SD1. In some example embodiments, when viewed in a plan view, the connecting conductive pattern ICP may include a first connection portion CP1 that contacts the first floating diffusion region FD1 and the second floating diffusion region FD2, and a second connection portion CP2 that extends from the first connection portion CP1 and contacts the first source / drain region SD1.

[0088] The first connection portion CP1 can contact, for example, the second doped region FDb of the first floating diffusion region FD1 and the second floating diffusion region FD2 in the first pixel region PR1 to the fourth pixel region PR4, for example, it can be in direct contact. The second connection portion CP2 can have a minimum width smaller than the minimum width of the first connection portion CP1, and can be in direct contact with at least one of the first source / drain regions SD1.

[0089] Reference Figure 6A The minimum width of the second connection portion CP2 can be approximately equal to the width W of the device isolation layer STI. (Refer to...) Figure 6B The minimum width of the second connection portion CP2 can be greater than the width of the device isolation layer STI. (See reference...) Figure 6C The pad portion PP of the conductive pattern ICP can be partially inserted into the device isolation layer STI.

[0090] In some example embodiments, when viewed in a plan view, the interconnecting conductive pattern (ICP) can have various shapes depending on the arrangement of the pixel transistors.

[0091] Reference Figure 3B , Figure 4B and Figure 5B The conductive pattern ICP can have a first top surface US1 in the edge portion EP and a second top surface US2 in the pad portion PP. Here, when measured from the first surface 100a of the semiconductor substrate 100, the first top surface US1 can be positioned at a level higher than the second top surface US2. Depending on the location, the edge portion EP of the conductive pattern ICP can be placed on the first active portion ACT1 and the second active portion ACT2 or on the device isolation layer STI and the PD isolation structure PIS.

[0092] The conductive pattern ICP can have a first bottom surface LS1 and a second bottom surface LS2. The first bottom surface LS1 is in contact with the device isolation layer STI, and the second bottom surface LS2 is in contact with the first floating diffusion region FD1, the second floating diffusion region FD2, and the first source / drain region SD1.

[0093] The first bottom surface LS1 of the conductive pattern ICP can be located at a level lower than the first surface 100a of the semiconductor substrate 100. The second bottom surface LS2 of the conductive pattern ICP can be located at a level lower than the top surface of the device isolation layer STI.

[0094] In some example embodiments, the blocking pattern BLK may be disposed between the edge portion EP of the connecting conductive pattern ICP and the semiconductor substrate 100, the device isolation layer STI, or the PD isolation structure PIS.

[0095] When viewed in a plan view, the barrier pattern BLK may overlap or at least partially overlap with the edge portion EP of the connecting conductive pattern ICP. For example, the barrier pattern BLK may be positioned along the outer edge surface of the connecting conductive pattern ICP.

[0096] The blocking pattern BLK may include the same insulating material as the insulating spacer SP, which is disposed on the opposing side surfaces of the first transmission gate electrode TG1 and the second transmission gate electrode TG2, and on the opposing side surfaces of the first pixel gate electrode PG1 and the second pixel gate electrode PG2. The blocking pattern BLK may be formed of, for example, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. The blocking pattern BLK can prevent or reduce the possibility of contact between the edge portion EP of the connected conductive pattern ICP and the first active portion ACT1 and the second active portion ACT2, and / or the effects of such contact.

[0097] Reference Figure 3B , Figure 4B and Figure 5B The bottom surface of the barrier pattern BLK can be located at a level higher than the bottom surface of the pad portion PP of the conductive pattern ICP. The barrier pattern BLK can have an outer side surface SWa adjacent to the outer side surface of the conductive pattern ICP and an inner side surface SWb opposite to the outer side surface SWa. The outer side surface SWa of the barrier pattern BLK can be perpendicularly aligned with the outer side surface of the conductive pattern ICP. The inner side surface SWb of the barrier pattern BLK can be tilted at a specific angle relative to the first surface 100a of the semiconductor substrate 100. The inner side surface SWb of the barrier pattern BLK can be in direct contact with the conductive pattern ICP.

[0098] Reference Figure 6A The blocking pattern BLK can be placed between the second connection portion CP2 of the conductive pattern ICP and the device isolation layer STI. (See reference...) Figure 5C and Figure 6B The blocking pattern BLK can be placed on the boundary between the semiconductor substrate 100 and the device isolation layer STI.

[0099] A first etch stop layer 140 and a second etch stop layer 150 may be sequentially formed on a first surface 100a of a semiconductor substrate 100. The first etch stop layer 140 and the second etch stop layer 150 may cover the first transfer gate electrode TG1 and the second transfer gate electrode TG2, the first pixel gate electrode PG1 and the second pixel gate electrode PG2, the pixel gate electrode PG, and the interconnect conductive pattern ICP with a uniform thickness. The first etch stop layer 140 and the second etch stop layer 150 may be formed of or comprise silicon nitride. The second etch stop layer 150 may be thicker than the first etch stop layer 140.

[0100] Reference Figure 3B , Figure 4B and Figure 5B The first etch stop layer 140 can cover the outer edge surface SWA of the blocking pattern BLK and the outer edge surface of the connecting conductive pattern ICP with a uniform thickness.

[0101] A surface insulating layer 102 may be disposed on a first surface 100a of a semiconductor substrate 100, and a portion of the surface insulating layer 102 may be disposed between the first surface 100a of the semiconductor substrate 100 and the bottom surface of the barrier pattern BLK. The surface insulating layer 102 may be formed of, for example, at least one of silicon oxide and / or silicon oxynitride, or may include, for example, at least one of silicon oxide and / or silicon oxynitride.

[0102] A cover insulating layer 131 may be provided to conformally cover the conductive pattern ICP. The cover insulating layer 131 may contact the outer edge surface of the conductive pattern ICP and the outer edge surface of the blocking pattern BLK. The cover insulating layer 131 may be formed of or include at least one of, for example, silicon oxide and / or silicon oxynitride.

[0103] Interlayer insulating layer 210 can be stacked on the first surface 100a of semiconductor substrate 100 to cover the structure Figure 1 The pixel circuit 2 includes pixel transistors RX, SF, DCX, and SEL, as well as a first transmission gate electrode TG1 and a second transmission gate electrode TG2. The interlayer insulating layer 210 may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0104] Connected to Figure 1 The contact plugs 221 of the pixel circuit 2 and the interconnects 223 connected to the contact plugs 221 can be disposed in the interlayer insulating layer 210. One of the contact plugs 221 can be provided to penetrate the interlayer insulating layer 210 and the first etch stop layer 140 and the second etch stop layer 150, and can be coupled to the connection conductive pattern ICP.

[0105] Reference Figure 3A , Figure 4A , Figure 5A and Figure 6A The optically transparent layer 30 can be disposed on the second surface 100b of the semiconductor substrate 100. The optically transparent layer 30 may include a planarization insulating layer 310, a mesh structure 320, a color filter 330, and a microlens 340. The optically transparent layer 30 can be configured to perform the operation of focusing and filtering light incident from the outside, and to provide light to the photoelectric conversion circuit layer 10.

[0106] The planarization insulating layer 310 may cover the second surface 100b of the semiconductor substrate 100. The planarization insulating layer 310 may be formed of a transparent insulating material and may include multiple layers. The planarization insulating layer 310 may be formed of an insulating material with a refractive index different from (e.g., greater than or less than) that of the semiconductor substrate 100. The planarization insulating layer 310 may include at least one of a metal oxide and / or silicon oxide.

[0107] The mesh structure 320 can be disposed on the planarized insulating layer 310. When viewed in a plan view, the mesh structure 320 can have a lattice shape, similar to the PD isolation structure PIS. When viewed in a plan view, the mesh structure 320 can overlap with the PD isolation structure PIS. That is, the mesh structure 320 can include a first portion extending in a first direction D1 and a second portion extending in a second direction D2 to intersect the first portion. The width of the mesh structure 320 can be substantially equal to or less than the minimum width of the PD isolation structure PIS.

[0108] The mesh structure 320 may include conductive patterns and / or low-refractive-index patterns. The conductive patterns may be formed of or include at least one of a metallic material (e.g., one or more of titanium, tantalum, and tungsten). The low-refractive-index patterns may be formed of a material with a refractive index lower than that of the conductive patterns. The low-refractive-index patterns may be formed of organic materials and may have a refractive index of about 1.1 to 1.3. For example, the mesh structure 320 may be or may include a polymer layer comprising silica nanoparticles.

[0109] Color filters 330 can be configured to correspond to pixel regions PR. Color filters 330 can be provided to fill the space defined by the grid structure 320. Color filters 330 can include red, green, blue, magenta, cyan, or yellow filters determined based on the position of a unit pixel. In some example embodiments, at least one of the color filters 330 can include a white filter or an infrared filter. In some example embodiments, color filters 330 can be arranged in a Bayer pattern; however, the example embodiments are not limited thereto.

[0110] Microlens 340 can be disposed on color filter 330. Microlens 340 can have a convex shape and can have a specific radius of curvature. Microlens 340 can be formed of optically transparent resin. Microlens 340 can be disposed on color filter 330 to correspond to pixel area PR respectively. In some example embodiments, at least one of microlenses 340 can be disposed together on at least two pixel areas PR.

[0111] Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a plan view illustrating an image sensor according to some example embodiments. For the sake of brevity, references may be omitted from the following description. Figure 3A , Figure 4A , Figure 5A and Figure 6A The image sensors described have the same technical features, and different technical features will be described below.

[0112] Reference Figure 7 The PD isolation structure PIS may include a pair of first portions Pa and a pair of second portions Pb defining first pixel regions PR1 to fourth pixel regions PR4. Furthermore, in each of the first pixel regions PR1 to fourth pixel regions PR4, the PD isolation structure PIS may also include a third portion Pc extending toward its center. The third portion Pc may extend from one of the first portions Pa in a second direction D2.

[0113] The third part Pc of the PD isolation structure PIS can be placed between the first photoelectric conversion element 110a and the second photoelectric conversion element 110b in each of the first pixel area PR1 to the fourth pixel area PR4. The third part Pc can be placed between the second active parts ACT2.

[0114] When viewed in a planar diagram, the connecting conductive pattern ICP can be spaced apart from the third part Pc of the PD isolation structure PIS.

[0115] Reference Figure 8 In each of the first pixel regions PR1 to the fourth pixel region PR4, the PD isolation structure PIS may include a third portion Pc that extends from one of the first portions Pa in the second direction D2, as described above. Here, the third portion Pc may be disposed between the first active portions ACT1, and a portion of the third portion Pc may overlap with the connecting conductive pattern ICP.

[0116] Reference Figure 9 In each of the first pixel regions PR1 to the fourth pixel region PR4, the PD isolation structure PIS may include a third portion Pc, which extends from one of the first portions Pa in the second direction D2, as described above. Here, the third portion Pc may be positioned between the second active portions ACT2, and refer to... Figure 2 The first active parts described can be connected to each other to form a common active part ACT.

[0117] Furthermore, the common active portion ACT in the first pixel region PR1 can be connected to the common active portion ACT in the third pixel region PR3. The portions of the PD isolation structure PIS between the first pixel region PR1 and the third pixel region PR3 can be spaced apart. Similarly, the common active portion ACT in the second pixel region PR2 can be connected to the common active portion ACT in the fourth pixel region PR4. The portions of the PD isolation structure PIS between the second pixel region PR2 and the fourth pixel region PR4 can be spaced apart.

[0118] The floating diffusion region FD1 or FD2 can be provided in the open region of the PD isolation structure PIS between the first pixel region PR1 and the third pixel region PR3.

[0119] The first connection portion CP1 of the conductive pattern ICP can connect the floating diffusion region FD between the first pixel region PR1 and the third pixel region PR3 to the floating diffusion region FD between the second pixel region PR2 and the fourth pixel region PR4, and the second connection portion CP2 of the conductive pattern ICP can extend from the first connection portion CP1 and can be connected to one of the first source / drain regions SD1.

[0120] The connecting conductive pattern ICP may include an edge portion EP adjacent to its outer side surface, and a blocking pattern BLK may be disposed between the edge portion EP and the first surface 100a of the semiconductor substrate 100. For example, as described above, when viewed in a plan view, the blocking pattern BLK may overlap with the edge portion EP of the connecting conductive pattern ICP.

[0121] Reference Figure 10 The semiconductor substrate 100 may include multiple pixel groups GPX. Each pixel group GPX may include at least 4, 8, or 16 pixel regions PR. In each pixel group GPX, the pixel regions PR may be arranged on a first direction D1 and a second direction D2 that are not parallel to each other, or arranged in a matrix shape.

[0122] The first photoelectric conversion element 110a to the fourth photoelectric conversion element 110d can be provided in the first pixel area PR1 to the fourth pixel area PR4, respectively.

[0123] The first active portion ACT1 and the second active portion ACT2 can be provided in each of the first pixel regions PR1 to PR4 via a device isolation layer STI, which is formed in the semiconductor substrate 100 adjacent to the first surface 100a. The first active portion ACT1 and the second active portion ACT2 can be defined by the device isolation layer STI adjacent to the first surface 100a of the semiconductor substrate 100.

[0124] The first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4 can be provided in the first pixel region PR1 to the fourth pixel region PR4, respectively. Each of the first to fourth transfer gate electrodes TG1, TG2, TG3, and TG4 can have a dual vertical gate electrode structure, which includes two vertical portions extending into the semiconductor substrate 100, as described above.

[0125] In each of the first pixel region PR1 to the fourth pixel region PR4, a pixel transistor can be provided on the second active portion ACT2.

[0126] The first floating diffusion regions FD1 to the fourth floating diffusion regions FD4 can be respectively provided in the portion of the first active portion ACT1 at the first side edge of the first transmission gate electrodes TG1, TG2, TG3 and TG4. The first floating diffusion regions FD1 to the fourth floating diffusion regions FD4 can be arranged adjacent to each other and can be arranged on the central portion of each of the pixel group GPX.

[0127] The first connection portion CP1 of the conductive pattern ICP can be connected to the first floating diffusion region FD1 to the fourth floating diffusion region FD4 of the adjacent pixel group in the pixel group. The second connection portion of the conductive pattern ICP can extend from the first connection portion CP1 and can be connected to one of the first source / drain regions SD1.

[0128] As described above, the connecting conductive pattern ICP may include an edge portion adjacent to the outer side surface of the connecting conductive pattern ICP, and the blocking pattern BLK may be disposed between the edge portion and the first surface 100a of the semiconductor substrate 100. For example, as described above, when viewed in a plan view, the blocking pattern BLK may overlap with the edge portion of the connecting conductive pattern ICP.

[0129] Reference Figure 11 The common active portion ACT can be provided together in the first pixel area PR1 to the fourth pixel area PR4, and the second active portion ACT2 can be provided in each of the first pixel area PR1 to the fourth pixel area PR4.

[0130] The first transfer gate electrode TG1 to the fourth transfer gate electrode TG4 can be provided on the common active portion ACT.

[0131] In each pixel group GPX, a common floating diffusion region CFD1 or CFD2 can be provided in a common active portion ACT. In some example embodiments, the common floating diffusion region CFD1 or CFD2 can be shared by at least four pixel regions PR1 to PR4. The first portions P1 of the PD isolation structure PIS can be spaced apart from each other in a first direction D1, with the common floating diffusion region CFD1 or CFD2 inserted between the first portions P1, and the second portions P2 can be spaced apart from each other in a second direction D2, with the common floating diffusion region CFD inserted between the second portions P2. The floating diffusion region FD can be provided in the semiconductor substrate 100 adjacent to the first transfer gate electrode TG1 to the fourth transfer gate electrode TG4.

[0132] The first connection portion CP1 of the conductive pattern ICP can connect the common floating diffusion regions CFD1 and CFD2 of the pixel group GPX to each other, and the second connection portion CP2 of the conductive pattern ICP can extend from the first connection portion CP1 and can be connected to one of the first source / drain regions SD1 in one of the pixel group GPX.

[0133] Figures 12 to 19 It is along Figure 2 A cross-sectional view taken along line A-A' to illustrate a method of manufacturing an image sensor according to some example embodiments.

[0134] Reference Figure 2 and Figure 12 The semiconductor substrate 100 may provide a first conductivity type (e.g., p-type). In some example embodiments, the semiconductor substrate 100 may include an epitaxial layer. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b, which are opposite to each other.

[0135] Alternatively, the semiconductor substrate 100 may be or may include a bulk semiconductor substrate, which includes a well of a first conductivity type. In some example embodiments, the semiconductor substrate 100 may be or may include a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate.

[0136] In each of the pixel regions PR, a device isolation layer STI may be formed in the portion of the semiconductor substrate 100 adjacent to the first surface 100a to define an active portion. Forming the device isolation layer STI may include patterning the first surface 100a of the semiconductor substrate 100 to form a shallow trench (e.g., a first trench), thereby forming a pad insulating layer to conformally cover the inner surface of the first trench, and forming an insulating layer to fill the first trench in which the pad insulating layer is provided. The device isolation layer STI may be formed before or after the formation of photoelectric conversion elements 110a and 110b.

[0137] A PD isolation structure PIS can be formed in a semiconductor substrate 100 to define a pixel region PR. The formation of the PD isolation structure PIS may include patterning and etching a first surface 100a of the semiconductor substrate 100 to form a second trench, forming a pad insulating layer using a process such as, but not limited to, chemical vapor deposition (CVD) to conformally cover the inner surface of the second trench, depositing a semiconductor layer to fill the second trench where the pad insulating layer is provided, and planarizing the pad insulating layer and the semiconductor layer to expose the first surface 100a of the semiconductor substrate 100, and forming a pad insulating pattern 111, a gap filling pattern 113, and a cap insulating pattern 115 in the second trench using a process such as, but not limited to, chemical mechanical planarization (CMP) and / or etch-back processes.

[0138] The second trench may also include an extension trench that extends toward the center of each pixel region PR. In each pixel region PR1-PR4, the extension trench may extend in the second direction D2 and may be spaced apart from each other in the second direction D2.

[0139] In some example embodiments, the pad insulation pattern 111 and the cover insulation pattern 115 may be formed of or include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride. The gap fill pattern 113 may include a doped polysilicon layer and / or an undoped polysilicon layer.

[0140] Next, a first photoelectric conversion element 110a and a second photoelectric conversion element 110b can be formed in each of the pixel areas PR1 to PR4.

[0141] In each of the pixel regions PR, a first photoelectric conversion element 110a and a second photoelectric conversion element 110b can be formed by doping a portion of the semiconductor substrate 100 with an impurity of a second conductivity type (e.g., n-type) different from the first conductivity type. The first photoelectric conversion element 110a and the second photoelectric conversion element 110b can be spaced apart from the first surface 100a and the second surface 100b of the semiconductor substrate 100. The first photoelectric conversion element 110a and the second photoelectric conversion element 110b can be formed before or after the formation of the PD isolation structure PIS.

[0142] Next, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 can be formed on the first active portion ACT1 in each pixel region PR, respectively. The formation of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may include: patterning the first surface 100a of the semiconductor substrate 100 to form a gate recess region in each of the pixel regions PR, forming a gate insulating layer to conformally cover the inner surface of the gate recess region, forming a gate conductive layer to fill the gate recess region, and patterning the gate conductive layer. Each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may include two vertical portions disposed in the semiconductor substrate 100.

[0143] The gate insulating layer (GIL) may include a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. A deposition process may be performed to form a gate insulating layer (GIL) that conformally covers the inner surface of the vertical trench (VT).

[0144] The first transport gate electrode TG1 and the second transport gate electrode TG2 can be formed by forming a gate conductive layer to fill a vertical trench VT on which a gate insulating layer GIL is provided and by patterning the gate conductive layer. The gate conductive layer may include a doped polysilicon layer, a metal silicide layer, a conductive metal nitride layer, or a metal layer.

[0145] During the formation of the first transfer gate electrode TG1 and the second transfer gate electrode TG2, the gate electrodes RG, SG and SFG of the pixel transistor may be formed in the second active portion ACT2 of each of the pixel regions PR1 and PR2.

[0146] After forming the first transport gate electrode TG1 and the second transport gate electrode TG2, a first doped region FDa can be formed in the portion of the semiconductor substrate 100 located on the sides of the first transport gate electrode TG1 and the second transport gate electrode TG2. The first doped region FDa can be formed by an ion implantation process that injects impurities of a second conductivity type using an ion implantation mask. Furthermore, the source / drain regions (not shown) of the pixel transistor can be formed during the formation of the first doped region FDa.

[0147] Reference Figure 13 The spacer insulating layer 120 can be deposited on the first surface 100a of the semiconductor substrate 100. The spacer insulating layer 120 can cover the first transmission gate electrode TG1, the second transmission gate electrode TG2, and the pixel gate electrode with a uniform thickness.

[0148] The spacer insulating layer 120 may be formed or include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN) or silicon carbonitride (SiCON).

[0149] The spacer insulating layer 120 can be deposited by one or more processes, such as atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), or flowable CVD (FCVD).

[0150] Reference Figure 2 and Figure 14 A first mask pattern MP1 can be formed on the spacer insulating layer 120, the first mask pattern MP1 having an opening that exposes the area where the connecting conductive pattern will be formed.

[0151] In each of the pixel regions PR1 to PR4, the opening of the first mask pattern MP1 may overlap with a portion of the first doped region FDa of the pixel transistor and a portion of one of the first source / drain regions SD1.

[0152] In some example embodiments, the first mask pattern MP1 can be formed by coating the first surface 100a of the semiconductor substrate 100 with a photoresist layer and performing exposure and development steps on the photoresist layer.

[0153] Reference Figure 2 and Figure 15 The spacer insulating pattern 121 can be formed by anisotropically etching the spacer insulating layer 120 using the first mask pattern MP1 as an etching mask.

[0154] Reference Figure 2 and Figure 16 The second doped region FDb can be formed within a portion of the first doped region FDa. The second doped region FDb can be formed by an ion implantation process that uses a spacer insulating pattern 121 as an ion implantation mask pattern to inject impurities of a second conductivity type.

[0155] Reference Figure 2 and Figure 17 The conductive layer 130 can be deposited on the semiconductor substrate 100 to have a substantially uniform thickness. The conductive layer 130 can be in direct contact with the second doped region FDb and can cover the spacer insulating pattern 121.

[0156] The conductive layer 130 may include, for example, a doped polysilicon layer, a metal silicide layer, a conductive metal nitride layer, or a metal layer. For example, the conductive layer 130 may be formed by depositing a semiconductor layer, and in some example embodiments, the conductive layer 130 may be in-situ doped with impurities during the deposition of the semiconductor layer. The doping concentration of the conductive layer 130 may be lower (e.g., an order of magnitude or more) than the doping concentration of the second doped region FDb.

[0157] Reference Figure 2 and Figure 18 The second mask pattern MP2 can be formed on the conductive layer 130 and can overlap with one of the first floating diffusion region FD1, the second floating diffusion region FD2, and the first source / drain region SD1.

[0158] Next, the conductive layer 130 can be anisotropically etched using the second mask pattern MP2 as an etching mask to form the interconnect conductive pattern ICP. After forming the interconnect conductive pattern ICP, the second mask pattern MP2 can be removed.

[0159] Reference Figure 2 and Figure 19 An etching process (e.g., an etch-back process) can be performed on the spacer insulating pattern 121. As a result, the insulating spacer SP, which is the remaining part of the spacer insulating pattern 121, can be formed on the opposite side surfaces of the first transmission gate electrode TG1 and the second transmission gate electrode TG2 and on the opposite side surfaces of the pixel gate electrodes PG1 and PG2, and the blocking pattern BLK can be formed below the edge portion EP of the connecting conductive pattern ICP.

[0160] Next, as Figure 3A As shown, the first etch stop layer 140 and the second etch stop layer 150 can be sequentially deposited on the first surface 100a of the semiconductor substrate 100 to have a uniform thickness.

[0161] The first etch stop layer 140 and the second etch stop layer 150 can be deposited by one or more processes, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure CVD (LPCVD), or flowable CVD (FCVD). The first etch stop layer 140 and the second etch stop layer 150 can be formed of or include silicon nitride or silicon oxynitride.

[0162] Figure 20 This is a plan view illustrating an image sensor according to some example embodiments.

[0163] Reference Figure 20The image sensor may include first pixel groups GPX1 to third pixel groups GPX2 and GPX3, which are arranged two-dimensionally in a first direction D1 and a second direction D2. In odd-numbered rows, the first pixel group GPX1 and the second pixel group GPX2 may be arranged alternately. In even-numbered rows, the second pixel group GPX2 and the third pixel group GPX3 may be arranged alternately. Each of the first pixel groups GPX1, GPX2, and GPX3 may include a pixel area PR arranged in a 2×2 shape. A PD isolation structure PIS can separate the first pixel groups GPX1, GPX2, and GPX3 from each other. When viewed in a planar view, the PD isolation structure PIS can be inserted into each of the pixel groups GPX1, GPX2, and GPX3 to separate the pixel areas PR from each other. However, the PD isolation structure PIS can be cut at the center of each of the pixel groups GPX1, GPX2, and GPX3, and therefore, the pixel areas PR included in each pixel group can be connected to each other. The first pixel group GPX1 may be covered by a first color filter CF1. The second pixel group GPX2 can be covered by the second color filter CF2. The third pixel group GPX3 can be covered by the third color filter CF3. In some example embodiments, the first color filter CF1 can have one of the colors red, green, and blue. The second color filter CF2 can have another color among red, green, and blue. The third color filter CF3 can have the remaining colors among red, green, and blue. Microlenses ML can be disposed on the first color filter CF1 through the third color filters CF2 and CF3. The microlenses ML can be positioned to correspond to and overlap with pixel areas PR, respectively. That is, one microlens ML can be disposed on each pixel PX. Microlenses ML arranged in a 2×2 shape can be disposed on each of the pixel groups GPX1, GPX2, and GPX3. Due to the arrangement of the microlenses ML, the light concentration in each pixel area PR can be increased, thereby achieving a sharp image.

[0164] Figure 21 This is a schematic plan view of an image sensor including a semiconductor device according to some example embodiments. Figure 22 and Figure 23 It is along Figure 21 A cross-sectional view taken by line I-I' to illustrate an image sensor according to some example embodiments.

[0165] Reference Figure 21 and Figure 22 The image sensor may include a sensor chip C1 and a logic chip C2. The sensor chip C1 may include a pixel array area R1 and a pad area R2.

[0166] The pixel array region R1 may include a plurality of unit pixels P, which are arranged in two dimensions in two different directions (e.g., in a first direction D1 and a second direction D2). Each of the unit pixels P may include a photoelectric conversion device and a readout device. An electrical signal generated by the incident light can be output from each unit pixel P of the pixel array region R1.

[0167] The pixel array region R1 may include a light-receiving region AR and a light-blocking region OB. When viewed in a planar view, the light-blocking region OB may be provided to surround the light-receiving region AR. For example, when viewed in a planar view, the light-blocking region OB may be provided to surround the light-receiving region AR in four different directions (e.g., up, down, left, and right). In some example embodiments, a reference pixel P in which no light is incident may be provided in the light-blocking region OB, and in this case, the amplitude of the electrical signal generated by the unit pixel P can be calculated by comparing the amount of charge obtained from the unit pixel P in the light-receiving region AR with the amount of charge generated in the reference pixel P.

[0168] Multiple conductive pads CP for inputting or outputting control signals and photoelectric signals can be disposed in pad area R2. When viewed in a plan view, pad area R2 can provide an enclosure for pixel array area R1, and in this case, the image sensor can be easily connected to an external device. The conductive pads CP can be used to transmit the electrical signals generated in a unit pixel P to an external device.

[0169] Sensor chip C1 can be provided with the same characteristics as the light-receiving area AR of the image sensor described above. In other words, as described above, sensor chip C1 can include a photoelectric conversion circuit layer 10, which is provided in the vertical direction between pixel circuit layer 20 and optically transparent layer 30. The photoelectric conversion circuit layer 10 of sensor chip C1 can include a semiconductor substrate 100, a PD isolation structure PIS defining the pixel area, and a photoelectric conversion element 110 provided in the pixel area, as described above. The PD isolation structure PIS can have substantially the same structure on the light-receiving area AR and the light-blocking area OB. The PD isolation structure PIS can be disposed in the semiconductor substrate 100 of the light-blocking area OB. The gap filling pattern 113 of the PD isolation structure PIS can be electrically connected to the back contact plug PLG in the light-blocking area OB. A predetermined bias can be applied to the gap filling pattern 113 through the back contact plug PLG. The back contact plug PLG can have a width greater than that of the PD isolation structure PIS. The back-side contact plug PLG may be formed of or comprise at least one of a metallic material and / or a metal nitride material. For example, the back-side contact plug PLG may be formed of or comprise at least one of titanium and / or titanium nitride.

[0170] The contact pattern CT can be embedded in the contact hole, and the back contact plug PLG is formed in the contact hole. The contact pattern CT can include a different material than the back contact plug PLG. For example, the contact pattern CT can be formed of or comprise aluminum (Al).

[0171] The contact pattern CT and the back contact plug PLG can be electrically connected to the gap-filling pattern 113 of the PD isolation structure PIS. A positive bias can be applied to the gap-filling pattern 113 of the PD isolation structure PIS through the contact pattern CT, and in this case, the positive bias can be supplied from the light-blocking region OB to the light-receiving region AR. Therefore, the dark current at the interface between the PD isolation structure PIS and the semiconductor substrate 100 can be reduced.

[0172] The optically transparent layer 30 may include a light-blocking pattern OBP, a filter layer 335, and an organic layer 345 in the light-blocking region OB. In some example embodiments, the PD isolation structure PIS may extend continuously from the light-receiving region AR to the light-blocking region OB.

[0173] In the light-blocking region OB, a light-blocking pattern OBP can be disposed on the top surface of the planarized insulating layer 310. The light-blocking pattern OBP can include the same material as the conductive pattern of the mesh structure 320 in the light-receiving region AR. In other words, the light-blocking pattern OBP can include metallic patterns and metal oxide patterns. For example, the light-blocking pattern OBP can be formed of or include at least one of titanium nitride or titanium oxynitride. The light-blocking pattern OBP may not extend into the light-receiving region AR.

[0174] The light-shielding pattern OBP prevents light from incident on the photoelectric conversion element PD provided in the light-shielding area OB. The photoelectric conversion element PD in the reference pixel area of ​​the light-shielding area OB can be configured to output a noise signal instead of a photoelectric signal. The noise signal can be generated by electrons generated by heat or dark current.

[0175] The filter layer 335 may cover the light-blocking pattern OBP in the light-blocking region OB. The filter layer 335 may block light of a different wavelength than that of the color filter 330. For example, the filter layer 335 may block infrared light. The filter layer 335 may include a blue color filter, but the example embodiment is not limited thereto.

[0176] Organic layer 345 and passivation layer can be provided on filter layer 335 in light-blocking region OB and pad region R2. Organic layer 345 can be formed of or comprise the same material as microlens 340.

[0177] A first penetrating conductive pattern 511 can be provided in the light-blocking region OB to penetrate the semiconductor substrate 100 and can be electrically connected to the metal lines of the pixel circuit layer 20 and the interconnect structure 1111 of the logic chip C2. The first penetrating conductive pattern 511 can have a first bottom surface and a second bottom surface, which are located at different levels. A first gap-filling pattern 521 can be provided in the first penetrating conductive pattern 511. The first gap-filling pattern 521 can be formed of or include a low-refractive-index material and can exhibit insulating properties.

[0178] In the pad region R2, a conductive pad CP can be provided on the second surface 100b of the semiconductor substrate 100. The conductive pad CP can be buried in the semiconductor substrate 100 and near the second surface 100b. In some example embodiments, the conductive pad CP can be provided in a pad trench formed in the second surface 100b of the semiconductor substrate 100 and in the pad region R2. The conductive pad CP can be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, titanium, tantalum, or alloys thereof). During the mounting of the image sensor, bonding wires can be bonded to the conductive pad CP. The conductive pad CP can be electrically connected to an external device via the bonding wires.

[0179] A second penetrating conductive pattern 520 may be provided in the pad region R2 to penetrate the semiconductor substrate 100 and may be electrically connected to the interconnect structure 1111 of the logic chip C2. The second penetrating conductive pattern 520 may extend to a region on the second surface 100b of the semiconductor substrate 100 and may be electrically connected to the conductive pad CP. A portion of the second penetrating conductive pattern 520 may cover the bottom surface and side surfaces of the conductive pad CP. A second gap-filling pattern 510 may be provided in the second penetrating conductive pattern 520. The second gap-filling pattern 510 may include a low-refractive-index material and may have insulating properties. In the pad region R2, a PD isolation structure PIS may be provided around the second penetrating conductive pattern 520.

[0180] The logic chip C2 may include a logic semiconductor substrate 1000, a logic circuit TR, an interconnect structure 1111 connected to the logic circuit TR, and an interlayer insulating layer 1100. The uppermost interlayer insulating layer of the logic layer 1100 may be bonded to the pixel circuit layer 20 of the sensor chip C1. The logic chip C2 may be electrically connected to the sensor chip C1 via a first through-conductive pattern 511 and a second through-conductive pattern 520.

[0181] In some example embodiments, the sensor and logic chips C1 and C2 are described as being electrically connected to each other through a first through conductive pattern 511 and a second through conductive pattern 520, but the example embodiments are not limited thereto.

[0182] exist Figure 23 In the embodiments, the following can be omitted Figure 22 The first and second penetrating conductive patterns are provided, and the sensor and logic chips C1 and C2 can be electrically connected to each other through bonding pads, which are respectively provided in the topmost metal layer of the sensor and logic chips C1 and C2 and directly bonded to each other.

[0183] In detail, the gap-filling pattern 113 of the PD isolation structure PIS extending from the light receiving area AR to the light blocking area OB in the sensor chip C1 can be connected to the back contact plug PLG in the light blocking area OB.

[0184] Furthermore, the sensor chip C1 may include a first bonding pad BP1, which is provided in the topmost metal layer of the pixel circuit layer 20, and the logic chip C2 may include a second bonding pad BP2, which is provided in the topmost metal layer of the interconnect structure 1111. The first bonding pad BP1 and the second bonding pad BP2 may be formed or include at least one of, for example, tungsten W, aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN).

[0185] The first bonding pad BP1 of sensor chip C1 and the second bonding pad BP2 of logic chip C2 can be electrically and directly connected to each other using a hybrid bonding method. A hybrid bonding structure refers to a bonding structure in which two materials of the same kind are fused together at their interface. For example, if the first pad BP1 and the second pad BP2 are made of copper (Cu), they can be physically and electrically connected to each other using a Cu-Cu bond. Furthermore, the insulating layers of the sensor and logic chips C1 and C2 can be bonded to each other using a dielectric-dielectric bond.

[0186] According to some example embodiments, by forming a conductive interconnect pattern that connects the floating diffusion regions to each other, the possibility and / or effects of capacitance increase and signal delay that may occur when a metal layer is used for interconnection can be prevented or reduced, and the conversion gain per unit pixel can be improved. Alternatively or additionally, the degrees of freedom in constructing the interconnect structure of the image sensor can be increased.

[0187] Alternatively or additionally, by placing a blocking pattern between the connected conductive pattern and the adjacent active pattern, the possibility of the influence of electrical connections between adjacent connected conductive patterns and active patterns and / or the influence of electrical connections between adjacent connected conductive patterns and active patterns can be prevented or reduced.

[0188] While some exemplary embodiments have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims. Furthermore, the exemplary embodiments are not necessarily mutually exclusive. For example, some exemplary embodiments may include one or more features described with reference to one or more of the accompanying drawings, and may also include one or more other features described with reference to one or more other of the accompanying drawings.

Claims

1. An image sensor, comprising: Semiconductor substrate; An isolation structure is provided in the semiconductor substrate and defines a first pixel region and a second pixel region; A transmission gate electrode is located in the first pixel region; A floating diffusion region is located in the first pixel region and on the side of the transmission gate electrode; The pixel gate electrode is located in the second pixel region; The source / drain region is located in the second pixel region and on the side of the pixel gate electrode; A connecting conductive pattern is formed on a first surface of the semiconductor substrate to connect the floating diffusion region to the source / drain region, the connecting conductive pattern including an edge portion adjacent to the outer side surface of the connecting conductive pattern; and A blocking pattern is located between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

2. The image sensor according to claim 1, wherein, When viewed in a plan view, the blocking pattern at least partially overlaps with the edge portion of the connecting conductive pattern.

3. The image sensor according to claim 1, wherein, The inner side surface of the blocking pattern contacts the portion of the connecting conductive pattern.

4. The image sensor according to claim 1, further comprising: The device isolation layer defines an active portion in each of the first pixel region and the second pixel region. The blocking pattern includes a first portion on the active portion and a second portion on the device isolation layer.

5. The image sensor according to claim 1, wherein, The conductive pattern includes pad portions that contact the floating diffusion region and the source / drain region, and The bottom surface of the pad portion is positioned at a level lower than the bottom surface of the blocking pattern.

6. The image sensor according to claim 1, wherein, The conductive pattern includes pad portions that contact the floating diffusion region and the source / drain region, and The top surface of the edge portion is at a higher level than the top surface of the pad portion.

7. The image sensor according to claim 1, wherein, The floating diffusion region, the source / drain region, and the connecting conductive pattern contain dopants of a first conductivity type. The concentration of the dopant in the conductive pattern is lower than the concentration of the dopant in the floating diffusion region.

8. The image sensor according to claim 1, wherein, The conductive pattern includes pad portions that contact the floating diffusion region and the source / drain region, and The thickness of the pad portion is less than the thickness of the pixel gate electrode.

9. The image sensor according to claim 1, further comprising: Insulating spacers are located at the first side of the transmission gate electrode, the second side of the transmission gate electrode, the first side of the pixel gate electrode, and the second side of the pixel gate electrode. The blocking pattern includes the same insulating material as the insulating spacer.

10. The image sensor according to claim 1, wherein, The floating diffusion region includes a first doped region and a second doped region within the first doped region. The doping concentration of the second doped region is higher than that of the first doped region, and The conductive pattern is connected to the second doped region of the floating diffusion region.

11. The image sensor according to claim 1, further comprising: An etch stop layer is applied to cover the transmission gate electrode and the pixel gate electrode. The etch stop layer covers the outer edge surface of the blocking pattern and the outer edge surface of the connecting conductive pattern with a uniform thickness.

12. The image sensor according to claim 1, further comprising: A first photoelectric conversion element and a second photoelectric conversion element are located in each of the first pixel region and the second pixel region and are situated within the semiconductor substrate. The transfer gate electrode includes a first transfer gate electrode and a second transfer gate electrode in each of the first pixel region and the second pixel region. The floating diffusion region includes a first floating diffusion region and a second floating diffusion region in each of the first pixel region and the second pixel region. The first transmission gate electrode is located between the first photoelectric conversion element and the first floating diffusion region, and The second transmission gate electrode is located between the second photoelectric conversion element and the second floating diffusion region.

13. An image sensor, comprising: Semiconductor substrate; An isolation structure is provided in the semiconductor substrate and defines a first pixel region and a second pixel region; Multiple photoelectric conversion elements are respectively located in the first pixel area and the second pixel area; A first transmission gate electrode and a first floating diffusion region, wherein the first transmission gate electrode is in the first pixel region and the first floating diffusion region is at the side of the first transmission gate electrode; The second transmission gate electrode is located in the second pixel area, and the second floating diffusion region is located on the side of the second transmission gate electrode. A plurality of pixel gate electrodes and source / drain regions are provided, wherein the plurality of pixel gate electrodes are respectively provided in the first pixel region and the second pixel region, and the source / drain regions are provided at a first side and a second side of each of the pixel gate electrodes; A conductive pattern is used to connect the first floating diffusion region and the second floating diffusion region to a first source / drain region, wherein the first source / drain region is one of the source / drain regions. The conductive pattern includes a first connection portion that contacts the first floating diffusion region and the second floating diffusion region, and a second connection portion that extends from the first connection portion and contacts the first source / drain region. and A blocking pattern is located between the bottom surface of the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate.

14. The image sensor according to claim 13, wherein, The outer edge surface of the connecting conductive pattern is perpendicularly aligned with the outer edge surface of the blocking pattern.

15. The image sensor according to claim 13, wherein, The portion of the connecting conductive pattern has a bottom surface at a level lower than the bottom surface of the blocking pattern.

16. The image sensor according to claim 13, wherein, The minimum width of the first connecting portion is greater than the minimum width of the second connecting portion.

17. The image sensor of claim 13, further comprising: A device isolation layer defines a first active portion and a second active portion in each of the first pixel region and the second pixel region. The first floating diffusion region and the second floating diffusion region are respectively arranged in the first active portion of the first pixel region and the second pixel region, and The source / drain regions are respectively arranged in the second active portion of the first pixel region and the second pixel region.

18. The image sensor according to claim 13, wherein, The first floating diffusion region, the second floating diffusion region, and the connecting conductive pattern include dopants of a first conductivity type. The concentration of the dopant in the conductive pattern is lower than the concentration of the dopant in the first floating diffusion region and the second floating diffusion region.

19. An image sensor, comprising: A semiconductor substrate having a first surface and a second surface opposite to each other; An isolation structure is provided in the semiconductor substrate to define a first pixel region to a fourth pixel region; Multiple photoelectric conversion elements are located in the first pixel region to the fourth pixel region and in the semiconductor substrate; A device isolation layer is adjacent to the first surface of the semiconductor substrate and defines a first active portion and a second active portion in each of the first pixel region to the fourth pixel region; Multiple transmission gate electrodes are located on the first active portion of the first pixel region to the fourth pixel region; Multiple floating diffusion regions are located in the first active portion of the first pixel region to the fourth pixel region; Multiple pixel transistors are located in the second active portion of the first to fourth pixel regions; A connecting conductive pattern is formed on the first surface of the semiconductor substrate and connects the floating diffusion region in the first pixel region to the fourth pixel region to a first source / drain region in one of the pixel transistors. The connecting conductive pattern includes an edge portion adjacent to the outer side surface of the connecting conductive pattern and a pad portion that contacts the floating diffusion region and the first source / drain region. A blocking pattern is located between the edge portion of the connecting conductive pattern and the first surface of the semiconductor substrate. Multiple color filters are arranged on the second surface of the semiconductor substrate to correspond to the first to the fourth pixel areas; A grid structure that overlaps at least partially with the isolation structure between the color filters; and Multiple microlenses are located on the multiple color filters.

20. The image sensor according to claim 19, wherein, The thickness of the pad portion of the conductive pattern is less than the thickness of the pixel gate electrode of the pixel transistor.

Images