A multi-valued memory

Abstract

The embodiment of the present application discloses a multi-value memory, which comprises: a plurality of storage sub-columns; each storage sub-column comprises a floating diffusion region and a plurality of storage units; the storage unit at least comprises: a charge storage region and a corresponding transfer transistor; part of the channel of the transfer transistor is in a vertical direction, and the transfer of the charge of the transfer transistor between the floating diffusion region and the charge storage region is controlled through a polysilicon gate structure located on both sides of the channel of the transfer transistor. The embodiment of the present application applies the transfer transistor with part of the channel in the vertical direction to the multi-value memory, and uses a photodiode as the charge storage region, so that the integration density of the transfer transistor is improved, and the cost of chip preparation is reduced.

Description

Technical Field

[0001] This invention relates to the field of storage processing, and more particularly to a multi-value memory. Background Technology

[0002] Random access memory (RAM) allows data to be read from or written on demand, and the read / write speed is independent of the data's storage location. This type of memory has the fastest read / write speeds among memory types, but it loses its stored data when power is off, so it is mainly used to store data needed for short periods. Based on the type of information stored, RAM can be further divided into static random access memory (SRAM) and dynamic random access memory (DRAM).

[0003] An existing type of SRAM, such as Figure 1 As shown, its storage cell is a flip-flop composed of six MOS transistors: P0, P1, N0, N1, N2, and N3. It has two stable states and is also called a bistable flip-flop. SRAM offers faster storage speeds and lower power consumption. However, compared to dynamic random access memory (DRAM), SRAM occupies a larger area for the same storage capacity, making it more suitable for applications requiring fast data access with relatively small data volumes.

[0004] An existing type of DRAM, such as Figure 2As shown, its memory cell is a memory circuit composed of a MOSFET M1 and a capacitor C1, where the MOSFET M1 acts as a switch and the capacitor C1 acts as the storage medium. The capacitor C1 in DRAM is generally formed using a stacked or trench configuration. The advantages are a small footprint and the ability to achieve large capacities. The disadvantages are that the manufacturing process is much more complex than logic circuits, and the access speed is slower than SRAM. Another disadvantage of DRAM is that the memory cells are stored based on the charge on the capacitor C1. This charge decreases over time and with temperature, therefore it must be refreshed periodically to maintain the correct information it originally stored. Another drawback of DRAM is the conductive interconnection between capacitor C1 and MOSFET M1, which requires a contact hole. This contact hole needs to contact the silicon surface when interconnecting with the MOSFET. This creates an interface state between the contact hole and the silicon. Electrons in the interface state are more active (the contact hole is made using plasma etching, which damages the chip surface. The presence of the interface state creates numerous defect centers on the surface, making it easier for charge carriers to be captured and released, greatly increasing leakage current). Leakage current is a very difficult problem to control (increased leakage current leads to shorter refresh time and increased power consumption). Furthermore, both DRAM and SRAM exhibit reset noise during read and write operations.

[0005] Semiconductor memory is a type of storage unit that distinguishes logical states by determining the amount of stored charge. It is characterized by low cost and simple structure, and often occupies a high density in chip design. With the continuous development of semiconductor technology, chip design is becoming increasingly complex, leading to larger and larger corresponding storage spaces. As the field of memory technology advances, memory density continues to increase, thus placing higher demands on memory structure design. Summary of the Invention

[0006] To address the above problems, the present invention aims to provide a multi-valued memory that enables a single memory cell to store multiple bits of data. A novel vertical transfer transistor is designed for this multi-valued memory, thereby achieving a high-density storage structure. The multi-valued memory includes:

[0007] Multiple storage sub-columns;

[0008] Each storage sub-column includes a floating diffusion area and multiple storage cells;

[0009] The storage unit includes at least: a charge storage region and a corresponding transfer transistor;

[0010] The transfer transistor has a partially vertical channel, and the transfer of charge between the floating diffusion region and the charge storage region is controlled by the polysilicon gate structure located on both sides of the transfer transistor channel.

[0011] In some embodiments, the method for forming the charge storage region of the memory cell includes:

[0012] The first hole structure is formed on the substrate;

[0013] A first doped epitaxial layer is formed within the pores of the first pore structure, thereby forming a lateral PN junction to achieve charge storage.

[0014] In some embodiments, the method for forming the charge storage region of the storage cell further includes:

[0015] A buffer layer is formed inside the holes of the first hole structure.

[0016] In some embodiments, the first doped epitaxial layer has a concentration gradient distribution from bottom to top.

[0017] In some embodiments, the first hole structure is formed on a P-type doped substrate, and an N-type doped epitaxial layer is used as the first doped epitaxial layer within the first hole structure of the charge storage region.

[0018] In some embodiments, the method of forming the transfer transistor includes:

[0019] The upper part of the charge storage region is etched to form a second hole structure;

[0020] An oxide layer is formed on the sides and bottom of the second porous structure;

[0021] A polycrystalline silicon layer is laid to fill the second void structure;

[0022] The polysilicon layer is etched back using an etching process, so that the surface of the polysilicon layer is lower than the upper surface of the floating diffusion region, and the gates of multiple transfer transistors are separated from each other, thereby forming the polysilicon gate of the transfer transistor.

[0023] In some embodiments, etching the upper portion of the charge storage region to form a second hole structure includes:

[0024] A second doped epitaxial layer is formed on the upper part of the charge storage region;

[0025] The second doped epitaxial layer is etched to form the second hole structure.

[0026] In some embodiments, there are isolation structures between the second perforation structures in the column direction, such that the floating diffusion areas of adjacent columns are isolated.

[0027] In some embodiments, after the polysilicon layer is laid to fill the second void structure, the following is further included:

[0028] The upper surface of the polycrystalline silicon layer is planarized using chemical mechanical polishing.

[0029] The upper part of the isolation structure is formed by etching between the second hole structures in the column direction.

[0030] In some embodiments, after the polysilicon layer is etched back through an etching process so that the surface of the polysilicon layer is lower than the upper surface of the floating diffusion region, and the gates of the multiple transfer transistors are separated from each other to form the polysilicon gate of the transfer transistor, the depth of the isolation structure is increased to complete the lower part of the isolation structure, thereby isolating the floating diffusion regions of adjacent columns.

[0031] In some embodiments, the floating diffusion region of each storage sub-column is a connected structure along the column direction.

[0032] In some embodiments, the polysilicon gate on the first side of the first transfer transistor and the polysilicon gate on the second side of the second transfer transistor in two adjacent transfer transistors in the row direction are connected to the same electrical contact point, thereby enabling the electrical contact point to control the two adjacent transfer transistors.

[0033] In some embodiments, at least two storage sub-columns share a single signal write line.

[0034] In some embodiments, when writing to each row of storage cells, a multiplexing method is used to write the signals to be stored to multiple floating diffusion areas corresponding to multiple storage sub-columns in batches.

[0035] The signals stored in the multiple floating diffusion regions are written into the charge storage region of the multiple storage sub-columns in the same row of the storage cells at once, reducing the inconsistency between adjacent storage cells.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] (1) The storage unit of the multi-value memory of the present invention is different from the existing memory structure. It can be compatible with the existing CMOS image sensor architecture and the circuit structure is simpler. It uses photodiodes as charge storage areas and realizes multi-value (multi-bit) storage by storing different amounts of charge through photodiodes.

[0038] (2) The transfer transistor of the memory cell differs from the traditional structure. Part of the channel of this transfer transistor is vertical, and the source and drain of the transfer transistor are placed from bottom to top. The source / drain regions and the channel are fabricated with epitaxial layers of different concentrations, and the structure is defined by etching. The gate of the transfer transistor does not require photolithography but is prepared through a single deposition-etch-back step with self-alignment. By using a polysilicon gate structure located on both sides of the transfer transistor channel, the transfer of charge between the floating diffusion region and the charge storage region is controlled, reducing the circuit design area and increasing the storage capacity. The fabrication process of the transfer transistor in this embodiment is fully compatible with existing transistor fabrication processes and significantly reduces the number of photomasks required. While increasing the integration density of the transfer transistor, it can reduce the cost of chip fabrication.

[0039] (3) Different storage sub-columns share a signal line. When writing to each row of storage cells, a multiple-choice method is used to write the signals to be stored to multiple floating diffusion areas corresponding to multiple storage sub-columns in batches. The signals stored in the multiple floating diffusion areas are written to the charge storage area of ​​the storage cells in the same row of the multiple storage sub-columns at one time, which reduces the inconsistency between adjacent storage cells and improves the storage speed. Attached Figure Description

[0040] The present invention will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same reference numerals denote the same structures, wherein:

[0041] Figure 1 This is a schematic diagram of the structure of a static random access memory (SRAM).

[0042] Figure 2 This is a schematic diagram of the structure of a dynamic random access memory;

[0043] Figure 3 This is a schematic diagram of a multi-value memory module according to an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of the readout circuit of the multi-value memory according to an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of the write circuit of the multi-value memory according to an embodiment of the present invention;

[0046] Figures 6 to 24 This is a schematic diagram illustrating an exemplary process for forming multiple transfer transistors corresponding to multiple memory cells, according to an embodiment of the present invention. Detailed Implementation

[0047] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0048] This invention provides a multi-value memory that differs from the architecture and implementation of existing dynamic random access memory (DRAM) and static random access memory (SRAM). It enables multi-value (multi-bit) storage while remaining compatible with CMOS image sensor architectures. Combined with... Figures 3 to 6 A multi-value memory according to an embodiment of the present invention is described.

[0049] like Figure 3 As shown, the multi-value memory 100 includes a storage area 10, a row decoder 20, and a write / read circuit 30. The storage area 10 includes multiple storage sub-arrays 110. Each storage sub-array 110 includes a floating diffusion region FD and multiple storage cells 130. For example, each storage sub-array 110 may include four storage cells 130. The read circuit 200 includes a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. The reset transistor RST is connected to the reset voltage VDD and the floating diffusion region FD, and is adapted to control the reset of the floating diffusion region FD. The source follower transistor SF is connected to the reset potential VDD, and its gate is connected to the floating diffusion region FD, and is adapted to convert the signal from the floating diffusion region FD and increase its gain to the output terminal. The row select transistor SEL is connected to the source follower transistor SF and the signal acquisition terminal, and is adapted to read the row selection of the control signal. During the readout process, the voltage of the floating diffusion region FD of a certain storage sub-array 110 is reset by the reset transistor RST, and the transfer transistor Tx corresponding to a certain storage cell 130 in the storage sub-array 110 is controlled to transfer the charge stored in the photodiode PD (also known as the charge storage region) of the storage cell 130 to the floating diffusion region FD. The signal voltage of the floating diffusion region FD is read out by the source follower transistor SF. The correlated double sampling operation is completed to obtain the charge value stored in the storage cell 130, which is converted into multi-bit wide data stored in the storage cell 130, and the readout operation of the specific storage cell 130 is completed.

[0050] like Figure 4 As shown, the storage cell 130 includes a photodiode PD and a corresponding transfer transistor Tx. The photodiode PD serves as a charge storage region. The floating diffusion region FD of each storage sub-column 110 is connected along the column direction.

[0051] like Figure 5 As shown, the write circuit 300 includes a digital-to-analog converter circuit 321. The digital-to-analog converter circuit is connected to a multiplexer switch 322. The multiplexer switch 322 is connected to multiple multiplexer switches 323. Each multiplexer switch 323 is connected to a switching transistor 324 corresponding to multiple memory sub-columns 110. In some embodiments, at least two memory sub-columns share a signal write line. For example, four memory sub-columns 110 are connected to one multiplexer switch 323 through corresponding switching transistors 324, and the four multiplexer switches 323 are connected to one multiplexer switch 322. When writing to each row of memory cells 130, a multiplexing method can be used to write the signals to be stored in batches to multiple floating diffusion regions 120 corresponding to multiple memory sub-columns 110, and then write the signals stored in the multiple floating diffusion regions FD to the charge storage region of the memory cells 130 in the same row of multiple memory sub-columns 110 at once, thereby reducing the inconsistency between adjacent memory cells. Specifically, through the switching transistor 324, multiplexer 323, and multiplexer 322, the signals to be stored can be temporarily stored sequentially into the floating diffusion regions FD corresponding to different storage sub-columns 110. The signals to be stored can be multi-bit wide data. The signals to be stored can be converted into corresponding charges and temporarily stored in the floating diffusion regions FD. The gates of the transfer transistors Tx corresponding to the storage cells 130 in the same row are connected to the word line. Therefore, by controlling the word line to simultaneously turn on the transfer transistors Tx corresponding to the storage cells 130 in the same row, signals stored in multiple floating diffusion regions FD can be written at once into the charge storage regions of multiple storage sub-columns 110 in the same row of storage cells 130.

[0052] Figures 6 to 24 This is a schematic diagram of an exemplary transfer transistor process for forming a memory cell according to an embodiment of the present invention.

[0053] like Figure 6 As shown, a substrate 401 is provided. In some embodiments, the substrate 401 may be a P-type epitaxial layer epitaxially grown on a single-crystal silicon wafer.

[0054] like Figure 7 As shown, a first hole structure 402 is formed by etching a substrate 401. In some embodiments, the first hole structures 402 are arranged in an array; the shape of the first hole structures 402 can be circular, square, rectangular, or the like. The first hole structures 402 are surrounded by a grid of active regions 403 that are mutually separated.

[0055] like Figure 8As shown, a first doped epitaxial layer 404 is formed by epitaxy of the first hole structure 402, thereby forming a lateral PN junction to realize the charge storage function, that is, the photodiode serves as the charge storage region 404. In some embodiments, a buffer layer (not shown) may also be formed within the holes of the first hole structure 402. In some embodiments, the first doped epitaxial layer 404 has a concentration gradient distribution from bottom to top. In some embodiments, the first hole structure 402 can be formed on a P-type doped substrate 401, and an N-type doped epitaxial layer is used as the first doped epitaxial layer 404 within the first hole structure 402 as the charge storage region. In some embodiments, when the first doped epitaxial layer 404 is formed by epitaxy of the first hole structure 402, the portion of the first doped epitaxial layer 404 covering the active region 403 (not shown) needs to be chemically mechanically polished to expose the grid-like active region 403 and the arrayed charge storage regions 404 (or the first doped epitaxial layer 404).

[0056] like Figure 9 As shown, a second doped epitaxial layer 405 is formed above the first doped epitaxial layer 404. The second doped epitaxial layer 405 can be P-type.

[0057] Figure 10 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 11 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 10 and 11 As shown, the second doped epitaxial layer 405 is etched to form a second hole structure 406. The remaining portion of the second epitaxial layer 405 between adjacent second hole structures 406 in the row direction serves as a transfer channel 405 for forming a transfer transistor, and the transfer channel 405 is at least partially perpendicular.

[0058] Figure 12 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 13 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 12 and 13 As shown, an oxide layer 407 is formed on the side and bottom of the second hole structure 406 and on the upper part of the transfer channel.

[0059] Figure 14 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 15 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 14 and 15 As shown, a polycrystalline silicon layer 408 is laid to fill the second void structure 406. The polycrystalline silicon layer 408 is doped with N-type ions.

[0060] Figure 16This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 17 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 16 and Figure 17 As shown, after the polysilicon layer 408 is laid to fill the second hole structure 406, chemical mechanical polishing (CMP) can be used to remove part of the polysilicon layer 408, while ensuring the removal of the oxide layer 407 on the upper part of the transfer channel 405.

[0061] Figure 18 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 19 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 18 and Figure 19 As shown, by injecting N-type ions, a floating diffusion region 409 can be formed above the vertical transfer channel 405.

[0062] Figure 20 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 21 This is a cross-sectional diagram of the corresponding column direction. For example... Figure 20 He Ru Figure 21 As shown, where, Figure 21 This is a schematic cross-sectional view along the column direction. Since two adjacent floating diffusion regions 409 are electrically connected along the row direction after N-type ion implantation, an isolation structure is needed between them to isolate them. The upper part of this isolation structure is formed by etching a third hole 410, thus preventing adjacent floating diffusion regions 120 from conducting in the row direction. The shape and size of the third hole 410 can be adjusted according to process requirements.

[0063] Figure 22 This is a three-dimensional structural diagram illustrating the process of forming the transfer transistor corresponding to the memory cell. Figure 23 This is a cross-sectional diagram of the corresponding column direction. Figure 24 This is a cross-sectional diagram of the corresponding row direction. For example... Figure 22 , 23As shown in Figure 24, to ensure complete isolation between two adjacent floating diffusion regions 409, the polysilicon layer 408 is etched back using an etching process, making the surface of the polysilicon layer 408 lower than the upper surface of the floating diffusion region 409. This separates the polysilicon gates 408 of different transfer transistors Tx along the column direction. After the etch-back process, the depth of the third hole 410 is further increased, thus deepening the isolation structure and completing the lower part of the isolation structure, thereby isolating the floating diffusion regions 409 of adjacent columns. Furthermore, electrical contact points can be formed above the polysilicon 408, allowing the same electrical contact point to control two adjacent transfer transistors Tx in the row direction.

[0064] like Figure 22 and Figure 24 As shown, a portion of the channel 405 of the transfer transistor Tx is vertical. Through the polysilicon 408 located on both sides of the transfer channel 405, the transfer of charge between the transfer transistor Tx and the floating diffusion region 409 and the charge storage region 404 can be controlled. In some embodiments, the floating diffusion region 409 corresponds to the area above the middle region of the charge storage region 404, that is, the floating diffusion region 409 is disposed above the center position of the charge storage region 404. In some embodiments, the floating diffusion region 409 may be offset from the middle region of the charge storage region 404, that is, the floating diffusion region 409 is offset from the center position of the charge storage region 404 to a certain extent.

[0065] The basic concepts have been described above. It is clear that the detailed disclosure above is merely illustrative and does not constitute a limitation of the present invention. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to the present invention by those skilled in the art. Such modifications, improvements, and corrections are suggested in this invention and therefore remain within the spirit and scope of the exemplary embodiments of the present invention.

[0066] It should be understood that the embodiments described in this invention are merely illustrative of the principles of the invention. Other modifications may also fall within the scope of this invention. Therefore, alternative configurations of the embodiments of this invention are considered as examples and not limitations, and are regarded as consistent with the teachings of this invention. Accordingly, the embodiments of this invention are not limited to those explicitly described and illustrated herein.

Claims

1. A multi-value memory, characterized in that, include: Multiple storage sub-columns; Each storage sub-column includes a floating diffusion area and multiple storage cells; The storage unit includes at least: a charge storage region and a corresponding transfer transistor; The transfer transistor has a partially vertical channel. The transfer of charge between the floating diffusion region and the charge storage region is controlled by a polysilicon gate structure located on both sides of the transfer transistor channel. The surface of the polysilicon gate structure is lower than the upper surface of the floating diffusion region.

2. The multi-value memory as described in claim 1, characterized in that, The method for forming the charge storage region of the memory cell includes: The first hole structure is formed on the substrate; A first doped epitaxial layer is formed within the pores of the first pore structure, thereby forming a lateral PN junction to achieve charge storage.

3. The multi-value memory as described in claim 2, characterized in that, The method for forming the charge storage region of the storage cell further includes: A buffer layer is formed inside the holes of the first hole structure.

4. The multi-value memory as described in claim 2, characterized in that, The first doped epitaxial layer has a concentration gradient distribution from bottom to top.

5. The multi-value memory as described in claim 2, characterized in that, The first hole structure is formed on a P-type doped substrate, and an N-type doped epitaxial layer is used as the first doped epitaxial layer within the first hole structure of the charge storage region.

6. The multi-value memory as described in claim 1, characterized in that, The method for forming the transfer transistor includes: The upper part of the charge storage region is etched to form a second hole structure; An oxide layer is formed on the sides and bottom of the second porous structure; A polycrystalline silicon layer is laid to fill the second void structure; The polysilicon layer is etched back using an etching process, so that the surface of the polysilicon layer is lower than the upper surface of the floating diffusion region, and the gates of multiple transfer transistors are separated from each other, thereby forming the polysilicon gate of the transfer transistor.

7. The multi-value memory as described in claim 6, characterized in that, The etching of the upper part of the charge storage region to form a second hole structure includes: A second doped epitaxial layer is formed on the upper part of the charge storage region; The second doped epitaxial layer is etched to form the second hole structure.

8. The multi-value memory as described in claim 7, characterized in that, There are isolation structures between the second hole structures in the column direction, which isolate the floating diffusion areas of adjacent columns.

9. The multi-value memory as described in claim 8, characterized in that, After the polycrystalline silicon layer is laid to fill the second void structure, the following is also included: The upper surface of the polycrystalline silicon layer is planarized using chemical mechanical polishing. The upper part of the isolation structure is formed by etching between the second hole structures in the column direction.

10. The multi-value memory as described in claim 9, characterized in that, After the polysilicon layer is etched back through an etching process, so that the surface of the polysilicon layer is lower than the upper surface of the floating diffusion region, and the gates of multiple transfer transistors are separated from each other to form the polysilicon gate of the transfer transistor, the depth of the isolation structure is increased, thereby completing the lower part of the isolation structure and isolating the floating diffusion regions of adjacent columns.

11. The multi-value memory as described in claim 1, characterized in that, The floating diffusion region of each storage sub-column has a connected structure along the column direction.

12. The multi-value memory as described in claim 1, characterized in that, In two adjacent transfer transistors in the row direction, the polysilicon gate on the first side of the first transfer transistor and the polysilicon gate on the second side of the second transfer transistor are connected to the same electrical contact point, thereby enabling the electrical contact point to control the two adjacent transfer transistors.

13. The multi-value memory as described in claim 1, characterized in that, At least two storage sub-columns share a single signal write line.

14. The multi-value memory as described in claim 13, characterized in that, When writing to each row of storage cells, a multi-way selection method is used to write the signals to be stored to multiple floating diffusion areas corresponding to multiple storage sub-columns in batches. The signals stored in the multiple floating diffusion regions are written into the charge storage region of the multiple storage sub-columns in the same row of the storage cells at once, reducing the inconsistency between adjacent storage cells.

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