Semiconductor device and method of manufacturing the same
By forming a dielectric repair layer on the surface of the shallow trench isolation structure, the problem of weakened isolation effect caused by the side trench is solved, and the electrical performance and reliability of the device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2026-06-23
AI Technical Summary
In the semiconductor device manufacturing process, the trenches formed at the top edge of the shallow trench isolation structure weaken the isolation effect and affect the electrical performance of the device.
After the oxide layer of the liner is removed, a dielectric repair layer is formed on the surface of the shallow trench isolation structure by selective deposition process to fill the side trench and improve the isolation effect.
This improves the isolation effect of shallow trench isolation structures, thereby enhancing the electrical performance and reliability of devices.
Smart Images
Figure CN122270129A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] Please refer to Figure 1 In current semiconductor device manufacturing processes, the shallow trench isolation (STI) structure fabrication process (STI Loop) is a crucial step for isolating adjacent devices and preventing leakage. It generally includes the following steps: growing a pad oxide layer 101 on a substrate 100 and depositing a silicon nitride layer 102 as a hard mask; performing dry etching (STI ecth) on the silicon nitride layer 102, pad oxide layer 101, and substrate 100 to form a shallow trench 104; growing a liner oxide layer 103a in the shallow trench 104 and filling it with silicon oxide 103b; performing top chemical mechanical polishing (STI CMP) on the filled silicon oxide until the top surface of the silicon nitride layer 102 is exposed; and removing the silicon nitride layer 102 through etching or chemical mechanical polishing to adjust the step height difference between the filled silicon oxide and the top surface of the substrate 100. (high); then the pad oxide layer 101 is removed by wet etching process to form shallow trench isolation structure 103.
[0003] In particular, because the wet etching process for removing the pad oxide layer 101 is isotropic, the etching solution can easily penetrate to the interface between the shallow trench isolation structure 103 and the substrate 100 during the removal of the pad oxide layer 101 and etch the top edge of the shallow trench isolation structure 103. This results in the appearance of a divot 103c at the top edge of the shallow trench isolation structure 103. This divot 103c will shorten the interval between the ion implantation regions formed in subsequent ion implantation processes (such as source-drain ion implantation processes), weaken the isolation effect of the shallow trench isolation structure 103, and affect the electrical performance of the device. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which can solve the problem that the side trench formed at the top edge of the shallow trench isolation structure weakens the isolation effect of the shallow trench isolation structure, thereby improving the electrical performance of the device.
[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
[0006] A substrate is provided, and a pad oxide layer and a hard mask layer are sequentially formed on the substrate;
[0007] The hard mask layer, the pad oxide layer, and the substrate are etched sequentially to form shallow trenches in the substrate;
[0008] An insulating dielectric layer is deposited on the hard mask layer and in the shallow trench, and the insulating dielectric layer fills the shallow trench;
[0009] The insulating dielectric layer is planarized at the top until the silicon nitride layer is exposed and the top height of the insulating dielectric layer filling the shallow trench reaches the required level.
[0010] The hard mask layer is removed by etching, and the pad oxide layer is removed by a first wet etching process to form a shallow trench isolation structure. The top edge of the shallow trench isolation structure generates a side trench in the first wet etching process.
[0011] A dielectric repair layer is formed on the surface of the shallow trench isolation structure using a selective deposition process, and the dielectric repair layer fills the trench.
[0012] Optionally, the insulating dielectric layer can be planarized at the top using a chemical mechanical polishing process until a portion of the hard mask layer is removed.
[0013] Optionally, the hard mask layer comprises a silicon nitride layer or comprises a silicon nitride layer and a silicon oxide layer sequentially stacked on the pad oxide layer; and / or, the insulating dielectric layer comprises silicon oxide.
[0014] Optionally, the hard mask layer may be removed using a dry etching process, a second wet etching process, or a chemical mechanical polishing process.
[0015] Optionally, the first wet etching process is achieved through multi-step wet cleaning or by using an etching solution formed by mixing multiple etching solutions. The etching solution used in the first wet etching process includes at least one of hydrofluoric acid solution, SC1 cleaning solution and SC2 cleaning solution. The SC1 cleaning solution includes ammonium hydroxide, hydrogen peroxide and water, and the SC2 cleaning solution includes hydrochloric acid, hydrogen peroxide and water.
[0016] Optionally, the first wet etching process contains corresponding functional groups on the exposed surface of the shallow trench isolation structure, and / or, after the pad oxide layer is removed by the first wet etching process and before the selective deposition process, the exposed surface of the shallow trench isolation structure is treated to enrich the exposed surface of the shallow trench isolation structure with the functional groups.
[0017] The selective deposition process utilizes the selectivity of the reaction precursor to the functional groups, so that the reaction precursor is adsorbed only on the exposed surface of the shallow trench isolation structure to generate the dielectric repair layer.
[0018] Optionally, the functional group includes a hydroxyl functional group, the reaction precursor includes diisopropylaminosilane, the selective deposition process is an atomic layer deposition process with a deposition temperature below 100°C, and the dielectric repair layer includes silicon oxide.
[0019] Optionally, the manufacturing method further includes at least one of the following (1) to (4):
[0020] (1) Before depositing the insulating dielectric layer, a line oxide layer is first grown on the inner surface of the shallow trench;
[0021] (2) The insulating dielectric layer is deposited using a high-density plasma chemical vapor deposition process or a high aspect ratio filling process;
[0022] (3) After the formation of the dielectric repair layer or before the formation of the shallow trench in the substrate, trap ion implantation is performed on the substrate;
[0023] (4) After forming the dielectric repair layer, a gate structure and a gate sidewall located on the sidewall of the gate structure are formed on the substrate, and source / drain ion implantation is performed on the substrates on both sides of the gate structure.
[0024] Based on the same inventive concept, the present invention also provides a semiconductor device comprising:
[0025] A substrate in which shallow trenches are formed;
[0026] A shallow trench isolation structure, filled in the shallow trench and having a side trench at its top edge;
[0027] The medium repair layer is formed on top of the shallow trench isolation structure and fills the side trench using a selective deposition process.
[0028] Optionally, the shallow trench isolation structure contains corresponding functional groups on the surfaces exposed by the substrate and the trench. The dielectric repair layer is formed by the selective deposition process whereby the reaction precursor is adsorbed onto the exposed surface of the shallow trench isolation structure by the functional groups and reacts. When the functional groups include hydroxyl functional groups and the reaction precursor includes diisopropylaminosilane, the dielectric repair layer includes silicon oxide.
[0029] Compared with the prior art, the semiconductor device manufacturing method of the present invention adds a selective deposition process after the pad oxide layer is removed by the first wet etching process in the manufacturing process of the shallow trench isolation structure. The selective deposition process forms a dielectric repair layer on the exposed surface of the formed shallow trench isolation structure, and the dielectric repair layer fills the side trench at the top edge of the shallow trench isolation structure. This solves the problem that the side trench formed at the top edge of the shallow trench isolation structure weakens the isolation effect of the shallow trench isolation structure, thereby improving the electrical performance of the device.
[0030] The semiconductor device of the present invention has a dielectric repair layer that is selectively deposited into the side trench at the top edge of the shallow trench isolation structure, thereby ensuring the isolation effect of the shallow trench isolation structure and improving the electrical performance and reliability of the device. Attached Figure Description
[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0032] Figure 1 This is a schematic diagram of a cross-sectional view of a device in an existing semiconductor device manufacturing method.
[0033] Figure 2 This is a schematic diagram of a semiconductor device manufacturing method according to an embodiment of the present invention.
[0034] Figure 3 This is a schematic cross-sectional view of a semiconductor device in a manufacturing method according to an embodiment of the present invention. Detailed Implementation
[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0036] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0037] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:
[0038] S1, a substrate is provided, and a pad oxide layer and a hard mask layer are sequentially formed on the substrate;
[0039] S2, the hard mask layer, the pad oxide layer and the substrate are etched sequentially to form shallow trenches in the substrate;
[0040] S3, deposit an insulating dielectric layer on the hard mask layer and in the shallow trench, and the insulating dielectric layer fills the shallow trench;
[0041] S4, planarize the top of the insulating dielectric layer until the silicon nitride layer is exposed and the top height of the insulating dielectric layer filled in the shallow trench reaches the requirement;
[0042] S5, the hard mask layer is etched away and the pad oxide layer is removed by a first wet etching process to form a shallow trench isolation structure. The top edge of the shallow trench isolation structure generates a side trench in the first wet etching process.
[0043] S6, a medium repair layer is formed on the surface of the shallow trench isolation structure using a selective deposition process, and the medium repair layer fills the trench.
[0044] Please refer to Figure 3 In step (A), in step S1, firstly, a substrate 100 is provided, which may be silicon, silicon carbide (SiC), or silicon germanide (SiGe), or silicon-on-insulator (SOI), or may include other materials such as indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Then, a pad oxide layer (e.g., silicon dioxide SiO2) 101 is grown on the substrate 100 by a thermal oxidation process, and a corresponding dielectric material is deposited by a chemical vapor deposition (CVD) process to form a hard mask layer 102 (also known as an "etch barrier layer"). The hard mask layer 102 may be a single dielectric material film, such as silicon nitride, or a composite structure composed of multiple layers of different dielectric material films, such as silicon nitride and silicon dioxide stacked sequentially from bottom to top (i.e., NO structure), or silicon nitride, silicon dioxide, and silicon nitride stacked sequentially from bottom to top (i.e., ONO structure). The pad oxide layer 101 serves as a stress buffer layer between the hard mask layer 102 and the silicon surface of the substrate 100, and prevents the hard mask layer 102 from damaging the silicon surface of the substrate 100.
[0045] Please refer to Figure 3 In step S2, (A) firstly, a patterned photoresist layer (not shown) can be formed on the hard mask layer 102 by photolithography. Then, using the patterned photoresist layer as a mask, the hard mask layer 102, the pad oxide layer 101 and the substrate 100 are sequentially etched by dry etching to form a shallow trench 104 in the substrate 100. After that, the patterned photoresist layer is removed.
[0046] In other examples, in step S2, after a patterned photoresist layer is formed on the hard mask layer 102 by photolithography, the hard mask layer 102 can be etched open by dry etching using the patterned photoresist layer as a mask, and then the patterned photoresist layer can be removed. The pad oxide layer 101 can be etched open by dry etching using the hard mask layer 102 as a mask, and the substrate 100 can be further etched to form a shallow trench 104 in the substrate 100.
[0047] Optionally, after forming the shallow trench 104, the hard mask layer 102 and the pad oxide layer 101 can be etched back using any suitable etching process, such as dry etching or wet etching, to increase the top opening size of the shallow trench 104.
[0048] Please refer to Figure 3 In step (B) of the above, in step S3, firstly, a linear oxide layer 103a can be formed on the inner surface of the shallow trench 104 using any suitable process such as thermal oxidation or atomic layer deposition to improve the interface characteristics between the substrate and the subsequently filled insulating dielectric layer 103b. Then, an insulating dielectric layer 103b can be deposited on the surface of the hard mask layer 102 and the shallow trench 104 using any suitable deposition process such as high-density plasma chemical vapor deposition (HDPCVD) or high aspect ratio (HARP) filling. The deposited insulating dielectric layer 103b can at least fill the shallow trench 104. The material of the insulating dielectric layer 103b can be any suitable material, such as silicon oxide.
[0049] Optionally, in step S3, after forming the linear oxide layer 103a and before depositing the insulating dielectric layer 103b, the linear oxide layer 103a is annealed in an oxygen atmosphere to improve the density of the linear oxide layer 103a.
[0050] Please refer to Figure 3 In step S4 (C), the deposited insulating dielectric layer 103b is planarized using a chemical mechanical polishing (CMP) process. This CMP process can stop at the hard mask layer 102 to remove the insulating dielectric layer 103b on the hard mask layer 102, forming a shallow trench isolation structure 103. Optionally, after exposing the top surface of the hard mask layer 102, the CMP process can further polish the top of the hard mask layer 102 to adjust the top height of the shallow trench isolation structure 103.
[0051] After the chemical mechanical polishing process in step S4 is completed, the top height of the insulating dielectric layer 103b filled in the shallow trench 104 meets the requirements. Due to the different polishing rates of the polishing slurry on different media, there will be a step height difference between the top of the insulating dielectric layer 103b filled in the shallow trench 104 and the top of the hard mask layer 102.
[0052] Please refer to Figure 3In step (D), in step S5, firstly, a dry etching process, a second wet etching process, or a chemical mechanical polishing process can be used to remove the hard mask layer 102 to expose the pad oxide layer 101, thereby adjusting the step height difference between the top of the shallow trench isolation structure 103 and the substrate 100; then, a first wet etching process is used to remove the pad oxide layer 101 to expose the top surface of the substrate 100 surrounding the shallow trench isolation structure 103. This first wet etching process not only removes the pad oxide layer 101 but also simultaneously etches the top of the shallow trench isolation structure 103 to reduce the step height difference between the top of the shallow trench isolation structure 103 and the substrate 100. For example, the top of the shallow trench isolation structure 103 is lowered to be basically flush with the substrate 100, while the etching solution penetrates into the junction of the shallow trench isolation structure 103 and the substrate 100 and performs etching, forming a side trench 103c at the top edge of the shallow trench isolation structure 103.
[0053] Optionally, the first wet etching process for removing the oxide layer 101 of the liner can be achieved through multi-step wet cleaning, or it can be achieved by using an etching solution formed by mixing multiple etching solutions in a single step. The etching solution used in the first wet etching process includes at least one of hydrofluoric acid solution, SC1 cleaning solution and SC2 cleaning solution. The SC1 cleaning solution includes ammonium hydroxide, hydrogen peroxide and water, and the SC2 cleaning solution includes hydrochloric acid, hydrogen peroxide and water.
[0054] In one example, in the first wet etching process, the pad oxide layer 101 is first wet etched with a diluted hydrofluoric acid solution (DHF) or a hydrofluoric acid buffer (BHF, whose components are NH4F, HF and water) to remove the pad oxide layer 101 and expose the top surface of the substrate 100; then, the surface is cleaned with SC1 cleaning solution at a reaction temperature of 25 degrees Celsius to remove particulate impurities and polymers on the surface of the substrate 100; after that, the surface is cleaned with SC2 cleaning solution to remove metal ions and other residues on the upper surface of the substrate 100.
[0055] In another example, in this first wet etching process, hydrofluoric acid and SC1 cleaning solution are used to wet etch the pad oxide layer 101 to remove the pad oxide layer 101 and expose the top surface of the substrate 100.
[0056] In one example, the second wet etching process described above uses an etching solution such as hot phosphoric acid to wet etch the hard mask layer 102, thereby removing the hard mask layer 102.
[0057] Please refer to Figure 3In step S6, any suitable selective deposition process can be used to deposit a medium repair layer 105 on the exposed surface of the shallow trench isolation structure 103 (i.e., the top surface of the shallow trench isolation structure 103 and the exposed sidewall surface of the side trench 103c) to repair the top damage of the shallow trench isolation structure 103 and fill the side trench 103c.
[0058] The shallow trench isolation structure 103 and the dielectric repair layer 105 together form a complete shallow trench isolation structure with good isolation effect. Thus, the shallow trench isolation structure formed by the combination of the shallow trench isolation structure 103 and the dielectric repair layer 105 defines multiple active regions in the substrate 100 and achieves the required insulation isolation effect between adjacent active regions.
[0059] In this embodiment, the first wet etching process used in step S5 will cause the exposed surface of the shallow trench isolation structure 103 to contain corresponding specific functional groups. The selective deposition process used in step S6 can utilize the selectivity of its reaction precursor to the specific functional group, so that the reaction precursor is only adsorbed and reacted on the exposed surface of the shallow trench isolation structure 103, thereby forming a dielectric repair layer 105. The thickness of the dielectric repair layer 105 is sufficient to fill the side trench 103c, thereby solving the problem that the side trench 103c formed at the top edge of the shallow trench isolation structure 103 weakens the isolation effect of the shallow trench isolation structure 103, and thus improving the electrical performance of the device.
[0060] As an example, the functional group includes a hydroxyl functional group (-OH), the selective deposition process is atomic layer deposition (ALD), and the reaction precursor used includes diisopropylaminosilane (DIPAS), whose deposition temperature is below 100°C. DIPAS is a special reaction precursor for the ALD process; its selectivity to surface functional groups below 100°C allows DIPAS to be adsorbed only on the exposed surface of the shallow trench isolation structure 103 containing hydroxyl functional groups (-OH), generating silicon oxide (SiO2) as the desired dielectric repair layer 105. Since there are no Si-OH bonds on the exposed surface of the substrate 100, the ALD process will not deposit the dielectric repair layer 105 on the exposed surface of the substrate 100.
[0061] In other examples, if the required functional groups cannot be generated or the generated functional groups are insufficient in step S5, the exposed surface of the shallow trench isolation structure 103 (including its top surface and its sidewall surface exposed by the side trench 103c) can be further processed after step S5 is completed and before the selective deposition process in step S6, so that the exposed surface of the shallow trench isolation structure 103 is rich in the functional groups that can be used to generate the medium repair layer 105.
[0062] Optionally, in the semiconductor device manufacturing method of this embodiment, after completing step S6 (i.e., forming the dielectric repair layer 105) or before performing step S2 (i.e., forming the shallow trench 104 in the substrate 100), the substrate 100 is implanted with n-type ions or p-type ions to form the desired well region in the substrate 100.
[0063] After completing step S6 (i.e., forming the dielectric repair layer 105), the semiconductor device manufacturing method of this embodiment can also perform some subsequent series of processes, such as further forming a gate structure (not shown) on the substrate 100, forming a gate sidewall (not shown) on the sidewall of the gate structure, performing source and drain ion implantation on the substrate 100 on both sides of the gate structure, etc.
[0064] The steps for forming the gate structure may include: first, forming a gate oxide layer (not shown) on the surface of the substrate 100 using a thermal oxidation process; then, depositing a polysilicon layer on both the surface of the gate oxide layer and the surface of the shallow trench isolation structure 103 using plasma-assisted chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDPCVD) processes, and forming a silicon nitride hard mask layer (not shown) on the surface of the polysilicon layer; next, etching the silicon nitride hard mask layer, the polysilicon layer, and the gate oxide layer using photolithography and etching processes to form a gate structure, which includes a polysilicon layer and a gate oxide layer at its bottom; and then removing the remaining photoresist.
[0065] The formed gate sidewall can be a single-layer film structure or a composite structure composed of multiple layers, such as an ONO structure, which includes silicon oxide (O), silicon nitride (N), and silicon oxide (O) stacked sequentially from the inside out, or an ONON structure. As an example, the steps for forming the gate sidewall include: firstly, using any suitable process such as CVD or HDP CVD, sequentially depositing a silicon oxide layer (not shown) and a silicon nitride layer (not shown), and then etching the silicon nitride layer and silicon oxide layer to form an offset sidewall; then, performing lightly doped drain ion implantation (LDD) on the substrate 100 on both sides of the gate structure to form a lightly doped region (not shown); then, sequentially depositing a silicon oxide layer and a silicon nitride layer, and then etching the silicon nitride layer and silicon oxide layer to form a spacer sidewall, which, together with the offset sidewall, constitutes the gate sidewall.
[0066] The semiconductor device manufacturing method of the present invention, in the manufacturing process of the shallow trench isolation structure, adds a selective deposition process after the pad oxide layer is removed by a first wet etching process. The selective deposition process forms a dielectric repair layer on the exposed surface of the formed shallow trench isolation structure, and the dielectric repair layer fills the side trench at the top edge of the shallow trench isolation structure. This solves the problem that the side trench formed at the top edge of the shallow trench isolation structure weakens the isolation effect of the shallow trench isolation structure, thereby improving the electrical performance of the device. It can be applied to the manufacturing of semiconductor devices including but not limited to 40nm process nodes.
[0067] Based on the same inventive concept, please refer to Figure 3 An embodiment of the present invention also provides a semiconductor device, which can be manufactured using the semiconductor device manufacturing method of the present invention. The semiconductor device includes a substrate 100, a shallow trench isolation structure 103, and a dielectric repair layer 105. A shallow trench 104 is formed in the substrate 100, and the shallow trench isolation structure 103 fills the shallow trench 104, with a side groove 103c at its top edge. The dielectric repair layer 105 is formed on the exposed surface of the shallow trench isolation structure 103 and fills the side groove 103c at the top edge of the shallow trench isolation structure 103.
[0068] The shallow trench isolation structure 103 may include a linear oxide layer 103a formed on the inner surface of the shallow trench 104 and an insulating dielectric layer 103b filled in the shallow trench 104.
[0069] Optionally, the shallow trench isolation structure 103 has corresponding functional groups on the surface exposed by the substrate 100 and the side trench 103c. The dielectric repair layer 105 is formed by selectively depositing a reaction precursor, which is adsorbed onto the exposed surface of the shallow trench isolation structure 103 by the functional group and reacted. When the functional group includes a hydroxyl functional group and the reaction precursor includes diisopropylaminosilane, the dielectric repair layer 105 includes silicon oxide.
[0070] It should be understood that multiple ion implantation regions can be formed in the substrate 100 as needed. A shallow trench 104 is formed in the substrate 100 between any two ion implantation regions that need to be spaced apart. The shallow trench 104 is filled with the shallow trench isolation structure 103 to separate them. The shallow trench isolation structure 103 and the dielectric repair layer 105 filled in each shallow trench 104 actually form the complete shallow trench isolation structure required in the shallow trench 104. This ensures the length of the interval between ion implantations formed in the substrate 100, and ensures that the isolation effect of the shallow trench isolation structure at the interval is weakened, thereby improving the electrical performance of the device.
[0071] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, and a pad oxide layer and a hard mask layer are sequentially formed on the substrate; The hard mask layer, the pad oxide layer, and the substrate are etched sequentially to form shallow trenches in the substrate; An insulating dielectric layer is deposited on the hard mask layer and in the shallow trench, and the insulating dielectric layer fills the shallow trench; The insulating dielectric layer is planarized at the top until the silicon nitride layer is exposed and the top height of the insulating dielectric layer filling the shallow trench reaches the required level. The hard mask layer is removed and the pad oxide layer is removed by a first wet etching process to form a shallow trench isolation structure. The top edge of the shallow trench isolation structure generates a side trench in the first wet etching process. A dielectric repair layer is formed on the surface of the shallow trench isolation structure using a selective deposition process, and the dielectric repair layer fills the trench.
2. The manufacturing method as described in claim 1, characterized in that, The insulating dielectric layer is planarized at the top using a chemical mechanical polishing process until a portion of the hard mask layer is removed.
3. The manufacturing method as described in claim 1, characterized in that, The hard mask layer includes a silicon nitride layer or includes a silicon nitride layer and a silicon oxide layer sequentially stacked on the pad oxide layer; and / or, the insulating dielectric layer includes silicon oxide.
4. The manufacturing method as described in claim 1, characterized in that, The hard mask layer is removed using a dry etching process, a second wet etching process, or a chemical mechanical polishing process.
5. The manufacturing method as described in claim 1, characterized in that, The first wet etching process is achieved through multi-step wet cleaning or by using an etching solution formed by mixing multiple etching solutions. The etching solution used in the first wet etching process includes at least one of hydrofluoric acid solution, SC1 cleaning solution and SC2 cleaning solution. The SC1 cleaning solution includes ammonium hydroxide, hydrogen peroxide and water, and the SC2 cleaning solution includes hydrochloric acid, hydrogen peroxide and water.
6. The manufacturing method according to any one of claims 1-5, characterized in that, The first wet etching process makes the exposed surface of the shallow trench isolation structure contain corresponding functional groups, and / or, after the pad oxide layer is removed by the first wet etching process and before the selective deposition process, the exposed surface of the shallow trench isolation structure is treated to make the exposed surface of the shallow trench isolation structure rich in the functional groups. The selective deposition process utilizes the selectivity of the reaction precursor to the functional groups, so that the reaction precursor is adsorbed only on the exposed surface of the shallow trench isolation structure to generate the dielectric repair layer.
7. The manufacturing method as described in claim 6, characterized in that, The functional group includes a hydroxyl functional group, the reaction precursor includes diisopropylaminosilane, the selective deposition process is an atomic layer deposition process, the deposition temperature is below 100°C, and the dielectric repair layer includes silicon oxide.
8. The manufacturing method according to any one of claims 1-5 or 7, characterized in that, It also includes at least one of the following (1) to (4): (1) Before depositing the insulating dielectric layer, a line oxide layer is first grown on the inner surface of the shallow trench; (2) The insulating dielectric layer is deposited using a high-density plasma chemical vapor deposition process or a high aspect ratio filling process; (3) After the formation of the dielectric repair layer or before the formation of the shallow trench in the substrate, trap ion implantation is performed on the substrate; (4) After forming the dielectric repair layer, a gate structure and a gate sidewall located on the sidewall of the gate structure are formed on the substrate, and source / drain ion implantation is performed on the substrates on both sides of the gate structure.
9. A semiconductor device, characterized in that, include: A substrate in which shallow trenches are formed; A shallow trench isolation structure, filled in the shallow trench and having a side trench at its top edge; The medium repair layer is formed on top of the shallow trench isolation structure and fills the side trench using a selective deposition process.
10. The semiconductor device as claimed in claim 9, characterized in that, The shallow trench isolation structure contains corresponding functional groups on the surfaces exposed by the substrate and the trench. The dielectric repair layer is formed by the selective deposition process whereby the reaction precursor is adsorbed onto the exposed surface of the shallow trench isolation structure by the functional groups and reacts. When the functional groups include hydroxyl functional groups and the reaction precursor includes diisopropylaminosilane, the dielectric repair layer includes silicon oxide.