Testing methods and apparatus for printed circuit board assemblies

Abstract

The method and apparatus for testing printed circuit board assemblies provided in this application include: acquiring the identification information of the printed circuit board assembly under test and determining a matching test configuration and functional dependency knowledge graph accordingly; performing electrical connection testing and static electrical parameter baseline acquisition on the printed circuit board assembly under test according to the test configuration to obtain static baseline data; applying dynamic load excitation to the associated power network of the printed circuit board assembly under test according to the test configuration and functional dependency knowledge graph to collect corresponding dynamic response data; determining a test execution strategy based on the functional dependency knowledge graph, static baseline data, and dynamic response data, and determining corresponding test data accordingly; and determining the root cause of the fault and generating a diagnostic report based on the functional dependency knowledge graph, test data, static baseline data, and dynamic response data; thereby improving the testing efficiency and accuracy of printed circuit board assemblies.

Description

Technical Field

[0001] This application relates to the field of electronic manufacturing testing and quality control technology, and in particular to a method and apparatus for testing printed circuit board assemblies. Background Technology

[0002] With the rapid development of electronic manufacturing technology and the urgent need for high reliability in fields such as industrial control, communication equipment, and consumer electronics, printed circuit board assemblies (PCBAs), as the core carriers, have become a major threat to product quality due to dynamic performance defects (such as poor power network soldering and electrostatic damage). Therefore, developing a PCBA testing method that can proactively induce defects under simulated real-world conditions, intelligently adjust testing strategies, and automatically locate the root cause of failures has become a challenging and significant research topic.

[0003] Existing technologies mainly include static testing, fixed-process functional circuit testing (FCT), and human experience-based diagnostics. Static testing uses Automated Optical Inspection (AOI) for visual inspection and in-circuit testing (ICT) for circuit connectivity testing; fixed-process functional testing relies on the entire machine or complete peripheral environment to verify PCBA functionality through preset programs; and human experience-based diagnostics relies on engineers' experience to locate the root cause of functional abnormalities.

[0004] However, existing static testing technologies cannot capture functional defects under dynamic loads, fixed-process functional testing has long development cycles, high costs, and is difficult to adapt to multi-variety, small-batch production, while manual experience-based diagnosis is inefficient and inconsistent. These factors result in the technical problems of poor testing efficiency and low accuracy for printed circuit board components in existing technologies. Summary of the Invention

[0005] This application provides a method and apparatus for testing printed circuit board assemblies, which aims to improve the testing efficiency and accuracy of printed circuit board assemblies.

[0006] In a first aspect, this application provides a method for testing printed circuit board assemblies, comprising:

[0007] Obtain the identification information of the printed circuit board assembly under test;

[0008] Based on the identification information, determine the matching test configuration and functional dependency knowledge graph;

[0009] According to the test configuration, electrical connection testing and static electrical parameter baseline acquisition are performed on the printed circuit board assembly under test to obtain static baseline data.

[0010] Based on the test configuration and functional dependency knowledge graph, dynamic load stimulation is applied to the associated power network of the printed circuit board assembly under test to collect the corresponding dynamic response data.

[0011] Based on the functional dependency knowledge graph, static baseline data, and dynamic response data, determine the test execution strategy;

[0012] Determine the corresponding test data based on the test execution strategy;

[0013] Based on the functional dependency knowledge graph, test data, static baseline data, and dynamic response data, the corresponding root causes of failures are identified and diagnostic reports are generated.

[0014] Secondly, this application provides a testing device for printed circuit board assemblies, comprising:

[0015] The acquisition module is used to acquire the identification information of the printed circuit board assembly under test;

[0016] The first processing module is used to determine the matching test configuration and functional dependency knowledge graph based on the identification information;

[0017] The second processing module is used to perform electrical connection detection and static electrical parameter baseline acquisition on the printed circuit board assembly under test according to the test configuration, and obtain static baseline data.

[0018] The acquisition module is used to apply dynamic load stimulation to the associated power network of the printed circuit board assembly under test based on the test configuration and functional dependency knowledge graph, so as to acquire the corresponding dynamic response data.

[0019] The third processing module is used to determine the test execution strategy based on the functional dependency knowledge graph, static baseline data, and dynamic response data.

[0020] The fourth processing module is used to determine the corresponding test data based on the test execution strategy;

[0021] The generation module is used to determine the corresponding root causes of failures and generate diagnostic reports based on the functional dependency knowledge graph, test data, static baseline data, and dynamic response data.

[0022] Thirdly, this application provides a testing device for printed circuit board assemblies, including: a memory and a processor;

[0023] The memory stores instructions that the computer executes;

[0024] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0025] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible embodiments of the first aspect.

[0026] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0027] This application provides a method and apparatus for testing printed circuit board (PCB) assemblies. By acquiring the identification information of the PCB assembly under test, it provides a foundation for accurately matching the corresponding test configuration and functional dependency knowledge graph, ensuring the directionality and accuracy of the testing. Based on the identification, the matching test configuration and functional dependency knowledge graph are determined, establishing a scientific framework for subsequent testing processes and ensuring orderly testing. Electrical connection testing and static electrical parameter baseline acquisition are performed according to the test configuration, enabling timely screening of basic faults such as short circuits and obtaining static baseline data. Applying dynamic load excitation to the associated power network and collecting dynamic response data simulates real-world operating conditions. By comprehensively considering the functional dependency knowledge graph, static baseline data, and dynamic response data, the test execution strategy and test data are determined, thereby identifying the root cause of the fault and generating a diagnostic report. Overall, this achieves the technical effect of improving testing efficiency and accuracy. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0029] Figure 1 This application provides a schematic diagram of an application data processing system architecture.

[0030] Figure 2 A schematic diagram of the structure of a printed circuit board assembly inspection system provided in an embodiment of this application;

[0031] Figure 3 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 1 ;

[0032] Figure 4 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 2 ;

[0033] Figure 5 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 3 ;

[0034] Figure 6 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 4 ;

[0035] Figure 7 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 5 ;

[0036] Figure 8 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 6 ;

[0037] Figure 9 A schematic diagram of the structure of the testing device for printed circuit board assemblies provided in the embodiments of this application;

[0038] Figure 10 This is a schematic diagram of the structure of the testing equipment for printed circuit board assemblies provided in an embodiment of this application.

[0039] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0041] Because static testing in existing technologies cannot capture functional defects under dynamic loads, fixed-process functional testing has long development cycles, high costs, and is difficult to adapt to multi-variety, small-batch production, while manual experience-based diagnosis is inefficient and inconsistent. These factors result in the technical problems of poor efficiency and low accuracy in the testing of printed circuit board components in existing technologies.

[0042] To address the aforementioned issues, this application provides a method and apparatus for testing printed circuit board (PCB) assemblies. By acquiring the identification information of the PCB assembly under test, a foundation is provided for accurately matching the corresponding test configuration and functional dependency knowledge graph, ensuring the directionality and accuracy of the testing. Based on the identification, the matching test configuration and functional dependency knowledge graph are determined, establishing a scientific framework for subsequent testing processes and ensuring orderly testing. Electrical connection testing and static electrical parameter baseline acquisition according to the test configuration can promptly screen for basic faults such as short circuits and obtain static baseline data. Applying dynamic load excitation to the associated power network and collecting dynamic response data can simulate real-world operating conditions. By comprehensively considering the functional dependency knowledge graph, static baseline data, and dynamic response data, the test execution strategy and test data are determined, thereby identifying the root cause of the fault and generating a diagnostic report. Overall, this achieves the technical effect of improving testing efficiency and accuracy.

[0043] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0044] Figure 1 This is a schematic diagram of an application data processing system architecture provided in an embodiment of this application. The application data processing system is a computer device. Figure 1 As shown, the above architecture includes at least one of a data acquisition device 101, a processing device 102, and a display device 103.

[0045] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the architecture of the application data processing system. In other feasible embodiments of this application, the above architecture may include more or fewer components than illustrated, or combine some components, or split some components, or arrange different components, which can be determined according to the actual application scenario and is not limited here. Figure 1 The components shown can be implemented in hardware, software, or a combination of both.

[0046] In the specific implementation process, the data acquisition device 101 may include an input / output interface or a communication interface, and the data acquisition device 101 can be connected to the processing device through the input / output interface or the communication interface.

[0047] The processing device 102 first acquires the printed circuit board component identification information, and then determines the matching test configuration and functional dependency knowledge graph accordingly. Next, it performs electrical connection testing on the components and collects static electrical parameter baseline data. Then, based on the test configuration and functional dependency knowledge graph, it applies dynamic load stimulation and collects dynamic response data. Subsequently, it integrates the functional dependency knowledge graph, static and dynamic data to determine the test execution strategy and test data, ultimately identifying the root cause of the fault and generating a diagnostic report, achieving efficient and accurate detection.

[0048] The display device 103 can also be a touch screen or the screen of a terminal device, used to receive user commands while displaying the above-mentioned content, so as to realize interaction with the user.

[0049] It should be understood that the aforementioned processing device can be implemented by a processor reading instructions from memory and executing those instructions, or it can be implemented by a chip circuit.

[0050] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0051] Figure 2 This is a schematic diagram of the structure of a printed circuit board assembly detection system provided in an embodiment of this application, as shown below. Figure 2 As shown, the printed circuit board assembly inspection system 200 provided in this application embodiment includes:

[0052] The programmable test fixture module 201 is used to adapt to the test points, power interfaces and communication interfaces of different printed circuit board assemblies to achieve reliable and fast electrical connections.

[0053] The multi-channel programmable power supply module 202 is used to provide programmable voltage and current outputs and has high-precision, high-bandwidth real-time voltage / current monitoring capabilities.

[0054] The signal excitation and acquisition unit 203 integrates digital input / output (I / O), arbitrary waveform generator, high-speed digitizer and protocol analyzer, and is used to generate excitation signals and acquire responses.

[0055] The main control computing and processing platform 204 runs an adaptive diagnostic engine and test management software, and stores a test configuration library, a functional dependency knowledge graph, and a fault mode database.

[0056] Adaptive diagnostic engine 205 is used for real-time analysis of data streams from various monitoring channels;

[0057] The adaptive diagnostic engine 205 also includes a rule reasoning unit 2051, a machine learning unit 2052, and a dynamic test scheduler 2053.

[0058] Among them, the rule reasoning unit 2051 is used to perform rapid fault propagation path analysis and preset rule matching based on knowledge graph; the machine learning unit 2052 is used to perform feature extraction, cluster analysis and classification model reasoning on unknown or complex multidimensional test data; and the dynamic test scheduler 2053 is used to make dynamic decisions and issue instructions based on real-time analysis results to adjust the test process, incentive parameters or monitoring focus.

[0059] The data interaction and communication bus 206 is used to connect and coordinate the synchronous operation of the above modules.

[0060] Figure 3 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 1 ,like Figure 3 As shown, this embodiment, based on the above embodiments, provides a method for detecting printed circuit board assemblies, including:

[0061] S301. Obtain the identification information of the printed circuit board assembly under test.

[0062] For example, by scanning the identification code on the printed circuit board component under test, the identification information of the printed circuit board component under test can be obtained, providing a basis for subsequent matching test configuration and functional dependency knowledge graph.

[0063] S302. Based on the identification information, determine the matching test configuration and functional dependency knowledge graph.

[0064] In one possible implementation, determining the matching test configuration and functional dependency knowledge graph based on the identification information includes: obtaining a preset test configuration library; matching the corresponding test items and device functional parameters from the test configuration library based on the identification information; using the test items and device functional parameters as test configurations; and matching the corresponding functional dependency knowledge graph from the test configuration library based on the identification information.

[0065] In this embodiment, the test items include basic electrical tests of the laser and insulation resistance tests, and the device functional parameters include laser threshold current, slope efficiency and center wavelength parameters.

[0066] For example, based on the identification information, the matching test configuration and functional dependency knowledge graph are determined, and a pre-defined test configuration library is first obtained. Matching is performed in the test configuration library based on the identification information, and the corresponding test items and device functional parameters are extracted. The extracted test items and device functional parameters are used together as the test configuration required for the current printed circuit board assembly under test. Then, based on the same identification information, the corresponding functional dependency knowledge graph is matched and retrieved from the test configuration library.

[0067] Specifically, the system scans the QR code on the printed circuit board component under test to obtain identification information. Based on this identification information, the system automatically matches the corresponding test items and parameters from the test configuration library: basic electrical tests for the laser include continuity testing, short-circuit testing, and open-circuit testing; the insulation resistance test is the insulation resistance test between the power supply and ground, requiring no less than 100MΩ, with a test voltage of 500V; the core performance parameters are the laser threshold current of 15mA±2mA, slope efficiency of 0.2mW / mA±0.02mW / mA, and center wavelength of 1310nm±0.5nm. The system integrates these contents into a complete test configuration file, generating an automated test plan containing 12 test steps, with a total test time of approximately 2 minutes.

[0068] S303. According to the test configuration, perform electrical connection testing and static electrical parameter baseline acquisition on the printed circuit board assembly under test to obtain static baseline data.

[0069] For example, an electrical connection is established between the printed circuit board assembly under test and the programmable test fixture according to the test configuration. Short circuit and open circuit tests are performed first, and then the stable voltage, quiescent current and noise floor ripple of each power rail are measured and recorded step by step to form static baseline data.

[0070] S304. Based on the test configuration and functional dependency knowledge graph, apply dynamic load stimulation to the associated power network of the printed circuit board assembly under test to collect the corresponding dynamic response data.

[0071] For example, by combining test configuration and functional dependency knowledge graph, dynamic current excitation simulating real load transitions is applied to the critical power network of printed circuit board components, and voltage drop, recovery time, ripple and functional chain performance are monitored simultaneously to collect dynamic response data.

[0072] S305. Determine the test execution strategy based on the functional dependency knowledge graph, static baseline data, and dynamic response data.

[0073] Based on the functional dependency knowledge graph, and combined with static baseline data and dynamic response data, real-time analysis is performed to determine test execution strategies that include test process adjustments, stimulus parameter modifications, key monitoring changes, and enhanced test intensity.

[0074] S306. Determine the corresponding test data according to the test execution strategy.

[0075] According to the established test execution strategy, we carry out refined diagnostic tests and enhancement tests, continuously collect and organize test data that meet the strategy requirements during the test process, and provide support for the determination of the root cause of the failure.

[0076] S307. Based on the functional dependency knowledge graph, test data, static baseline data, and dynamic response data, determine the corresponding root cause of the failure and generate a diagnostic report.

[0077] For example, test data, static baseline data, and dynamic response data are integrated, and probabilistic reasoning is performed using a functional dependency knowledge graph to determine the final root cause of the failure and generate a corresponding diagnostic report.

[0078] This application provides a method for testing printed circuit board (PCB) assemblies. By acquiring the identification information of the PCB assembly under test, a foundation is provided for accurately matching the corresponding test configuration and functional dependency knowledge graph, ensuring the directionality and accuracy of the testing. Based on the identification, the matching test configuration and functional dependency knowledge graph are determined, establishing a scientific framework for subsequent testing processes and ensuring orderly testing. Electrical connection testing and static electrical parameter baseline acquisition are performed according to the test configuration, enabling timely screening of basic faults such as short circuits and obtaining static baseline data. Applying dynamic load excitation to the associated power network and collecting dynamic response data simulates real-world operating conditions. By comprehensively considering the functional dependency knowledge graph, static baseline data, and dynamic response data, the test execution strategy and test data are determined, thereby identifying the root cause of the fault and generating a diagnostic report. Overall, this method achieves the technical effect of improving testing efficiency and accuracy.

[0079] Figure 4 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 2 ,like Figure 4 As shown, this embodiment, based on the above embodiments, provides a detailed explanation of the specific process for obtaining dynamic response data, including:

[0080] S401. According to the test configuration, activate the core functional units of the printed circuit board assembly under test and perform built-in self-test operations to obtain the corresponding core function self-test results.

[0081] For example, the core functional unit of the printed circuit board component under test is activated through a preset communication interface according to the test configuration. The communication interface includes Joint Test Action Group (JTAG), Serial Wire Debug (SWD), and Universal Asynchronous Receiver / Transmitter (UART). This triggers the core functional unit to run the Built-In Self-Test (BIST) program to complete the basic function verification of the kernel and memory, and obtain the core function self-test result.

[0082] S402. Based on the functional dependency knowledge graph and test configuration, activate the peripheral function links of the printed circuit board component under test and determine the corresponding peripheral function running status.

[0083] For example, based on the dependency paths in the functional dependency knowledge graph and the test configuration requirements, the peripheral function links of the printed circuit board component under test are activated sequentially. Signal excitation and acquisition units simulate signals and perform functional interactions, collecting peripheral function link operation data in real time, and determining the peripheral function operation status based on the data.

[0084] S403. Apply dynamic load excitation to the associated power network according to the peripheral function link to obtain power disturbance response data.

[0085] For example, based on the activated peripheral function links, a dynamic current excitation simulating a real load transition is applied to the associated power network of the printed circuit board assembly under test. Simultaneously, the voltage sag, recovery time, ripple variation, and function link performance of the associated power network are monitored at high speed to acquire power disturbance response data.

[0086] In one possible implementation, dynamic load excitation is applied to the associated power network based on the peripheral functional link to obtain power disturbance response data, including:

[0087] Based on the peripheral functional links, the laser driver circuit and its corresponding associated power network in the printed circuit board assembly under test are determined. Based on the laser type of the printed circuit board assembly under test, the laser's specific operating mode is determined. Based on the specific operating mode, continuous fluctuation drive, pulse modulation, or constant power constant current switching excitation is applied to the associated power network through the laser driver circuit to collect the laser's optical power, backlight current, forward voltage, and case temperature data. Based on the optical power, backlight current, forward voltage, and case temperature data, power supply disturbance response data are obtained.

[0088] For example, firstly, the laser driver circuit and its associated power network in the printed circuit board assembly under test are accurately located by analyzing the peripheral function link. Then, the laser-specific working mode is determined according to the laser type of the printed circuit board assembly under test. According to the working mode, continuous wave drive, pulse modulation or constant power constant current switching excitation is applied to its associated power network through the laser driver circuit. At the same time, the laser's optical power, backlight current, forward voltage and tube temperature data are collected simultaneously to obtain power disturbance response data.

[0089] Specifically, taking the printed circuit board assembly under test as a 10G optical module transmitter control board equipped with a distributed feedback laser as an example, the system first analyzes the peripheral function links in the functional dependency knowledge graph to determine the laser diode driver chip and its 3.3V analog power supply network as the excitation object. Then, based on the laser model, it retrieves the dedicated operating mode parameters and controls the driver chip via a digital interface to sequentially execute an excitation sequence of 50mA continuous wave drive for 10 seconds, 1GHz pulse modulation for 20 seconds, and constant power and constant current mode switching three times. Throughout the excitation process, the system synchronously collects optical power, backlight current, forward voltage, and tube shell temperature data at a 10kHz sampling rate, ultimately forming a power disturbance response data set containing 1.4 million data points for subsequent fault analysis.

[0090] S404. Based on the core function self-test results, peripheral function operating status, and power disturbance response data, obtain dynamic response data.

[0091] For example, the self-test results of core functions, the operating status of peripheral functions, and power disturbance response data are integrated and standardized. These three types of data are then incorporated into a dynamic dataset to form dynamic response data that can be used for subsequent analysis and strategy formulation.

[0092] The printed circuit board assembly testing method provided in this application can quickly verify the basic effectiveness of core functions by activating core functional units and completing built-in self-tests. Activating peripheral functional links according to knowledge graphs and test configurations can accurately determine the working status of peripherals. Applying dynamic load stimulation to the associated power network can realistically obtain the power network's disturbance rejection capability. Integrating three types of data to form dynamic response data provides comprehensive and realistic dynamic evidence for test strategy adjustment and fault root cause localization, improving testing accuracy and reliability.

[0093] Figure 5 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 3 ,like Figure 5 As shown, this embodiment, based on the above embodiments, provides a detailed explanation of the process for obtaining static baseline data, including:

[0094] S501. Obtain the preset programmable test fixture.

[0095] For example, a programmable test fixture with pre-set parameters and interfaces according to testing requirements can be obtained. This fixture can be adapted to the test points, power interfaces and communication interfaces of the printed circuit board assembly under test to ensure stable and reliable electrical connections.

[0096] S502. An electrical connection is established between the programmable test fixture and the printed circuit board assembly under test, and a preset safe voltage is applied according to the test configuration to perform short-circuit and open-circuit tests to obtain the continuity test results.

[0097] For example, a programmable test fixture is used to electrically connect the test points, power interface, and communication interface to the printed circuit board assembly under test. A preset minimum safe voltage is applied according to the test configuration requirements to perform preliminary short-circuit and open-circuit screening of the circuit, and the continuity test results are obtained based on the test data.

[0098] S503. According to the preset timing of the test configuration, power on each power rail step by step based on the path detection results, measure and record the static electrical parameters of each power rail to form static baseline data.

[0099] For example, based on the preset timing of the test configuration, the printed circuit board components under test are powered on to their respective nominal voltages step by step, provided that the path detection results are qualified. The stable voltage value, quiescent current, and noise floor ripple of each power rail are measured and fully recorded, and the above parameters are integrated to form static baseline data.

[0100] The printed circuit board assembly testing method provided in this application provides stable hardware support for subsequent electrical connections and testing by acquiring a preset programmable test fixture. Establishing a reliable electrical connection and applying a safe voltage to complete the path detection can effectively avoid the risk of circuit damage during power-on. Powering on the circuit step by step according to a preset timing sequence and collecting static electrical parameters of the power rail can establish accurate reference data, providing a reliable static reference for subsequent dynamic testing and fault diagnosis.

[0101] Figure 6 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 4 ,like Figure 6 As shown, this embodiment, based on the above embodiments, provides a detailed explanation of the process for determining the test execution strategy, including:

[0102] S601. Compare the static baseline data with the dynamic response data to obtain the corresponding comparison results.

[0103] For example, the collected static baseline data and dynamic response data are compared item by item and deviations are calculated. The differences in parameters such as voltage, current, timing, and response accuracy are checked in detail to form a comparison result that includes deviation values, over-limit states, and abnormal points.

[0104] S602. Based on the comparison results, determine the corresponding power supply abnormality state and functional performance degradation state.

[0105] Based on the parameter deviation and threshold judgment rules in the comparison results, abnormal power supply states such as voltage drop, excessive ripple, and recovery timeout are identified, while functional link response abnormalities, data verification errors, and timing violations are also judged.

[0106] Specifically, the comparison results include comparisons of parameters such as voltage deviation, current deviation, ripple difference, response time difference, data verification result difference, and timing deviation between static baseline data and dynamic response data. It also includes a flag indicating whether each parameter exceeds a preset threshold. The judgment rule is to calculate the difference between each measured parameter in the dynamic response data and the corresponding benchmark parameter in the static baseline data, and compare the calculated deviation value with a preset safety threshold. When the voltage drop difference, ripple value, or power recovery time exceeds the preset threshold, it is judged as an abnormal power supply state. When the functional link response times out, data verification results do not match, or timing deviation exceeds the allowable range, it is judged as a degraded state of the corresponding function.

[0107] S603. Determine the test execution strategy based on the functional dependency knowledge graph, power supply abnormality status, and functional performance degradation status.

[0108] By combining the knowledge graph of functional dependencies to trace the anomaly propagation path, and based on the abnormal power supply state and the functional performance degradation state, a test execution strategy including enhanced testing, refined diagnosis, retest verification, and key monitoring is dynamically determined.

[0109] In one possible implementation, a test execution strategy is determined based on a functional dependency knowledge graph, abnormal power conditions, and functional performance degradation states, including:

[0110] Based on the functional dependency knowledge graph, the dependencies between predefined laser drive current, optical power, backlight monitoring feedback, and automatic power control loop are extracted. Based on the dependencies, abnormal power supply states, and functional performance degradation states, the corresponding fault propagation paths are determined. Based on the fault propagation paths, the additional spectral stability checks, pulse overshoot tests, or high-temperature aging compensation verification tests that need to be added are determined. Based on the spectral stability checks, pulse overshoot tests, or high-temperature aging compensation verification tests, the test execution strategy is determined.

[0111] For example, the system first extracts the predefined dependencies of laser drive current, optical power, backlight monitoring feedback and automatic power control loop from the functional dependency knowledge graph. Then, based on the dependencies, abnormal power supply state and functional performance degradation state, the corresponding fault propagation path is determined. Then, based on the fault propagation path, the required additional spectral stability check, pulse overshoot test or high temperature aging compensation verification test items are determined. Finally, the required additional test items are incorporated into the test execution strategy.

[0112] Specifically, during dynamic testing, the system detected excessive ripple in the 3.3V analog power supply, with a peak-to-peak value of 120mV, exceeding the standard value of 50mV. Simultaneously, it detected optical power jitter, with a peak-to-peak value of 0.8mW, exceeding the standard value of 0.2mW. The system extracted the dependencies between the laser drive current, optical power, backlight monitoring feedback, and the automatic power control loop from the functional dependency knowledge graph. Combining this with the detected abnormal states, it deduced through reverse reasoning that the fault propagation path was caused by the 3.3V power supply ripple leading to drive current fluctuations, which in turn caused optical power jitter and backlight current fluctuations. Based on this fault propagation path, the system automatically determined that three additional test items were needed: spectral stability check, pulse overshoot test, and high-temperature aging compensation verification. These were then inserted into the original test flow to form a new test execution strategy.

[0113] The printed circuit board assembly testing method provided in this application can quickly locate parameter anomalies by comparing static baseline data with dynamic response data, providing a direct basis for status determination. Based on the comparison results, abnormal and deteriorated states are determined, enabling accurate identification of power supply and functional issues. Combining knowledge graphs and abnormal states to determine testing strategies allows for adaptive adjustment of the testing process, improving fault detection efficiency and diagnostic accuracy.

[0114] Figure 7 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 5 ,like Figure 7 As shown, this embodiment, based on the above embodiments, provides a detailed explanation of the process for determining test data, including:

[0115] S701. Determine the corresponding power network based on the printed circuit board assembly under test.

[0116] For example, based on the identification information and test configuration of the printed circuit board assembly under test, all power supply circuits that supply power to the core functional units and peripheral functional links are identified, and the power network corresponding to the printed circuit board assembly under test is determined.

[0117] S702. Based on the test execution strategy, determine the corresponding target test items and the number of iterations.

[0118] For example, according to the determined test execution strategy, functional verification items related to abnormal states and performance degradation states are selected as target test items, and the corresponding number of loops for repeated execution is set.

[0119] S703. Based on the target test items and the number of cycles, perform corresponding functional link tests on the printed circuit board assembly under test to obtain the corresponding first data.

[0120] For example, according to the target test items and the set number of cycles, repetitive functional verification tests are carried out on the peripheral functional links and core functional units, and information such as response, data verification, and running status are collected in real time to obtain the first data.

[0121] S704. According to the test execution strategy, perform refined diagnostic tests on the power network to obtain the corresponding second data.

[0122] For example, by conducting specific tests on a determined power network according to the test execution strategy, communication rate retries can be reduced, frequency sweep impedance analysis can be performed, and information such as power stability, impedance, and disturbance response can be collected to obtain second data.

[0123] S705, integrate the first data and the second data to obtain the test data.

[0124] For example, the first data obtained from the functional link test and the second data obtained from the power network refined diagnostic test are summarized, organized, and standardized to form complete and unified test data.

[0125] The printed circuit board assembly testing method provided in this application can clarify the subsequent power-specific testing targets by identifying the corresponding power network, thus improving the testing focus. Determining the target test items and cycle count based on a strategy can strengthen the detection of abnormal areas. Performing functional link testing as required can stably reproduce intermittent problems and obtain effective functional data. Conducting refined diagnostic testing on the power network can accurately locate the root cause of power-related faults. Integrating these two types of data can form comprehensive testing information, providing complete support for fault root cause determination.

[0126] Figure 8 A flowchart illustrating the testing method for printed circuit board assemblies provided in this application embodiment. Figure 6 ,like Figure 8 As shown, this embodiment, based on the above embodiment, provides supplementary explanations of the process for generating the root cause and diagnostic report of the fault, as well as its corresponding subsequent processes, including:

[0127] S801. Integrate the test data, static baseline data, and dynamic response data to obtain the corresponding test feature set.

[0128] For example, information such as parameters, timing, status, and abnormal events in test data, static baseline data, and dynamic response data can be extracted and fused to form a test feature set containing multi-dimensional detection information, providing a complete data foundation for subsequent fault analysis.

[0129] S802. Obtain the pre-trained probabilistic inference model and the preset fault mode database; wherein, the fault mode database includes multiple historical cases.

[0130] For example, a probabilistic inference model that has completed model training is obtained, which includes a Bayesian network. At the same time, a fault pattern database storing multiple sets of historical case detection and fault confirmation information is obtained to provide model and data support for fault matching and inference.

[0131] S803. Match the test feature set with historical cases in the fault mode database to obtain the corresponding fault mode matching results.

[0132] For example, feature comparison and clustering analysis are performed between the test feature set and historical cases in the fault mode database to filter out historical cases that are highly similar to the current detection features, forming a fault mode matching result that includes the degree of similarity and the associated fault type.

[0133] S804. Based on the fault mode matching results, the functional dependency knowledge graph, and the probabilistic reasoning model, determine the corresponding fault hypothesis probability.

[0134] For example, based on the failure mode matching results and the dependency paths in the functional dependency knowledge graph, the posterior probability of each failure hypothesis is calculated using a probabilistic inference model to obtain the failure hypothesis probability corresponding to different failure causes.

[0135] S805. Based on the fault hypothesis probability, determine the corresponding root cause of the fault, and generate the corresponding diagnostic report based on the root cause of the fault.

[0136] For example, the fault cause with the highest probability of fault hypothesis is selected as the final root cause of the fault. Based on the root cause of the fault, confidence level, related evidence and detection parameters, a diagnostic report is generated that includes the judgment conclusion, fault location and detection basis.

[0137] S806. Obtain the test characteristics, diagnostic process, and root cause information of confirmed fault cases.

[0138] For example, information related to fault cases that have been finally confirmed by humans can be obtained. This information includes the test characteristics of this detection, the complete diagnostic process, and the finally confirmed root cause of the fault, providing real and effective samples for knowledge base updates.

[0139] S807. Add test features, diagnostic processes, and root cause information as new samples to the fault mode database.

[0140] For example, the test characteristics, diagnostic process, and root cause information of confirmed failure cases are used as new samples and written into the failure mode database in an incremental learning manner to enrich the failure type and feature information in the database.

[0141] In one possible implementation, test features, diagnostic processes, and root cause information are written as new samples into the failure mode database, including:

[0142] The test features, diagnostic process, and root cause information are integrated to form new samples; a set of laser-specific failure modes is extracted from the failure mode database; the root cause information in the new samples is matched with the set of laser-specific failure modes to determine the corresponding laser failure mode type; the laser failure mode type is associated with the new samples to obtain associated new samples, and the associated new samples are written into the failure mode database.

[0143] In this embodiment, the laser-specific failure mode set includes optical power drift caused by thermal cycling fatigue of the drive circuit solder joints, catastrophic optical damage caused by electrostatic damage, modulation bandwidth reduction caused by poor gold wire bonding, and wavelength drift caused by poor soldering of the semiconductor cooler control circuit.

[0144] For example, the system first integrates test features, diagnostic processes, and root cause information to form new samples. Then, it extracts a pre-stored set of laser-specific failure modes from the failure mode database. This set includes optical power drift caused by thermal cycling fatigue of drive circuit solder joints, catastrophic optical damage caused by electrostatic discharge, modulation bandwidth reduction caused by poor gold wire bonding, and wavelength drift caused by poor soldering of the semiconductor cooler control circuit. The system matches the root cause information in the new samples with the laser-specific failure mode set to determine the corresponding failure mode type, associates the failure mode type with the new samples, and finally writes the new samples associated with the failure mode type into the failure mode database.

[0145] Specifically, after the test, the system determined that the root cause of the fault was a faulty solder joint on the power input filter capacitor of the drive circuit. The system integrated the test characteristics (3.3V power supply ripple of 120mV, optical power jitter of 0.8mW, backlight current fluctuation of 0.1mA), the diagnostic process (determining the fault propagation path based on knowledge graph reverse reasoning), and the root cause information into a new sample. Next, it extracted a laser-specific failure mode set from the fault mode database and, through string matching and semantic similarity algorithms, successfully matched the root cause information of the new sample with the failure mode of excessive power supply ripple caused by the faulty solder joint on the power input filter capacitor. The system associated this failure mode type label with the new sample and then wrote the associated new sample into the fault mode database, increasing the number of samples for this type of failure mode from 127 to 128.

[0146] S808. Adjust the functional dependency knowledge graph based on the newly added samples.

[0147] For example, based on the fault associations and propagation paths in the newly added samples, the node association weights and path dependencies in the functional dependency knowledge graph can be optimized to improve the accuracy and applicability of the knowledge graph.

[0148] In one possible implementation, the functional dependency knowledge graph is adjusted based on the new samples, including:

[0149] Based on the new samples, determine the associated laser failure mode types; based on the laser failure mode types, determine the corresponding laser function nodes in the functional dependency knowledge graph; based on the laser function nodes, adjust the association weights between laser function nodes in the functional dependency knowledge graph.

[0150] For example, the system determines the associated laser failure mode type based on the new sample, then determines the corresponding laser functional node in the functional dependency knowledge graph based on the laser failure mode type, and finally adjusts the association weights between laser functional nodes in the functional dependency knowledge graph based on the laser functional nodes. For node pairs that exhibit a strong causal relationship in the failure, their association weights are increased; for node pairs that exhibit a weak causal relationship, their association weights are decreased.

[0151] Through this continuous incremental adjustment, the fault reasoning accuracy of the functional dependency knowledge graph will continuously improve as the number of samples increases, enabling the system to better adapt to the testing needs of different batches and types of laser printed circuit board assemblies.

[0152] Specifically, the system extracted the corresponding laser failure mode type from newly added samples associated with failure mode types: excessive power ripple caused by a faulty solder joint in the power input filter capacitor. Based on this failure mode type, the system located the corresponding laser functional nodes in the functional dependency knowledge graph: 3.3V analog power network, laser diode driver chip, optical power output, and backlight current monitoring. Combining this fault propagation path, the system increased the association weights of the node pairs from 3.3V analog power network to laser diode driver chip, and from laser diode driver chip to optical power output, in the functional dependency knowledge graph from 0.6 to 0.75. After this adjustment, when 3.3V power ripple anomalies reappear in subsequent tests, the system will prioritize inferring faults related to the driver circuit and optical power, thereby improving diagnostic speed and accuracy.

[0153] The printed circuit board assembly detection method provided in this application integrates multiple types of detection data to form a test feature set, which can comprehensively reflect the state of the detected object. It acquires a reasoning model and a fault database, providing core tools and basis for intelligent fault analysis. Historical case matching can quickly identify similar fault types. Combining knowledge graphs and probabilistic models can accurately calculate fault probabilities, improving the reliability of root cause localization. Determining the root cause based on the fault probability and generating a report can intuitively present the detection conclusions and maintenance guidance. Obtaining confirmed case information provides real data for knowledge base iteration. Adding new samples continuously enriches the fault database, and adjusting the knowledge graph continuously optimizes fault reasoning and path analysis capabilities, enabling the continuous evolution of the detection system.

[0154] Figure 9 This is a schematic diagram of the structure of a testing device for a printed circuit board assembly provided in an embodiment of this application. The device in this embodiment can be in the form of software and / or hardware. For example... Figure 9 As shown in the embodiment of this application, the printed circuit board assembly detection device 900 includes: an acquisition module 901, a first processing module 902, a second processing module 903, a data acquisition module 904, a third processing module 905, a fourth processing module 906, and a generation module 907.

[0155] The acquisition module 901 is used to acquire the identification information of the printed circuit board assembly under test;

[0156] The first processing module 902 is used to determine the matching test configuration and functional dependency knowledge graph based on the identification information.

[0157] The second processing module 903 is used to perform electrical connection detection and static electrical parameter baseline acquisition on the printed circuit board assembly under test according to the test configuration, and obtain static baseline data.

[0158] The acquisition module 904 is used to apply dynamic load stimulation to the associated power network of the printed circuit board assembly under test according to the test configuration and functional dependency knowledge graph, so as to acquire the corresponding dynamic response data.

[0159] The third processing module 905 is used to determine the test execution strategy based on the functional dependency knowledge graph, static baseline data and dynamic response data;

[0160] The fourth processing module 906 is used to determine the corresponding test data according to the test execution strategy;

[0161] The generation module 907 is used to determine the corresponding root cause of the failure and generate a diagnostic report based on the functional dependency knowledge graph, test data, static baseline data and dynamic response data.

[0162] In one possible implementation, the acquisition module 904 is further configured to:

[0163] According to the test configuration, activate the core functional units of the printed circuit board assembly under test and perform built-in self-test operations to obtain the corresponding core function self-test results.

[0164] Based on the functional dependency knowledge graph and test configuration, activate the peripheral function links of the printed circuit board component under test and determine the corresponding peripheral function running status;

[0165] Based on the peripheral functional links, dynamic load excitation is applied to the associated power network to obtain power disturbance response data;

[0166] Dynamic response data is obtained based on the self-test results of core functions, the operating status of peripheral functions, and power disturbance response data.

[0167] In one possible implementation, the first processing module 902 is further configured to:

[0168] Obtain the preset test configuration library;

[0169] Based on the identification information, match the corresponding test items and device functional parameters from the test configuration library;

[0170] Use test items and device functional parameters as test configurations;

[0171] Based on the identification information, the corresponding functional dependency knowledge graph is matched from the test configuration library.

[0172] In one possible implementation, the second processing module 903 is further configured to:

[0173] Obtain a preset programmable test fixture;

[0174] An electrical connection is established between the programmable test fixture and the printed circuit board assembly under test, and a preset safe voltage is applied according to the test configuration to perform short circuit and open circuit tests to obtain the continuity test results.

[0175] According to the preset timing of the test configuration, power is applied step by step based on the path detection results, and the static electrical parameters of each power rail are measured and recorded to form static baseline data.

[0176] In one possible implementation, the third processing module 905 is further configured to:

[0177] The static baseline data is compared with the dynamic response data to obtain the corresponding comparison results;

[0178] Based on the comparison results, the corresponding abnormal power supply state and functional performance degradation state are determined;

[0179] The test execution strategy is determined based on the functional dependency knowledge graph, power supply abnormality status, and functional performance degradation status.

[0180] In one possible implementation, the fourth processing module 906 is further configured to:

[0181] Determine the corresponding power network based on the printed circuit board assembly under test;

[0182] Based on the test execution strategy, determine the corresponding target test items and the number of iterations;

[0183] Based on the target test items and the number of cycles, perform corresponding functional link tests on the printed circuit board assembly under test to obtain the corresponding first data;

[0184] According to the test execution strategy, a detailed diagnostic test is performed on the power network to obtain the corresponding second data;

[0185] By integrating the first and second data, test data is obtained.

[0186] In one possible implementation, the generation module 907 is further configured to:

[0187] Obtain a preset fault mode database, which includes multiple historical cases;

[0188] Obtain test characteristics, diagnostic process, and root cause information for confirmed failure cases;

[0189] Test features, diagnostic processes, and root cause information are added as new samples and written into the failure mode database.

[0190] Adjust the functional dependency knowledge graph based on the new samples.

[0191] In one possible implementation, the generation module 907 is further configured to:

[0192] The test data, static baseline data, and dynamic response data are integrated to obtain the corresponding test feature set;

[0193] The test feature set is matched with historical cases in the failure mode database to obtain the corresponding failure mode matching results;

[0194] Obtain a pre-trained probabilistic inference model;

[0195] Based on the failure mode matching results, the functional dependency knowledge graph, and the probabilistic reasoning model, the corresponding failure hypothesis probability is determined.

[0196] Based on the probability of the fault assumption, the corresponding root cause of the fault is determined, and a corresponding diagnostic report is generated based on the root cause of the fault.

[0197] In one possible implementation, the acquisition module 904 is further configured to:

[0198] Based on the peripheral function link, determine the laser driver circuit and the associated power network of the laser driver circuit in the printed circuit board assembly under test.

[0199] Determine the specific operating mode of the laser based on the type of laser corresponding to the printed circuit board assembly under test;

[0200] According to the dedicated working mode, the laser driver circuit applies continuous fluctuation drive, pulse modulation or constant power constant current switching excitation to the associated power network to collect the laser's optical power, backlight current, forward voltage and tube temperature data.

[0201] Based on the optical power, backlight current, forward voltage, and casing temperature data, the power supply disturbance response data are obtained.

[0202] In one possible implementation, the third processing module 905 is further configured to:

[0203] Based on the functional dependency knowledge graph, the predefined dependencies between laser drive current, optical power, backlight monitoring feedback and automatic power control loop are extracted.

[0204] Based on dependencies, abnormal power conditions, and functional performance degradation, determine the corresponding fault propagation path;

[0205] Based on the fault propagation path, determine the additional spectral stability checks, pulse overshoot tests, or high-temperature aging compensation verification tests that need to be performed.

[0206] The test execution strategy is determined based on the spectral stability check, pulse overshoot test, or high temperature aging compensation verification test.

[0207] In one possible implementation, the generation module 907 is further configured to:

[0208] The test features, diagnostic process, and root cause information are integrated to form new samples;

[0209] Extract the pre-stored set of laser-specific failure modes from the failure mode database. The set of laser-specific failure modes includes optical power drift caused by thermal cycling fatigue of the solder joints in the drive circuit, catastrophic optical damage caused by electrostatic damage, modulation bandwidth reduction caused by poor gold wire bonding, and wavelength drift caused by poor soldering of the control circuit of the semiconductor cooler.

[0210] The root cause information in the new samples is matched with the laser-specific failure mode set to determine the corresponding laser failure mode type.

[0211] The laser failure mode type is associated with the new sample to obtain the associated new sample, and the associated new sample is written into the failure mode database.

[0212] In one possible implementation, the generation module 907 is further configured to:

[0213] Based on the new samples, determine the associated laser failure mode types;

[0214] Based on the laser failure mode type, determine the corresponding laser function node in the functional dependency knowledge graph;

[0215] Adjust the association weights between laser functional nodes in the functional dependency knowledge graph based on the laser functional nodes.

[0216] The printed circuit board assembly testing device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0217] Figure 10 This is a schematic diagram of the structure of a testing device for a printed circuit board assembly provided in an embodiment of this application. Figure 10 As shown, the printed circuit board assembly testing device 1000 provided in this embodiment includes at least one processor 1001 and a memory 1002. Optionally, the device 1000 further includes a communication component 1003. The processor 1001, memory 1002, and communication component 1003 are connected via a bus.

[0218] In a specific implementation, at least one processor 1001 executes computer execution instructions stored in memory 1002, causing at least one processor 1001 to perform the above-described method.

[0219] The specific implementation process of processor 1001 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0220] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0221] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0222] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0223] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0224] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0225] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0226] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0227] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0228] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0229] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0230] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0231] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0232] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for testing printed circuit board assemblies, characterized in that, include: Obtain the identification information of the printed circuit board assembly under test; Based on the identification information, determine the matching test configuration and functional dependency knowledge graph; According to the test configuration, electrical connection detection and static electrical parameter baseline acquisition are performed on the printed circuit board assembly under test to obtain static baseline data. Based on the test configuration and the functional dependency knowledge graph, dynamic load stimulation is applied to the associated power network of the printed circuit board assembly under test to collect corresponding dynamic response data. Based on the functional dependency knowledge graph, the static baseline data, and the dynamic response data, a test execution strategy is determined; Based on the aforementioned test execution strategy, determine the corresponding test data; Based on the functional dependency knowledge graph, the test data, the static baseline data, and the dynamic response data, the corresponding root cause of the failure is determined and a diagnostic report is generated.

2. The method according to claim 1, characterized in that, The step of applying dynamic load stimulation to the associated power network of the printed circuit board assembly under test based on the test configuration and the functional dependency knowledge graph to collect corresponding dynamic response data includes: According to the test configuration, the core functional units of the printed circuit board assembly under test are activated and a built-in self-test is performed to obtain the corresponding core function self-test results. Based on the functional dependency knowledge graph and the test configuration, the peripheral function links of the printed circuit board component under test are activated, and the corresponding peripheral function running status is determined. Based on the peripheral functional link, the dynamic load excitation is applied to the associated power network to obtain power disturbance response data; The dynamic response data is obtained based on the core function self-test results, the peripheral function operating status, and the power disturbance response data.

3. The method according to claim 2, characterized in that, The step of determining the matching test configuration and functional dependency knowledge graph based on the identification information includes: Obtain the preset test configuration library; Based on the identification information, match the corresponding test items and device functional parameters from the test configuration library; The test items and the device functional parameters are used as the test configuration; Based on the identification information, the corresponding functional dependency knowledge graph is matched from the test configuration library.

4. The method according to claim 3, characterized in that, The step of performing electrical connection testing and static electrical parameter baseline acquisition on the printed circuit board assembly under test according to the test configuration to obtain static baseline data includes: Obtain a preset programmable test fixture; An electrical connection is established between the programmable test fixture and the printed circuit board assembly under test, and a preset safe voltage is applied according to the test configuration to perform short-circuit and open-circuit tests to obtain the continuity detection result. According to the preset timing of the test configuration, power is applied step by step based on the path detection results, and the static electrical parameters of each power rail are measured and recorded to form the static baseline data.

5. The method according to claim 4, characterized in that, The step of determining the test execution strategy based on the functional dependency knowledge graph, the static baseline data, and the dynamic response data includes: The static baseline data is compared with the dynamic response data to obtain the corresponding comparison results; Based on the comparison results, the corresponding power supply abnormality state and functional performance degradation state are determined; The test execution strategy is determined based on the functional dependency knowledge graph, the power supply abnormality state, and the functional performance degradation state.

6. The method according to claim 5, characterized in that, The step of determining the corresponding test data according to the test execution strategy includes: Determine the corresponding power network based on the printed circuit board assembly under test; Based on the test execution strategy, determine the corresponding target test items and the number of iterations; Based on the target test item and the number of cycles, the corresponding functional link test is performed on the printed circuit board assembly under test to obtain the corresponding first data; According to the test execution strategy, a refined diagnostic test is performed on the power network to obtain the corresponding second data; The test data is obtained by integrating the first data and the second data.

7. The method according to any one of claims 1-6, characterized in that, After determining the corresponding root cause of the fault and generating a diagnostic report based on the test data, the static baseline data, and the dynamic response data, the method further includes: Obtain a preset fault mode database, wherein the fault mode database includes multiple historical cases; Obtain test characteristics, diagnostic process, and root cause information for confirmed failure cases; The test features, the diagnostic process, and the root cause information are added as new samples and written into the fault mode database. Based on the newly added samples, adjust the functional dependency knowledge graph.

8. The method according to claim 7, characterized in that, The step of determining the corresponding root cause of the fault and generating a diagnostic report based on the functional dependency knowledge graph, the test data, the static baseline data, and the dynamic response data includes: The test data, the static baseline data, and the dynamic response data are integrated to obtain the corresponding test feature set; The test feature set is matched with the historical cases in the fault mode database to obtain the corresponding fault mode matching results; Obtain a pre-trained probabilistic inference model; Based on the fault mode matching results, the functional dependency knowledge graph, and the probabilistic reasoning model, the corresponding fault hypothesis probability is determined. Based on the assumed probability of the failure, the corresponding root cause of the failure is determined, and a corresponding diagnostic report is generated based on the root cause of the failure.

9. The method according to claim 2, characterized in that, The step of applying the dynamic load stimulus to the associated power network according to the peripheral functional link to obtain power disturbance response data includes: Based on the peripheral function link, determine the laser driver circuit in the printed circuit board assembly under test and the associated power network corresponding to the laser driver circuit; The specific operating mode of the laser is determined based on the type of laser corresponding to the printed circuit board assembly under test. According to the dedicated working mode, the laser driving circuit applies continuous fluctuation drive, pulse modulation or constant power constant current switching excitation to the associated power network to collect the laser's optical power, backlight current, forward voltage and tube temperature data. The power supply disturbance response data are obtained based on the optical power, backlight current, forward voltage, and casing temperature data.

10. The method according to claim 5, characterized in that, The step of determining the test execution strategy based on the functional dependency knowledge graph, the abnormal power supply state, and the functional performance degradation state includes: Based on the aforementioned functional dependency knowledge graph, the predefined dependencies between laser drive current, optical power, backlight monitoring feedback, and automatic power control loop are extracted. Based on the dependencies, the abnormal power supply state, and the functional performance degradation state, determine the corresponding fault propagation path; Based on the fault propagation path, determine the additional spectral stability check, pulse overshoot test, or high temperature aging compensation verification test items that need to be added. The test execution strategy is determined based on the spectral stability check, pulse overshoot test, or high-temperature aging compensation verification test.

11. The method according to claim 7, characterized in that, The step of writing the test features, the diagnostic process, and the root cause information as new samples into the fault mode database includes: The test features, the diagnostic process, and the root cause information are integrated to form the new sample; From the failure mode database, a pre-stored set of laser-specific failure modes is extracted, which includes optical power drift caused by thermal cycling fatigue of the drive circuit solder joints, catastrophic optical damage caused by electrostatic damage, modulation bandwidth reduction caused by poor gold wire bonding, and wavelength drift caused by poor soldering of the semiconductor cooler control circuit. The root cause information in the newly added samples is matched with the laser-specific failure mode set to determine the corresponding laser failure mode type; The laser failure mode type is associated with the new sample to obtain the associated new sample, and the associated new sample is written into the failure mode database.

12. The method according to claim 11, characterized in that, The step of adjusting the functional dependency knowledge graph based on the newly added samples includes: Based on the newly added samples, determine the associated laser failure mode type; Based on the laser failure mode type, determine the corresponding laser function node in the functional dependency knowledge graph; Based on the laser functional nodes, adjust the association weights between the laser functional nodes in the functional dependency knowledge graph.

13. A testing device for printed circuit board assemblies, characterized in that, include: The acquisition module is used to acquire the identification information of the printed circuit board assembly under test; The first processing module is used to determine the matching test configuration and functional dependency knowledge graph based on the identification information. The second processing module is used to perform electrical connection detection and static electrical parameter baseline acquisition on the printed circuit board assembly under test according to the test configuration, and obtain static baseline data. The acquisition module is used to apply dynamic load stimulation to the associated power network of the printed circuit board assembly under test according to the test configuration and the functional dependency knowledge graph, so as to acquire the corresponding dynamic response data. The third processing module is used to determine the test execution strategy based on the functional dependency knowledge graph, the static baseline data, and the dynamic response data; The fourth processing module is used to determine the corresponding test data according to the test execution strategy; The generation module is used to determine the corresponding root cause of the fault and generate a diagnostic report based on the functional dependency knowledge graph, the test data, the static baseline data, and the dynamic response data.

Images