Method and device for constructing a computing power board model and computer program product

Abstract

This application proposes a method, apparatus, and computer program product for constructing a computing board model, relating to the field of electronic repair technology. The method for constructing the computing board model includes: obtaining layout element information of a corresponding model of computing board; displaying a preview image of the computing board effect matching the layout element information, wherein there is a mapping relationship between the preview image and the computing board parameter values; determining the positions and dimensions of multiple computing chips in the preview image; adding interactive controls corresponding to the computing chip dimensions at each computing chip position; and adjusting the computing board parameter values ​​of the interactive controls to generate the target computing board model. This application can significantly improve fault diagnosis efficiency, increase diagnostic accuracy, and lower the technical threshold for electronic repair.

Description

[0001] This application is a divisional application of the parent application filed on December 1, 2025, with application number 202511784965.9 and invention title "Method for constructing computing board model, construction device and computer program product". Technical Field

[0002] This application relates to the field of electronic repair technology, and in particular to a method, apparatus and computer program product for constructing a computing board model. Background Technology

[0003] In the operation and maintenance of blockchain servers, the computing power board, as a core hardware component, has long relied on manual operation by technicians using special measuring tools for fault repair. Fault diagnosis requires point-by-point measurement and verification, and the average time for a single computing power board is as long as two to three hours, which seriously slows down the overall maintenance progress. The diagnostic results are significantly affected by subjective experience, and the fault identification accuracy rate is only maintained at about 75%, which is prone to misjudgment or missed detection. Summary of the Invention

[0004] The main objective of this invention is to provide a method for constructing a computing board model, which aims to improve fault diagnosis efficiency, increase diagnostic accuracy, and reduce the technical threshold for maintenance.

[0005] To achieve the above objectives, the present invention provides a method for constructing a computing board model, the method comprising: Obtain the layout element information of the corresponding model of computing board; Display a preview image of the computing board effect that matches the layout element information, and there is a mapping relationship between the preview image of the computing board effect and the computing board parameter values; Determine the positions and dimensions of multiple computing chips in the preview image of the computing board effect; Draw an interactive control corresponding to the size of the computing chip at each of the aforementioned computing chip locations; Adjust the computing board parameter values ​​of the interactive control to generate the target computing board model.

[0006] Optionally, drawing an interactive control corresponding to the size of the computing chip at each location of the computing chip includes: In response to the selection operation of the preview image of the computing board, the selected location of the computing chip is determined; Generate an interactive rectangle with dimensions matching those of the computing chip at any corner point of the location of the computing chip; The interactive control is generated by filling the corresponding location number and computing board parameter value into the interactive rectangle.

[0007] Optionally, the step of filling the interactive rectangle with the corresponding position number and computing board parameter value to generate the interactive control includes: Obtain the position numbers of the interactive rectangles corresponding to all computing power chips; After filling the corresponding position numbers into the interactive rectangle, the position numbers are checked for duplicate sorting. If duplicate position numbers exist, display the corresponding prompt message and highlight the interactive control for the duplicate number; If there are no duplicate location numbers, fill the computing board parameter values ​​into the corresponding interactive rectangle.

[0008] Optionally, the method for drawing the preview image of the computing board includes: Obtain the dimensions of the corresponding computing board, the number of computing chips, and the arrangement of the computing chips; Draw the substrate outline of the computing board according to the dimensions; Based on the number of computing chips and their arrangement, calculate the chip layout coordinates corresponding to the outer contour of the substrate. The computing chip is positioned at a first location within the outline according to the chip layout coordinates, and a preview image of the computing board is drawn according to the first location.

[0009] Optionally, obtaining the size of the corresponding model computing board, the number of computing chips, and the arrangement of the computing chips includes: In response to a parameter search request, it links to the corresponding parameter database; Search the parameter database for parameter information of the corresponding model of computing board; In response to the listening command event of the operation interface, the computing board size, number of computing chips and their arrangement are obtained from the parameter information.

[0010] Optionally, obtaining the layout element information of the corresponding model of computing board includes: In response to the model selection operation for the computing board, the configuration of the selected computing board model is imported. The computing board configuration includes the substrate shape parameters, computing chip parameters, interface positions and power supply positions. The layout element information is generated based on the substrate shape parameters, the computing chip parameters, the interface location, and the power supply location.

[0011] Optionally, the method for constructing the computing board model further includes: Obtain the temperature chip parameters, sensor chip parameters, and interface circuit parameters of the corresponding computing board model; Based on the temperature chip parameters, the sensor chip parameters, and the interface circuit parameters, corresponding auxiliary component layout information is generated; The temperature chip, sensor chip, and interface circuit corresponding to the layout information of the auxiliary components are displayed on the preview image of the computing board. The corresponding interactive controls are filled in according to the first position of the temperature chip, the second position of the sensor chip, and the third position of the interface circuit, and the numbering information and warning threshold information of the interactive controls are adjusted.

[0012] Optionally, the method for constructing the computing board model further includes: Obtain the actual operating parameters of the corresponding model of the actual computing board; The actual operating parameters are compared with the operating parameters in the target computing board model to determine the correspondence between each computing chip in the target computing board model and the chip in the actual computing board.

[0013] In addition, to achieve the above objectives, the present invention also provides a construction apparatus, the construction apparatus comprising: a memory, a processor, and a construction program for a computing board model stored in the memory and executable on the processor, the computing board model construction program being configured to implement the computing board model construction method as described above.

[0014] In addition, to achieve the above objectives, the present invention also provides a computer program product, including the construction apparatus described above.

[0015] This invention first acquires the layout element information of a corresponding model of computing board, then displays a preview image of the computing board based on the layout element information. A mapping relationship exists between the preview image and the computing board parameter values. Next, the positions and sizes of multiple computing chips in the preview image are determined, and interactive controls corresponding to the chip size are drawn at each chip position. Finally, the computing board parameter values ​​of the interactive controls are adjusted to generate a target computing board model. Thus, by constructing a visual preview image of the computing board and integrating interactive controls, the physical layout is transformed into a dynamically adjustable digital model. This allows maintenance personnel to intuitively identify chip positions and parameter states, thereby quickly locating fault points and optimizing maintenance processes. This significantly improves fault diagnosis efficiency, increases diagnostic accuracy, and lowers the technical threshold for electronic repair. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a method for constructing a computing board model according to an embodiment of the present invention; Figure 2 for Figure 1 A flowchart illustrating step S400 in the diagram; Figure 3 for Figure 2 A flowchart illustrating step S430 in the diagram; Figure 4 This is a schematic diagram of the construction method of the computing board model according to another embodiment of the present invention; Figure 5 for Figure 4 A flowchart illustrating step S600 in the diagram; Figure 6 for Figure 1 A flowchart illustrating step S100 in the diagram; Figure 7 This is a schematic diagram of the construction method of the computing board model according to another embodiment of the present invention; Figure 8 This is a schematic diagram of the construction method of the computing board model according to an embodiment of the present invention; Figure 9 This is a preview image of the computing board's performance. Figure 10 This is a schematic diagram of the display interface for interactive controls.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Well-known modules, units, and their connections, links, communications, or operations are not shown or described in detail. Furthermore, the described features, architectures, or functions can be combined in any way in one or more embodiments. Those skilled in the art should understand that the various embodiments described below are only for illustrative purposes and not for limiting the scope of protection of the present invention. It is also readily understood that the modules, units, or processing methods in the various embodiments described herein and shown in the accompanying drawings can be combined and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The definitions of various terms or methods used in the following embodiments are, except where logically impossible, generally defined as broad concepts that can be implemented under the premise of the content disclosed in the embodiments. Under this understanding, all specific subordinate limitations of the terms or methods should be considered as part of the invention and should not be narrowly interpreted or biased simply because the specification does not disclose such a specific limitation. Similarly, provided that it is logically feasible, the order of the steps in the method is flexible and varied, and all specific subordinate limitations in the broad concepts of various terms or methods fall within the scope of protection of this invention.

[0022] In the operation and maintenance of blockchain servers, the computing board, as a core hardware component, has long relied on manual operation by technicians using specialized measuring tools for troubleshooting. This repair process is highly dependent on accumulated personal experience and lacks intuitive visualization tools.

[0023] In existing technologies, troubleshooting requires point-by-point measurement and verification, with an average time of two to three hours for a single computing board, which seriously slows down the overall maintenance progress. The diagnostic results are significantly affected by subjective experience, and the accuracy of fault identification is only maintained at about 60%, which is prone to misjudgment or missed detection. In the process of team collaboration, maintenance personnel and technical support personnel cannot share a clear circuit layout view and need to repeatedly describe details such as chip location and interface type verbally, which results in low communication efficiency and is prone to misunderstanding.

[0024] Furthermore, novice technicians lack intuitive guidance tools and must undergo extensive practice to master repair skills, resulting in a high barrier to entry into the industry. These shortcomings lead to continuously rising repair costs and make it difficult to adapt to the high-density, high-complexity hardware architecture requirements of modern servers.

[0025] Research revealed that the aforementioned problems stemmed from the inability of existing fault repair equipment to directly visualize the physical distribution, dimensional parameters, and circuit connections of the chips within the computing board. This resulted in multiple challenges for repair personnel when locating fault points. Current technology has not yet resolved how to utilize visualization modeling techniques to transform the physical layout of the computing board into an interactive digital model, intuitively displaying chip arrangement, parameter status, and circuit link relationships, thereby enabling rapid fault location and accurate diagnosis.

[0026] The main solution of this application embodiment is as follows: First, obtain the layout element information of the corresponding model of computing board, then display the corresponding computing board effect preview according to the layout element information, wherein there is a mapping relationship between the computing board effect preview and the computing board parameter values, then determine the positions and sizes of multiple computing chips in the computing board effect preview, and draw interactive controls corresponding to the computing chip size at each computing chip position, and finally adjust the computing board parameter values ​​of the interactive controls to generate the target computing board model.

[0027] In this embodiment, for ease of description, the construction device will be used as the execution subject in the following description.

[0028] This application provides a solution that transforms the physical layout into a dynamically adjustable digital model by constructing a visual preview of the computing board and integrating interactive controls. This allows maintenance personnel to intuitively identify the chip location and parameter status, thereby quickly locating the fault point and optimizing the maintenance process. It can significantly improve fault diagnosis efficiency, increase diagnostic accuracy, and lower the technical threshold for electronic maintenance.

[0029] To this end, the present invention proposes a method for constructing a computing board model; it is understood that the computer program product is provided with a construction device for storing and executing the following method, and the construction device can be implemented by a main controller, such as MCU (Micro controller Unit), DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), SOC (System On Chip), etc.

[0030] Blockchain servers encompass various types, including large-scale computing servers, distributed storage servers, and edge computing servers. Their core computing power units all rely on computing boards for basic computational support. In the maintenance of blockchain server computing boards, current technologies rely on manual measurement and fault location using specialized tools, making the core process highly dependent on the personal experience of maintenance personnel. Due to the lack of a directly visualized circuit model, maintenance personnel cannot intuitively obtain the chip distribution and circuit link relationships of the computing board. This leads to prolonged fault location time, reduced accuracy, decreased team collaboration efficiency, and a higher learning curve for new personnel. These issues directly affect the response speed and overall reliability of the maintenance system.

[0031] For example, when maintaining blockchain servers in a data center, if a computing board malfunctions, maintenance personnel need to use tools such as multimeters to measure circuit parameters point by point to locate the faulty chip. Because the chips on the computing board are densely packed and their layout and status cannot be visualized in real time, maintenance personnel are required to repeatedly refer to circuit diagrams and communicate with remote technical support via voice to describe the specific location. During this process, unclear descriptions of circuit details often lead to misdiagnosis of the fault point, requiring repeated measurements. This not only prolongs the maintenance process but also increases the risk of errors, especially for new employees, who face increased difficulty in independently locating the fault.

[0032] If the above issues are not addressed, the maintenance process will continue to be limited by human experience, fault location time will be uncontrollably prolonged, maintenance accuracy cannot be effectively guaranteed, communication misunderstandings in team collaboration will significantly impact maintenance efficiency, and extended training cycles for new personnel will increase human resource costs. These problems will lead to slow maintenance responses for blockchain servers, affecting the stable operation and availability of the system, and consequently negatively impacting the overall operational capabilities of the data center.

[0033] Based on the above issues, referring to Figure 1 In one embodiment of the present invention, the method for constructing the computing board model includes steps S100-S500, wherein: S100: Obtain the layout element information of the corresponding model of computing board; S200: Display a preview image of the computing board effect that matches the layout element information. There is a mapping relationship between the preview image of the computing board effect and the computing board parameter values. S300. Determine the location and size of multiple computing chips in the computing board effect preview image; S400: Draw an interactive control corresponding to the size of the computing chip at each computing chip location; S500: Adjust the parameter values ​​of the computing board in the interactive control to generate the target computing board model.

[0034] The layout element information includes key information such as the overall structural framework of the computing board, the preset arrangement rules of the chips, the layout plan of the heat dissipation module, and the distribution of interfaces. This layout element information ensures that the preview image accurately reflects the layout of the computing board in actual applications. Through the mapping relationship with the computing board parameter values, it allows users to intuitively understand the presentation effect of the computing board under different parameter settings. The computing board effect preview image refers to an image generated based on the layout element information during the construction of the computing board model. This image visually displays the layout and appearance of the computing board. It not only presents the overall structure of the computing board but also shows the specific arrangement of chips, the layout of the heat dissipation module, and the distribution of interfaces. Through the computing board effect preview image, users can anticipate the performance of the computing board in actual applications during the model construction stage, allowing for more precise parameter adjustments and optimizations. The computing chip positions refer to the coordinate positions clearly marked in the computing board effect preview image for installing computing chips. These coordinate positions can be located using a precise coordinate system or adjusted manually to ensure that each computing chip is accurately placed in its predetermined position. The size of a computing chip refers to its physical dimensions, such as length, width, and height, determined according to the proportions of the chips on the actual computing board. The computing board parameters include the board size, the number of chips, and the chip layout.

[0035] Interactive controls are used to adjust the parameter values ​​of the corresponding computing chips in response to user input. An interactive control is a graphical element that responds to user operations and interacts with data. During the construction of the computing board model, interactive controls are precisely drawn on the location of each computing chip, with their size corresponding to the chip's size. These interactive controls not only have intuitive visual identifiers, such as numbered displays, allowing users to clearly identify each computing chip, but also display the computing power value at the time of the anomaly in real time, providing users with immediate fault feedback. Even more conveniently, when the anomaly duration reaches a certain threshold, a long press on an interactive control will display a corresponding repair method prompt, guiding the user to quickly and effectively troubleshoot the problem.

[0036] Obtaining the layout element information of the corresponding computing board model refers to acquiring the physical and electrical characteristic parameters of the computing board. In practical applications, this can be achieved by reading a pre-stored parameter file from a local storage device or by having the user manually input specified parameter values. Displaying a preview image of the computing board that matches the layout element information refers to presenting a graphical representation of the computing board. This can be achieved by calling a graphics rendering engine to generate a two-dimensional image or by loading an existing image resource file. Therefore, determining the positions and dimensions of multiple computing chips in the preview image can be accomplished by automatically detecting the chip areas using image recognition algorithms or by manually marking the positions using a coordinate input interface.

[0037] In this embodiment, drawing interactive controls corresponding to the size of each computing chip at its location can be achieved by generating text labels or icons, such as adding clickable button elements to the chip area. Adjusting the computing board parameter values ​​of the interactive controls can be done through slider controls or by modifying parameters via form input boxes to generate the target computing board model. This embodiment constructs an interactive visual model using the above method, enabling maintenance personnel to intuitively view the chip distribution and perform parameter operations, thereby solving the problems of long fault location time, low accuracy, poor collaboration efficiency, and high maintenance threshold in blockchain server computing board maintenance.

[0038] The method for constructing the computing board model in this embodiment generates a visual model through systematic steps, addressing the problems of long fault location time, low accuracy, poor collaboration efficiency, and high maintenance threshold in blockchain server computing board repair. Specifically, layout element information is acquired based on the hardware parameters of the corresponding computing board model, including board size, number of chips, and chip layout, providing a precise data foundation and avoiding positioning errors caused by missing information during manual measurement. A preview image of the computing board is displayed, showing a mapping relationship between the preview image and the computing board parameter values, which encompass board size, number of chips, and chip layout. This makes the chip distribution and size intuitively presented, reducing communication misunderstandings caused by unclear circuit details during repair. The positions and sizes of multiple computing chips are determined; this step accurately locates the physical coordinates and dimensions of each chip based on the preview image, providing an accurate basis for subsequent interactive operations. At each computing chip location, an interactive control matching the chip's size is drawn. This control responds to user-inputted parameter adjustment commands to adjust the corresponding computing chip's parameter values. For example, it can display the chip's number, the computing power value during anomalies, or pop up a maintenance message at regular intervals during anomalies, ensuring the control perfectly corresponds to the actual physical location of the chip. Finally, the computing board parameter values ​​of the interactive control are adjusted to generate a target computing board model, enabling real-time parameter adjustment and model comparison by the user.

[0039] In one implementation, for the Avalon computing board model "1346_3200C_38X3", layout element information is acquired, such as the computing board size being 220 mm × 180 mm, the number of chips being 114, and the chip layout being four groups: a first array of 9 × 2, a second array of 10 × 2, a third array of 10 × 2, and a fourth array of 9 × 2. A preview image of the computing board is generated and displayed, such as... Figure 9 As shown, the chip positions are precisely located; an interactive rectangle of the same size is drawn at each chip position, and the drawing interface is as follows. Figure 10 As shown, the filling positions are numbered from "1" to "8". By adjusting the control parameters, including the chip number, computing power range, and size, the target computing board model is generated. This allows maintenance personnel to intuitively operate the model, quickly identify the location of faulty chips, and reduce time spent in fault localization. The interactive controls provide real-time parameter information and maintenance guidance, improving the accuracy of fault diagnosis. The visual interface reduces communication costs between maintenance personnel and technical support, improving collaboration efficiency. Furthermore, novices can obtain key maintenance information without relying on extensive experience, effectively lowering the barrier to entry for maintenance operations.

[0040] It should be noted that, Figure 10 This is merely a schematic diagram of an interactive control for a computing board design, such as... Figure 9 The diagrams of computing boards shown, or other computing board diagrams not shown in the diagrams, are all drawn in the same way.

[0041] The overall principle of this embodiment is as follows: First, import a pre-drawn computing board style diagram that matches the shape and size of the actual computing board. This computing board style diagram can be downloaded from a browser, queried from a database, or manually drawn in software such as Adobe Photoshop or Adobe Illustrator. The computing board style diagram will show the positions of the computing chips. At the same time, if the computing board of this model is also equipped with temperature sensing chips or other sensing chips, they will also be drawn on the computing board style diagram. Then, manually draw an interactive control at the position of each computing chip. If there are temperature sensing chips or other sensing chips, interactive controls will also be drawn at the corresponding positions. After the drawing is completed, the computing board parameter values ​​of the interactive control, namely the computing chip number, computing power value range, and size, can be adjusted so that the interactive control can display the number, the computing power value when there is an anomaly, and pop up the corresponding maintenance method when there is an anomaly. Finally, the target computing board model displayed is the computing board model, that is, the actual computing board and the computing chips and sensor chips on the board are scaled up to a certain ratio and displayed on the screen.

[0042] The core principle of this embodiment is to transform the hardware circuit of the computing board into a visual model. By collecting the internal chip data of the computing board during operation and comparing it with the normal model data, the abnormal chip is located and marked on the visual interface. The graphical intuitiveness simplifies the fault diagnosis logic.

[0043] The implementation steps can be as follows: 1. Collect hardware information of the computing board, including PCB shape, number of chips, distribution location, reference numbers and circuit link relationships; 2. Construct a visualization model based on the collected information and draw the background: Use Adobe Illustrator software to draw the background of the computing board model according to the actual computing board circuit, that is, the style diagram of the computing board (mainly the arrangement and position of the computing chips on it; this step highlights the model background).

[0044] 3. Draw chip grid (interactive control): In the self-developed management backend, draw grids for each brand and model of computing board chip, and number the chips according to the actual circuit (the actual circuit has a default number set at the factory, and the numbering is transplanted here. This step focuses on the numbering).

[0045] 4. Establish communication between the visualization model and the computing board under repair, collect the working data of each chip in real time, and compare the collected data with a standard database through an algorithm to identify chips with abnormal data; 5. Mark the location and fault type of the faulty chip in the visualization model with prominent markers (such as a red background). (Points 4 and 5 mainly involve using the program to locate the faulty chip and control its displayed content and color.) in, Figure 9 Background panels created for Adobe Illustrator software or background images downloaded from the internet. Figure 10 The grid drawn for the management backend.

[0046] This embodiment simplifies the understanding of complex circuits by constructing a visual model of the computing board, enabling junior electronic repair engineers to operate independently after simple training, thus lowering the repair threshold. Furthermore, the intuitive graphical display improves cross-functional collaboration efficiency, reduces communication costs between technical support and repair personnel, and avoids information misunderstandings.

[0047] This embodiment first obtains the layout element information of the corresponding computing board model, then displays a preview image of the computing board based on the layout element information. There is a mapping relationship between the preview image and the computing board parameter values. Next, the positions and sizes of multiple computing chips in the preview image are determined, and interactive controls corresponding to the chip size are drawn at each chip position. Finally, the computing board parameter values ​​of the interactive controls are adjusted to generate the target computing board model. In this way, by constructing a visual preview image of the computing board and integrating interactive controls, the physical layout is transformed into a dynamically adjustable digital model. This allows maintenance personnel to intuitively identify chip positions and parameter states, thereby quickly locating fault points and optimizing maintenance processes. This significantly improves fault diagnosis efficiency, increases diagnostic accuracy, and lowers the technical threshold for electronic repair.

[0048] Optionally, refer to Figure 2 Another embodiment of the present invention provides a method for constructing a computing board model, based on the above. Figure 1 The embodiment shown draws an interactive control corresponding to the size of the computing chip at each computing chip location, including steps S410-S430, wherein: S410, in response to the selection operation of the preview image of the computing board, determine the location of the selected computing chip; S420: Generate an interactive rectangle with dimensions matching the dimensions of the computing chip at any corner point of the computing chip location; S430. Fill the interactive rectangle with the corresponding position number and computing board parameter value to generate an interactive control.

[0049] The selection operation refers to the technical means by which users interactively locate the computing board preview image through input devices. This can be achieved by clicking on a touchscreen, dragging with a mouse, or entering coordinates into a input box. The purpose is to ensure that the location of the computing chip is determined based on the user's active selection rather than preset coordinates, thereby avoiding physical position deviations caused by manual estimation. The interactive rectangle refers to the visual operation area covering the location of the computing chip. It can be generated using vector graphics rendering or bitmap overlay. The purpose is to dynamically match the chip size to build a control framework consistent with the actual outline, reducing the risk of misoperation caused by size mismatch. The location number refers to the character sequence used to uniquely identify the computing chip. It can be presented in the form of numbers, letters, or a combination of codes. The purpose is to provide clear visual guidance, making it easy for users to quickly identify the chip status and make targeted adjustments.

[0050] In this embodiment, the solution precisely locates the physical position of the computing chip in response to a user selection operation. Based on the corner coordinates of this position, a rectangular frame that strictly matches the chip size is generated. The location number and computing board parameter values ​​are then embedded within the rectangle to form a complete interactive control. Since the selection operation is directly related to the user's interaction behavior, it ensures that the control position strictly corresponds to the actual chip layout. Because the size of the interactive rectangle dynamically matches the chip's physical size, the control outline remains consistent with the chip's actual shape. Furthermore, considering that the filling operation of the location number and parameter values ​​is completed within the size-matched frame, information confusion is avoided. These steps are executed sequentially, forming a complete technical chain from location determination to information embedding, which avoids problems such as inaccurate location, size mismatch, and information redundancy during the control construction process.

[0051] In one preferred implementation, when a user taps the target computing chip area in the computing board preview image on the touchscreen, the construction device automatically captures the tap coordinates as input for the selection operation, thereby determining the location of the computing chip. Then, using the upper left corner (or lower right, lower right, or lower left corner) of this location as a reference point, a rectangle matching the chip size is generated based on pre-stored chip size data. The rectangle's border is semi-transparently filled to maintain the visibility of the underlying chip outline. Finally, the location number "15" and the computing power alarm threshold "below 12.5TH / s" are filled into the center of the rectangle, forming an interactive control. Users can long-press this control to access the parameter adjustment interface and modify the computing power threshold in real time.

[0052] Through the above solution, this embodiment achieves precise matching between the interactive controls and the physical location and size of the computing chip, significantly improving the accuracy of constructing the visualization model of the computing board, and providing reliable visual guidance and data support for maintenance personnel to quickly locate faulty chips.

[0053] Optionally, refer to Figure 3 Another embodiment of the present invention provides a method for constructing a computing board model, based on the above. Figure 2 The embodiment shown involves filling the interactive rectangle with the corresponding location number and computing board parameter values ​​to generate an interactive control, including steps S431-S434, wherein: S431. Obtain the position number of the interactive rectangle to be filled for all computing power chips; S432. After filling the corresponding position numbers into the interactive rectangle, perform duplicate sorting and verification on the position numbers; S433. If there are duplicate position numbers, display the corresponding prompt message and highlight the interactive control for the duplicate number; S434. If there are no duplicate location numbers, fill the computing board parameter values ​​into the corresponding interactive rectangle.

[0054] Location ID acquisition refers to extracting location identifier data from all created interactive controls. This can be achieved by traversing the control list and reading the ID attribute value of each control, providing a basis for subsequent duplicate detection. Duplicate sorting verification can be understood as sorting the collected location IDs and detecting duplicates. By using the ID attribute value of each identified control, a one-to-one comparison is made to efficiently identify ID conflicts and promptly capture errors. Error message display refers to presenting error notifications on the user interface. This can be achieved by popping up dialog boxes and highlighting the border color or background color of duplicate controls, visually exposing the problem location for quick user correction. Parameter value filling refers to writing the computing board parameters into the interactive controls. This can be achieved by binding parameter data to control properties, ensuring the reliability of the control data.

[0055] In this embodiment, the solution first acquires all location numbers to form a global dataset. Then, based on the real-time status after filling, it performs sorting and duplicate detection. If a conflict is detected, a visual feedback mechanism is immediately triggered, allowing the user to correct duplicate numbers. The parameter filling operation is only performed after confirming that the number is unique. This execution order ensures that errors are intercepted before parameter filling, preventing conflicting data from entering the subsequent model building stage. Through conditional branching logic driven by the verification result, a closed-loop process of data verification and user correction is achieved, thereby ensuring the uniqueness of chip location identifiers and data integrity in the computing board model.

[0056] In one preferred implementation, the location number can be filled into the interactive rectangle in the form of strings such as "24" and "45". During the duplicate verification stage, the construction device sorts the number list and compares adjacent items one by one. For example, if "12" is found to be repeated, a "Duplicate Location Number" prompt message will pop up on the interface, and the border of the duplicate control will be set to red to highlight it. When the verification confirms that there is no duplicate, the system fills the computing power range, chip size and other parameter values ​​into the corresponding interactive rectangle, thus completing the generation of the interactive control.

[0057] Through the above solution, this embodiment effectively avoids the problem of interactive control identification conflict caused by duplicate location numbers, ensuring that each chip location in the computing board model has a unique identification identifier, thereby improving the accuracy of fault location and maintenance efficiency, reducing the risk of chip location confusion in maintenance scenarios, shortening troubleshooting time and improving accuracy.

[0058] Optionally, refer to Figure 4 In another embodiment of the present invention, a method for constructing a computing board model is provided, based on the above. Figure 1The embodiment shown illustrates a method for drawing a preview image of the computing board, including steps S600-S900, wherein: S600: Obtain the dimensions of the corresponding model computing board, the number of computing chips, and the arrangement of the computing chips; S700: Draw the outline of the computing board substrate according to the dimensions; S800: Calculate the chip layout coordinates corresponding to the outer contour of the substrate based on the number and arrangement of the computing chips. S900, and based on the chip layout coordinates, configure the first position of the computing chip within the outer contour, and draw a preview image of the computing board effect according to the first position.

[0059] Obtaining the dimensions, number of computing chips, and chip arrangement of the corresponding computing board model refers to acquiring key hardware parameters from a reliable data source. This can be achieved by parsing local configuration files, calling external service interfaces, or receiving input through a user interface. The purpose is to ensure the accuracy of the basic data and avoid errors in manual estimation. Drawing the substrate outline of the computing board based on its dimensions can be understood as generating a geometric reference frame based on precise dimensions. This can be achieved using a vector graphics rendering engine or a computer-aided design module. The purpose is to establish a proportional benchmark consistent with the actual physical dimensions and prevent layout distortion due to dimensional deviations. Based on the computing chip... The number and arrangement of chips, and the calculation of chip layout coordinates corresponding to the outer contour of the substrate, refer to the automatic determination of the chip spatial position through algorithms. This can be achieved by using grid coordinate calculation, matrix transformation, or rule-based layout engines. The purpose is to handle the complexity of different layout methods and reduce human intervention and positioning errors. Based on the chip layout coordinates, the first position of the computing chip is configured within the outer contour, and a preview image of the computing board is drawn according to the first position. Specifically, the calculated coordinates are mapped to the graphical interface. This can be achieved by using a graphical user interface framework or real-time rendering technology. The purpose is to achieve automated generation of the preview image and ensure a high degree of consistency with the actual hardware layout.

[0060] In this embodiment, the solution first obtains the dimensions, number of chips, and arrangement of the computing board as initial input parameters, providing an accurate data foundation for subsequent rendering. Then, based on the dimension parameters, a precise substrate outline is drawn, forming a proportionally accurate spatial reference frame. Next, according to the number and arrangement of chips, an algorithm calculates the precise coordinate position of each chip within the outline, achieving automated position determination. Finally, the calculated coordinates are directly applied to the graphics configuration and rendering process to generate the final preview image. The parameter acquisition ensures the reliability of the input data, the outline drawing establishes an accurate spatial reference, the coordinate calculation achieves precise position positioning, and the configuration drawing completes the automatic generation of the preview image. Overall, this achieves a high degree of matching between the preview image and the actual computing board layout, avoiding deviations caused by manual intervention.

[0061] As a preferred implementation, for a specific model of computing board, the construction device obtains the computing board size parameters, number of computing chips and arrangement information by parsing the locally stored configuration file; draws the outline of a rectangular substrate that matches the size using a vector graphics library; calculates the precise coordinate position of the chips within the outline using a grid layout algorithm based on the number and arrangement of chips; configures the first position of the computing chips in the graphical interface according to the calculated coordinates, and generates an effect preview image through a UI rendering engine, where each chip position is represented by a visual marker.

[0062] Through the above solution, this embodiment achieves accurate and automated generation of the computing board effect preview image, effectively solving the problem of discrepancies between the preview image and the actual layout, and improving the accuracy of chip position determination and model building efficiency.

[0063] Optionally, refer to Figure 5 Furthermore, this invention provides a method for constructing a computing board model, based on the above. Figure 4 The embodiment shown obtains the size of the corresponding model computing board, the number of computing chips, and the arrangement of the computing chips, including steps S610-S630, wherein: S610, In response to a parameter search request, link to the corresponding parameter database; S620, Search the parameter database for parameter information of the corresponding computing board model; S630 responds to the listening command event of the operation interface and obtains the computing board size, number of computing chips and their arrangement from the parameter information.

[0064] In this embodiment, to avoid inaccurate and inefficient information caused by manually input or unstructured data sources, which would affect the accuracy and speed of subsequent model construction, accurate and structured parameter information is obtained directly from external websites or internal databases.

[0065] Among them, parameter search request refers to the query operation initiated by the user, which can be achieved by clicking on the interface button or typing on the keyboard, with the purpose of initiating the parameter acquisition process; parameter database can be understood as a structured data source that stores the parameters of the computing board, which can be implemented using a cloud database or a local server database, with the purpose of ensuring the reliability and consistency of the data source; listening to command events refers to the mechanism by which the operation interface responds to user interaction in real time, which can be implemented using an event-driven architecture or a polling mechanism, with the purpose of capturing user commands and extracting the required parameters in a timely manner.

[0066] This embodiment automates parameter acquisition through a collaborative mechanism that establishes database links on demand, executes structured queries, and monitors interface events in real time. First, when a user initiates a parameter search request, the construction device sends a dynamic link to the parameter database, avoiding the waste of preloading system resources and ensuring the consistency and reliability of the data source. Second, the construction device utilizes the database's indexing mechanism to quickly locate the complete parameter set for the corresponding model, significantly improving the accuracy and speed of parameter acquisition. Third, by monitoring command events on the operation interface, the system instantly extracts the computing board size, the number of computing chips, and their arrangement, seamlessly integrating user interface interaction with the data extraction process, thereby optimizing the overall parameter acquisition workflow.

[0067] As a preferred implementation, when a user enters the computing board model in the search box of the operation interface and triggers the search operation, the system automatically connects to the internal parameter database and the parameter database returns the complete parameter information of the model; after the interface listens for the user confirmation event, it immediately parses and obtains data such as the computing board size, the number of computing chips and their arrangement, for use in subsequent model construction.

[0068] Through the above solution, this embodiment automates and structures the parameter acquisition process, effectively avoids errors caused by manual input, and significantly improves the accuracy and efficiency of parameter acquisition, thereby providing a reliable guarantee for the efficient and accurate construction of the computing board model.

[0069] Optionally, refer to Figure 6 Another embodiment of the present invention provides a method for constructing a computing board model, based on the above. Figure 1 The embodiment shown obtains the layout element information of the corresponding model of computing board, including steps S110-S120, wherein: S110. In response to the model selection operation for the computing board, import the configuration of the selected computing board model. The computing board configuration includes the substrate shape parameters, computing chip parameters, interface positions and power supply positions. S120. Generate layout element information according to the substrate shape parameters, computing chip parameters, interface positions and power supply positions.

[0070] The model selection operation refers to the user's action of triggering model recognition through a graphical user interface. This can be achieved through drop-down menu selection, model code input, or clicking on a model list, with the aim of quickly associating with predefined configuration data sources. The computing board configuration refers to a standardized set of information stored in the parameter database, which may include structured defined substrate shape parameters, computing chip parameters, interface locations, and power supply locations, aiming to provide a unified and traceable model description benchmark. The computing chip parameters include the size, power, computing power value, and communication interface type of the computing chip. The substrate shape parameters refer to the set of parameters defining the physical outline of the computing board, which can be implemented using two-dimensional outline coordinate description, geometric parameterization, or three-dimensional model reference, aiming to accurately define the physical framework boundaries of the computing board. In practical applications, the computing chip parameters refer to the parameter group describing the characteristics of the computing chip, which may include dimensions such as size specifications, power range, computing power value range, and communication interface type, aiming to provide a complete basis for chip function analysis and layout planning.

[0071] In addition, interface location and power supply location refer to the spatial positioning information of functional nodes on the computing board. They can be implemented by means of absolute coordinate system positioning, relative position reference or topological relationship description, with the aim of accurately mapping circuit link relationships. Among them, generating layout element information refers to the process of automatically constructing layout description data based on structured parameters. It can be implemented by means of parameter parsing engine, data mapping rules or information integration algorithm, with the aim of forming a complete input that can directly drive model construction.

[0072] This embodiment triggers the configuration import mechanism through model selection, using the model as a unique identifier to automatically associate predefined configurations, avoiding parameter input errors caused by reliance on manual experience. The imported computing board configuration includes structured information such as substrate shape parameters, computing chip parameters, interface positions, and power supply positions. These parameters collectively define the complete physical and functional characteristics of the computing board. The construction device automatically integrates and generates layout element information according to these parameters, ensuring the uniformity and traceability of information sources, and avoiding fragmentation problems caused by manual piecing together. The generated layout element information directly drives the drawing of the computing board effect preview image, thereby providing accurate input for chip position determination and parameter adjustment, improving the consistency between the model and the actual computing board.

[0073] In one implementation, when a user selects a specific model of computing board on the operation interface, the building device responds to the model selection operation by automatically importing the corresponding computing board configuration from the parameter database. This configuration includes substrate shape parameters (such as the outline shape description of a rectangular substrate), computing chip parameters (such as the size specifications, power range, computing power value range, and communication interface type of the computing chip), interface location (such as the coordinate positioning of the communication interface), and power supply location (such as the installation area of ​​the power connector). The building device generates layout element information according to these parameters to display a preview image of the computing board effect and determine the location of the computing chip in subsequent steps.

[0074] The above solution avoids errors caused by manual input during the acquisition of layout element information, ensuring the integrity and consistency of parameters, thereby improving the matching degree between the computing board model and the actual computing board, and effectively improving the accuracy of fault location and maintenance efficiency.

[0075] In the above embodiments, the integration of auxiliary components such as temperature monitoring, sensing and interface circuits is ignored, which makes the model unable to cover potential fault points such as abnormal temperature, sensor failure or interface problems. This results in insufficient completeness of fault diagnosis, and maintenance personnel still need to rely on experience to manually check the related problems of auxiliary components, which affects the overall positioning efficiency and accuracy.

[0076] Based on the above issues, referring to Figure 7 Another embodiment of the present invention provides a method for constructing a computing board model, based on the above. Figure 1 The embodiment shown further includes steps S1000-S1300 in the method for constructing the computing board model, wherein: S1000: Obtain the temperature chip parameters, sensor chip parameters, and interface circuit parameters of the corresponding computing board model; S1100: Generate corresponding auxiliary component layout information based on temperature chip parameters, sensor chip parameters, and interface circuit parameters; S1200: Display the temperature chip, sensor chip, and interface circuit corresponding to the layout information of auxiliary components on the computing board effect preview image; S1300, and fill in the corresponding interactive controls according to the first position of the temperature chip, the second position of the sensor chip and the third position of the interface circuit, and adjust the numbering information and warning threshold information of the interactive controls.

[0077] Among them, temperature chip parameters refer to the chip specification data used to monitor the temperature status of the computing board, which may include chip size, interface type, and measurement range. In practical applications, these parameters can be obtained by querying a hardware configuration database. The purpose is to ensure that the model accurately reflects the physical characteristics of the temperature monitoring element. Sensor chip parameters can be understood as the configuration information of various sensing elements, covering sensor type, sensitivity, and installation requirements. In implementing the scheme of this embodiment, these parameters can be imported from the device management platform to provide complete sensing data support for the model. Interface circuit parameters specifically refer to the electrical characteristics of the interface on the computing board, including protocol standards, pin definitions, and signal transmission characteristics. In practical applications, these parameters can be extracted from circuit design documents to ensure the accuracy of the interface circuit in the model. The auxiliary component layout information refers to the spatial coordinates of the temperature chip, sensor chip, and interface circuit on the computing board. This information can be generated using coordinate calculation algorithms. In implementing the scheme of this embodiment, the layout can be dynamically performed based on the substrate shape parameters. The purpose is to ensure that the visual model strictly matches the actual hardware layout. Interactive controls can be understood as user-operable interface elements, which are represented by clickable rectangles or icons. In implementing the scheme of this embodiment, graphical user interface technology can be used for rendering. The purpose is to provide a channel for users to interact with the model. Warning threshold information specifically refers to the parameter boundary values ​​that trigger abnormal warnings. These are set as the upper limit of temperature, the sensor reading range, etc. In practical applications, they can be input through the configuration interface. The purpose is to achieve real-time monitoring of the operating status and abnormal warnings.

[0078] This embodiment uses temperature chip parameters, sensor chip parameters, and interface circuit parameters as input. It dynamically calculates component positions based on the correlation between these parameters to generate auxiliary component layout information. This auxiliary component is integrated with the computing chip in the same view. Based on the layout information, the location of interactive controls is precisely determined, and warning thresholds are set, thus expanding fault location from a single computing chip to the entire component range. The device first acquires parameters based on the actual hardware configuration to ensure data reliability. Then, it generates auxiliary component layout information based on the parameters, ensuring the layout accurately reflects the differences between different computing board models. Next, the temperature chip, sensor chip, and interface circuit are simultaneously displayed on the computing board preview image, achieving visual integration of all components. Finally, interactive controls are filled according to the first position of the temperature chip, the second position of the sensor chip, and the third position of the interface circuit, and the numbering and warning threshold information are adjusted, allowing users to focus on specific components and monitor abnormal states through the controls. This process, through the organic integration of parameter acquisition, layout generation, visualization display, and control configuration, forms a fault diagnosis support system covering all components.

[0079] In a preferred implementation, for a certain type of computing board, the construction device acquires its temperature chip parameters, including a temperature sensor using a standard digital interface, sensor chip parameters covering voltage monitoring sensors, and interface circuit parameters including high-speed serial interface characteristics. Based on these parameters, auxiliary component layout information is generated, positioning the temperature chip in the substrate's heat dissipation area, arranging the sensor chip around the power management unit, and distributing the interface circuit along the substrate edge. These components are displayed at corresponding positions on the computing board preview image, and interactive controls are added. The temperature chip control sets a temperature warning threshold, and the sensor chip control configures a signal anomaly threshold. Users can click on the controls to view real-time operating data or adjust threshold parameters, enabling intuitive monitoring of temperature anomalies, sensor malfunctions, and interface problems.

[0080] Through the above solution, this embodiment achieves comprehensive coverage of potential fault points such as abnormal temperature, sensor failure, and interface problems, reducing the need for maintenance personnel to manually troubleshoot related issues of auxiliary components, improving the completeness and efficiency of fault diagnosis, and thus enhancing the overall maintenance accuracy.

[0081] In some of the above embodiments, a method for constructing a computing board model is proposed to intuitively present the chip distribution and circuit link relationship. However, in its implementation process, the target computing board model is only generated based on preset parameters and is not dynamically associated with the actual running computing board for verification. This results in the chip positions and parameters in the model not being accurately mapped to the actual hardware, which may cause positioning deviations during fault repair, affecting the repair accuracy and efficiency.

[0082] To solve this problem, refer to Figure 8 The present invention provides a method for constructing a computing board model based on the above. Figure 1 The embodiment shown, the method for constructing the computing board model, further includes steps S1400-S1500, wherein: S1400: Obtain the actual operating parameters of the corresponding model of the actual computing board; S1500: Compare the actual operating parameters with the operating parameters in the target computing board model to determine the correspondence between each computing chip in the target computing board model and the chip in the actual computing board.

[0083] Among these steps, obtaining the actual operating parameters of the corresponding computing board model refers to collecting real-time data from the actual operating computing board. This can be achieved using sensor monitoring modules, remote monitoring interfaces, or data acquisition terminals. The purpose is to ensure the objectivity and reliability of the data source and provide a true benchmark for model verification. Comparing the actual operating parameters with the operating parameters in the target computing board model refers to analyzing the differences between the model parameters and the actual data through algorithms. This can be achieved using threshold comparison mechanisms, difference analysis engines, or dynamic calibration algorithms. The purpose is to identify potential errors or hardware state changes in the model construction and achieve real-time model calibration. Determining the correspondence between each computing chip in the target computing board model and the chips in the actual computing board refers to establishing a precise mapping between model elements and physical hardware. This can be achieved using unique identifier matching, coordinate mapping tables, or location code association. The purpose is to accurately associate the chip location during maintenance operations and improve the accuracy of fault diagnosis.

[0084] This embodiment first obtains actual operating parameters as an objective benchmark, then dynamically compares this benchmark with the model parameters to identify differences, and finally establishes a precise chip correspondence based on the comparison results, thus forming a closed-loop verification mechanism. This mechanism ensures that the target computing board model can reflect the actual hardware status in real time. When maintenance personnel operate on the visual interface, the chip positions in the model correspond one-to-one with the actual physical chips, avoiding positioning errors caused by parameter deviations. Furthermore, this mechanism is organically linked with the construction process of the computing board effect preview and interactive controls, allowing model parameter adjustments and actual hardware data verification to be carried out simultaneously, effectively solving the problem of model-to-actual hardware disconnect.

[0085] As a preferred implementation, when the computing board is in operation, the construction device obtains the real-time computing power value and temperature data of each computing chip through the monitoring interface; compares these actual operating parameters with the preset parameters stored in the target computing board model item by item; if it is found that the actual computing power value of a certain chip is consistently lower than the normal range, the construction device automatically marks the location of the chip in the model and generates maintenance instructions corresponding to the actual hardware, so that maintenance personnel can directly locate the faulty chip.

[0086] Through the above solution, this embodiment ensures the dynamic consistency between the computing board model and the actual hardware. In fault repair scenarios, repair personnel can quickly locate the fault point based on the accurate model mapping, which significantly reduces misjudgments caused by model deviation and improves repair efficiency and accuracy.

[0087] The present invention also proposes a construction apparatus, which includes: a memory, a processor, and a construction program for a computing board model stored in the memory and executable on the processor, wherein the construction program for the computing board model is configured to implement the above-described construction method for the computing board model.

[0088] It is worth noting that since the construction device of the present invention is based on the above-described construction method of the computing board model, the embodiments of the construction device of the present invention include all the technical solutions of all embodiments of the above-described construction method of the computing board model, and the technical effects achieved are exactly the same, which will not be repeated here.

[0089] The present invention also proposes a computer program product, which includes a construction apparatus as described in the above embodiments.

[0090] It is worth noting that since the computer program product of the present invention is based on the above-described construction device, the embodiments of the computer program product of the present invention include all the technical solutions of all embodiments of the above-described construction device, and the technical effects achieved are exactly the same, which will not be repeated here.

[0091] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0092] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0094] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for constructing a computing board model, characterized in that, The method for constructing the computing board model includes: Obtain the layout element information of the corresponding model of computing board; Display a preview image of the computing board effect that matches the layout element information, and there is a mapping relationship between the preview image of the computing board effect and the computing board parameter values; Determine the positions and dimensions of multiple computing chips in the preview image of the computing board effect; Draw an interactive control corresponding to the size of the computing chip at each of the aforementioned computing chip locations; Adjust the computing board parameter values ​​of the interactive control to generate the target computing board model; The method for constructing the computing board model also includes: Obtain the temperature chip parameters, sensor chip parameters, and interface circuit parameters of the corresponding computing board model; Based on the temperature chip parameters, the sensor chip parameters, and the interface circuit parameters, corresponding auxiliary component layout information is generated; The temperature chip, sensor chip, and interface circuit corresponding to the layout information of the auxiliary components are displayed on the preview image of the computing board. The corresponding interactive controls are filled in according to the first position of the temperature chip, the second position of the sensor chip, and the third position of the interface circuit, and the numbering information and warning threshold information of the interactive controls are adjusted.

2. The method for constructing the computing board model as described in claim 1, characterized in that, The step of drawing an interactive control corresponding to the size of the computing chip at each location of the computing chip includes: In response to the selection operation of the preview image of the computing board, the selected location of the computing chip is determined; Generate an interactive rectangle with dimensions matching those of the computing chip at any corner point of the location of the computing chip; The interactive control is generated by filling the corresponding location number and computing board parameter value into the interactive rectangle.

3. The method for constructing the computing board model as described in claim 2, characterized in that, The step of filling the interactive rectangle with the corresponding position number and computing board parameter value to generate the interactive control includes: Obtain the position numbers of the interactive rectangles corresponding to all computing power chips; After filling the corresponding position numbers into the interactive rectangle, the position numbers are checked for duplicate sorting. If duplicate position numbers exist, display the corresponding prompt message and highlight the interactive control for the duplicate number; If there are no duplicate location numbers, fill the computing board parameter values ​​into the corresponding interactive rectangle.

4. The method for constructing the computing board model as described in claim 1, characterized in that, The step of obtaining the layout element information of the corresponding model of computing board includes: In response to the model selection operation for the computing board, the configuration of the selected computing board model is imported. The computing board configuration includes the substrate shape parameters, computing chip parameters, interface positions and power supply positions. The layout element information is generated based on the substrate shape parameters, the computing chip parameters, the interface location, and the power supply location.

5. The method for constructing the computing board model as described in claim 1, characterized in that, The method for constructing the computing board model further includes: Obtain the actual operating parameters of the corresponding model of the actual computing board; The actual operating parameters are compared with the operating parameters in the target computing board model to determine the correspondence between each computing chip in the target computing board model and the chip in the actual computing board.

6. A construction apparatus, characterized in that, The construction apparatus includes: a memory, a processor, and a construction program for a computing board model stored in the memory and executable on the processor, the computing board model construction program being configured to implement the construction method of the computing board model as described in any one of claims 1 to 8.

7. A computer program product, characterized in that, Includes the construction apparatus as described in claim 9.

Images