Methods, apparatus, equipment and media for cross-chip clock detection during chip prototype verification

Abstract

This invention discloses a method, apparatus, device, and medium for cross-chip clock detection during chip prototype verification, relating to the field of chip design technology. The method includes: acquiring clock segmentation information generated after segmentation of various field-programmable gate arrays (FPGAs) during chip prototype verification design; determining the port interconnection relationships of the segmented cross-chip clock signals in the corresponding netlists of each FPGA based on the clock segmentation information; determining the cross-chip path traversed by the cross-chip clock signals in the netlist based on the port interconnection relationships; judging the rationality of the cross-chip behavior corresponding to the cross-chip clock signals based on whether the cross-chip path meets preset reasonableness conditions for cross-chip behavior, thereby obtaining a rationality judgment result; and outputting a detection report containing the cross-chip path of the cross-chip clock signals and the rationality judgment result. This achieves rapid and accurate detection of the rationality of the cross-chip behavior of the segmented clocks.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method, apparatus, equipment and medium for cross-chip clock detection in the chip prototype verification process. Background Technology

[0002] As chip design scales up, single-chip FPGAs (Field Programmable Gate Arrays) can no longer meet the resource requirements for prototyping verification, making multi-FPGA verification platforms the mainstream. One of the key technologies of multi-FPGA verification platforms is design partitioning, which involves using EDA (Electronic Design Automation) tools to partition large-scale chip designs across multiple FPGAs.

[0003] During the partitioning process, the processing of clock signals directly affects the performance of the prototype verification system. To achieve clock synchronization among multiple FPGAs, existing technologies typically require that the same clock be transferred across FPGAs at most once. If a transfer is necessary, a new clock should be generated by the Digital Clock Manager (DCM) after the transfer before subsequent transfers are made. This is to avoid introducing additional interconnection delays due to multiple clock transfers, which would reduce the system operating frequency.

[0004] However, existing partitioning tools only output a list of port interconnections for clock signals, making it impossible to intuitively determine whether there are abnormal cross-chip issues (the same clock continuously spanning multiple FPGAs) in the partitioned clock. Designers can only manually check the cross-chip status of each clock by tracing the clock path one by one in the schematic based on the partitioned netlist. When the clock tree structure is complex and there are many partitioned clocks, this process is tedious and time-consuming, severely reducing the design efficiency of prototype verification.

[0005] It is evident that how to quickly and accurately detect whether the cross-chip behavior of the segmented clock is reasonable during the chip prototype verification segmentation process is a technical problem that needs to be solved in this field. Summary of the Invention

[0006] The purpose of this invention is to provide a method, apparatus, device, and medium for cross-chip clock detection during chip prototype verification, which can quickly and accurately detect whether the cross-chip behavior of the divided clock is reasonable during the chip prototype verification segmentation process.

[0007] To address the aforementioned technical problems, embodiments of the present invention provide a method for cross-chip clock detection during chip prototype verification, comprising: Obtain clock segmentation information generated after segmentation of various field-programmable gate arrays during the chip prototype verification design process; Determine the port interconnection relationship of the segmented cross-chip clock signal in the corresponding netlist of each field programmable gate array based on the clock segmentation information; Determine the cross-chip path of the cross-chip clock signal based on the port interconnection relationship in the netlist; Based on whether the cross-chip path meets the preset reasonable conditions for cross-chip behavior, the reasonableness of the cross-chip behavior corresponding to the cross-chip clock signal is determined to obtain the reasonableness judgment result. The preset reasonable conditions for cross-chip behavior are: if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit, it is determined to be an unreasonable cross-chip; if the same cross-chip clock signal in the cross-chip path passes through the clock management unit after crossing the field programmable gate array once, it is determined to be a reasonable cross-chip. Output a test report containing the cross-chip clock signal cross-chip path and the rationality judgment results.

[0008] Optionally, obtain clock segmentation information generated after segmentation of each field-programmable gate array during the chip prototype verification design process, including: Obtain the clock segmentation report output after segmenting each field-programmable gate array during the prototype verification design process using the segmentation tool, and use it as clock segmentation information; Accordingly, based on the clock segmentation information, the port interconnection relationships of the segmented cross-chip clock signals in the corresponding netlists of each field-programmable gate array are determined, including: Parse the report structure of the clock segmentation report to find the clock segmentation information fields; Extract the interconnection relationship between the segmented cross-chip clock signals and each field programmable gate array from the clock segmentation information field to determine the port interconnection relationship of the cross-chip clock signals in the corresponding netlist of each field programmable gate array.

[0009] Optionally, the cross-chip path of the cross-chip clock signal is determined in the netlist based on port interconnection relationships, including: Starting from the input port of the cross-chip clock signal in the port interconnection relationship, search the netlist for the nets connected to the input port in sequence; Locate the connected logic cell instance along the wire mesh and trace the output wire mesh of the logic cell instance until the output port of the cross-chip clock signal is reached; Record nets and logic cell instances to generate cross-chip paths for cross-chip clock signals.

[0010] Optionally, logic unit instances include any one or more of the following: input buffer, output buffer, global clock buffer, gated clock buffer, differential input buffer, differential output buffer, clock control unit, latch control unit, and lookup table.

[0011] Optionally, based on whether the cross-chip path meets the preset reasonable conditions for cross-chip behavior, the reasonableness of the cross-chip behavior corresponding to the cross-chip clock signal is determined to obtain a reasonableness judgment result, including: If the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit when it crosses two or more field programmable gate arrays in succession, it is judged as an unreasonable cross-chip, so as to obtain an unreasonable cross-chip result. If the same cross-chip clock signal in the cross-chip path passes through the clock management unit and generates a new cross-chip clock signal every time it crosses the field programmable gate array, it is determined to be a reasonable cross-chip, thus obtaining a reasonable cross-chip result.

[0012] Optionally, cross-chip clock detection methods during chip prototype verification also include: Obtain the clock constraint file for the chip prototype verification design; The name information of the clock management unit used to generate new cross-chip clock signals is determined based on the clock constraint file.

[0013] Optionally, the output includes a test report containing the cross-chip clock signal cross-chip path and the rationality judgment result, including: Output a test report containing the names of the nets traversed by the cross-chip clock signal, the names of the logic cell instances traversed, the cross-chip level of the cross-chip clock signal, and a reasonableness judgment result including reasonable or unreasonable cross-chip results.

[0014] Secondly, the present invention provides a cross-chip clock detection device in the chip prototype verification process, comprising: The information acquisition module is used to acquire clock segmentation information generated after segmentation of various field-programmable gate arrays during the chip prototype verification design process; The interconnection information determination module is used to determine the port interconnection relationship of the segmented cross-chip clock signals in the corresponding netlists of each field-programmable gate array based on the clock segmentation information; The path determination module is used to determine the cross-chip path through which the cross-chip clock signal passes in the netlist based on the port interconnection relationship; The reasonableness judgment module is used to determine whether the cross-chip behavior corresponding to the cross-chip clock signal is reasonable based on whether the cross-chip path meets the preset reasonableness conditions for cross-chip behavior, so as to obtain a reasonableness judgment result. The preset reasonableness conditions for cross-chip behavior are: if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit, it is judged as unreasonable cross-chip; if the same cross-chip clock signal in the cross-chip path passes through the clock management unit after crossing the field programmable gate array once, it is judged as reasonable cross-chip. The report output module is used to output a test report containing the cross-chip clock signal, the cross-chip path, and the rationality judgment results.

[0015] Thirdly, the present invention provides an electronic device, comprising: Memory, used to store computer programs; A processor for executing computer programs to implement the steps of the cross-chip clock detection method in the chip prototyping process disclosed above.

[0016] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the cross-chip clock detection method in the chip prototype verification process disclosed above.

[0017] This invention provides a method for acquiring clock segmentation information generated after segmentation of various field-programmable gate arrays (FPGAs) during chip prototype verification design; determining the port interconnection relationships of the segmented cross-chip clock signals in the corresponding netlists of each FPGA based on the clock segmentation information; determining the cross-chip path traversed by the cross-chip clock signals in the netlist based on the port interconnection relationships; judging whether the cross-chip behavior corresponding to the cross-chip clock signals is reasonable based on whether the cross-chip path meets preset reasonable cross-chip behavior conditions, thereby obtaining a reasonableness judgment result; wherein, the preset reasonable cross-chip behavior conditions are: if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit, it is judged as unreasonable cross-chip; if the same cross-chip clock signal in the cross-chip path passes through the clock management unit after crossing the FPGA once, it is judged as reasonable cross-chip; and outputting a detection report containing the cross-chip clock signals, the cross-chip path, and the reasonableness judgment result.

[0018] As can be seen from the above technical solution, by acquiring clock segmentation information, determining port interconnection relationships, automatically tracing cross-chip paths in the netlist, and automatically judging the rationality of cross-chip behavior based on the preset condition that the same clock can only cross chips once, automated detection of cross-chip clocks is achieved. This avoids the tedious method of manually tracing clock paths step by step in the schematic diagram, significantly improving detection efficiency, reducing the risk of human error, and enabling the rapid discovery of unreasonable clock cross-chip issues in the early stages of prototype verification design, reducing the number of design iterations, and ensuring the performance and reliability of the prototype verification system. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating a general prototype verification design process method provided for embodiments of the present invention; Figure 2This invention provides a schematic diagram of interconnect signal allocation after a netlist is segmented and laid out, with the boundary cut. Figure 3 This invention provides a diagram illustrating six common clock cross-chip scenarios. Figure 4 A flowchart of a cross-chip clock detection method in a chip prototype verification process provided by an embodiment of the present invention; Figure 5 A flowchart illustrating a cross-chip clock detection method during a specific chip prototype verification process, as provided in this embodiment of the invention; Figure 6 This invention provides a flowchart of normal clock cross-chip segmentation under a scenario-two netlist structure. Figure 7 A flowchart for abnormal clock cross-chip segmentation under a scenario six-netlist structure is provided in an embodiment of the present invention; Figure 8 A schematic diagram of a cross-chip clock detection device in the chip prototype verification process provided by an embodiment of the present invention; Figure 9 This is a diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0022] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0023] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] As semiconductor processes advance to 5 nanometers and below, the complexity and cost of chip design have reached unprecedented levels. A single high-performance computing chip can integrate tens of billions of transistors, encompassing diverse technologies such as heterogeneous computing units, high-speed interconnects, and advanced packaging, posing a severe challenge to traditional verification methods. On the one hand, software simulation is slow (typically only at the Hz-KHz level), requiring months to verify ultra-large-scale designs, making it difficult to meet the demands of rapid iteration; on the other hand, the cost of a single tape-out is skyrocketing, and any design flaw can lead to huge losses. Against this backdrop, chip prototype verification has become the core bridge connecting design simulation and physical tape-out, aiming to simulate the behavior of real chips through hardware or virtualization platforms to achieve three main goals: functional correctness verification, performance evaluation, and hardware-software co-development, thereby significantly reducing tape-out risks and shortening product launch cycles.

[0025] FPGA prototyping has become the mainstream and mature verification method for chip prototyping. It verifies chip functionality by porting RTL (Register Transfer Level) circuitry to an FPGA. Once the basic functionality of the chip is verified, driver development can begin and continue until the chip design is completed and the chip is delivered to the FPGA. After the chip is delivered, applications can be directly applied to the chip with simple adaptations to the FPGA version of the driver. More importantly, FPGA prototyping is several orders of magnitude faster than EDA verification. Among these advantages, "pre-tape-out hardware and software co-development" is the most irreplaceable aspect of FPGA prototyping. In today's era of deep hardware and software customization and the requirement for one-stop delivery from chip to application, the importance of FPGA prototyping platforms has been greatly enhanced.

[0026] Currently, ASIC (Application Specific Integrated Circuit) designs are becoming increasingly large-scale and complex. A single FPGA can no longer meet the resource requirements for prototyping verification, leading to the emergence of multi-FPGA verification platform technology. A key technology involved in multi-FPGA verification platform technology is RTL-level or netlist-level partitioning of the design. Chip prototyping verification partitioning is a crucial step in the chip design flow, primarily used to partition large-scale chip designs into modules suitable for verification on FPGAs or dedicated prototyping platforms. The main challenges include I / O (Input / Output) pin limitations, reliance on high-speed SerDes, cross-FPGA timing violations, clock synchronization issues, and debugging complexity.

[0027] A common prototyping and design process is as follows: Figure 1 As shown, in Figure 1The seven steps can be roughly divided into four stages. In the first stage, steps ①-②, the synthesis EDA tool completes the input of RTL source files, synthesis of the design, and output of the netlist file EDF (European Data Format). In the second stage, steps ③-⑤, the design is constrained and input, mainly involving the utilization of resources such as logic units (LUTs), memory (BRAM), and DSPs on each FPGA; the allocation of interconnect width and location between FPGA chips; the replication of the clock tree in the design; and the allocation and placement of modules and I / O in the design. The partitioning EDA tool completes the pre-partition, partitioning, and system routing of the design. In the implementation of this step, advanced partitioning technology and optimized and reliable timing convergence technology between multiple FPGAs are applied, which is a key step in the entire prototype verification design. In step 6 of the third stage, the netlist file generated in the first stage is imported into Vivado to complete the design implementation, which mainly includes placement, routing, timing optimization, and generating download files. In step 7 of the fourth stage, in the EDA tool that interacts with the prototype verification hardware platform, an adapter file related to the prototype verification hardware platform is generated in combination with the relevant constraints from the previous stage. This adapter file is used for configuring the prototype verification hardware platform, downloading the design bit file, and debugging the design functions.

[0028] Chip prototyping is a process of continuous trial and iteration to achieve optimal results. The second stage of chip prototyping, the partitioning step, is particularly important in ensuring the accuracy and optimality of the netlist partitioning. Specifically, it's crucial to determine whether the partitioned netlist, after being stitched together with the cut edges, can accurately and completely reconstruct the original netlist and its timing requirements, and whether the performance of the partitioned design can reach its best. To achieve clock synchronization between multiple FPGAs and address the delays and timing constraints introduced by external interconnects for cross-FPGA signals, most prototyping vendors currently offer the following solution: each FPGA is configured with the same global clock source, also known as global clock network replication. This avoids clock transfer across FPGAs. For clocks that must cross FPGAs, the clock transfer from the source clock to the destination clock should not exceed one cross-FPGA step, and the source and destination clocks must be placed on the FPGA's global clock network for global clock tree reconstruction, thereby reducing clock delay, jitter, and skew. Other ordinary signals (including reset signals) utilize the FPGA's built-in high-speed SerDes (serial-to-parallel and parallel-to-serial) and TDM (time-division multiplexing) to ensure signal integrity and timing compliance with design requirements. (See design concept below.) Figure 2 ,exist Figure 2In this scenario, a netlist of a design is partitioned and deployed across two FPGAs. The interconnect signals at the partition boundaries are then distributed across both FPGAs. These include clock signals and other signals besides the clock (including reset signals, collectively referred to as data signals). Since the number of pins required for these interconnect signals exceeds the available I / O on the FPGA, this can lead to congestion and bottlenecks in the interconnect network. Therefore, when the number of partition boundaries, i.e., the number of interconnect signals, exceeds the maximum number of I / O supported by the FPGA, TDM (Telematics Multiplexing) technology must be used to address this issue. (See above.) Figure 2 In this process, the data signal utilizes the FPGA's built-in high-speed SerDes and registers to achieve high-speed serial-to-parallel (S2P) and parallel-to-serial (P2S) conversion, significantly reducing hardware I / O usage while meeting the overall timing requirements of the design. Similarly, the slow_clk clock signal path is also segmented, and the clock signal cannot cross the chip more than once from the source clock to the destination clock. This requirement is to minimize the performance degradation of the prototype verification system caused by multiple clock crossings, i.e., the system's maximum operating frequency. Common clock crossing scenarios include... Figure 3 As shown, there are the following 6 types, in Figure 3 Of the six common clock cross-chip scenarios listed, scenarios one, two, and four are normal clock cross-chip partitioning, where these clocks (including clocks newly generated by the DCM module) cross chip at most once. However, scenarios three, five, and six are abnormal clock cross-chip partitioning because in these three scenarios, a certain clock crosses chip more than or twice. Such clock partitioning schemes will seriously affect the design performance of the entire prototype verification.

[0029] Generally, after completing the segmentation process, the EDA provided by various prototyping vendors outputs a report to the user detailing the clock signal segmentation, based on a custom rule. This clock segmentation information shows the port interconnections between the segmented clock signals. As a prototyping designer, to ensure errors are detected early in the prototyping design process and to improve efficiency, checking for abnormal cross-chip situations in the segmented clock signals is a crucial checkpoint. However, existing prototyping vendors only provide a list of port interconnections after clock signal segmentation, making it impossible to quickly and intuitively view the cross-chip situation. Instead, one must check the interconnections one by one in the schematic corresponding to the segmented netlist, starting from each top-level clock or its derived clock, following the path of the segmented clock signal to the leaf node of that clock, examining the cross-chip situations traversed by each top-level clock or its derived clock. If these cross-chip situations are normal, the design continues; otherwise, the design constraints must be revised. This process is not technically complex but rather tedious. If the clock tree structure of a design is complex and there are many segmented clock signals, this process becomes a labor-intensive and time-consuming task, thereby reducing the design efficiency of prototype verification.

[0030] Therefore, in the segmentation process of prototype verification development, the speed of checking whether the split clock segments in the design are reasonable should be accelerated to improve the design efficiency of prototype verification.

[0031] like Figure 4 As shown, this invention provides a cross-chip clock detection method during chip prototype verification, comprising: Step S11: Obtain the clock segmentation information generated after segmentation of each field-programmable gate array during the chip prototype verification design process.

[0032] This embodiment starts with the netlist of the segmented design in prototype verification, focusing on the analysis of the segmented clock paths. It proposes the analysis principle, inspection method, and automatic control process for the cross-chip nature of segmented clocks in prototype verification. The specific implementation process is as follows: Figure 5As shown: First, the design undergoes RTL input and syntax checking; then, design synthesis and netlist export are performed using synthesis tools such as Vivado and Synplify; the synthesized netlist is exported as an EDF file. EDF is a text-based general-purpose hardware description format used to transfer design netlists (logic connections, component instantiations, constraints, etc.) between EDA tools. Its syntax adopts a Lisp-like S-Expression (symbolic expression) structure with strict hierarchical nesting rules, which will not be described in detail here. Basic elements of an EDF file include libraries, cells, instances, nets, ports, etc. A library defines a logic unit (Xilinx primitives: LUT, FDCE, LDCE, RAMB36E1, etc.); a cell describes the function of a specific component, potentially including ports and internal logic; an instance instantiates a component, such as calling the same LUT multiple times in the design; and a net describes the connection relationships of signal lines, connecting the ports of the instance.

[0033] In this embodiment, the clock segmentation report output after segmenting each Field-Programmable Gate Array (FPGA) during the prototype verification design process using a segmentation tool is obtained as clock segmentation information. It can be understood that after the multi-FPGA segmentation process for chip prototype verification is completed, the segmentation EDA tool (such as a dedicated segmentation tool provided by various prototype verification vendors) will output a clock segmentation report as clock segmentation information according to its internal algorithm and user-defined segmentation constraints. Specifically, as shown... Figure 5 As shown, after exporting the netlist, the cross-chip clock signals in the netlist are segmented to obtain clock segmentation information. First, the netlist is segmented according to the provided segmentation constraints. Netlist segmentation is performed in the segmentation EDA tools of various prototype verification vendors. The constraints of netlist segmentation mainly include the reconstruction and constraints of the design clock tree, the setting of the number and location of interconnects, the limitation of FPGA resource utilization (LUT, FF, BRAM resources), and the layout and distribution settings of design modules. Finally, a clock segmentation report is output after the segmentation is completed.

[0034] Step S12: Determine the port interconnection relationship of the segmented cross-chip clock signal in the corresponding netlist of each field programmable gate array based on the clock segmentation information.

[0035] In this embodiment, the report structure of the clock segmentation report is parsed to locate the clock segmentation information field; the interconnection relationship between the segmented cross-chip clock signals and each field-programmable gate array (FPGA) is extracted from the clock segmentation information field to determine the port interconnection relationship of the cross-chip clock signals in the corresponding netlists of each FPGA. For example... Figure 5As shown, after completing the comprehensive netlist partitioning, the report generation interface of the partitioning tool is called or its output report file is read. The report is presented in text form, and its structure is related to the specific manufacturer, but it contains the port interconnection relationship of the partitioned clock signals between the FPGAs. The clock partitioning report is parsed, and the correspondence between the source FPGA output port and the target FPGA input port of each pair of cross-chip clocks is extracted based on the key fields of the report (such as "Clock Partition", "Cross-FPGA Connection", "Source Port", "Destination Port").

[0036] For example, the segmentation tool report will list the following information: clock signal name: clk_a, source FPGA: FPGA_A, source port: port_a_out, target FPGA: FPGA_B, target port: port_b_in. By reading and structuring the above information one by one, the complete clock segmentation information can be obtained.

[0037] Furthermore, the port interconnection relationship at the port level refers to the relationship between the clock signal output port of one FPGA and the input port of another FPGA. Based on the information listed in the segmentation tool report, the port interconnection relationship is port_a_out → port_b_in. Since each FPGA corresponds to a netlist file, the port interconnection relationship essentially describes the connection points for signal transmission between different netlists. That is, in netlist A, the clock signal is output through port_a_out, and in netlist B, the clock signal is input through port_b_in. These two ports are physically connected and logically transmit the same clock signal. Therefore, in this invention, the port interconnection relationship specifically refers to the signal transmission correspondence established between different FPGA netlists through input / output ports.

[0038] Step S13: Determine the cross-chip path through which the cross-chip clock signal passes in the netlist based on the port interconnection relationship.

[0039] In this embodiment, the input port of the cross-chip clock signal in the port interconnection relationship is used as the starting point of the path. The netlist sequentially searches for the nets connected to the input port; the connected logic cell instances are searched along the nets, and the output nets of the logic cell instances are traced until the output port of the cross-chip clock signal is reached; the nets and logic cell instances are recorded to generate the cross-chip path of the cross-chip clock signal. It can be understood that the input port of the cross-chip clock signal in the port interconnection relationship is used as the starting point for path tracing. For example, if the clock splitting report records that a clock signal connects from the output port port_a_out of FPGA A to the input port port_b_in of FPGA B, then in the netlist file corresponding to FPGA B, port_b_in is used as the starting point of the path for that clock signal in the current netlist. In the netlist file, the input port is usually directly connected to a net. By parsing the connection description of the netlist, the net with that input port as the connection end is found and recorded as the current net. For example, in Figure 6In this example, port_b_in is connected to net ⑥. The other end of the net is connected to the input pin of a logic unit instance. Based on the instantiation information in the netlist, the logic unit instance connected to the net is located. Logic unit instances include input buffers, output buffers, global clock buffers, gated clock buffers, differential input buffers, differential output buffers, clock control units, latch control units, and any one or more of the following from lookup tables: input buffer (IBUF), global clock buffer (BUFG / BUFGCE), register (FDCE), latch (LDCE), lookup table (LUT), output buffer (OBUF), etc. For example, net ⑥ is connected to the I terminal of instance ibuf_inst_1. The net connected to the output pin of the current logic unit instance is obtained. If the logic unit instance has multiple outputs, the correct output pin (usually the O terminal or Q terminal) is selected according to the propagation direction of the clock signal. For example, the O terminal of instance ibuf_inst_1 is connected to net ⑦. Using the output net obtained in the previous step as the new current net, the steps of "finding the logic cell instance connected to the net → tracing from the instance to its output net" are repeated until the output port of the current FPGA netlist is reached. The condition for reaching the output port is: the current net is connected to the I-pin of an output buffer instance (e.g., OBUF), and the O-pin of the output buffer is connected to the output port of the netlist (e.g., port_b_out). At this time, the output port is the exit point for the clock signal leaving the current FPGA. During each tracing step, the net name and logic cell instance name traversed are recorded sequentially to form an ordered path sequence. This sequence constitutes the cross-chip path of the cross-chip clock signal within the current FPGA. For example, a complete cross-chip path can be represented as: port_b_in → net ⑥ → ibuf_inst_1 → net ⑦ → bufgce_inst_3 → net ⑧ → ... → obuf_inst_2 → port_b_out. When the same clock signal needs to cross multiple FPGAs, the above tracing process is performed on the netlist of each FPGA in sequence, and the beginning and end of each path are connected to obtain the complete cross-chip path from the source FPGA to the target FPGA.

[0040] It's important to note that in actual netlists, some logic cells (such as BUFGCE) may be optimized away due to their small fan-out. In such cases, if the expected cell cannot be found, skip that cell and directly search for its downstream connected logic cell or net, without affecting the continuity of path tracing. Using this automated tracing method, the complete transmission path of each cross-chip clock signal can be extracted from the netlist without manual intervention.

[0041] In this embodiment, determining the cross-chip path of the cross-chip clock signal in the netlist includes: modeling the netlist as a directed graph, where the nodes of the directed graph include the input pins, output pins, and nets of logic unit instances, and the edges of the directed graph represent the connection relationship between pins and nets; starting from the node corresponding to the input port of the cross-chip clock signal, traversing the directed graph using a depth-first search or breadth-first search algorithm until reaching the node corresponding to the output port of the cross-chip clock signal; and recording the sequence of nodes traversed in the traversal path as the cross-chip path of the cross-chip clock signal. It can be understood that, in order to efficiently and accurately extract the complete transmission path of the cross-chip clock signal from the netlist, this embodiment provides an automatic path tracing method based on graph search. First, the netlists corresponding to each FPGA after segmentation are converted into a directed graph structure. Specifically, the input pins and output pins of each logic unit instance (e.g., IBUF, BUFG, DCM, FDCE, OBUF, etc.) in the netlist are used as nodes of the graph, and the nets connecting the pins are used as edges of the graph, with the direction of the edges determined by the signal transmission direction (i.e., from the output pin to the input pin). For example, in an IBUF instance, the I-end is an input node and the O-end is an output node. A wire connects the O-end to the I-end of the next instance, forming a directed edge. Next, the node corresponding to the cross-chip clock signal input port determined in the port interconnection relationship is used as the starting point for the search. For example, if the clock signal enters the input port port_b_in of FPGA_B from FPGA_A, the node corresponding to port_b_in is found in the directed graph of FPGA_B. Then, a depth-first search (DFS) or breadth-first search (BFS) algorithm is used to traverse the directed graph. The algorithm starts from the starting point and visits subsequent nodes along the directed edges until it reaches the output port node of the FPGA (e.g., port_b_out). Branch paths are automatically handled during the search. If multiple branches are encountered (i.e., the clock signal fans out to multiple downstream nodes), each branch path is recorded, and the design can choose to trace all paths or only the main path according to the design requirements. Finally, the node sequence obtained from the search (including the pin nodes and wire nodes traversed) is recorded in the order of access, thus generating the complete cross-chip path of the cross-chip clock signal within the current FPGA.

[0042] For clocks spanning multiple FPGAs, the above search is performed sequentially on the directed graphs of each FPGA, and the beginning and end of each path segment are concatenated. Compared to the previous sequential step-by-step search method, the graph search algorithm can automatically handle complex branch and loop structures, avoiding manual intervention and improving the reliability and efficiency of path tracing. It is suitable for large-scale designs with complex clock tree structures and numerous branches, and can automatically handle signal fan-out branches and irregular connections in the netlist, avoiding omissions or duplications, and improving the accuracy of path generation. At the same time, the time complexity of the graph search algorithm is significantly reduced, enabling rapid path extraction from large-scale netlists.

[0043] Step S14: Determine whether the cross-chip behavior corresponding to the cross-chip clock signal is reasonable based on whether the cross-chip path meets the preset reasonable cross-chip behavior conditions, so as to obtain the reasonableness judgment result; wherein, the preset reasonable cross-chip behavior conditions are: if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit, it is determined to be unreasonable cross-chip; if the same cross-chip clock signal in the cross-chip path passes through the clock management unit after crossing the field programmable gate array once, it is determined to be reasonable cross-chip.

[0044] In this embodiment, a clock constraint file for the chip prototype verification design is obtained; based on the clock constraint file, the name information of the clock management unit used to generate new cross-chip clock signals is determined. It can be understood that in the chip prototype verification design process, a clock constraint file is typically provided during the synthesis or partitioning stage. This file defines information such as clock sources, clock cycles, clock relationships, and clock generation logic in the design. This step obtains the clock constraint file from the design environment as input. The clock constraint file contains instantiation information of clock management units (e.g., DCM, PLL, MMCM, etc.) used to generate derived clocks. Therefore, by parsing the constraint statements in the constraint file, or by directly searching for timing constraints related to the clock management unit, the instance name of the clock management unit, the input clock source of the clock management unit, the derived clock name output by the clock management unit, and the division / multiplication parameters can be extracted. Therefore, the parsed clock management unit instance names and corresponding input and output clock information are structured and stored to form a clock management unit name information database. This database is used to quickly determine whether a logic unit instance is a clock management unit and to identify the new cross-chip clock signals it generates during subsequent netlist path tracing.

[0045] In this embodiment, if the same cross-chip clock signal in the cross-chip path passes through the clock management unit and generates a new cross-chip clock signal every time it crosses the field-programmable gate array (FPGA), it is determined to be a reasonable cross-chip, thus obtaining a reasonable cross-chip result. It can be understood that when tracing the cross-chip path using the aforementioned method, if the same cross-chip clock signal in the cross-chip path encounters a logic unit instance every time it crosses the FPGA, its name is matched with a record in the clock management unit name information database. If the match is successful, the current instance is determined to be the clock management unit, and the clock signal generates a new derived clock at this point, thus obtaining a reasonable cross-chip result; if the match fails, it continues to be processed as a regular logic unit. For example... Figure 6As shown, one of its clock paths is clk_p (clk_n) → port_a_out → port_b_in → port_b_out → port_a_in. This clock path is both an input and an output in netlist B, but it passes through DCM in the netlist, generating a new derived clock. Therefore, each clock in this clock path only crosses the chip once, thus it is a reasonable cross-chip clock. Specifically, Figure 6 In the design, a top-level clock is split and moved from netlist A to netlist B. Then, its derived clock is generated from netlist B via a DCM (Distributed Clock Management) and moved back to netlist A. A top-level clock output from netlist A continuously moves across netlists B and C without a DCM. After clarifying the interconnections between the inputs and outputs of the netlists, the cross-chip analysis method for split clocks is introduced. Figure 6 In the process, a clock signal is split at port_a_out and port_b_in. The clock network path in netlist A is not important because it belongs to the internal clock of the FPGA. The clock signal enters netlist B through port_b_in. Netlist B searches for netnet ⑥, which connects port_b_in to the I-pin of instance ibuf_inst_1. Then it searches for instance ibuf_inst_1, whose O-pin is connected to one end of netnet ⑦, and the other end of netnet ⑦ is connected to the I-pin of instance bufgce_inst_3. Next, it searches for instance bufgce_inst_3, whose O-pin is connected to one end of netnet ⑦. The next search strategy depends on the case: (1) There is no DCM module and gated clock in the split clock path. In this scenario, the I terminal of instance bufgce_inst_4 can be found at the other end of wire ⑦.

[0046] (2) There is no gated clock in the DCM module in the segmented clock path. In this scenario, the instance name of the clock generation unit can be determined by referring to the clock constraints of the design. The I and O terminals of instance bufgce_inst_3 can be found through net ⑦. Next, net ⑧ will be found. The I terminal of instance bufgce_inst_4 can be found through the other end of net ⑧.

[0047] (3) The divided clock path contains both DCM modules and gated clocks. Similar to the above, it passes through net ⑦, the I and O terminals of instance bufgce_inst_3, net ⑧, the C and Q terminals of fdce_inst, net ⑨, the D and Q terminals of ldce_inst, the IO terminals of lut_inst, net ⑩, and finally finds the I terminal of instance bufgce_inst_4.

[0048] In the three scenarios described above, after the clock signal arrives at the I-pin of instance bufgce_inst_4, it sequentially passes through the O-pin and the wire mesh of instance bufgce_inst_4. The I and O ports of instance obuf_inst_2 are then input into netlist A, and finally sent to its downstream logic via the I and O ports of instance ibuf_inst_2 again. Furthermore, some BUFGCE cells may not exist in the netlist. This is related to the size of their fan-out and the load behind them. If a BUFGCE cell cannot be found in the netlist, this is normal; simply skip that cell and search for its downstream cells.

[0049] In this embodiment, if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit during the continuous crossing of two or more field-programmable gate arrays, it is determined to be an unreasonable cross-chip crossing, thus obtaining an unreasonable cross-chip crossing result; it can be understood that after obtaining the interconnection relationship between the clock segmentation ports, for example... Figure 7 A design is distributed across three FPGAs, with corresponding netlists A, B, and C. One clock path is clk_p (clk_n) → port_a_out → port_b_in → port_b_out → port_c_in. Based on the analysis principles and checking methods for cross-chip clocks, the logic cell instances traversed by this clock path can be reproduced netlist by netlist. Since this clock path is both an input and an output in netlist B, its behavior in netlist B is the focus of the investigation. The investigation reveals that it does not pass through the DCM in netlist B, meaning it does not generate a new derived clock. Therefore, this clock is passed through netlist B to netlist C, making it an unreasonable cross-chip clock. Specifically... Figure 7 The method for finding the split clock path in the netlist is the same as described above. Figure 6 The method described in the text is similar. Figure 7 and Figure 6 The difference lies in the fact that after the split clock is output from port_a_out of netlist A, it passes through netlist B and netlist C sequentially without any DCM modules appearing in the subsequent clock path. This clock splitting method significantly reduces the design performance of the entire prototype verification system, i.e., it reduces the maximum operating frequency of the prototype verification system. This is because the multiple cross-chip transitions of the split clock introduce unnecessary delays in the interconnects between FPGAs, such as... Figure 7 The wire meshes ⑥ and ⑨ in the diagram. Because... Figure 6 A new clock was derived from netlist B, so Figure 6 The clocks in the chip only crossed over once, while Figure 7There are no new derived clocks, and the same clock is used twice across different chips, which is not allowed in chip prototyping. Therefore, the standard for judging whether split clock crossings are normal is that the same clock should cross chips at most once. Figure 6 The split clock and its derived new clock both span across chips once, thus it is a reasonable clock splitting method. Figure 7 The same clock was transmitted between more than two FPGAs, which is an unreasonable clock splitting method. This method, which allows for rapid identification of clock splitting risks in the early stages of prototype verification by analyzing the netlists corresponding to each FPGA after splitting, significantly saves manual verification time and improves prototype verification efficiency. It also verifies whether the prototype verification vendor's splitting algorithm has any vulnerabilities and informs them of necessary improvements.

[0050] Step S15: Output a test report containing the cross-chip clock signal, the cross-chip path, and the rationality judgment result.

[0051] In this embodiment, the output includes a detection report showing the names of the nets traversed by the cross-chip clock path containing the cross-chip clock signal, the names of the logic cell instances traversed, the cross-chip level of the cross-chip clock signal, and a reasonableness judgment result including reasonable or unreasonable cross-chip results. It is understood that after the above reasonableness detection, these clock path cross-chip check results will be automatically fed back to the user in the form of a report, specifically including the cross-chip clock path and the cross-chip level. Furthermore, this invention also supports checking user-specified segmented clock signal paths, and the check results can also be automatically fed back, which will not be elaborated here.

[0052] It is important to note that after outputting the report, it is necessary to identify any unreasonable cross-chip clocks during the prototype verification design process. If no unreasonable cross-chip clocks exist, the subsequent FPGA placement and routing can continue. If they do exist, the constraints in the netlist partitioning constraints, such as the design module layout and distribution, the number of interconnects between FPGA chips, and the FPGA resource utilization limit, need to be updated and the netlist partitioning re-partitioned until there are no unreasonable cross-chip clocks.

[0053] As can be seen from the above technical solution, by acquiring clock segmentation information, determining port interconnection relationships, automatically tracing cross-chip paths in the netlist, and automatically judging the rationality of cross-chip behavior based on the preset condition that the same clock can only cross chips once, automated detection of cross-chip clocks is achieved. This avoids the tedious method of manually tracing clock paths step by step in the schematic diagram, significantly improving detection efficiency, reducing the risk of human error, and enabling the rapid discovery of unreasonable clock cross-chip issues in the early stages of prototype verification design, reducing the number of design iterations, and ensuring the performance and reliability of the prototype verification system.

[0054] like Figure 8As shown, the present invention also discloses a cross-chip clock detection device in the chip prototype verification process, comprising: Information acquisition module 11 is used to acquire clock segmentation information generated after segmentation of each field-programmable gate array during the chip prototype verification design process; Interconnection information determination module 12 is used to determine the port interconnection relationship of the segmented cross-chip clock signal in the corresponding netlist of each field programmable gate array according to the clock segmentation information; The path determination module 13 is used to determine the cross-chip path through which the cross-chip clock signal passes in the netlist based on the port interconnection relationship; The reasonableness judgment module 14 is used to determine whether the cross-chip behavior corresponding to the cross-chip clock signal is reasonable based on whether the cross-chip path meets the preset reasonableness conditions for cross-chip behavior, so as to obtain a reasonableness judgment result; wherein, the preset reasonableness conditions for cross-chip behavior are: if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit, it is judged as unreasonable cross-chip; if the same cross-chip clock signal in the cross-chip path passes through the clock management unit after crossing the field programmable gate array once, it is judged as reasonable cross-chip. The report output module 15 is used to output a test report containing the cross-chip clock signal, the cross-chip path and the rationality judgment result.

[0055] Therefore, after the chip prototype verification design partitioning process is completed, starting from the netlist of the partitioned design in the prototype verification, focusing on the analysis of the partitioned clock paths, and based on the analysis principle of partitioned clock cross-chip proposed in this invention, an automatic control process for acquiring partitioned clock information and checking for partitioned clock cross-chip in prototype verification is realized. In the early stage of prototype verification, by using the netlist corresponding to each FPGA after partitioning, the risk of unreasonable cross-chip splitting of the partitioned clock can be quickly checked, which greatly saves the time of manual verification and improves the efficiency of prototype verification design.

[0056] Furthermore, embodiments of this application also disclose an electronic device, Figure 9 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the cross-chip clock detection method during the chip prototype verification process disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0057] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0058] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0059] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the cross-chip clock detection method in the chip prototype verification process disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0060] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the cross-chip clock detection method in the aforementioned chip prototype verification process. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0061] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0062] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0063] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0064] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for cross-chip clock detection in a chip prototyping process, the method comprising: include: Obtain clock segmentation information generated after segmentation of various field-programmable gate arrays during the chip prototype verification design process; The port interconnection relationship of the segmented cross-chip clock signal in the corresponding netlist of each field programmable gate array is determined based on the clock segmentation information. Based on the port interconnection relationship, the cross-chip path traversed by the cross-chip clock signal is determined in the netlist; Based on whether the cross-chip path meets the preset reasonable conditions for cross-chip behavior, the reasonableness of the cross-chip behavior corresponding to the cross-chip clock signal is determined to obtain a reasonableness judgment result; wherein, the preset reasonable conditions for cross-chip behavior are: if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit, it is determined to be an unreasonable cross-chip; if the same cross-chip clock signal in the cross-chip path passes through the clock management unit after crossing the field programmable gate array once, it is determined to be a reasonable cross-chip. Output a detection report containing the cross-chip clock signal, the cross-chip path, and the rationality judgment result.

2. The method of claim 1, wherein, The acquisition of clock segmentation information generated after segmentation of each field-programmable gate array during the chip prototype verification design process includes: Obtain the clock segmentation report output after segmenting each field-programmable gate array during the prototype verification design process using the segmentation tool, and use it as clock segmentation information; Accordingly, determining the port interconnection relationship of the segmented cross-chip clock signal in the corresponding netlist of each field-programmable gate array based on the clock segmentation information includes: Parse the report structure of the clock segmentation report to locate the clock segmentation information field; The interconnection relationship between the segmented cross-chip clock signals and each of the field-programmable gate arrays is extracted from the clock segmentation information field to determine the port interconnection relationship of the cross-chip clock signals in the corresponding netlist of each field-programmable gate array.

3. The method of claim 1, wherein, Determining the cross-chip path of the cross-chip clock signal in the netlist based on the port interconnection relationship includes: Taking the input port of the cross-chip clock signal in the port interconnection relationship as the starting point of the path, the netlist is searched sequentially for the net connected to the input port; Locate the connected logic cell instance along the net and trace the output net of the logic cell instance until the output port of the cross-chip clock signal is reached; Record the nets and the logic cell instances to generate the cross-chip path of the cross-chip clock signal.

4. The method of claim 3, wherein, The logic unit examples include any one or more of the following: input buffer, output buffer, global clock buffer, gated clock buffer, differential input buffer, differential output buffer, clock control unit, latch control unit, and lookup table.

5. The method of claim 1, wherein, The step of determining whether the cross-chip behavior corresponding to the cross-chip clock signal is reasonable based on whether the cross-chip path meets the preset reasonable conditions for cross-chip behavior, in order to obtain a reasonableness judgment result, includes: If the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit during the process of continuously crossing two or more field programmable gate arrays, it is determined to be an unreasonable cross-chip, thus obtaining an unreasonable cross-chip result. If the same cross-chip clock signal in the cross-chip path passes through the clock management unit and generates a new cross-chip clock signal every time it crosses the field programmable gate array, it is determined to be a reasonable cross-chip, so as to obtain a reasonable cross-chip result.

6. The method of claim 5, wherein, Also includes: Obtain the clock constraint file for the chip prototype verification design; The name information of the clock management unit used to generate new cross-chip clock signals is determined based on the clock constraint file.

7. The method of claim 1, wherein, The output includes a detection report containing the cross-chip clock signal's cross-chip path and the rationality judgment result, including: Output a test report containing the names of the nets traversed by the cross-chip clock signal, the names of the logic unit instances traversed, the cross-chip level of the cross-chip clock signal, and a reasonableness judgment result including reasonable or unreasonable cross-chip results.

8. An apparatus for cross-chip clock detection in a chip prototyping process, comprising: include: The information acquisition module is used to acquire clock segmentation information generated after segmentation of various field-programmable gate arrays during the chip prototype verification design process; The interconnection information determination module is used to determine the port interconnection relationship of the segmented cross-chip clock signals in the corresponding netlists of each field-programmable gate array based on the clock segmentation information. The path determination module is used to determine the cross-chip path through which the cross-chip clock signal passes in the netlist based on the port interconnection relationship; A reasonableness judgment module is used to determine whether the cross-chip behavior corresponding to the cross-chip clock signal is reasonable based on whether the cross-chip path meets the preset reasonableness conditions for cross-chip behavior, so as to obtain a reasonableness judgment result; wherein, the preset reasonableness conditions for cross-chip behavior are: if the same cross-chip clock signal in the cross-chip path does not pass through the clock management unit, it is determined to be an unreasonable cross-chip; if the same cross-chip clock signal in the cross-chip path passes through the clock management unit every time it crosses the field programmable gate array, it is determined to be a reasonable cross-chip. The report output module is used to output a detection report containing the cross-chip clock signal, the cross-chip path, and the rationality judgment result.

9. An electronic device, comprising: include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the cross-chip clock detection method in the chip prototyping process as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the cross-chip clock detection method in the chip prototype verification process as described in any one of claims 1 to 7.

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