A receiver card and display screen system

Abstract

This disclosure provides a receiver card and display screen system, relating to the field of display technology. The receiver card includes a circuit board and a connector electrically connected to the circuit board. The connector includes a first surface and a second surface disposed opposite to each other along its thickness direction. Along the length direction of the connector, the first surface of the connector is provided with a plurality of first signal interface pins and a plurality of second signal interface pins. The second surface of the connector is provided with a plurality of second signal interface pins. Thus, using a single connector to connect to the circuit board helps to reduce the size of the receiver card and minimize its space occupation.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a receiver card and display screen system. Background Technology

[0002] Besides its advantages of high brightness and wide color gamut, the ability to flexibly splice together LED displays to form large-scale screens is also particularly important. An LED display is composed of individual display cabinets equipped with receiver cards. In existing LED display systems, the video source sends video signals to the transmitting card via a video interface. The transmitting card then converts the video signals into digital signals and distributes them, outputting them from multiple output interfaces to the receiver cards in different display cabinets connected to it.

[0003] Currently, high-density receiver cards typically consist of two connectors arranged in pairs, which generally result in large size and large space occupation. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a receiver card and display system designed to reduce the size of the receiver card and minimize its footprint.

[0005] In a first aspect, this disclosure provides a receiver card, including a circuit board and a connector electrically connected to the circuit board. The connector includes a first surface and a second surface disposed opposite to each other along the thickness direction of the connector. Along the length direction of the connector, the first surface of the connector is provided with a plurality of first signal interface pins and a plurality of second signal interface pins, and the second surface of the connector is provided with a plurality of second signal interface pins.

[0006] Optionally, the first signal interface pin includes a first sub-signal interface pin group and a second sub-signal interface pin group, and a grounding pin is provided between adjacent first sub-signal interface pin groups and second sub-signal interface pin groups along the length direction of the connector.

[0007] Optionally, the first and second surfaces of the connector are further provided with a plurality of custom interface pins.

[0008] Optionally, the second signal interface pin and the custom interface pin form a plurality of first pin groups, the first pin group including N pins arranged continuously along the length direction of the connector, where N is a positive integer; along the length direction of the connector, a ground pin or an unused pin is provided between adjacent first pin groups.

[0009] Optionally, on the first surface and the second surface, the custom interface pins include a plurality of first custom interface pins, and along the length direction of the connector, at least two of the first custom interface pins are located between two adjacent second signal interface pins.

[0010] Optionally, on the first surface and the second surface, the custom interface pin includes a plurality of second custom interface pins, which are located between the first signal interface pin and the second signal interface pin along the length direction of the connector.

[0011] Optionally, both the second signal interface pin and the custom interface pin support a first voltage and a second voltage, wherein the voltage values ​​of the first voltage and the second voltage are different.

[0012] Optionally, the custom interface pins include multiple third custom interface pins, and the receiving card includes a first state and a second state;

[0013] In the first state, the second signal interface pin is used to connect to the first driving mode display module to transmit image signals and display control signals;

[0014] In the second state, the second signal interface pin is used to connect to the second drive mode display module to transmit image signals and display control signals.

[0015] Optionally, in the second state, at least some of the third custom interface pins are used to connect to the second drive mode display module to transmit image signals and display control signals.

[0016] Optionally, in the second state, at least some of the third custom interface pins are multiplexed as peripheral device connection pins.

[0017] Optionally, in the first state, at least some of the third custom interface pins are multiplexed as peripheral device connection pins.

[0018] Secondly, this disclosure also provides a display screen system, including an adapter board, a display screen, and a receiving card provided in the first aspect, wherein the adapter board is electrically connected to the receiving card and the display screen respectively.

[0019] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0020] In the receiver card provided in this embodiment, there is only one connector connected to the circuit board. Compared with the traditional high-density connector receiver card, which requires two connectors, the receiver card in this embodiment is smaller in size and occupies less space. Even if the HUB circuit design is compact, the receiver card can be easily installed. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0022] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 The diagram shown is a schematic representation of the front and back of a receiving card provided in an embodiment of this disclosure.

[0024] Figure 2 The diagram shown is a schematic diagram of the pin definitions of region A1 and region B1 in the connector provided in the embodiment of this disclosure;

[0025] Figure 3 The diagram shown is a schematic representation of the pin definitions for regions A2 and B2 in the connector provided in this embodiment of the present disclosure.

[0026] Figure 4 The diagram shown is a schematic diagram of the pin definitions of region A1 and region B1 when the connector provided in this embodiment is adapted to an AM-driven display module.

[0027] Figure 5 The diagram shown is a schematic of the pin definitions for regions A2 and B2 when the connector provided in this embodiment is adapted to an AM-driven display module.

[0028] Figure 6 The diagram shown is a schematic of the pin definitions of region A1 and region B1 when the connector provided in this embodiment is adapted to a display module of PM driver type.

[0029] Figure 7 The diagram shown is a schematic of the pin definitions for regions A2 and B2 when the connector provided in this embodiment is adapted to a PM-driven display module.

[0030] Figure 8 The diagram shown is a schematic of another pin definition for region A2 and region B2 when the connector provided in this embodiment is adapted to a PM-driven display module.

[0031] Figure 9 The diagram shown is a structural schematic of a display screen system provided in an embodiment of this disclosure. Detailed Implementation

[0032] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0033] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0034] Figure 1 The diagram shows a structural schematic of the front M1 and back M2 of a receiver card provided in this embodiment. The positional relationship between the front M1 and back M2 of the receiver card and the connector is illustrated. The receiver card 10 of this embodiment includes a circuit board 00 and a connector 90 connected to the circuit board 00. The connector 90 includes multiple pins (1, 3, 5, 7…203) disposed on its first surface S1 (e.g., located on the front M1 of the receiver card 10) and multiple pins (2, 4, 6, 8…204) disposed on its second surface S2 (e.g., located on the back M2 of the receiver card 10). It should be noted that the first surface S1 of the connector 90 may also correspond to the back M2 of the circuit board, and the second surface S2 of the connector 90 may also correspond to the front M1 of the circuit board. Considering the large number of pins on the connector 90, to clearly illustrate the different pins on the connector 90, this embodiment divides the connector 90 into regions. Its first surface S1 includes region A1 and region A2, and its second surface S2 includes region B1 and region B2. Figure 2 The diagram shown is a schematic representation of the pin definitions for regions A1 and B1 in the connector 90 provided in this embodiment of the present disclosure. Figure 3 The diagram shown is a schematic representation of the pin definitions for regions A2 and B2 in the connector 90 provided in this embodiment of the present disclosure. Figure 2 and Figure 3 The diagram is shown separately, but in reality, the structure of connector 90 is as follows: Figure 2 and Figure 3 The connector 90 is an integral structure formed by splicing parts along its length. In the actual product, the connector 90 is an integral structure. Optionally, the connector 90 in this embodiment includes 204 pins, wherein the odd-numbered pins 1, 3, 5, 7...203 are located on the first surface S1 of the connector 90, and the even-numbered pins 2, 4, 6, 8...204 are located on the second surface S2 of the connector 90.

[0035] Please refer to Figures 1 to 3This disclosure provides a receiver card 10, including a circuit board 00 and a connector 90 electrically connected to the circuit board 00. The connector 90 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction of the connector 90. Along the length direction of the connector 90, the first surface S1 of the connector 90 is provided with a plurality of first signal interface pins 01 and a plurality of second signal interface pins 02, and the second surface S2 of the connector 90 is provided with a plurality of first signal interface pins 01 and a plurality of second signal interface pins 02.

[0036] Optionally, along the thickness direction of the connector 90, the first signal interface pin 01 located on the first surface S1 and the second surface S2 are arranged opposite to each other, and the second signal interface pin 02 located on the first surface S1 and the second surface S2 are arranged opposite to each other. Arranging pins of the same type opposite to each other is beneficial to simplifying the layout of pins on the connector 90, but this disclosure is not limited thereto.

[0037] It should be noted that, Figure 2 and Figure 3 The embodiment illustrates a flat structure of connector 90. In practice, when connector 90 is electrically connected to circuit board 00, its odd-numbered pins are located on the first surface S1 of connector 90, and its even-numbered pins are located on the second surface S2 of connector 90. Distributing the odd-numbered and even-numbered pins on two opposing surfaces of connector 90 helps reduce the size of connector 90 and its space occupation. It should also be noted that in some other embodiments of this disclosure, the odd-numbered pins may be located on the first surface S1 of connector 90, and the even-numbered pins may be located on the second surface S2 of connector 90; this disclosure does not specifically limit this arrangement.

[0038] Furthermore, compared to the traditional high-density connector type receiver card which requires two connectors, the receiver card 10 in this embodiment only needs to have one connector 90 electrically connected to the circuit board 00. This helps to reduce the overall size of the receiver card 10 and the space occupied by the receiver card 10. Even if the HUB circuit design is compact, the receiver card 10 can be easily installed.

[0039] Optionally, the receiver card provided in this embodiment is applicable to receiver cards with a DDR3 SODIMM slot as the hardware form.

[0040] It should be noted that GPIO, mentioned in the embodiments of this disclosure, is an abbreviation for General-purpose input / output. LVDS is an abbreviation for Low-Voltage Differential Signaling. PHY is an abbreviation for Physical Layer, representing a gigabit transmission chip. GTP is an abbreviation for Gigabit TransceiverPort, representing a high-speed interface.

[0041] In the receiver card 10 provided in this disclosure, the first signal interface pin 01 represents a high-speed interface, such as a SerDes high-speed serial interface. Optionally, the SerDes high-speed serial interface includes a GTP interface, which is used for the receiver card 10 and the transmitter card to communicate via SerDes signals. It can be used with different hardware design HUBs to achieve communication in physical form such as network port, optical port, and Type-C port. Of course, it is not limited to connecting to the transmitter card. The first signal interface pin 01 can also be connected to any device that can output standard SerDes signals, such as video processors, SOCs, etc. Optionally, this disclosure uses the example of a first signal interface pin 01 comprising 16 pins, including pins GTP_TX1_N, GTP_TX1_P, GTP_RX1_N, GTP_RX1_P, GTP_TX2_N, GTP_TX2_P, GTP_RX2_N, and GTP_RX2_P located in region A1 of the first surface S1, and pins GTP_TX3_N, GTP_TX3_P, GTP_RX3_N, GTP_RX3_P, GTP_TX4_N, GTP_TX4_P, GTP_RX4_N, and GTP_RX4_P located in region A2 of the second surface S2.

[0042] In the receiver card 10 provided in this disclosure, the second signal interface pin 01 may include, for example, an LVDS interface pin and a TTL single-ended interface pin.

[0043] Please continue to refer to this. Figure 1 , Figure 2 and Figure 3In one optional embodiment of the connector 90, on the first surface S1 and the second surface S2, the first signal interface pin 01 includes a first sub-signal interface pin group 011 and a second sub-signal interface pin group 012. Along the length direction of the connector, a ground pin GND or an unused pin is provided between adjacent first sub-signal interface pin groups 011 and 012. This embodiment only illustrates the example of providing a ground pin; in some other embodiments, an unused pin may also be provided. Optionally, the ground pin GND located on the first surface S1 and the second surface S2 are arranged opposite each other along the thickness direction of the connector. The first sub-signal interface pin group 011 includes pin groups GTP_TX1_N and GTP_TX1_P, pin groups GTP_TX2_N and GTP_TX2_P, pin groups GTP_TX3_N and GTP_TX3_P, and pin groups GTP_TX4_N and GTP_TX4_P. The second sub-signal interface pin group 012 includes pin groups GTP_RX1_N and GTP_RX1_P, pin groups GTP_RX2_N and GTP_RX2_P, pin groups GTP_RX3_N and GTP_RX3_P, and pin groups GTP_RX4_N and GTP_RX4_P.

[0044] In this disclosure, when a ground pin GND is provided between adjacent first sub-signal interface pin groups 011 and second sub-signal interface pin groups 012, it can ensure that there is no voltage difference in the loop during data transmission, and the stability is better. At the same time, it can also prevent pin misalignment. When an unused pin is provided between adjacent first sub-signal interface pin groups 011 and second sub-signal interface pin groups 012, pin misalignment can also be prevented.

[0045] Please refer to Figure 1 , Figure 2 and Figure 3In one optional embodiment of this disclosure, the first surface S1 and the second surface S2 of the connector are further provided with a plurality of custom interface pins 03. Optionally, the custom interface pins 03 include a first custom interface pin 031, a second custom pin 032, and a third custom pin 033. The first custom pin 031 includes GPIO1_1V8, GPIO2_1V8, GPIO3_1V8, and GPIO4_1V8. These pins can be configured as functional pins with a level standard of 1.8V and can be used for communication with peripherals such as QSPI, SPI, UART, and IIC. These 1.8V level standard functional pins can also be used as differential pairs. The second custom interface pin 032 includes PHY_MDCLK, PHY_MDIO, PHY_RST, and MCU_GPIO. PHY type pins are used to configure the PHY chip. When using a network port, the PHY chip is needed to convert signals. This type of pin can be introduced to realize corresponding extended functions. MCU_GPIO can be used as a arbitrarily configured functional pin. The third custom interface pin 033 can be flexibly configured according to actual needs, which will be explained in detail in subsequent embodiments.

[0046] In one optional embodiment of this disclosure, on the first surface S1 and the second surface S2 of the connector 90, the second signal interface pin 02 and the custom interface pin 03 form a plurality of first pin groups 101. Each first pin group 101 includes N pins arranged continuously along the length direction of the connector, where N is a positive integer. Along the length direction of the connector, a ground pin GND or an unused pin is provided between adjacent first pin groups 101. Optionally, this embodiment uses N=8 as an example for explanation. Please refer to... Figure 2 and Figure 3In connector area A1, eight pins—PHY_MDCLK, PHY_MDIO, LVDS1.8_1_N, LVDS1.8_1_P, LVDS1.8_2_N, LVDS1.8_2_P, LVDS1.8_3_N, and LVDS1.8_3_P—form a first pin group 101. Similarly, eight pins—LVDS1.8_4_N, LVDS1.8_4_P, LVDS1.8_5_N, LVDS1.8_5_P, LVDS1.8_6_N, LVDS1.8_6_P, LVDS1.8_7_N, and LVDS1.8_7_P—form another first pin group 101. The eight pins LVDS1.8_8_N, LVDS1.8_8_P, LVDS1.8_9_N, LVDS1.8_9_P, GPIO1_1V8, GPIO2_1V8, LVDS1.8_10_N, and LVDS1.8_10_P form a first pin group 101, and the eight pins LVDS1.8_11_N, LVDS1.8_11_P, LVDS1.8_12_N, LVDS1.8_12_P, LVDS1.8_13_N, LVDS1.8_13_P, LVDS1.8_14_N, and LVDS1.8_14_P form a first pin group 101.

[0047] In connector areas A1 and A2, eight pins, namely LVDS1.8_15_N, LVDS1.8_15_P, LVDS1.8_16_N, LVDS1.8_16_P, LVDS1.8_17_N, LVDS1.8_17_P, LVDS1.8_18_N, and LVDS1.8_18_P, constitute a first pin group 101.

[0048] In connector area A2, eight pins, namely LVDS1.8_19_N, LVDS1.8_19_P, LVDS1.8_20_N, LVDS1.8_20_P, LVDS1.8_21_N, LVDS1.8_21_P, LVDS1.8_22_N, and LVDS1.8_22_P, constitute a first pin group 101; eight pins, namely LVDS1.8_23_N, LVDS1.8_23_P, LVDS1.8_24_N, LVDS1.8_24_P, LVDS1.8_25_N, LVDS1.8_25_P, LVDS1.8_26_N, and LVDS1.8_26_P, constitute a first pin group 101.

[0049] In connector area B1, eight pins—PHY_RST, MCU_GPIO, LVDS1.8_27_N, LVDS1.8_27_P, LVDS1.8_28_N, LVDS1.8_28_P, LVDS1.8_29_N, and LVDS1.8_29_P—form a first pin group 101. Eight other pins—LVDS1.8_30_N, LVDS1.8_30_P, LVDS1.8_31_N, LVDS1.8_31_P, LVDS1.8_32_N, LVDS1.8_32_P, LVDS1.8_33_N, and LVDS1.8_33_P—form a first pin group. Pin group 101 consists of eight pins: LVDS1.8_34_N, LVDS1.8_34_P, LVDS1.8_35_N, LVDS1.8_35_P, GPIO3_1V8, GPIO4_1V8, LVDS1.8_36_N, and LVDS1.8_36_P. Pin group 101 consists of eight pins: LVDS1.8_37_N, LVDS1.8_37_P, LVDS1.8_38_N, LVDS1.8_38_P, LVDS1.8_39_N, LVDS1.8_39_P, LVDS1.8_40_N, and LVDS1.8_40_P.

[0050] In connector areas B1 and B2, eight pins, namely LVDS1.8_41_N, LVDS1.8_41_P, LVDS1.8_42_N, LVDS1.8_42_P, LVDS1.8_43_N, LVDS1.8_43_P, LVDS1.8_44_N, and LVDS1.8_44_P, constitute a first pin group 101.

[0051] In connector area B2, eight pins, namely LVDS1.8_45_N, LVDS1.8_45_P, LVDS1.8_46_N, LVDS1.8_46_P, LVDS1.8_47_N, LVDS1.8_47_P, LVDS1.8_48_N, and LVDS1.8_48_P, constitute a first pin group 101; eight pins, namely LVDS1.8_49_N, LVDS1.8_49_P, LVDS1.8_50_N, LVDS1.8_50_P, LVDS1.8_51_N, LVDS1.8_51_P, LVDS1.8_52_N, and LVDS1.8_52_P, constitute a first pin group 101.

[0052] In this embodiment, a ground pin GND or an unused pin is provided between adjacent first pin groups 101, which helps to avoid pin misalignment. When a ground pin GND is introduced, it can also ensure that there is no voltage difference in the loop during data transmission and improve stability. In addition, N can optionally be set to an even number to prevent the ground pin GND or an unused pin from separating the differential pair. Furthermore, the introduction of the ground pin GND can also serve to shield and reduce interference, provide a signal loop, and achieve impedance matching.

[0053] Please refer to Figure 1 , Figure 2 and Figure 3 On the first surface S1 and the second surface S2 of the connector, the custom interface pins 03 include first custom interface pins 031. Along the length direction of the connector, at least two first custom interface pins 031 are located between two adjacent second signal interface pins 02. The connector includes a notch K. Along the length direction of the connector, the first custom interface pins 031 are located on both sides of the notch K and are adjacent to the notch K. This embodiment takes the first custom interface pins 031 including pins GPIO1_1V8 and GPIO2_1V8 located in region A1, and pins GPIO3_1V8 and GPIO4_1V8 located in region B1 as examples. Among them, GPIO1_1V8 and GPIO2_1V8 are respectively located on both sides of the notch K, and GPIO3_1V8 and GPIO4_1V8 are respectively located on both sides of the notch K. That is to say, along the length direction of the connector, the distance between two adjacent first custom interface pins 031 is greater than the distance between two adjacent second signal interface pins 02 in the same first pin group 101, which is reflected in Figure 2 In this context, the distance between GPIO1_1V8 and GPIO2_1V8 is greater than the distance between LVDS_1.8_9_N and LVDS_1.8_9_P, and the distance between GPIO3_1V8 and GPIO4_1V8 is greater than the distance between LVDS_1.8_35_N and LVDS_1.8_35_P.

[0054] When a notch is provided on the connector, considering that placing the differential pins at the notch would cause changes in the distance between the differential pins, affecting the formation of differential pairs, the first custom interface pin 031 can be placed at the notch. Optionally, the first custom interface pin 031 is a GPIO interface pin. In this case, the functions of the first custom interface pins GPIO1_1V8 and GPIO2_1V8, and the first custom interface pins GPIO3_1V8 and GPIO4_1V8 can be configured as needed. For example, when the receiver card in this embodiment is used to connect to an AM-driven display module, it can be configured as a 1.8V level pin, which can be used for QSPI, SPI, UART, IIC communication with peripherals. Of course, such a 1.8V level pin can also be used as a differential pair. When the receiver card is used to connect to a PM-driven display module, the above-mentioned custom interface pin can be configured for other functions.

[0055] In the first surface S1 and the second surface S2 of the connector, the second signal interface pin 02 can be used to transmit differential signals. Compared with traditional single-ended signals, LVDS differential signals have strong anti-interference capabilities. Interference noise is generally applied equally and simultaneously to the two signal lines, and the difference is 0, meaning that the noise does not affect the logical meaning of the signal. In addition, LVDS differential signals can effectively suppress electromagnetic interference. Because the two lines are very close and the signal amplitudes are equal, the amplitudes of the coupled electromagnetic fields between these two lines and the ground line are also equal. At the same time, their signal polarities are opposite, and their electromagnetic fields will cancel each other out, thus minimizing electromagnetic interference to the outside world.

[0056] Please continue to refer to this. Figure 1 , Figure 2 and Figure 3 The custom interface pin 03 also includes a second custom interface pin 032, which is located between the first signal interface pin 01 and the second signal interface pin 02 along the length of the connector. This embodiment uses four pins as an example: PHY_MDCLK, PHY_MDIO, PHY_RST, and MCU_GPIO. In the receiver card mentioned in this disclosure, the PHY type pin in the second custom interface pin 032 is used for configuring the PHY chip. When using a network port, the PHY chip is needed to convert signals; introducing this type of pin enables corresponding extended functions. Furthermore, this disclosure also introduces an MCU_GPIO pin below PHY_RST, which can be used as a configurable functional pin.

[0057] Please refer to Figure 2 and Figure 3In one optional embodiment of this disclosure, the second signal interface pin 02 and at least some custom interface pins 03 in the connector can both support a first voltage and a second voltage, with different voltage values ​​for the first and second voltages. For example, the second signal interface pin 02, the first custom interface pin 031, and the third custom interface pin 033 in the connector can all support both the first and third voltages. Optionally, the first voltage is 1.8V, and the second voltage is 3.3V. For example, when adapting to an AM driving mode display module, the voltage value of some pins can be set to 1.8V, and when adapting to a PM driving mode display module, the voltage value can be adjusted to 3.3V. However, this disclosure is not limited to this. In some other embodiments of this disclosure, the voltage values ​​of the first and second voltages can be set to other values. When the above-mentioned interface pins support different voltage standards, the scope of application of the receiver card provided in the embodiments of this disclosure is increased, allowing the receiver card to be applied to different scenarios.

[0058] Please continue to refer to this. Figures 1 to 3 In one optional embodiment of this disclosure, the custom interface pin 03 includes a plurality of third custom interface pins 033. For example, the third custom interface pins 033 may include pins GPIO1-GPIO33. Optionally, along the length of the receiver card, the third custom interface pins 033 are located on the side of the second signal interface pin 02 away from the first signal interface pin 01. The receiver card includes a first state and a second state. In the first state, the second signal interface pin 02 is used to connect with the first driving mode display module to transmit image signals and display control signals; in the second state, the second signal interface pin 02 is used to connect with the second driving mode display module to transmit image signals and display control signals.

[0059] The first state mentioned above could be, for example, the state where the receiving card is connected to an AM-driven display module, and the second state mentioned above could be, for example, the state where the receiving card is connected to a PM-driven display module. When adapting to an AM-driven display module, the second signal interface pin 02 in the receiving card can be configured to a 1.8V level standard; when adapting to a PM-driven display module, the second signal interface pin 02 in the receiving card can be configured to a 3.3V level standard. This allows the receiving card to support interface standards for different display modes, such as AM-driven and PM-driven display modules, and correspondingly, enables the receiving card to adapt to multiple levels, such as 1.8V and 3.3V level standards. Of course, in some other embodiments of this disclosure, the level standards of the second custom interface pin 032 and the third custom interface pin 033 can also be configured as needed to adapt to different level standards in different modes, such as 1.8V and 3.3V level standards. Thus, there is no need to introduce different receiver cards for display modules with different driving modes. Adaptation to display modules with different driving types can be achieved simply by configuring the pins of the receiver card provided in this embodiment.

[0060] When the receiver card provided in this embodiment is adapted to AM-driven and PM-driven display modules, the second signal interface pin 02 and the third custom interface pin 033 can be defined differently, thereby enabling it to adapt to different types of display modules. The following will describe, with reference to the accompanying drawings, the adaptation of the receiver card in this disclosure to display modules of different drive types.

[0061] Please refer to Figure 4 and Figure 5 , Figure 4 The diagram shown is a schematic representation of the pin definitions for regions A1 and B1 when the connector provided in this embodiment is adapted to an AM-driven display module. Figure 5The diagram shows the pin definitions of regions A2 and B2 when the connector provided in this embodiment is adapted to an AM-driven display module. When the receiver card of this disclosure is adapted to an AM-driven display module, that is, in the first state, pins LVDS1.8_1_N / P to LVDS1.8_52_N / P in the second signal interface pin 02 can be used to connect to the AM-driven display module to output image signals (e.g., P2P signals, LVDS, MIPI). These differential pins can also be configured as other functional pins with a 1.8V level standard. Such differential 1.8V level standard functional pins can be used for peripheral LVDS image input and QSPI, SPI, UART, IIC communication, etc. GPIO1_1V8 to GPIO4_1V8 in the first custom interface pin 031 can be configured as functional pins with a 1.8V level standard, and can be used for QSPI, SPI, UART, IIC communication, etc. Such 1.8V level standard functional pins can also be used as differential pairs. In the first state, at least some of the third custom interface pins 033 are multiplexed as peripheral device pins. For example, GPIO1-GPIO33 in the third custom interface pins 033 can be configured as functional pins with a 3.3V level standard, and can be used for communication with peripherals such as QSPI, SPI, UART, and IIC. This part of the pins supports multiple level standards such as 1.8V and 3.3V.

[0062] In both the first and second states, the definition of the first signal interface pin 01 in the connector can be set to the same. The first signal interface pin 01 in the connector is used for communication between the receiving card 10 and the transmitting card via SerDes signals. It can be used with different hardware design HUBs to achieve communication in physical form via Ethernet port, optical port, and Type-C port. Of course, it is not limited to connecting to the transmitting card. This first signal interface pin 01 can also be connected to any device that can output standard SerDes signals, such as video processors, SOCs, etc.

[0063] In one optional embodiment of this disclosure, in the second state, at least a portion of the first custom interface 031 and at least a portion of the third custom interface pins 033 are used to connect to the second driving mode display module to transmit image signals and display control signals. Please refer to... Figure 6 and Figure 7 , Figure 6 The diagram shown is a schematic representation of the pin definitions for regions A1 and B1 when the connector provided in this embodiment is adapted to a PM-driven display module. Figure 7The diagram shows the pin definitions of regions A2 and B2 when the connector provided in this embodiment is adapted to a PM-driven display module. When the receiver card of this disclosure is adapted to a PM-driven display module, that is, in the second state, the second signal interface pin 02, the first custom interface pin 031, and the third custom interface pin 033 are redefined. These interface pins are reused as pins A, B, C, D, LAT1, GCLK1, DCLK1, RFU1~RFU3, BUFFER_EN, READBACK_EN, R1 / G1 / B1~R40 / G40 / B40, etc., which are matched with the PM-driven display module. They can be used to connect to the PM-driven display module to output drive timing and TTL image signals. They can also be configured as other functional pins with a 3.3V level standard. These 3.3V level standard functional pins can be used for QSPI, SPI, UART, IIC communication with peripherals.

[0064] Figure 8 The diagram shown illustrates another pin definition for regions A2 and B2 when the connector provided in this embodiment is adapted to a PM-driven display module. It can be used with... Figure 6 The corresponding pins are used in combination. In one alternative embodiment of this disclosure, in the second state, at least a portion of the third custom interface pin 033 is multiplexed as a peripheral device connection pin. Please refer to... Figure 6 and Figure 8In this embodiment, when the receiving card of this disclosure is adapted to a PM driver type display module, that is, in the second state, the second signal interface pin 02 and the first custom interface pin 031 are redefined, and these interface pins are reused as pins such as A, B, C, D, LAT1, GCLK1, DCLK1, RFU1~RFU3, BUFFER_EN, READBACK_EN, R1 / G1 / B1~R32 / G32 / B32. At this time, it is equivalent to only reusing the second signal interface pin 02 and the first custom interface pin 031, and not using the third custom interface pin 033. In this case, at least part of the third custom interface pin 033 is reused as a connection pin for peripheral devices (such as peripheral flash). For example, the pins that are multiplexed for connection to peripheral devices include SPI_CLK, SPI_CS1, SPI_MISO1, SPI_CS2, SPI_MISO2, SPI_CS3, SPI_MISO3, SPI_CS4, SPI_MISO4, SPI_CS5, SPI_MISO5, SPI_CS6, SPI_MISO6, SPI_CS7, SPI_MISO7, SPI_CS8, SPI_MISO8, SPI_MOSI, MS_ID, MS_DATA, Power_DET1, Power_DET2, Power_EN, RFU4, RFU5, LDM_Temp_SS1 to LDM_Temp_SS8, etc.

[0065] Please continue to refer to this. Figures 1 to 8 The connector also has MCU interface pins 06 on its first surface S1 and second surface S2. MCU interface pins 06 may include, for example, MCU_ADC1 and MCU_ADC2 pins for acquiring external sensor voltages, and may also include MCU_SDA and MCU_SCL pins for communication with peripheral IIC devices. The connector may also have STA_LEDR, STA_LEDG, and STA_LEDB pins to transmit signals corresponding to the three-color indicator lights, and may further include an Input_KEY pin; this disclosure does not specifically limit this. In some other embodiments of this disclosure, these pins may be defined in other ways as needed; this disclosure does not specifically limit this. Optionally, the connector also has EXT interface pins on its first surface S1 and second surface S2 as extended interface pins. The voltage of this pin may be different from the voltages of other pins, for example, it may support 5V. Optionally, the EXT interface pin is located on the side of the MCU interface pin 06 near the lower edge of the receiver card. Optionally, a ground pin GND is provided between the MCU interface pin and the EXT interface pin.

[0066] In summary, the receiving card provided in this embodiment of the present disclosure has the following technical effects:

[0067] The receiver card provided in this embodiment has only one connector connected to the circuit board. Compared to the traditional high-density connector receiver card which requires two connectors, the receiver card in this embodiment is smaller and occupies less space. Even with a compact HUB circuit design, this receiver card can be easily installed. Furthermore, the receiver card supports different fixed voltages and can support AM drive mode display modules and PM drive mode display modules by updating firmware (interface definition) without replacing the receiver card. Additionally, the structure of the receiver card provided in this disclosure allows for flexible design of the receiver card's flip-chip configuration, achieving better heat dissipation at a low cost.

[0068] Based on the same inventive concept, this disclosure also provides a display screen system. Figure 9 The diagram shows a schematic representation of a display system provided in an embodiment of this disclosure. The display system includes an adapter board 20, a display screen 30, and a receiver card 10 as mentioned in the foregoing embodiments. The adapter board 20 is electrically connected to both the receiver card 10 and the display screen 30. The display screen is either an AM driving mode display screen or a PM driving mode display screen. In practical applications, the adapter board 20 is a HUB board.

[0069] The display screen system provided in this embodiment has the beneficial effects of the display screen system provided in this embodiment. For details, please refer to the specific description of the receiving card in the above embodiment. This embodiment will not repeat the description here.

[0070] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A receiving card, characterized in that, The device includes a circuit board and a connector electrically connected to the circuit board. The connector includes a first surface and a second surface disposed opposite to each other along the thickness direction of the connector. Along the length direction of the connector, the first surface of the connector is provided with a plurality of first signal interface pins and a plurality of second signal interface pins, and the second surface of the connector is provided with a plurality of first signal interface pins and a plurality of second signal interface pins.

2. The receiving card according to claim 1, characterized in that, The first signal interface pin includes a first sub-signal interface pin group and a second sub-signal interface pin group. Along the length direction of the connector, a ground pin or an unused pin is provided between adjacent first sub-signal interface pin groups and second sub-signal interface pin groups.

3. The receiving card according to claim 1, characterized in that, The first and second surfaces of the connector are further provided with a plurality of custom interface pins.

4. The receiving card according to claim 3, characterized in that, The second signal interface pin and the custom interface pin form multiple first pin groups. Each first pin group includes N pins arranged continuously along the length of the connector, where N is a positive integer. Along the length of the connector, a ground pin or an unused pin is provided between adjacent first pin groups.

5. The receiving card according to claim 3, characterized in that, The custom interface pins include a plurality of first custom interface pins, and along the length of the connector, at least two of the first custom interface pins are located between two adjacent second signal interface pins.

6. The receiving card according to claim 3, characterized in that, The custom interface pins include a plurality of second custom interface pins, which are located between the first signal interface pins and the second signal interface pins along the length of the connector.

7. The receiving card according to claim 3, characterized in that, The second signal interface pin and at least some of the custom interface pins support a first voltage and a second voltage, the first voltage and the second voltage having different values.

8. The receiving card according to claim 5, characterized in that, The custom interface pins include multiple third custom interface pins, and the receiving card includes a first state and a second state. In the first state, the second signal interface pin is used to connect to the first driving mode display module to transmit image signals and display control signals; In the second state, the second signal interface pin is used to connect to the second drive mode display module to transmit image signals and display control signals.

9. The receiving card according to claim 8, characterized in that, In the second state, at least some of the first custom interface pins and at least some of the third custom interface pins are used to connect to the second drive mode display module to transmit image signals and display control signals.

10. The receiving card according to claim 8, characterized in that, In the second state, at least some of the third custom interface pins are multiplexed as peripheral device connection pins.

11. The receiving card according to claim 8, characterized in that, In the first state, at least some of the third custom interface pins are multiplexed as peripheral device connection pins.

12. A display screen system, characterized in that, It includes an adapter board, a display screen, and a receiving card as described in any one of claims 1 to 11, wherein the adapter board is electrically connected to the receiving card and the display screen, respectively.

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