Package structure and method of manufacturing the same
By introducing through-substrate windows and heat sinks into the packaging structure, the heat dissipation problem of semiconductor chips is solved, achieving more efficient heat dissipation and a smaller packaging structure, which is suitable for high-performance terminal products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JCET GROUP CO LTD
- Filing Date
- 2023-06-07
- Publication Date
- 2026-06-26
AI Technical Summary
In existing 3D packaging, the heat dissipation management of semiconductor chips, especially the heat dissipation of chips on the lower substrate, has not been effectively solved, which may lead to heat accumulation that could damage the device and pose safety hazards.
Design a packaging structure in which a second substrate has a window extending through the upper and lower surfaces, a heat sink passes through the window and is mounted on the back of the first chip, and is electrically connected to the substrate through an inter-board connection structure. Combined with a 3D adapter device, the interconnect density is improved and the interconnect distance is shortened, thereby achieving more efficient heat dissipation.
It improves the heat dissipation capacity and system performance of the packaging structure, while achieving a smaller package size and greater system flexibility, making it suitable for high-performance miniaturized terminal products.
Smart Images
Figure CN116682788B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging, and more particularly to a packaging structure and its manufacturing method. Background Technology
[0002] With the increasing demand for applications such as smartphones, smart wearables, smart manufacturing, automotive and motor vehicle driver assistance systems, and AIoT, end products need to maintain higher performance while keeping their size and power consumption small. Besides chip manufacturers focusing on System-on-Chips (SoCs) based on advanced silicon technology nodes, packaging and testing companies focusing on System-in-Package (SiP) based on advanced packaging technologies are also highly competitive due to their low cost, flexibility, and high yield. As integration density increases, SiP is also evolving from early 2D packaging forms (such as Multi-Chip Modules) towards 2.5D and 3D.
[0003] As a type of 3D packaging, PoP (Package on Package) stacked packaging typically consists of an upper substrate and a lower substrate stacked one on top of the other, on which corresponding semiconductor chips are mounted respectively. Since semiconductor chips generate heat during operation, excessively high temperatures can damage devices and even pose safety hazards. Therefore, effectively improving the heat dissipation of semiconductor chips, especially the heat dissipation management of semiconductor chips on the lower substrate, is a pressing issue in this field. Summary of the Invention
[0004] Therefore, this application provides a packaging structure, including: a first substrate, a second substrate, a first chip, a second chip, a heat sink and an inter-board connection structure, wherein the second substrate has a first window penetrating the upper and lower surfaces of the second substrate;
[0005] The first chip is mounted on the upper surface of the first substrate and is electrically connected to the first substrate.
[0006] The second substrate is mounted on the upper surface of the first substrate, the inter-board connection structure is located between the lower surface of the second substrate and the upper surface of the first substrate, the second substrate is electrically connected to the first substrate through the inter-board connection structure, and the first window in the second substrate exposes at least a portion of the back side of the first chip.
[0007] The second chip is mounted on the upper surface of the second substrate, and the second chip is electrically connected to the second substrate;
[0008] The heat sink passes through the first opening and is mounted on the back of the first chip.
[0009] Optionally, the size of the first chip is larger than the size of the first window, and the thickness of the first chip is smaller than the thickness of the inter-board connection structure.
[0010] Optionally, the surface of the back of the first chip, other than the first opening, is bonded to the lower surface of the second substrate at the edge of the first opening by a sealing material, with the first opening exposing the back of the first chip between the sealing materials.
[0011] Optionally, the sealing material may completely seal, partially seal, or not seal the space between the second substrate at the edge of the first window and the surface outside the first window on the back of the first chip.
[0012] Optionally, the space between the first substrate and the second substrate is filled with molding compound.
[0013] Optionally, the heat sink is also attached to the back of the second chip.
[0014] Optionally, the heat sink includes a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area. The bottom end of the first vertical pin is attached to the back side of the first chip, a portion of the bottom surface of the horizontal heat dissipation area is attached to the back side of the second chip, and the bottom end of the second vertical pin is attached to the upper surface of the second substrate.
[0015] Optionally, the size of the first chip is smaller than the size of the first window, and the thickness of the first chip is greater than or equal to the thickness of the inter-board connection structure, with the back side of the first chip located in the first window.
[0016] Optionally, the first chip has a back gold layer on its back side, and the heat sink is attached to the surface of the back gold layer through the first opening.
[0017] Optionally, the inter-board connection structure includes one or more of the following: solder balls, cored metal balls, plastic core balls, metal pillars, metal blocks, and 3D adapters. The 3D adapter is a substrate, PCB board, molding compound, through-silicon via, or through-glass via.
[0018] Optionally, a third chip and / or a first passive device electrically connected to the first substrate are further mounted on the upper surface of the first substrate; a fourth chip and / or a second passive device electrically connected to the second substrate are further mounted on the upper surface of the second substrate; a third passive device electrically connected to the second substrate is further mounted on the lower surface of the second substrate; and a fourth passive device electrically connected to the first substrate is further mounted on the lower surface of the first substrate.
[0019] Optionally, underfill adhesive is filled between the first chip and the upper surface of the first substrate, and between the second chip and the upper surface of the second substrate.
[0020] This application also provides a method for manufacturing a packaging structure, including:
[0021] A first substrate, a second substrate, a first chip, and a second chip are provided, wherein the second substrate has a first window extending through the upper and lower surfaces of the second substrate;
[0022] The first chip is mounted on the upper surface of the first substrate, and the first chip is electrically connected to the first substrate.
[0023] An inter-plate connection structure is formed on the lower surface of the second substrate;
[0024] The second substrate is mounted on the upper surface of the first substrate, the second substrate is electrically connected to the first substrate through the inter-board connection structure, and the first window in the second substrate exposes at least a portion of the back side of the first chip.
[0025] The second chip is mounted on the upper surface of the second substrate, and the second chip is electrically connected to the second substrate;
[0026] The heat sink is attached to the back of the first chip through the first opening.
[0027] Optionally, the size of the first chip is larger than the size of the first window, and the thickness of the first chip is smaller than the thickness of the inter-board connection structure.
[0028] Optionally, the surface of the back of the first chip, other than the first opening, is bonded to the lower surface of the second substrate at the edge of the first opening by a sealing material, with the first opening exposing the back of the first chip between the sealing materials.
[0029] Optionally, the sealing material may completely seal, partially seal, or not seal the space between the second substrate at the edge of the first window and the surface outside the first window on the back of the first chip.
[0030] Optionally, it further includes: filling the space between the first substrate and the second substrate with molding compound; and removing excess molding compound from the back of the first chip below the first window when the sealing material does not seal or completely seal the space between the second substrate at the edge of the first window and the surface outside the first window on the back of the first chip.
[0031] Optionally, the first chip has a back gold layer on its back side, and the heat sink is attached to the surface of the back gold layer through the first opening.
[0032] Optionally, the heat sink includes a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area. The bottom end of the first vertical pin is attached to the back side of the first chip, a portion of the bottom surface of the horizontal heat dissipation area is attached to the back side of the second chip, and the bottom end of the second vertical pin is attached to the upper surface of the second substrate.
[0033] Optionally, the size of the first chip is smaller than the size of the first window, and the thickness of the first chip is greater than or equal to the thickness of the inter-board connection structure, with the back side of the first chip located in the first window.
[0034] Optionally, the heat sink is also attached to the back of the second chip.
[0035] Optionally, the inter-board connection structure includes one or more of the following: solder balls, cored metal balls, plastic core balls, metal pillars, metal blocks, and 3D adapters. The 3D adapter is a substrate, PCB board, molding compound, through-silicon via, or through-glass via.
[0036] Optionally, it further includes: mounting a third chip and / or a first passive device electrically connected to the first substrate on the upper surface of the first substrate; mounting a fourth chip and / or a second passive device electrically connected to the second substrate on the upper surface of the second substrate; mounting a third passive device electrically connected to the second substrate on the lower surface of the second substrate; and further mounting a fourth passive device electrically connected to the first substrate on the lower surface of the first substrate.
[0037] Optionally, it further includes filling the space between the first chip and the upper surface of the first substrate and between the second chip and the upper surface of the second substrate with underfill adhesive.
[0038] Compared with the prior art, the advantages of the technical solution of this application are as follows:
[0039] The packaging structure and manufacturing method of this application include: a first substrate, a second substrate, a first chip, a second chip, a heat sink, and an inter-board connection structure. The second substrate has a first window penetrating its upper and lower surfaces. The first chip is mounted on the upper surface of the first substrate and is electrically connected to it. The second substrate is mounted on the upper surface of the first substrate. The inter-board connection structure is located between the lower surface of the second substrate and the upper surface of the first substrate, and the second substrate is electrically connected to the first substrate through the inter-board connection structure. The first window in the second substrate exposes at least a portion of the back side of the first chip. The second chip is mounted on the upper surface of the second substrate and is electrically connected to it. The heat sink passes through the first window and is mounted on the back side of the first chip. Because the second substrate has a first window that penetrates the upper and lower surfaces of the second substrate, the heat sink passes through the first window and is attached to the back of the first chip, thereby improving the heat dissipation of the first chip packaged between the first and second substrates. At the same time, because the second substrate is electrically connected to the first substrate through the inter-board connection structure, especially when the inter-board connection structure is a 3D adapter device that can increase the interconnection density per unit area and shorten the interconnection distance, it provides a more flexible and versatile system design for the package, so as to achieve a smaller package size, higher heat dissipation capacity and higher system performance.
[0040] Furthermore, the heat sink is also attached to the back of the second chip, that is, the heat generated by the first chip and the second chip in the package structure is dissipated simultaneously through a heat sink.
[0041] Furthermore, the size of the first chip is larger than the size of the first window, and the thickness of the first chip is less than the thickness of the inter-board connection structure; or, the size of the first chip is smaller than the size of the first window, and the thickness of the first chip is greater than or equal to the thickness of the inter-board connection structure, with the back of the first chip located in the first window, thereby improving heat dissipation for first chips of different thicknesses. Attached Figure Description
[0042] Figures 1-6 The following are schematic diagrams of the packaging structure in some embodiments of this application;
[0043] Figures 7-9 This is a schematic diagram of the encapsulation structure in some other embodiments of this application;
[0044] Figure 10 This is a schematic diagram of the formation process of the encapsulation structure in one embodiment of this application. Detailed Implementation
[0045] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0046] Some embodiments of this application first provide a packaging structure, see reference. Figure 1 (or reference) Figures 2-6 (Any of the attached figures), including:
[0047] The first substrate 101, the second substrate 102, the first chip 201, the second chip 202, the heat sink 301 and the inter-board connection structure (209, 215), wherein the second substrate 102 has a first window 108 that penetrates the upper and lower surfaces of the second substrate 102.
[0048] The first chip 201 is mounted on the upper surface of the first substrate 101 and is electrically connected to the first substrate 101.
[0049] The second substrate 102 is mounted on the upper surface of the first substrate 101. The inter-board connection structure (209, 215) is located between the lower surface of the second substrate 102 and the upper surface of the first substrate 101. The second substrate 102 is electrically connected to the first substrate 101 through the inter-board connection structure (209, 215), and the first window 108 in the second substrate 102 exposes at least a portion of the back side of the first chip 201.
[0050] The second chip 202 is mounted on the upper surface of the second substrate 102, and the second chip 202 is electrically connected to the second substrate 102;
[0051] The heat sink 301 passes through the first window 108 and is attached to the back of the first chip 201.
[0052] The aforementioned packaging structure includes two substrates stacked one on top of the other, specifically including a first substrate 101 and a second substrate 102 located above the first substrate 101.
[0053] The first substrate 101 has a first circuit (not shown in the figure). The upper and lower surfaces of the first substrate 101 respectively have an upper pad 103 and a lower pad 104 connected to the first circuit. The first circuit, the upper pad 103, and the lower pad 104 are made of metal, which can be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. The first circuit can be a single-layer or multi-layer structure, and can include metal lines and plug or via interconnect structures (or through-hole interconnect structures) electrically connected to the metal lines. In one embodiment, the first substrate 101 can be a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate, or a printed circuit board (PCB). In one embodiment, the surfaces of the upper pad 103 and the lower pad 104 also have a solder layer. In one embodiment, some of the surfaces of the upper pad 103 and the lower pad 104 also have raised metal pillars and a solder layer located on the top surface of the metal pillars. The solder layer is made of one or more of the following materials: tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony. The metal pillar is made of one or more of the following materials: aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.
[0054] The second substrate 102 has a second circuit (not shown in the figure). The upper and lower surfaces of the second substrate 102 respectively have an upper pad 107 and a lower pad 106 connected to the second circuit. The second circuit, the upper pad 107, and the lower pad 106 are made of metal, which can be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. The second circuit can be a single-layer or multi-layer structure, and can include metal lines and plug or via interconnect structures (or through-hole interconnect structures) electrically connected to the metal lines. In one embodiment, the second substrate 102 can be a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate, or a printed circuit board (PCB). In one embodiment, the surfaces of the upper pad 107 and the lower pad 106 also have a solder layer. In one embodiment, some of the surfaces of the upper pad 107 and the lower pad 106 also have raised metal pillars and a solder layer located on the top surface of the metal pillars. The solder layer is made of one or more of the following materials: tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony. The metal pillar is made of one or more of the following materials: aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.
[0055] The second substrate 102 also has a first window 108 that penetrates the upper and lower surfaces of the second substrate 102. The first window 108 serves as a channel when the heat sink 301 is attached to the back side of the first chip 201 (attached to the upper surface of the first substrate 101), thereby improving the heat dissipation of the first chip 201 packaged between the first substrate 101 and the second substrate 102.
[0056] The first chip 201 generates heat during operation. To avoid affecting the performance of the first chip 201 and its packaging structure, the heat generated by the first chip 201 needs to be dissipated. The first chip 201 can be a logic chip or a memory chip. In one embodiment, the logic chip can include a gate array, a cell substrate array, an embedded array, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessor unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power supply chip, or a complementary metal-oxide-semiconductor (CMOS) image sensor. In one embodiment, the memory chip can include volatile memory chips (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or non-volatile memory chips (such as flash memory (Flash), phase-change RAM (PCRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)).
[0057] The first chip 201 is mounted on the upper surface of the first substrate 101. In one embodiment, the first chip 201 includes a front side and a back side, and an integrated circuit (not shown) is formed in the first chip 201. The front side of the first chip 201 has pads (not shown), and the pads are electrically connected to the integrated circuit. In one embodiment, a first solder bump 203 is also formed on the surface of the pads of the first chip 201. The material of the first solder bump 203 can be one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.
[0058] In one embodiment, when the first chip 201 is mounted (flip-chip) on the upper surface of the first substrate 101, the pads on the front side of the first chip 201 are soldered to the upper pads 103 on the upper surface of the first substrate 101 via first solder bumps 203. In other embodiments, the first chip 201 can be mounted upright on the upper surface of the first substrate 101 via an adhesive layer, and the pads on the front side of the first chip 201 are electrically connected to the upper pads 103 on the upper surface of the first substrate 101 via leads or other connection methods.
[0059] In one embodiment, reference Figures 1-6 In any of the figures, the size of the first chip 201 is larger than the size of the first window 108, and the thickness of the first chip 201 is smaller than the thickness of the inter-board connection structure (209), or the thickness of the first chip 201 is smaller than the vertical distance between the upper surface of the first substrate 101 and the lower surface of the second substrate 102.
[0060] In one embodiment, the surface of the back side of the first chip 201, excluding the first opening, is bonded to the lower surface of the second substrate 102 at the edge of the first opening 108 via a sealing material 205. The first opening 108 exposes the back side of the first chip 201 between the sealing materials 205. The sealing material 205 provides a sealed vacuum molding channel at the first opening 108 for forming a molding compound 111 that fills the space between the first substrate 101 and the second substrate 102. In one embodiment, the sealing material 205 can be at least one of a metal bonding layer or an adhesive, which may contain fillers or not. The sealing material 205 can completely seal, partially seal, or not seal the space between the second substrate at the edge of the first opening and the surface of the back side of the first chip excluding the first opening. Specifically, in some embodiments, when completely sealed (see reference...), Figure 1 , Figure 2 , Figure 3 , Figure 5 or Figure 6 The sealing material 205 forms a complete ring around the back edge of the first chip 201, sealing the space between the first window 108 and the first substrate 101 and the second substrate 102. This provides a sealed vacuum molding channel for the molding compound 111 that fills the space between the first substrate 101 and the second substrate 102, preventing the molding compound from overflowing into the first window 108. In other embodiments, when the seal is not completely closed (see reference...), Figure 4 The sealing material 205 may be in the form of a broken ring or several dots on the back edge of the first chip 201, or it may not be sealed (see reference). Figure 4When the molding compound 111 fills the space between the first substrate 101 and the second substrate 102, a sealed vacuum molding channel can be formed using a special-shaped mold that matches the first window 108. In this case, the molding compound will not overflow into the first window 108. Alternatively, a conventional mold can be used to form a sealed vacuum molding channel on the upper surface of the second substrate 102. In this case, the molding compound on the back of the first chip 201 at the bottom of the first window 108 needs to be removed to provide a heat conduction channel for the first chip 201 to dissipate heat directly to the outside.
[0061] In one embodiment, the back surface of the first chip 201 further has a back gold layer 207, which helps to improve heat dissipation efficiency. The heat sink 301 passes through the first opening 108 and is attached to the surface of the back gold layer 207. In one embodiment, the material of the back gold layer 207 is a thermally conductive metal, which can be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.
[0062] The first substrate 101 and the second substrate 102 are electrically connected via an inter-board connection structure (209, 215), which also serves to support the first substrate 101 and the second substrate 102 during the packaging process. The inter-board connection structure includes one or more of the following: solder balls, cored metal balls, plastic core balls, metal pillars, metal blocks, substrates, PCBs, molding compounds, through-silicon vias (TSVs), or through-glass vias. Specifically, in some embodiments, refer to... Figure 1 , Figure 2 or Figure 4 The inter-board interconnect structure (209) is a cored metal sphere. The cored metal sphere may include a core and a metal outer layer covering the core. The core material may be plastic or metal, and the metal outer layer may be one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony. In other specific embodiments, refer to... Figure 3 The inter-board interconnect structure (209, 215) includes a cored metal ball and a 3D adapter device. The inter-board interconnect structure (209) is a cored metal ball, and the inter-board interconnect structure (215) is a 3D adapter device. In some other specific embodiments, refer to... Figure 5 or Figure 6The inter-board interconnect structure (215) is a 3D adapter. The 3D adapter is one or more of a substrate, PCB board, molding compound, through-silicon via (TSV), or through-glass via. The 3D adapter has a third circuit, and its upper and lower surfaces respectively have upper and lower pads electrically connected to the third circuit. Through the combination of the aforementioned various inter-board interconnect structures, the vertical distance between the first substrate 101 and the second substrate 201 is maintained. Furthermore, the 3D adapter increases the interconnect density of the package while also shortening the interconnect distance.
[0063] In one embodiment, a third chip 210 and / or a first passive device 211 electrically connected to the first substrate 101 are further mounted on the upper surface of the first substrate 101. Specifically, the upper surface of the first substrate 101 may only have the third chip 210 or the first passive device 211 electrically connected to the first substrate 101 mounted on it, or the upper surface of the first substrate 101 may have both the third chip 210 and the first passive device 211 electrically connected to the first substrate 101 mounted on it simultaneously. The thickness of both the third chip 210 and the first passive device 211 is less than the vertical distance between the first substrate 101 and the second substrate 102, and the number of the third chip 210 and the first passive device 211 mounted can be adjusted according to actual needs. In one embodiment, the third chip 210 includes an analog-to-digital converter chip and / or a digital-to-analog converter chip, and the first passive device 211 can be one or more of a resistor, capacitor, and inductor. It should be noted that in other embodiments, the upper surface of the first substrate 101 may not have the third chip and / or the first passive device mounted on it.
[0064] In one embodiment, an external connection protrusion 105 connected to a portion of the lower pad 104 is formed on the lower surface of the first substrate 101. The external connection protrusion 105 is used to connect external devices. The external connection protrusion 105 is a solder protrusion, or includes a metal pillar and a solder layer located on top of the metal pillar. In another embodiment, a (fourth) passive device (not shown in the figure) electrically connected to a portion of the lower pad 104 is also mounted on the lower surface of the first substrate 101. The (fourth) passive device can be one or more of a resistor, capacitor, and inductor. It should be noted that in other embodiments, the (fourth) passive device may not be mounted on the lower surface of the first substrate 101.
[0065] In one embodiment, reference Figures 1-6In any of the figures, the space between the first chip 201 and the first substrate 101 is also filled with underfill 204. The material of the underfill 204 can be a silicone-based resin, a thermoplastic resin, a thermosetting resin, or a UV-curable resin. The underfill 204 can be formed using a dispensing process. It should be noted that, in other embodiments, the space between the first chip 201 and the first substrate 101 may not be filled with underfill, but rather with molding compound.
[0066] In one embodiment, reference Figures 1-5 In any of the figures, the space between the first substrate 101 and the second substrate 102 can be filled with molding compound 111 to protect the device between the first substrate 101 and the second substrate 102. The molding compound 111 can be made of epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, and the forming process can be injection molding or transfer molding. In another embodiment, refer to... Figure 6 The space between the first substrate 101 and the second substrate 102 may not be filled with molding material.
[0067] The second chip 202 is attached to the upper surface of the second substrate 102. The second chip 202 also generates heat when it is working. In order not to affect the performance of the first chip 201 and the package structure, it is necessary to dissipate the heat generated by the second chip 202. The heat sink 301 described in this application is also attached to the back of the second chip 202, that is, the heat generated by the first chip 201 and the second chip 202 in the package structure is dissipated at the same time through a heat sink 301.
[0068] The second chip 202 can be a logic chip or a memory chip. In one embodiment, the logic chip may include a gate array, a cell substrate array, an embedded array, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessor unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power supply chip, or a complementary metal-oxide-semiconductor (CMOS) image sensor. In one embodiment, the memory chip may include a volatile memory chip (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or a non-volatile memory chip (such as flash memory (Flash), phase-change RAM (PCRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)).
[0069] In one embodiment, the second chip 202 includes a front side and a back side, and an integrated circuit (not shown) is formed in the second chip 202. The front side of the second chip 202 has pads (not shown), which are electrically connected to the integrated circuit. In one embodiment, a second solder bump 208 is also formed on the surface of the pads of the second chip 202. The material of the second solder bump 208 can be one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.
[0070] In one embodiment, when the second chip 202 is mounted (flip-chip) on the upper surface of the second substrate 102, the pads on the front side of the second chip 202 are soldered to the upper pads 107 on the upper surface of the second substrate 102 via second solder bumps 208. In other embodiments, the second chip can be mounted upright on the upper surface of the second substrate 102 via an adhesive layer, and the pads on the front side of the second chip 202 are electrically connected to the upper pads 107 on the second substrate 102 via leads or other connection structures.
[0071] The heat sink 301 is used to release or dissipate the heat generated on the first chip 201 and the second chip 202 to control the first chip 201 and the second chip 202 within a suitable temperature range. The heat sink 301 is formed of a material with high thermal conductivity. In one embodiment, the material with high thermal conductivity includes metals (e.g., copper, aluminum, gold, nickel, steel, or stainless steel) or carbon-containing materials (e.g., graphite, graphene, or carbon nanotubes).
[0072] In one embodiment, the heat sink 301 includes a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area 301. The first vertical pin passes through a first opening 108 in the second substrate 102 and its bottom end is attached to the back surface of the first chip 201. A portion of the bottom surface of the horizontal heat dissipation area is attached to the back surface of the second chip 202, and the bottom end of the second vertical pin is attached to the upper surface of the second substrate 102. This allows the packaging structure of this application to simultaneously dissipate heat from the first chip 201 mounted on the first substrate 101 and the second chip 202 mounted on the second substrate 102 using only one heat sink 301.
[0073] In one embodiment, the bottom end of the first vertical pin of the heat sink 301 is attached to the back side of the first chip 201 via a thermal interface material layer 206. A portion of the bottom surface of the horizontal heat dissipation area of the heat sink 301 is also attached to the back side of the second chip 202 via the same or different thermal interface material layers 206. The bottom end of the second vertical pin of the heat sink 301 is attached to the upper surface of the second substrate 102 via an adhesive layer 303. The thermal interface material layer (TIM) (206) effectively reduces the contact thermal resistance between different structures, rapidly transferring the heat generated by the first chip 201 and the second chip 202 to the heat sink 301. The material of the thermal interface material layer can be one or more of thermally conductive grease, thermally conductive gel, thermal interface material layer, or metal-based thermal interface material. The adhesive layer 303 is made of adhesive, which may contain fillers or not.
[0074] In some embodiments, a fourth chip 212 and / or a second passive device 213 electrically connected to the second substrate 102 are further mounted on the upper surface of the second substrate 102; a third passive device 214 electrically connected to the second substrate 102 is further mounted on the lower surface of the second substrate 102. In a specific embodiment, refer to... Figure 1 or Figure 3 or Figure 4 The upper surface of the second substrate 102 is further mounted with a fourth chip 212 and a second passive device 213 electrically connected to the second substrate 102. The lower surface of the second substrate 102 may also be mounted with a third passive device 214 electrically connected to the second substrate 102 (in one embodiment, see reference 214). Figure 3 The third passive device 214 may not be mounted on the lower surface of the second substrate 102. In another specific embodiment, refer to... Figure 2 or Figure 5 or Figure 6 The upper surface of the second substrate 102 is also equipped with a second passive device 213 electrically connected to the second substrate 102, and the lower surface of the second substrate 102 can be equipped with a third passive device 214 electrically connected to the second substrate 102. The number of the fourth chip 212, the second passive device 213, and the third passive device 214 can be adjusted according to actual needs.
[0075] In one embodiment, reference Figure 1 or Figure 3 or Figure 4When the fourth chip 212 or the second passive device 213 mounted on the upper surface of the second substrate 102 is relatively high, in order to minimize the thickness of the packaging structure, the heat sink 301 also has a second window 302 that penetrates the upper and lower surfaces of the heat sink, and the back side of the fourth chip 212 or the second passive device 213 can extend into the second window 302.
[0076] In another embodiment, the height of the fourth chip 212 and the height of the second passive device 213 are both less than the vertical distance between the bottom surface of the heat sink and the upper surface of the second substrate 102, in which case the heat sink 301 does not need to have a window.
[0077] In one embodiment, the space between the second chip 202 and the upper surface of the second substrate 102 is filled with underfill adhesive 204.
[0078] Other embodiments of this application also provide a packaging structure (the main difference between this embodiment and the previous embodiments is the different thickness of the first chip and the different size of the first window 108 formed in the second substrate 102; the limitations of the same or similar parts in this embodiment and the previous embodiments will not be repeated in this embodiment, please refer to the limitations of the corresponding parts in the previous embodiments for details). Please refer to... Figure 7 , Figure 8 or Figure 9 The packaging structure includes a first substrate 101, a second substrate 102, a first chip 201, a second chip 202, a heat sink 301, and an inter-board connection structure (209, 215). The second substrate 102 has a first window 108 penetrating its upper and lower surfaces. The first chip 201 is smaller than the first window 108, and its thickness is greater than or equal to the thickness of the inter-board connection structure (209, 215). The first chip 201 is mounted on the upper surface of the first substrate 101 and is electrically connected to it. The back side of the first chip 201 is located in the first window 108; the second substrate 102 is mounted on the upper surface of the first substrate 101, and the inter-board connection structure (209, 215) is located between the lower surface of the second substrate 102 and the upper surface of the first substrate 101. The second substrate 102 is electrically connected to the first substrate 101 through the inter-board connection structure (209, 215); the second chip 202 is mounted on the upper surface of the second substrate 102 and is electrically connected to the second substrate 102; the heat sink 301 passes through the first window 108 and is mounted on the back side of the first chip 201.
[0079] In one embodiment, reference Figure 7The heat sink 301 can also be attached to the back side of the second chip 202. The heat sink 301 may include a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area. The first vertical pin passes through a first opening 108 in the second substrate 102, and its bottom end (via a thermal interface material 206) is attached to the back side of the first chip 201. A portion of the bottom surface of the horizontal heat dissipation area is attached to the back side of the second chip 202. The bottom end of the second vertical pin (via an adhesive layer 303) is attached to the top surface of a pillar 306 located on the upper surface of the first substrate 101. The pillar 306 can be made of metal.
[0080] In another embodiment, reference Figure 8 The heat sink 301 may include a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area. The first vertical pin is attached to the back of the first chip 201 through a thermal interface material 206, and the bottom end of the second vertical pin is attached to the upper surface of the first substrate 101 (through an adhesive layer 303). The horizontal heat dissipation area has a second opening 302 that exposes the back of the second chip 202.
[0081] In yet another embodiment, reference is made to Figure 9 The heat sink 301 is not attached to the second chip 202. The heat sink 301 has a second opening 302 to expose the back side of the second chip 202. Except for a portion (via a thermal interface material 206) attached to the back side of the first chip 201, the other portion of the heat sink 301 can be attached (via an adhesive layer 303) to the surface of the molding compound 111 filling the space between the first substrate 101 and the second substrate 101.
[0082] In one embodiment, a third chip 210 and / or a first passive device 211 electrically connected to the first substrate 101 are further mounted on the upper surface of the first substrate 101; a fourth chip (not shown) and / or a second passive device 213 electrically connected to the second substrate 102 are further mounted on the upper surface of the second substrate 102; a third passive device (not shown) electrically connected to the second substrate 102 is further mounted on the lower surface of the second substrate 102; and a fourth passive device (not shown) electrically connected to the first substrate 101 is further mounted on the lower surface of the first substrate 101. It should be noted that in other embodiments, the third chip and / or the second passive device may not be mounted on the upper surface of the first substrate 101; the fourth chip and / or the second passive device may not be mounted on the upper surface of the second substrate 102; the third passive device may not be mounted on the lower surface of the second substrate 102; and the fourth passive device may not be mounted on the lower surface of the first substrate 101.
[0083] In one embodiment, an underfill 204 is filled between the first chip 201 and the upper surface of the first substrate 101 and between the second chip 202 and the upper surface of the second substrate 102.
[0084] In one embodiment, a second molding compound 112 for encapsulating the second chip 202 and the second passive device 213 is formed on the upper surface of the second substrate 102.
[0085] In one embodiment, the inter-board connection structure (209, 215) is one or more of the following: solder balls, cored metal balls, plastic core balls, metal pillars, metal blocks, and 3D adapters. In a specific embodiment, the inter-board connection structure (209) is a solder ball. The inter-board connection structure (215) is a 3D adapter.
[0086] This application also provides a method for manufacturing a packaging structure (the limitations of the same or similar parts in this manufacturing method embodiment and the aforementioned packaging structure embodiment will not be repeated in this embodiment; please refer to the corresponding limitations in the aforementioned packaging structure embodiment for details). Figure 10 ,include:
[0087] A first substrate 101, a second substrate 102, a first chip 201, and a second chip 202 are provided. The second substrate 102 has a first window 108 penetrating the upper and lower surfaces of the second substrate 102 (see reference). Figure 10 (The first and second figures in the middle);
[0088] The first chip 201 is mounted on the upper surface of the first substrate 101, and the first chip 201 is electrically connected to the first substrate 101 (see reference). Figure 10 (The first image in the middle);
[0089] An inter-plate connection structure (209) is formed on the lower surface of the second substrate 102 (see reference). Figure 10 (Second image in the middle);
[0090] The second substrate 102 is mounted on the upper surface of the first substrate 101. The second substrate 201 is electrically connected to the first substrate 101 through the inter-board connection structure (209), and the first window 108 in the second substrate 201 exposes at least a portion of the back side of the first chip 201 (see reference). Figure 10 (The third figure in the middle);
[0091] The second chip 202 is mounted on the upper surface of the second substrate 102 (reference). Figure 10 (The fourth figure in the middle);
[0092] The heat sink 301 is mounted on the back of the first chip 201 through the first opening 108 (see reference). Figure 10 (The fifth figure in the middle).
[0093] In one embodiment, the size of the first chip 201 is larger than the size of the first window 108, and the thickness of the first chip 201 is smaller than the thickness of the inter-board connection structure (209).
[0094] In one embodiment, the surface of the back side of the first chip 201, other than the first window, is bonded to the lower surface of the second substrate 102 at the edge of the first window 108 by a sealing material 205, and the first window 108 exposes the back side of the first chip 201 between the sealing materials 205.
[0095] In one embodiment, the sealing material 205 completely seals, partially seals, or does not seal the space between the second substrate 102 at the edge of the first window 108 and the surface outside the first window on the back of the first chip 201.
[0096] In one embodiment, forming a sealing material 205 and electrically connecting the second substrate 201 to the first substrate via the inter-board connection structure (209) further includes: filling the space between the first substrate 101 and the second substrate 102 with a molding compound 111; when the sealing material 205 does not seal or does not completely seal the space between the second substrate 102 at the edge of the first window 108 and the surface outside the first window on the back of the first chip 101, removing excess molding compound from the back of the first chip 201 below the first window 108.
[0097] In one embodiment, the first chip 201 has a back gold layer 207 on its back side, and the heat sink 301 is attached to the surface of the back gold layer 207 through the first opening 108.
[0098] In one embodiment, the heat sink 301 is also attached to the back surface of the second chip 202. In another embodiment, the heat sink 301 includes a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area. The bottom end of the first vertical pin is attached to the back surface of the first chip 201, a portion of the bottom surface of the horizontal heat dissipation area is attached to the back surface of the second chip 202, and the bottom end of the second vertical pin is attached to the upper surface of the second substrate 102.
[0099] In one embodiment, the inter-board connection structure includes one or more of the following: solder balls, cored metal balls, plastic core balls, metal pillars, metal blocks, and 3D adapters. In a specific embodiment, the inter-board connection structure (209) is a cored metal ball. The inter-board connection structure (215) is a 3D adapter.
[0100] In another embodiment, the first chip 101 is smaller than the first window 108, and the thickness of the first chip 101 is greater than or equal to the thickness of the inter-board connection structure (209, 215), with the back side of the first chip located within the first window 108 (see reference). Figure 7 , Figure 8 or Figure 9 ).
[0101] In one embodiment, the method further includes: mounting a third chip 210 and / or a first passive device 211 (see reference) electrically connected to the first substrate 101 on the upper surface of the first substrate 101. Figure 10 (First figure in the middle); A fourth chip 212 and / or a second passive device 213 (see reference) that are electrically connected to the second substrate 102 are mounted on the upper surface of the second substrate 102. Figure 10 (Fourth figure in the middle); A third passive device 214 electrically connected to the second substrate 102 is mounted on the lower surface of the second substrate 102 (see reference). Figure 10 (Second figure in the middle).
[0102] In one embodiment, the method further includes filling the space between the first chip 201 and the upper surface of the first substrate 101, and between the second chip 202 and the upper surface of the second substrate 102, with underfill adhesive 204 (see reference). Figure 10 (The first and fourth figures in the middle).
[0103] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.
Claims
1. A packaging structure, characterized in that, include: The system comprises a first substrate, a second substrate, a first chip, a second chip, a heat sink, and an inter-board connection structure, wherein the second substrate has a first window penetrating through the upper and lower surfaces of the second substrate. The first chip is mounted on the upper surface of the first substrate and is electrically connected to the first substrate. The second substrate is mounted on the upper surface of the first substrate, the inter-board connection structure is located between the lower surface of the second substrate and the upper surface of the first substrate, the second substrate is electrically connected to the first substrate through the inter-board connection structure, and the first window in the second substrate exposes at least a portion of the back side of the first chip. The second chip is mounted on the upper surface of the second substrate, and the second chip is electrically connected to the second substrate; The heat sink passes through the first window and is mounted on the back of the first chip. The heat sink includes a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area. The bottom end of the first vertical pin is mounted on the back of the first chip. A portion of the bottom surface of the horizontal heat dissipation area is mounted on the back of the second chip. The bottom end of the second vertical pin is mounted on the upper surface of the second substrate.
2. The packaging structure as described in claim 1, characterized in that, The size of the first chip is larger than the size of the first window, and the thickness of the first chip is smaller than the thickness of the inter-board connection structure.
3. The packaging structure as described in claim 2, characterized in that, The surface of the back of the first chip, excluding the first opening, is bonded to the lower surface of the second substrate at the edge of the first opening by a sealing material, and the first opening exposes the back of the first chip between the sealing materials.
4. The packaging structure as described in claim 3, characterized in that, The sealing material may completely seal, partially seal, or not seal the space between the second substrate at the edge of the first window and the surface outside the first window on the back of the first chip.
5. The packaging structure as described in claim 4, characterized in that, The space between the first substrate and the second substrate is filled with molding compound.
6. The packaging structure as described in claim 1, characterized in that, The size of the first chip is smaller than the size of the first window, and the thickness of the first chip is greater than or equal to the thickness of the inter-board connection structure. The back side of the first chip is located in the first window.
7. The packaging structure as described in claim 1, 2, or 6, characterized in that, The first chip has a gold backing layer on its back side, and the heat sink is attached to the surface of the gold backing layer through the first opening.
8. The packaging structure as described in claim 1, 2, or 6, characterized in that, The inter-board connection structure includes one or more of the following: solder balls, cored metal balls, plastic core balls, metal pillars, metal blocks, and 3D adapters; the 3D adapter is a substrate, PCB board, molding compound, through-silicon via, or through-glass via.
9. The packaging structure as described in claim 1, 2, or 6, characterized in that, The upper surface of the first substrate is further mounted with a third chip and / or a first passive device electrically connected to the first substrate; the upper surface of the second substrate is further mounted with a fourth chip and / or a second passive device electrically connected to the second substrate; the lower surface of the second substrate is further mounted with a third passive device electrically connected to the second substrate; and the lower surface of the first substrate is further mounted with a fourth passive device electrically connected to the first substrate.
10. The packaging structure as described in claim 1, 2, or 6, characterized in that, Underfill adhesive is filled between the first chip and the upper surface of the first substrate, and between the second chip and the upper surface of the second substrate.
11. A method for manufacturing a packaging structure, characterized in that, include: A first substrate, a second substrate, a first chip, and a second chip are provided, wherein the second substrate has a first window extending through the upper and lower surfaces of the second substrate; The first chip is mounted on the upper surface of the first substrate, and the first chip is electrically connected to the first substrate. An inter-plate connection structure is formed on the lower surface of the second substrate; The second substrate is mounted on the upper surface of the first substrate, the second substrate is electrically connected to the first substrate through the inter-board connection structure, and the first window in the second substrate exposes at least a portion of the back side of the first chip. The second chip is mounted on the upper surface of the second substrate, and the second chip is electrically connected to the second substrate; A heat sink is attached to the back of the first chip through the first opening. The heat sink includes a horizontal heat dissipation area and a first vertical pin and a second vertical pin protruding from the bottom surface of the horizontal heat dissipation area. The bottom end of the first vertical pin is attached to the back of the first chip. A portion of the bottom surface of the horizontal heat dissipation area is attached to the back of the second chip. The bottom end of the second vertical pin is attached to the upper surface of the second substrate.
12. The method for manufacturing the packaging structure as described in claim 11, characterized in that, The size of the first chip is larger than the size of the first window, and the thickness of the first chip is smaller than the thickness of the inter-board connection structure.
13. The method for manufacturing the packaging structure as described in claim 12, characterized in that, The surface of the back of the first chip, excluding the first opening, is bonded to the lower surface of the second substrate at the edge of the first opening by a sealing material, and the first opening exposes the back of the first chip between the sealing materials.
14. The method for manufacturing the packaging structure as described in claim 13, characterized in that, The sealing material may completely seal, partially seal, or not seal the space between the second substrate at the edge of the first window and the surface outside the first window on the back of the first chip.
15. The method for manufacturing the packaging structure as described in claim 14, characterized in that, Also includes: The space between the first substrate and the second substrate is filled with molding compound; When the sealing material does not seal or does not completely seal the space between the second substrate at the edge of the first window and the surface outside the first window on the back of the first chip, remove the excess molding material from the back of the first chip below the first window.
16. The method for manufacturing the packaging structure as described in claim 12, characterized in that, The first chip has a gold backing layer on its back side, and the heat sink is attached to the surface of the gold backing layer through the first opening.
17. The method for manufacturing the packaging structure as described in claim 11, characterized in that, The size of the first chip is smaller than the size of the first window, and the thickness of the first chip is greater than or equal to the thickness of the inter-board connection structure. The back side of the first chip is located in the first window.
18. The method for manufacturing the packaging structure as described in claim 11, 12, or 17, characterized in that, Also includes: A third chip and / or a first passive device electrically connected to the first substrate are mounted on the upper surface of the first substrate. A fourth chip and / or a second passive device electrically connected to the second substrate are mounted on the upper surface of the second substrate; a third passive device electrically connected to the second substrate is mounted on the lower surface of the second substrate; and a fourth passive device electrically connected to the first substrate is also mounted on the lower surface of the first substrate.
19. The method for manufacturing the packaging structure as described in claim 11, 12, or 17, characterized in that, Also includes: Underfill adhesive is filled between the first chip and the upper surface of the first substrate, and between the second chip and the upper surface of the second substrate.