Voltage conversion circuit, chip, and electronic device
By using multiple N-MOS transistors to conduct alternately in the chip, the problem of not providing high-voltage P-MOS transistors in the chip manufacturing process is solved, realizing the conversion of low-voltage signals to high-voltage signals, reducing energy consumption and improving stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FREMONT MICRO DEVICES SHENZHEN LTD
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-26
AI Technical Summary
The lack of high-voltage P-MOS transistors in chip manufacturing processes makes it difficult for circuits to convert low-voltage signals to high-voltage signals.
Multiple N-MOS transistors are cascaded in sequence, and the odd and even arrays of transistors are turned on alternately by a control signal to pump charge to the voltage output node step by step, thereby realizing the conversion of low voltage signal to high voltage signal.
In chip manufacturing processes that do not provide high-voltage P-MOS transistors, an effective conversion from low-voltage signals to high-voltage signals is achieved, reducing energy consumption and improving stability.
Smart Images
Figure CN122292876A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit power management technology, specifically to a voltage conversion circuit, chip, and electronic device. Background Technology
[0002] In many chip applications, it is necessary to convert low-voltage signals to high-voltage signals. For example, in EEPROM (Electrically Erasable Programmable Read-Only Memory) chips, a charge pump is used to generate high voltage to erase and program the memory array. Similarly, in some scenarios of MCU chips, it is also necessary to convert low-voltage signals to high-voltage signals.
[0003] Currently, commonly used chip manufacturing processes provide high-voltage P-MOS transistors (P-channel metal-oxide-semiconductor field-effect transistors). High-voltage P-MOS transistors make it easy to convert low-voltage signals to high-voltage signals. However, some chip manufacturing processes do not provide high-voltage P-MOS transistors, making it difficult for circuits to convert low-voltage signals to high-voltage signals. Summary of the Invention
[0004] The main technical problem solved by this invention is that some chip manufacturing processes do not provide high-voltage P-MOS transistors, making it difficult for circuits to convert low-voltage signals to high-voltage signals.
[0005] According to a first aspect, one embodiment of this application provides a voltage conversion circuit, comprising:
[0006] Voltage output node, used to output the target voltage;
[0007] Capacitor;
[0008] Multiple first transistors are cascaded sequentially. The control terminal of each first transistor is connected to its first terminal. Each first transistor is associated with a capacitor. The connection node between the control terminal and the first terminal of each first transistor is connected to the corresponding capacitor. In the multiple first transistors, the first terminal of the first stage first transistor is used to receive a power signal, and the second terminal of the last stage first transistor is connected to the voltage output node. The multiple first transistors are divided into odd-numbered groups and even-numbered groups according to their bit order. The first transistor is an N-MOS transistor.
[0009] Multiple first transistors are associated with corresponding capacitors for receiving first control signals. The first control signals are used to control the conduction and cutoff of the corresponding first transistors through the corresponding capacitors, so that the odd-numbered first transistors and the even-numbered first transistors are alternately turned on, pumping the power signal to the voltage output node step by step, thereby causing the voltage output node to output a target voltage higher than or equal to the power signal.
[0010] In one embodiment, the first control signal includes a first clock signal and a second clock signal; the first clock signal is used to control the first transistor of the odd array to be in the on state when the first transistor of the even array is in the off state; the second clock signal is used to control the first transistor of the even array to be in the on state when the first transistor of the odd array is in the off state.
[0011] In one embodiment, the first clock signal includes a first level signal and a first reference level signal, and the second clock signal includes a second level signal and a second reference level signal. The first level signal and the second level signal have opposite polarities, and the first level signal is a positive voltage. The first level signal and the second level signal appear synchronously.
[0012] In one embodiment, the voltage conversion circuit further includes: a clock signal providing module, including a first clock signal output terminal and a second clock signal output terminal; the first clock signal output terminal is connected to a capacitor corresponding to the first transistor of the odd array, and the first clock signal output terminal is used to output the first clock signal; the second clock signal output terminal is connected to a capacitor corresponding to the first transistor of the even array, and the second clock signal is used to output the second clock signal.
[0013] In one embodiment, the clock signal providing module includes: a first inverter, a second inverter, and a clock signal generation circuit;
[0014] The clock signal generation circuit includes a third clock signal output terminal and a fourth clock signal output terminal. The third clock signal output terminal is connected to the input terminal of the first inverter, and the fourth clock signal output terminal is connected to the input terminal of the second inverter. The third clock signal output terminal is used to output a third clock signal, and the fourth clock signal output terminal is used to output a fourth clock signal.
[0015] The first inverter is used to invert the third clock signal to form the first clock signal;
[0016] The second inverter is used to invert the fourth clock signal to form the second clock signal.
[0017] In one embodiment, the capacitor is a capacitor, the upper plate of the capacitor is connected to the control terminal of the corresponding first transistor, the first clock signal output terminal is connected to the lower plate of the corresponding capacitor, and the second clock signal output terminal is connected to the lower plate of the corresponding capacitor.
[0018] In one embodiment, it further includes:
[0019] A switching module includes a first terminal, a second terminal, and a control terminal. The first terminal of the switching module is used to receive the power signal, the second terminal of the switching module is connected to the first terminal of the first transistor of the first stage, and the control terminal of the switching module is used to receive a second control signal and, in response to the second control signal, turn on its first terminal and second terminal.
[0020] In one embodiment, the switching module includes a second transistor and a third transistor;
[0021] The second terminal of the second transistor is used to receive the second control signal, the first terminal of the second transistor is connected to the voltage output node, and the control terminal of the second transistor is used to connect to the first supply voltage, wherein the second transistor is in a constant conduction state;
[0022] The control terminal of the third transistor is connected to the first terminal of the second transistor, the first terminal of the third transistor is used to receive the power signal, and the second terminal of the third transistor is connected to the first terminal of the first transistor of the first stage.
[0023] The second transistor is an N-MOS transistor or a triode, and the third transistor is an N-MOS transistor or a triode.
[0024] In one embodiment, the upper limit of the withstand voltage values of the first crystal, the second transistor, and the third transistor is greater than the target voltage.
[0025] According to a second aspect, one embodiment of this application provides a chip, including: a voltage conversion circuit as described above.
[0026] According to the voltage conversion circuit and chip of the above embodiments, for chips that do not provide high-voltage P-MOS transistors in their chip manufacturing process, the first transistors of the odd-numbered array and the first transistors of the even-numbered array can be alternately turned on by a control signal, so that the charge is transferred in a directional manner step by step, and the power signal is pumped to the voltage output node step by step, thereby causing the voltage output node to output a target voltage higher than or equal to the power signal. Since the first transistor is an N-MOS transistor, voltage conversion can be achieved by using multiple N-MOS transistors for chips that do not provide high-voltage P-MOS transistors in their chip manufacturing process. Attached Figure Description
[0027] Figure 1 This is a circuit diagram of a voltage conversion circuit in one embodiment;
[0028] Figure 2 This is a circuit structure diagram showing two first transistors in one embodiment;
[0029] Figure 3 This is a schematic diagram illustrating the low-voltage to high-voltage conversion in one embodiment;
[0030] Figure 4 Here is a logic diagram for one embodiment;
[0031] Figure 5 This is a logic diagram and a boost process diagram for one embodiment where two first transistors are provided.
[0032] Figure label:
[0033] 100. Clock signal providing module; 101. Clock signal generating circuit; 102. First inverter; 103. Second inverter; 200. Switching module; M3. First transistor; M2. Second transistor; M1. Third transistor; C1. Capacitor. Detailed Implementation
[0034] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.
[0035] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.
[0036] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).
[0037] This application provides a voltage conversion circuit that, for chips that do not have high-voltage P-MOS transistors in their chip manufacturing process, can achieve voltage conversion through multiple N-MOS transistors (N-channel Metal-Oxide-Semiconductor Field-Effect Transistors), thus solving the problem that the lack of high-voltage P-MOS transistors in the chip manufacturing process makes it difficult for the circuit to convert low-voltage signals to high-voltage signals.
[0038] In some embodiments, such as Figure 1 , Figure 2 As shown, the voltage conversion circuit may include a voltage output node, a capacitor C1 (the voltage between the upper and lower plates of capacitor C1 cannot change abruptly), and multiple first transistors M3. The voltage output node is used to output the target voltage V. out Multiple first transistors M3 are cascaded sequentially. The control terminal of each first transistor M3 is connected to its first terminal. Each first transistor M3 is associated with a capacitor C1. The connection node between the control terminal and the first terminal of each first transistor M3 is connected to the corresponding capacitor C1. Among the multiple first transistors M3, the first terminal of the first-stage first transistor M3 is used to connect to the power signal. Vcp The second terminal of the last stage's first transistor M3 is connected to the voltage output node, thus forming a series charge transport path. Among the multiple first transistors M3, they are divided into odd-numbered and even-numbered groups according to their bit order. The first transistors M3 are N-MOS transistors. Each of the multiple first transistors M3 has a corresponding capacitor C1 for receiving a first control signal. This first control signal controls the on / off state of the corresponding first transistor M3 through the corresponding capacitor C1, causing the odd-numbered and even-numbered first transistors M3 to conduct alternately, transmitting the power signal V... cp The charge is pumped stepwise to the voltage output node, that is, the charge is transferred along the formed charge transport path, thereby outputting a voltage at the voltage output node that is higher than or equal to the power supply signal V. cp Target voltage V out ,like Figure 3 As shown, the power signal V cp It is the supply voltage V cc The signal in the voltage domain may be higher than the supply voltage V. cc The signal.
[0039] In some embodiments, the first transistor M3 is an N-MOS transistor with an independent substrate terminal. The first terminal of the first transistor M3 is the drain of the N-MOS transistor, the control terminal is the gate of the N-MOS transistor, and the second terminal is the source of the N-MOS transistor. The substrate terminal of each first transistor M3 is grounded. During sequencing, the first transistors M3 of the first stage can have an odd-numbered bit sequence. Among multiple first transistors M3, they are sequentially sequenced starting from the first transistor M3 of the first stage. For example, when sequencing multiple first transistors M3, they can be numbered sequentially from 1, 2, 3, 4, 5, 6...n. At least two first transistors M3 are configured.
[0040] In some embodiments, for each capacitor C1, the upper plate of capacitor C1 is connected to the first terminal of the corresponding first transistor M3, and the lower plate of capacitor C1 receives a first control signal. The capacitor C1 may be, but is not limited to, a metal-insulator-metal capacitor.
[0041] Since multiple first transistors M3 form a charge transport path, and the first control signal can control the odd-numbered and even-numbered first transistors M3 to conduct alternately, the power supply signal V... cp The charge can be transferred step by step, so that the output of the voltage output node is higher than or equal to the power supply signal V. cp Target voltage V out .
[0042] In some embodiments, such as Figure 1 As shown, the first control signal includes a first clock signal CLK and a second clock signal CLK-. The lower plate of the capacitor C1 corresponding to the odd-array first transistor M3 receives the first clock signal CLK; the lower plate of the capacitor C1 corresponding to the even-array first transistor M3 receives the second clock signal CLK-. The first clock signal CLK can control the on and off states of the odd-array first transistor M3; the second clock signal CLK- can control the on and off states of the even-array first transistor M3. Specifically, when the first clock signal CLK controls the on and off states of the odd-array first transistor M3, all of the odd-array first transistor M3 are either in the on state or all are in the off state; when the second clock signal CLK- controls the on and off states of the even-array first transistor M3, all of the even-array first transistor M3 are either in the on state or all are in the off state.
[0043] In some embodiments, such as Figure 4As shown, the first clock signal CLK includes a first level signal and a first reference level signal, and the second clock signal CLK- includes a second level signal and a second reference level signal. The first level signal and the second level signal have opposite polarities, and the first level signal is a positive voltage. The first level signal and the second level signal appear synchronously. In the first clock signal CLK, the level signal during time period t1 is the first level signal, and the level signal during time period t2 is the first reference level signal. In the second clock signal CLK-, the level signal during time period t1 is the second level signal, and the level signal during time period t2 is the second reference level signal.
[0044] In some embodiments, the voltage conversion circuit further includes a clock signal providing module 100, which may include a first clock signal CLK output terminal and a second clock signal CLK- output terminal; the first clock signal CLK output terminal is connected to the capacitor C1 corresponding to the odd-numbered first transistor M3, and the first clock signal CLK output terminal is used to output the first clock signal CLK; the second clock signal CLK- output terminal is connected to the capacitor C1 corresponding to the even-numbered first transistor M3, and the second clock signal CLK- is used to output the second clock signal CLK-.
[0045] Specifically, the output terminal of the first clock signal CLK is connected to the lower plate of the capacitor C1 corresponding to the first transistor M3 of the odd-array; the output terminal of the second clock signal CLK- is connected to the lower plate of the capacitor C1 corresponding to the first transistor M3 of the even-array. Since the first transistors M3 of the odd-array are simultaneously turned on or off, they can share the first clock signal CLK; similarly, since the first transistors M3 of the even-array are simultaneously turned on or off, they can share the second clock signal CLK-, reducing hardware overhead.
[0046] In some embodiments, the clock signal providing module 100 may include a first inverter 102, a second inverter 103, and a clock signal generating circuit 101; the clock signal generating circuit 101 may include a third clock signal output terminal and a fourth clock signal output terminal, the third clock signal output terminal being connected to the input terminal of the first inverter 102, and the fourth clock signal output terminal being connected to the input terminal of the second inverter 103, the third clock signal output terminal being used to output a third clock signal, and the fourth clock signal output terminal being used to output a fourth clock signal; the first inverter 102 being used to invert the third clock signal to form a first clock signal CLK; the second inverter 103 being used to invert the fourth clock signal to form a second clock signal CLK-.
[0047] In this embodiment, the third clock signal can be derived from the waveform of the first clock signal CLK. When the first clock signal CLK is high, the corresponding third clock signal is low; when the first clock signal CLK is low, the corresponding third clock signal is high. Similarly, the fourth clock signal can be derived from the waveform of the second clock signal CLK-. When the second clock signal CLK- is high, the corresponding fourth clock signal is low; when the second clock signal CLK- is low, the corresponding fourth clock signal is high. The clock signal generation circuit 101 can be any circuit structure capable of implementing the above functions, that is, any circuit structure capable of outputting the third and fourth clock signals. Those skilled in the art can determine the specific circuit structure of the clock signal generation circuit 101 according to the actual situation, and no further limitations are imposed here.
[0048] In some embodiments, such as Figure 1 , Figure 2 As shown, the voltage conversion circuit also includes a switching module 200, which includes a first terminal, a second terminal, and a control terminal. The first terminal of the switching module 200 is used to connect to the power signal V. cp The second terminal of the switching module 200 is connected to the first terminal of the first transistor M3 of the first stage. The control terminal of the switching module 200 is used to receive a second control signal and, in response to the second control signal, turn on its first and second terminals. The second control signal is a voltage signal V. in Voltage signal V in It is the supply voltage V CC Signals in the voltage domain.
[0049] Since the first terminal of the switching module 200 is connected to the power signal V cp The second terminal of the switching module 200 is connected to the first terminal of the first transistor M3 of the first stage, and when the control terminal of the switching module 200 receives the second control signal, it turns on its first and second terminals, so that the first terminal of the first transistor M3 of the first stage is connected to the power supply signal V. cp Therefore, when multiple sets of these transistors are configured, the target output voltage V can be controlled via the second control signal. out The corresponding multiple transistors operate to reduce power consumption.
[0050] If multiple sets of first transistors M3 are configured, and these multiple sets of first transistors M3 share a single clock signal supply module 100, then without the switch module 200, one set of multiple first transistors M3 needs to output the target voltage V. out At that time, multiple groups of first transistors M3 all received the power supply signal V. cp Thus, the target voltage V is output. outAfter setting the switch module 200, the switch module 200 of the corresponding group of multiple first transistors M3 can be controlled to be in the conducting state, so that only the corresponding group of multiple first transistors M3 receive the power signal V. cp Output target voltage V out This reduces energy consumption.
[0051] It should be noted that in some cases, the target voltage V out It needs to be equal to the power signal V cp If the required power signal V is... cp The circuit is directly connected to the power signal V. cp If the output terminal is not connected, control is difficult to achieve; that is, a power supply signal V is required. cp At that time, with power signal V cp The output terminal is connected, and a power signal V is not required. cp At that time, with power signal V cp The output terminal is disconnected. In this embodiment, a switch module 200 is provided. When the switch module 200 is turned on, the first transistor M3 of the first stage is connected to the power signal V. cp When the switching module 200 is turned off, the first transistor M3 of the first stage interacts with the power signal V. cp The connection is broken, therefore, at the target voltage V out Equal to power signal V cp When the target voltage V is required out Then, by controlling the switch module 200 to be in the conducting state, the voltage output node outputs a value equal to the power supply signal V. cp Target voltage V out If the target voltage V is not required out When the voltage output node stops outputting the target voltage V, the control switch module 200 can be turned off. out .
[0052] In some embodiments, such as Figure 1 , Figure 2 As shown, the switching module 200 may include a second transistor M2 and a third transistor M1; the second terminal of the second transistor M2 is used to receive a second control signal, the first terminal of the second transistor M2 is connected to a voltage output node, and the control terminal of the second transistor M2 is used to connect to a first supply voltage, wherein the second transistor M2 is in a constant conduction state; the control terminal of the third transistor M1 is connected to the first terminal of the second transistor M2, and the first terminal of the third transistor M1 is used to connect to a power supply signal V. cp The second terminal of the third transistor M1 is connected to the first terminal of the first transistor M3 of the first stage.
[0053] Specifically, the second transistor M2 is in a constant conduction state. When the second control signal is a high-level signal, the control terminal of the third transistor M1 is pulled high, and the third transistor M1 is turned on. The first terminal of the first transistor M3 in the first stage is connected to the power supply signal V. cp When the clock signal providing module 100 provides the first clock signal CLK and the second clock signal CLK-, the voltage output node can output the target voltage V. out When the second control signal is low, the control terminal of the third transistor M1 is pulled low, the third transistor M1 is turned off, and the first terminal of the first transistor M3 in the first stage is connected to the power supply signal V. cp Disconnect between them.
[0054] Because transistors have isolation characteristics, the second transistor M2 can isolate the voltage output node from the circuit that outputs the second control signal, thus preventing the target voltage V output by the voltage output node from being affected. out When the voltage exceeds the withstand voltage limit of the circuit that outputs the second control signal, the circuit that outputs the second control signal will be damaged. In addition, since the control terminal of the third transistor M1 is connected to the voltage output node, as the voltage output by the voltage output node gradually increases, the conduction degree of the third transistor M1 can be increased, further reducing losses.
[0055] In some embodiments, the second transistor M2 is an N-MOS transistor or a bipolar transistor, and the third transistor M1 is an N-MOS transistor or a bipolar transistor. Specifically, the second transistor M2 is an N-MOS transistor, and the third transistor M1 is an N-MOS transistor. Thus, it can be seen that this voltage conversion circuit achieves the target voltage Vout at the voltage output node through N-MOS transistors.
[0056] In some embodiments, the upper limit of the withstand voltage values of the first transistor M3, the second transistor M2, and the third transistor M1 is greater than the target voltage V. out Since the upper limit of the withstand voltage of the first transistor M3, the second transistor M2, and the third transistor M1 is all greater than the target voltage V. out Therefore, the target voltage V is output at the voltage output node. out At this time, the transistor will not be damaged due to voltage exceeding the upper limit of its withstand voltage, thus improving stability.
[0057] Designed for target voltage V out Equal to or less than the power supply signal V cp When considering the substrate bias effect of the N-MOS transistor, the target voltage V out When stable, V t1 +V t2 +V t3 +···+V t2n +V t2n+1 =2nVclk In design for target voltage V out Greater than the power signal V cp At this time, the target voltage V needs to be increased. out To increase the substrate bias of the N-MOS transistor, thereby increasing the threshold voltage, when the target voltage Vout is stable, V out =V cp +2nV clk –V t2 –V t3 –···–V t2n –V t2n+1 .
[0058] Among them, V t1 V represents the threshold voltage of the third transistor M1; t2 V represents the threshold voltage of the first transistor M3 in the first stage; t3 V represents the threshold voltage of the first transistor M3 in the second stage; t2n V represents the threshold voltage of the first transistor M3 in stage 2n-1; t2n+1 V represents the threshold voltage of the first transistor M3 in the 2nth stage; clk This indicates the voltage level of the clock signal; n represents the number, for example, if there are 5 transistors, then n represents 2; V out Indicates the target voltage V out V cp Indicates power signal V cp .
[0059] The working principle of the voltage conversion circuit is described in detail below with reference to the diagram:
[0060] like Figure 2 As shown, there are two first transistors M3. The first terminal of the first transistor M3 in the first stage is connected to the power supply signal V. cp Assume V cp =V CC At this time, the voltage at node V1 is V. cp -V t1 The voltage at node V2 is V. cp -V t1 -V t2 .
[0061] Phase 1 (time period t1): The first clock signal CLK is high (first level signal), the second clock signal CLK- is low (second level signal), the first transistor M3 of the odd-numbered array is in the on state, the first transistor M3 of the even-numbered array is in the off state, the voltage between the upper and lower plates of capacitor C1 cannot change abruptly, at this time, the voltage at node V1 is V. cp -V t1 +V clkThe voltage at node V2 is V. cp -V t1 -V t2 -V clk The first transistor M3 of the first stage is turned on, and then the second stage begins.
[0062] In the second stage (time period t2): the first clock signal CLK is low (first reference level signal), and the second clock signal CLK- is high (second reference level signal). The first transistor M3 of the odd-numbered array is in the off state, and the first transistor M3 of the even-numbered array is in the on state. At this time, the charge temporarily stored at the node connected to the first transistor M3 of the first stage and the second transistor M2 of the second stage is transferred to the node connected to the first transistor M3 of the second stage and the first transistor M3 of the third stage, and is temporarily stored at that node, thus increasing the target voltage V. out With the target voltage V out As the substrate bias of the first transistor M3 and the third transistor M1 increases, V also increases. t1 V t2 V t3 It increases accordingly.
[0063] By periodically applying the first clock signal CLK and the second clock signal CLK-, charge is gradually transferred from the first terminal of the first transistor M3 in the first stage to the voltage output node, causing the voltage output node to output a value higher than the power supply signal V. cp Target voltage V out V out Ultimately, it reaches its maximum value, V. out =V cp +2nV clk –V t2 –V t3 .
[0064] One embodiment of this application provides a chip, including the voltage conversion circuit described above. The chip can be an MCU chip or an EEPROM chip. The voltage conversion circuit enables the conversion of low-voltage signals to high-voltage signals within the chip. Specific implementations are as described in the specific embodiment of the voltage conversion circuit above, and will not be elaborated further here.
[0065] One embodiment of this application provides an electronic device, including: the chip described above. The chip can be an MCU chip or an EEPROM chip. The voltage conversion circuit enables the conversion of low-voltage signals to high-voltage signals within the chip. Specific implementations are as described in the specific embodiment of the voltage conversion circuit above, and will not be elaborated further here.
[0066] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.
Claims
1. A voltage conversion circuit, characterized in that, include: Voltage output node, used to output the target voltage; Capacitor; Multiple first transistors are cascaded sequentially. The control terminal of each first transistor is connected to its first terminal. Each first transistor is associated with a capacitor. The connection node between the control terminal and the first terminal of each first transistor is connected to the corresponding capacitor. In the multiple first transistors, the first terminal of the first stage first transistor is used to receive a power signal, and the second terminal of the last stage first transistor is connected to the voltage output node. The multiple first transistors are divided into odd-numbered groups and even-numbered groups according to their bit order. The first transistor is an N-MOS transistor. In this configuration, multiple first transistors are associated with capacitors that receive first control signals. These first control signals control the on / off states of the first transistors via the capacitors, causing the odd-numbered first transistors and the even-numbered first transistors to conduct alternately, pumping the power signal step-by-step to the voltage output node, thereby causing the voltage output node to output a target voltage higher than or equal to the power signal.
2. The voltage conversion circuit as described in claim 1, characterized in that, The first control signal includes a first clock signal and a second clock signal; the first clock signal is used to control the on and off of the first transistors of the odd array, and the second clock signal is used to control the on and off of the first transistors of the even array. When the first transistor of the odd array is in the ON state, the first transistor of the even array is in the OFF state; when the first transistor of the odd array is in the OFF state, the first transistor of the even array is in the ON state.
3. The voltage conversion circuit as described in claim 2, characterized in that, The first clock signal includes a first level signal and a first reference level signal, and the second clock signal includes a second level signal and a second reference level signal. The first level signal and the second level signal have opposite polarities, and the first level signal is a positive voltage. The first level signal and the second level signal appear synchronously.
4. The voltage conversion circuit as described in claim 3, characterized in that, The voltage conversion circuit further includes a clock signal providing module, comprising a first clock signal output terminal and a second clock signal output terminal; the first clock signal output terminal is connected to the capacitor corresponding to the first transistor of the odd array, and the first clock signal output terminal is used to output the first clock signal; the second clock signal output terminal is connected to the capacitor corresponding to the first transistor of the even array, and the second clock signal is used to output the second clock signal.
5. The voltage conversion circuit as described in claim 4, characterized in that, The clock signal providing module includes: a first inverter, a second inverter, and a clock signal generation circuit; The clock signal generation circuit includes a third clock signal output terminal and a fourth clock signal output terminal. The third clock signal output terminal is connected to the input terminal of the first inverter, and the fourth clock signal output terminal is connected to the input terminal of the second inverter. The third clock signal output terminal is used to output a third clock signal, and the fourth clock signal output terminal is used to output a fourth clock signal. The first inverter is used to invert the third clock signal to form the first clock signal; The second inverter is used to invert the fourth clock signal to form the second clock signal.
6. The voltage conversion circuit as described in claim 1, characterized in that, Also includes: A switching module includes a first terminal, a second terminal, and a control terminal. The first terminal of the switching module is used to receive the power signal, the second terminal of the switching module is connected to the first terminal of the first transistor of the first stage, and the control terminal of the switching module is used to receive a second control signal and, in response to the second control signal, turn on its first terminal and second terminal.
7. The voltage conversion circuit as described in claim 6, characterized in that, The switching module includes: a second transistor and a third transistor; The second terminal of the second transistor is used to receive the second control signal, the first terminal of the second transistor is connected to the voltage output node, and the control terminal of the second transistor is used to connect to the first supply voltage, wherein the second transistor is in a constant conduction state; The control terminal of the third transistor is connected to the first terminal of the second transistor, the first terminal of the third transistor is used to receive the power signal, and the second terminal of the third transistor is connected to the first terminal of the first transistor of the first stage. The second transistor is an N-MOS transistor or a triode, and the third transistor is an N-MOS transistor or a triode.
8. The voltage conversion circuit as described in claim 7, characterized in that, The upper limit of the withstand voltage values of the first crystal, the second transistor, and the third transistor is greater than the target voltage.
9. A chip, characterized in that, include: The voltage conversion circuit as described in any one of claims 1-8.
10. An electronic device, characterized in that, include: The chip as described in claim 9.