Switching control circuit, analog switch system and chip

Abstract

This disclosure provides a switch control circuit, an analog switch system, and a chip. The circuit includes a signal detection module, a potential conversion module, and a control module. The potential conversion module converts a low-voltage enable signal into a high-voltage control signal based on the bias voltage output by the signal detection module. The control module outputs a drive signal based on the control signal and the lowest potential, so that the analog switch is completely turned off when the chip is not enabled, thereby reducing operating power consumption and supporting the transmission requirements of symmetrical positive and negative voltage signals.

Description

Technical Field

[0001] This disclosure relates to the field of switching circuit technology, and in particular to a switch control circuit, an analog switch system, and a chip. Background Technology

[0002] In high-performance analog switching applications (such as multiplexers and signal routing), a wide range of input signals, including both positive and negative voltages, is often required. While traditional dual charge pump architectures can achieve high-voltage drive, they still need to maintain the bandgap reference, level shifting, and charge pump module operation when the chip is off, making it impossible to reduce static power consumption to near zero. Furthermore, when transmitting negative voltage signals, the Zener diode cathode may exhibit a negative potential, causing the current mirror module to experience excessively high voltage differences, potentially leading to device breakdown and limiting negative voltage transmission capabilities.

[0003] Therefore, there is an urgent need for a switching control technology that can be compatible with the transmission of wide-range positive and negative analog signals, completely cut off the internal power consumption path in the off state, and solve the voltage withstand problem. Summary of the Invention

[0004] In view of this, this disclosure provides a switch control circuit, an analog switch system, and a chip that can completely shut down all internal modules when the chip is disabled to reduce power consumption, and is compatible with analog signal transmission with equal positive and negative voltage amplitudes.

[0005] According to a first aspect of this disclosure, a switch control circuit is provided for use in an analog switch. The switch control circuit includes: a signal detection module configured to detect the highest and lowest potentials among various voltage signals for the analog switch and generate a bias voltage; a potential conversion module connected to the signal detection module and configured to convert a low-voltage enable signal into a high-voltage control signal based on the bias voltage; and a control module connected to the signal detection module, the potential conversion module, and the analog switch and configured to output a drive signal to the analog switch based on the control signal and the lowest potential to drive the analog switch to turn on or off.

[0006] According to a second aspect of this disclosure, a switch control circuit is provided, comprising an inverter, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The input terminal of the inverter is used to connect to the control signal input node; the gate of the first PMOS transistor is connected to the output terminal of the inverter, the gate of the second PMOS transistor is used to connect to the control signal input node, the sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage, the body terminal of the first PMOS transistor is shorted to its source, the body terminal of the second PMOS transistor is shorted to its source, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are respectively used to obtain bias voltage signals, the body terminals of the first NMOS transistor and the second NMOS transistor are both connected to the power supply voltage, the source of the first NMOS transistor is connected to the drain of the third NMOS transistor and the gate of the fourth NMOS transistor via the target signal output node, and the source of the second NMOS transistor is connected to the gate of the third NMOS transistor and the drain of the fourth NMOS transistor; the sources of the third NMOS transistor and the fourth NMOS transistor are both used to connect to the low-voltage signal input node.

[0007] According to a third aspect of this disclosure, an analog switch system is provided, comprising a switch control circuit as described in the first or second aspect and an analog switch, for controlling the opening or closing of the analog switch via the switch control circuit.

[0008] According to a fourth aspect of this disclosure, a chip is provided, including a switch control circuit as described in the first or second aspect, or an analog switch system as described in the second aspect.

[0009] According to the switching control technology provided in this disclosure, by dynamically detecting the highest and lowest potentials among the voltage signals used for simulating the switch, a floating power rail that dynamically changes with the voltage signals is constructed in real time. This allows the internal control logic of the switching control circuit to always operate within this safe voltage window, ensuring reliable switching on / off of the analog switch while avoiding overvoltage stress on the internal components of the circuit. Furthermore, in the off state, the entire circuit requires no auxiliary power supply, thus reducing operating power consumption. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0011] Figure 1 This is a structural block diagram of a switch control circuit that is an exemplary embodiment of the present disclosure.

[0012] Figure 2 This is a structural block diagram of a switch control circuit for another exemplary embodiment of the present disclosure.

[0013] Figure 3 This describes a specific circuit implementation of a switch control circuit that is an exemplary embodiment of this disclosure.

[0014] Figure 4 This is a schematic diagram of the circuit structure of a switch control circuit, which is another exemplary embodiment of this disclosure.

[0015] Figure 5 This is a simplified structural diagram of an analog switch system that is an exemplary embodiment of the present disclosure.

[0016] Component designation: 100. Switch control circuit 110. Signal Detection Module 112. High Voltage Comparator Unit 114. Low-voltage comparator unit 116. Bias Unit 118. Voltage regulator 120. Potential Conversion Module 122. Inverter 124. Conversion Unit 126. Potentiometer 128. Potentiometer 130. Control Module 132. Control Unit 134. Drive Unit 200. Analog Switch 202. First MOSFET 204. Second MOSFET VS, power supply voltage VCP, high voltage drive signal VMID, switch feedback signal GS, ground signal NO. First transmission port COM, Second Transmission Port VH, highest potential VL, lowest potential NG, bias voltage EN, Enable signal ENB, Inverting Enable Signal VC1, First Control Signal VC2, Second Control Signal N1, First High Voltage Signal N2, Second High Voltage Signal HP1, First PMOS transistor HP2, Second PMOS transistor HN1, First NMOS transistor HN2, second NMOS transistor HN3, Third NMOS transistor HN4, the fourth NMOS transistor HN5, the fifth NMOS transistor SW_NBL, the highest potential of the analog switch 400. Switch control circuit A. Control signal input node B. Target signal output node C. High-voltage signal input node D. Low-voltage signal input node Detailed Implementation To enable those skilled in the art to better understand the technical solutions in the embodiments of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art should fall within the protection scope of this disclosure.

[0017] Reference is made to the accompanying drawings, which form part of the detailed description and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that orientations and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0018] Numerous details are set forth in the following description. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without these specific details. In some instances, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the embodiments described herein. Throughout this specification, references to “embodiment,” “one embodiment,” or “some embodiments” mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment herein. Therefore, the phrases “in an embodiment,” “in one embodiment,” or “some embodiments” appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, functions, or characteristics can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment in any way that does not mutually exclude particular features, structures, functions, or characteristics associated with two embodiments.

[0019] As used in the description and appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0020] The terms “coupling” and “connection”, along with their derivatives, are used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” can be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupling” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship).

[0021] As described throughout this document and in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the listed items. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0022] The terms "circuit" or "unit" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially," "close to," "approximately," "near," and "about" generally refer to within ±10% of the target value.

[0023] Analog switches are electronic components that dynamically switch analog signal paths using control signals. They possess key characteristics such as low on-resistance, low leakage current, and fast switching. Their core functions encompass signal routing, channel isolation, multiplexing, and time-division multiplexing, making them widely used in various analog signal processing systems. With their high flexibility, analog switches not only help reduce overall system costs but also significantly improve circuit integration.

[0024] In practical applications, analog switches need to support multiple signal types: they may transmit voltages that are positive to ground, or voltages that are negative to ground, and even need to handle a wide range of analog signals with uncertain polarity, which can be positive or negative. In addition, since many application scenarios (such as portable or battery-powered devices) are extremely sensitive to power consumption, the static power consumption of analog switches in the off state also faces stringent requirements, ideally approaching zero, in order to extend device battery life and improve energy efficiency.

[0025] However, existing analog switch-related shutdown circuits and charge pump architectures suffer from numerous technical defects in practical applications, severely limiting their applicability and performance. On one hand, in the traditional dual-charge pump architecture, even in the off state, core circuits such as the internal bandgap reference, level shifter, and charge pump still need to remain operational, preventing a complete shutdown of all modules within the chip. This results in persistently high standby power consumption, contradicting the current trend of low power consumption and long battery life in electronic devices, especially in power-sensitive applications such as portable electronic devices. On the other hand, when transmitting negative voltage signals, multi-stage charge pump systems face a significant voltage difference between high and negative voltages due to the negative voltage at the Zener diode cathode. Limited by the device's own voltage withstand capability, this voltage difference poses a reliability risk, severely limiting the analog switch's ability to transmit negative voltages. This makes it impossible to meet the requirement of transmitting analog signals with equal positive and negative voltage amplitudes, greatly restricting the application of analog switches in scenarios requiring simultaneous processing of positive and negative high-voltage signals.

[0026] To address the various problems existing in current analog switch control circuits, this disclosure provides a switch control circuit, analog switch system, and chip that support positive and negative voltage transmission. Its objectives are: 1. To completely shut down all internal functional modules when the chip is disabled, reducing power consumption to near zero; 2. To be compatible with and reliably transmit positive and negative voltage analog signals of equal amplitude.

[0027] The specific implementations of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings: Switch control circuit Figure 1 This is a simplified structural diagram of a switch control circuit that is an exemplary embodiment of the present disclosure.

[0028] like Figure 1 As shown, the switch control circuit 100 in this embodiment mainly includes: a signal detection module 110, a potential conversion module 120, and a control module 130.

[0029] The signal detection module 110 can detect the highest and lowest potentials among the voltage signals used for the analog switch 200 and generate a bias voltage.

[0030] In some embodiments, the signal detection module 110 can compare multiple high-voltage signals used for the analog switch 200 to determine the highest potential among the high-voltage signals, and compare multiple low-voltage signals used for the analog switch 200 to determine the lowest potential among the low-voltage signals. Based on the highest and lowest potentials, bias processing is performed, and a bias voltage is output.

[0031] The potential conversion module 120 is connected to the signal detection module 110 and is configured to convert the low-voltage enable signal EN into a high-voltage control signal based on the bias voltage.

[0032] The control module 130 is connected to the signal detection module 110, the potential conversion module 120 and the analog switch 200, and is configured to output a drive signal to the analog switch 200 based on the control signal output by the potential conversion module 120 and the lowest potential detected by the signal detection module 110, so as to drive the analog switch 200 to turn on or off.

[0033] In summary, this embodiment uses a signal detection module to obtain the highest and lowest potentials of the analog switch and generate a bias voltage to construct a floating internal operating reference point. This allows the circuit to seamlessly adapt to signal transmission across a full range from deep negative voltage to high positive voltage. A potential conversion module converts the low-voltage logic signal (enable signal) into a high-voltage control signal, which is then output by the control module to control the analog switch's on / off state. This allows for complete circuit shutdown when the chip is disabled (when the enable signal EN is invalid), without requiring any external auxiliary circuitry, thus reducing power consumption.

[0034] Figure 2 The circuit structure of the switch control circuit 100 according to another embodiment of this disclosure is shown. Figure 1 The specific implementation of each functional module; Figure 3 for Figure 2 The specific circuit implementation of the circuit structure shown will be discussed below. Figure 2 and Figure 3 This section provides a detailed explanation of each functional module in the switch control circuit 100.

[0035] The signal detection module 110 may include a high voltage comparison unit 112, a low voltage comparison unit 114, and a bias unit 116.

[0036] The high-voltage comparison unit 112 is configured to acquire multiple high-voltage signals for the analog switch 200, perform potential comparison, and output the highest potential VH among the multiple high-voltage signals. The low-voltage comparison unit 114 is configured to acquire multiple low-voltage signals for the analog switch 200, perform potential comparison, and output the lowest potential VL among the multiple low-voltage signals.

[0037] In some embodiments, a plurality of high-voltage MOSFETs (e.g., NMOS or PMOS) corresponding to each high-voltage signal can be provided in the high-voltage comparison unit 112 to perform comparison of each high-voltage signal and output the highest potential VH. Preferably, a current-limiting resistor can be further provided to provide overcurrent protection. Similarly, a plurality of high-voltage MOSFETs (e.g., NMOS or PMOS) corresponding to each low-voltage signal can be provided in the low-voltage comparison unit 114 to perform comparison of each low-voltage signal and output the lowest potential VL.

[0038] This embodiment avoids the control circuit from being damaged by high voltage by selecting the highest potential among multiple high-voltage signals; and selects the lowest potential among multiple low-voltage signals as a floating ground reference; to ensure that the subsequent circuit operates within a safe voltage window, and to achieve the internal control circuit's self-adaptation to the external positive and negative high voltage environment.

[0039] In some embodiments, the analog switch 200 includes two MOSFETs connected in series (e.g., Figure 5 The MOSFETs 202 and 204 shown are connected to two transmission ports (e.g., MOSFETs 202 and 204) respectively. Figure 5 The transmission ports NO and COM are shown. In this case, the multiple high-voltage signals detected by the signal detection module 110 may include: the power supply voltage signal VS, the high-voltage drive signal VCP, and the switch feedback signal VMID. The high-voltage drive signal VCP characterizes the charge pump output voltage when the enable signal EN is at a high potential (that is, the output voltage of the charge pump driving the analog switch when the chip is enabled); the switch feedback signal VMID characterizes the reference voltage at the series node of the two MOS transistors in the analog switch. The multiple low-voltage signals detected by the signal detection module 110 include the ground signal GS and the two port signals NO and COM corresponding to the two transmission ports. This embodiment, by clearly defining the specific types of key signals acting on the analog switch, ensures stable transmission of positive and negative voltage signals through the dual transmission ports of the analog switch, providing specific signal support for subsequent potential comparison and control logic implementation.

[0040] It should be noted that the types and number of signals involved in the high-voltage and low-voltage comparisons are not limited to those shown in the above embodiments. Those skilled in the art can arbitrarily adjust the types and / or number of signals involved in the comparisons based on actual needs, and this disclosure does not impose any restrictions on this.

[0041] The bias unit 116 is connected to the high voltage comparator unit 112 and the low voltage comparator unit 114, and is used to perform bias processing based on the highest potential VH and the lowest potential VL, and output the bias voltage NG.

[0042] In some embodiments, the bias unit 116 may further include a voltage regulator 118 for limiting the bias voltage NG output by the bias unit 116 within a preset voltage range. Optionally, the voltage regulator 118 may be a Zener diode, which clamps the bias voltage NG at the lowest potential VL + a preset regulated value to ensure that the operating voltage difference of the subsequent modules does not exceed the device's withstand voltage threshold. For example, when the transmission ports NO and COM of an analog switch need to transmit negative voltage signals, assuming the COM port voltage is -12V, the VS voltage is 3.3V, the VCP voltage is -7V, and the VMID voltage is typically equal to the NO or COM voltage (-12V), in this case, the highest potential VH is 3.3V. The voltage difference between the highest potential VH and the lowest potential VL is 15.3V. The Zener diode will clamp the bias voltage NG at -12V + 5V = -7V. When the analog switch's transmission ports NO and COM need to transmit positive voltage signals, assuming the COM port voltage is 12V, the VS voltage is 3.3V, the VCP voltage is 17V, and the VMID voltage is usually equal to the NO or COM voltage (12V), the highest voltage VH is 17V, and the voltage difference between the highest voltage VH and the lowest voltage VL is 17V. The Zener diode will clamp the bias voltage NG at 0V + 5V = 5V. In practical applications, voltage clamping can also be achieved in other ways, not limited to Zener diodes. For example, multiple MOSFETs connected in series can be used to provide voltage clamping, and this disclosure does not limit this.

[0043] This embodiment, by setting a voltage regulator, can avoid abnormal bias voltage caused by input signal fluctuations or external interference, prevent subsequent potential conversion and control modules from being damaged by overvoltage or undervoltage, improve the circuit's withstand voltage and stability, especially in positive and negative voltage transmission scenarios, it can effectively avoid the device loss problem caused by excessive high and low voltage difference, and ensure the reliability of the circuit under wide voltage operating conditions.

[0044] The potential conversion module 120 may include an inverter 122 and a conversion unit 124.

[0045] Inverter 122 is configured to acquire the enable signal EN and invert it to output an inverted enable signal ENB.

[0046] For example, refer to Figure 3 Inverter 122 is connected to ground signal GS and power supply voltage signal VS, providing a stable operating circuit for inverter 122 to invert the low-voltage enable signal EN into an inverted enable signal ENB.

[0047] The conversion unit 124 is connected to the inverter 122 and the bias unit 116, and is used to selectively raise the potential of the first control signal VC1 or the second control signal VC2 according to the enable signal EN, the inverting enable signal ENB and the bias voltage NG.

[0048] This embodiment generates an inverted enable signal using an inverter. This signal, combined with a conversion unit, selectively boosts the potential of the first / second control signal based on the enable signal, the inverted enable signal, and the bias voltage. This solves the problem in existing technologies where low-voltage enable signals cannot directly drive high-voltage analog switches. It achieves precise conversion between high and low voltage signal domains, and the generation of control signals is more targeted, providing a signal foundation adapted to the high-voltage domain for subsequent precise control of the analog switch. It also improves the response speed of the control signals.

[0049] In some embodiments, the conversion unit 124 includes a potential converter 126 and a potential regulator 128.

[0050] A potential converter 126 is connected to an inverter 122 to acquire an enable signal EN and an inverting enable signal ENB. Specifically, when the enable signal EN is low (and the inverting enable signal ENB is high), a second high-voltage signal N2 is output; or, when the enable signal EN is high (and the inverting enable signal ENB is low), a first high-voltage signal N1 is output. A potential regulator 128 is connected to the bias unit 116 of the signal detection module 110 and the potential converter 126, and is configured to, based on the bias voltage NG of the bias unit 116, raise the potential of the second control signal VC2 when the potential converter 126 outputs the first high-voltage signal N1, or raise the potential of the first control signal VC1 when the potential converter 126 outputs the second high-voltage signal N2.

[0051] This embodiment uses a potential converter to selectively output a first high-voltage signal or a second high-voltage signal N1 / N2 based on the high or low potential of the enable signal. This allows the potential regulator to raise the potential of the first control signal VC1 or the second control signal VC2 according to the corresponding high-voltage signal. This achieves precise mapping from the low-voltage enable signal to the high-voltage control signal. Through the step-by-step logic from "signal judgment" to "potential raising," it ensures that the potential of the control signal accurately matches the operating state (on / off) of the analog switch. This solves the problems of low level conversion efficiency and poor compatibility between control signals and switch states in existing technologies, and is particularly suitable for high-speed transmission scenarios, improving the circuit's response sensitivity.

[0052] refer to Figure 3In some embodiments, the potential converter 126 may include a first PMOS transistor HP1 and a second PMOS transistor HP2. Specifically, the source of both the first PMOS transistor HP1 and the source of the second PMOS transistor HP2 are connected to the power supply voltage VS; the gate of the first PMOS transistor HP1 is connected to an inverter 122 to obtain an inverted enable signal ENB, and the gate of the second PMOS transistor HP2 is used to obtain an enable signal EN; the body terminal (BN terminal) of the first PMOS transistor HP1 is shorted to its source, and the body terminal of the second PMOS transistor HP2 is shorted to its source. Based on the low conduction characteristics of PMOS transistors, when the enable signal EN is at a low potential (the inverted enable signal ENB is at a high potential), the first PMOS transistor HP1 is turned off and the second PMOS transistor HP2 is turned on, and a second high-voltage signal N2 is output through the drain of the second PMOS transistor HP2; conversely, when the enable signal EN is at a high potential, the first PMOS transistor HP1 is turned on and the second PMOS transistor HP2 is turned off, and a first high-voltage signal N1 is output through the drain of the first PMOS transistor HP1.

[0053] Correspondingly, the potential regulator 128 may include a first NMOS transistor HN1 and a second NMOS transistor HN2. Specifically, the gate of the first NMOS transistor HN1 and the gate of the second NMOS transistor HN2 are both connected to the bias unit 116 of the signal detection module 110 to obtain the bias voltage NG; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor HP1, and the drain of the second NMOS transistor HN2 is connected to the drain of the second PMOS transistor HP2; the body terminal of the first NMOS transistor HN1 and the body terminal of the second NMOS transistor HN2 are both connected to the power supply voltage VS; the source of the first NMOS transistor HN1 is used to output a first control signal VC1, and the source of the second NMOS transistor HN2 is used to output a second control signal VC2. Specifically, based on the high conduction characteristics of NMOS transistors, when the first PMOS transistor HP1 outputs the first high voltage signal N1, the first NMOS transistor HN1 operates to raise the potential of the first control signal VC1 output from its source; conversely, when the second PMOS transistor HP2 outputs the second high voltage signal N2, the second NMOS transistor HN2 operates to raise the potential of the second control signal VC2 output from its source.

[0054] This embodiment utilizes a potential converter composed of dual PMOS transistors. Leveraging the conduction / cutoff characteristics of the PMOS transistors, it selectively outputs a first / second high-voltage signal based on the high or low potential of the enable signal. By connecting the PMOS transistor source to the power supply voltage and shorting the body terminal to the source, the stability and withstand voltage of the high-voltage signal output are ensured, preventing high-voltage signal leakage or distortion caused by device characteristics. This solves the problems of unstable high-voltage signal generation and insufficient device withstand voltage in existing level conversion circuits.

[0055] Furthermore, this embodiment utilizes a potential regulator composed of dual NMOS transistors, leveraging the source-following characteristic of NMOS transistors to ensure the smoothness of the control signal potential rise. Simultaneously, the design of connecting the body terminal to the power supply voltage VS enhances the device's withstand voltage capability. This solves the problems of large potential fluctuations and device susceptibility to high voltage damage during the high-voltage domain control signal rise process, ensuring that the first / second control signals can accurately adapt to the high-voltage drive requirements of the analog switch. Especially in positive and negative voltage transmission scenarios, it can stably achieve potential matching between the control signal and the transmitted signal.

[0056] The control module 130 may include a control unit 132 and a drive unit 134.

[0057] The control unit 132 is connected to the low-voltage comparator unit 114 and the potential regulator 128 of the conversion unit 124, and is configured to selectively pull down the potential of the first control signal VC1 or the second control signal VC2 based on the lowest potential VL. In this embodiment, through the coordinated operation of the control unit and the potential regulator 128, a bidirectional logic control of the potential rise / fall of the first control signal VC1 and the second control signal VC2 is formed, achieving precise calibration of the control signal potential and avoiding false triggering of the analog switch due to excessively high or low control signal potentials. This solves the problem of insufficient signal control accuracy in existing control circuits, ensuring precise matching between the on / off state of the analog switch and the potentials of the enable signal and transmission signal, thus improving the control reliability of the circuit.

[0058] For example, refer to Figure 3 The control unit 132 may include a third NMOS transistor HN3 and a fourth NMOS transistor HN4. Specifically, the source of the third NMOS transistor HN3 and the source of the fourth NMOS transistor HN4 are both connected to the low-voltage comparator unit 114; the body of the third NMOS transistor HN3 and the body of the fourth NMOS transistor HN4 are both connected to the power supply voltage VS; the gate of the third NMOS transistor HN3 and the drain of the fourth NMOS transistor HN4 are connected to the potential regulator 128 of the conversion unit 124 to obtain the second control signal VC2 output by the potential regulator 128 (for example, the gate of the third NMOS transistor HN3 and the drain of the fourth NMOS transistor HN4 can be connected to the source of the second NMOS transistor HN2 to obtain the second control signal VC2); the drain of the third NMOS transistor HN3 and the gate of the fourth NMOS transistor HN4 are connected to the potential regulator 128 of the conversion unit 124 to obtain the first control signal VC1 output by the potential regulator 128 (for example, the drain of the third NMOS transistor HN3 and the gate of the fourth NMOS transistor HN4 can be connected to the source of the first NMOS transistor HN1 to obtain the first control signal VC1).

[0059] Based on the high conduction characteristics of NMOS transistors, when the potential of the second control signal VC2 is raised, the third NMOS transistor HN3 is turned on to pull down the potential of the first control signal VC1 based on the lowest potential VL, so that the potential of the first control signal VC1 is close to the lowest potential VL; conversely, when the potential of the first control signal VC1 is raised, the fourth NMOS transistor HN4 is turned on to pull down the potential of the second control signal VC2 based on the lowest potential VL, so that the potential of the second control signal VC2 is close to the lowest potential VL.

[0060] This embodiment employs a cross-connection design with dual NMOS transistors. Leveraging the high conduction characteristics of NMOS transistors, it pulls down the potential of the first control signal VC1 when the potential of the second control signal rises, and pulls down the potential of the second control signal VC2 when the potential of the first control signal VC1 rises, thus forming a positive feedback acceleration mechanism to improve the response speed of the control signal. Simultaneously, the pull-down operation is based on the lowest potential VL, ensuring that the control signal potential matches the operating potential of the analog switch (especially the low potential in negative voltage transmission scenarios). This solves the problems of slow response and asynchronous control signal and switch state under wide voltage ranges in existing control circuits, adapting to the requirements of high-speed transmission applications, and enhancing the stability of the circuit in positive and negative voltage switching scenarios.

[0061] The drive unit 134 is connected to the low-voltage comparator unit 114, the potential regulator 128 of the conversion unit 124, the control unit 132, and the analog switch 200. It is configured to acquire the lowest potential VL, the first control signal VC1, and the second control signal VC2, and output a drive signal to the analog switch 200. By integrating the lowest potential VL, the first control signal VC1, and the second control signal VC2, the output drive signal can be ensured to meet the drive requirements of the analog switch, solving the problem of insufficient direct drive capability of the control signal. Especially in positive and negative voltage transmission scenarios, the potential reference of the drive signal can be adjusted according to the lowest potential, ensuring that the analog switch can be stably turned on / off under different potential conditions, improving the drive reliability and adaptability of the circuit.

[0062] refer to Figure 3 For example, the driving unit 134 includes a fifth NMOS transistor HN5, and the driving signal output by the driving unit 134 includes a gate driving signal VG_CTRL.

[0063] Specifically, the gate of the fifth NMOS transistor HN5 is connected to the first NMOS transistor HN1 of the switching unit 124 and the third NMOS transistor HN3 of the control unit 132 to obtain the first control signal VC1; the source of the fifth NMOS transistor HN5 is connected to the low voltage comparator unit 114 to obtain the lowest potential VL; the body of the fifth NMOS transistor HN5 is connected to the highest potential SW_NBL of the analog switch 200; and the drain of the fifth NMOS transistor HN5 is connected to the gate of the analog switch 200 to output the gate drive signal VG_CTRL to the analog switch 200.

[0064] Based on the high conduction characteristics of NMOS transistors, when the first control signal VC1 is pulled low to the minimum potential VL (i.e., EN=1 when the chip is enabled), the fifth NMOS transistor HN5 is turned off. The gate drive signal VG_CTRL will be pulled up to a sufficiently high voltage (e.g., high voltage drive signal VCP) through other paths (such as charge pumps), allowing the analog switch to conduct smoothly. Conversely, when the first control signal VC1 is pulled high (i.e., EN=0 when the chip is off), the gate-source voltage VGS of the fifth NMOS transistor HN5 is approximately equal to the bias voltage NG minus the threshold voltage VTH of the first NMOS transistor HN1. This ensures that the fifth NMOS transistor HN5 conducts smoothly, forcibly pulling the gate drive signal VG_CTRL low to near the minimum potential VL. Since the source / drain potential of the analog switch is ≥VL (because VL is the lowest potential among NO / COM / GS), the VGS of the analog switch is ≤0, thus ensuring the reliable turn-off of the analog switch.

[0065] In some embodiments, a resistor R can be connected to the drain of the fifth NMOS transistor HN5 to protect the gate current of the fifth NMOS transistor HN5 and prevent device damage.

[0066] The driving unit in this embodiment uses an NMOS transistor. It achieves precise generation of the driving signal by acquiring the first control signal VC1 through the gate, acquiring the lowest potential VL through the source, and outputting the gate drive signal VG_CTRL through the drain. The design of connecting the body terminal to the highest potential of the analog switch prevents leakage current from the parasitic diode of the NMOS transistor, ensuring that the gate drive signal VG_CTRL can accurately control the gate potential of the analog switch. This solves the problems of insufficient driving capability and signal distortion in existing driving circuits under high and negative voltage scenarios, ensuring that the analog switch can respond quickly and stably to control commands during positive and negative voltage transmission, thus improving the accuracy and reliability of the switch action.

[0067] Figure 4This is a schematic diagram of the circuit structure of a switch control circuit 400 according to an exemplary embodiment of the present disclosure. As shown in the figure, the switch control circuit 400 of this embodiment mainly includes: an inverter 122, a first PMOS transistor HP1, a second PMOS transistor HP2, a first NMOS transistor HN1, a second NMOS transistor HN2, a third NMOS transistor HN3, and a fourth NMOS transistor HN4.

[0068] The input of inverter 122 is used to connect to control signal input node A, and is configured to acquire control signal (e.g., enable signal EN) and invert it to generate an inverted signal (e.g., inverted enable signal ENB).

[0069] The gate of the first PMOS transistor HP1 is connected to the output of the inverter 122 to obtain an inverted signal (e.g., an inverting enable signal ENB). The gate of the second PMOS transistor HP2 is connected to the control signal input node A to obtain a control signal (e.g., an enable signal EN). The sources of both the first PMOS transistor HP1 and the second PMOS transistor HP2 are connected to the power supply voltage VS. The body of the first PMOS transistor HP1 is shorted to its source, and the body of the second PMOS transistor HP2 is shorted to its source. The drain of the first PMOS transistor HP1 is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor HP2 is connected to the drain of the second NMOS transistor HN2.

[0070] The gates of the first NMOS transistor HN1 and the second NMOS transistor HN2 are used to acquire the bias voltage signal NG, respectively. The body terminals of both the first NMOS transistor HN1 and the second NMOS transistor HN2 are connected to the power supply voltage VS. The source of the first NMOS transistor HN1 is connected to the drain of the third NMOS transistor HN3 and the gate of the fourth NMOS transistor HN4 via the target signal output node B, and the source of the second NMOS transistor HN2 is connected to the gate of the third NMOS transistor HN3 and the drain of the fourth NMOS transistor HN4.

[0071] The sources of the third NMOS transistor HN3 and the fourth NMOS transistor HN4 are both used to connect to the low-voltage signal input node D.

[0072] In summary, the switch control circuit 400 of this embodiment constructs a dual-terminal complementary drive architecture. This architecture utilizes the differential control of the first PMOS transistor HP1 and the second PMOS transistor HP2, combined with the source-following characteristics of the first NMOS transistor HN1 and the second NMOS transistor HN2, to convert the low-voltage control signal input at control signal input node A into a complementary drive potential in the high-voltage domain. Simultaneously, by connecting the sources of the third NMOS transistor HN3 and the fourth NMOS transistor HN4 to the low-voltage signal input node D, a floating reference potential is introduced into the control loop, thereby enabling the circuit to adaptively track changes in the input signal potential.

[0073] In some embodiments, the switch control circuit 400 can be applied to the analog switch 200. The switch control circuit 400 also includes a fifth NMOS transistor HN5. The gate of the fifth NMOS transistor HN5 is connected to the target signal output node B, the source of the fifth NMOS transistor HN5 is connected to the low-voltage signal input node D, the body of the fifth NMOS transistor HN5 is connected to the highest potential of the analog switch 200, and the drain of the fifth NMOS transistor HN5 is connected to the analog switch 200. By configuring the fifth NMOS transistor HN5 as an output stage transistor, the control signal generated by the target signal output node B can be converted into the voltage that actually drives the gate of the analog switch. Simultaneously, by connecting the body of the fifth NMOS transistor HN5 to the highest potential of the analog switch, the voltage withstand characteristic of the parasitic diode is utilized to ensure that the body potential follows the signal change when transmitting negative voltage, thereby preventing device breakdown and ensuring the reliability of the circuit under extreme voltages.

[0074] In some embodiments, the switch control circuit 400 further includes a bias unit 116. The input terminal of the bias unit 116 is connected to a low-voltage signal input node D and a high-voltage signal input node C, and the output terminal of the bias unit 116 is connected to the gate of the first NMOS transistor HN1 and the gate of the second NMOS transistor HN2. The low-voltage signal input node D and the high-voltage signal input node C are used to provide a reference high-voltage signal and a reference low-voltage signal for the analog switch 200. The bias unit 116 can perform bias processing based on the reference high-voltage signal and the reference low-voltage signal, and output a bias voltage NG to the gate of the first NMOS transistor HN1 and the gate of the second NMOS transistor HN2. In some embodiments, the reference high-voltage signal and the reference low-voltage signal of the analog switch 200 can be obtained by detecting the highest and lowest potentials among the voltage signals used for the analog switch 200.

[0075] This embodiment introduces a bias unit 116 to dynamically generate a bias signal based on the reference high voltage signal and reference low voltage signal of the analog switch 200. This ensures that the source output signals of the first NMOS transistor HN1 and the second NMOS transistor HN2 can stably follow the changes in the input signal, thereby meeting the signal transmission requirements under a wide voltage range (especially negative voltage).

[0076] Analog switch system Another embodiment of this disclosure also provides an analog switch system, which includes a switch control circuit 100 and an analog switch 200 as described in the above embodiments, so as to control the opening or closing of the analog switch 200 by the switch control circuit 100.

[0077] refer to Figure 5 For example, the analog switch 200 may include a first MOSFET 202, a second MOSFET 204, a first transmission port NO, and a second transmission port COM.

[0078] The first MOSFET 202 and the second MOSFET 204 are connected in series. The gates of the first MOSFET 202 and the second MOSFET 204 are both connected to the switch control circuit 100 to obtain the gate drive signal VG_CTRL output by the switch control circuit 100. The first transmission port NO is connected to the first MOSFET 202, and the second transmission port COM is connected to the second MOSFET 204.

[0079] In some embodiments, the first MOS transistor 202 and the second MOS transistor 204 are NMOS transistors, and the drain of the first MOS transistor 202 and the source of the second MOS transistor 204 serve as signal transmission ports NO and COM, enabling bidirectional transmission of positive and negative voltage signals.

[0080] chip Another embodiment of this disclosure provides a chip including the switch control circuit or analog switch system described in the above embodiments, to realize the opening or closing of the analog switch.

[0081] Specific embodiments of the subject matter have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0082] It should also be noted that improvements to a technology can be hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology), or even direct improvements to the hardware circuit structure. Therefore, it cannot be said that an improvement to a methodology cannot be implemented using hardware modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and fabricate dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and Verilog are the most commonly used. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0083] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0084] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A switch control circuit (100) applied to an analog switch (200), the switch control circuit (100) comprising: A signal detection module (110) is configured to detect the highest and lowest potentials among the voltage signals used for the analog switch (200) and generate a bias voltage (NG). A potential conversion module (120), which is connected to the signal detection module (110), is configured to convert a low-voltage enable signal (EN) into a high-voltage control signal based on the bias voltage; A control module (130) is connected to the signal detection module (110), the potential conversion module (120), and the analog switch (200), and is configured to output a drive signal to the analog switch (200) based on the control signal and the lowest potential, so as to drive the analog switch (200) to open or close.

2. The switch control circuit (100) according to claim 1, wherein, The signal detection module (110) includes: A high-voltage comparison unit (112) is configured to acquire multiple high-voltage signals for the analog switch (200), perform potential comparison, and output the highest potential (VH) among the multiple high-voltage signals. A low-voltage comparison unit (114) is configured to acquire a plurality of low-voltage signals for the analog switch (200), perform a potential comparison, and output the lowest potential (VL) among the plurality of low-voltage signals. The bias unit (116) is connected to the high voltage comparator (112) and the low voltage comparator (114) and is configured to acquire the highest potential (VH) and the lowest potential (VL) and perform bias processing to output a bias voltage (NG).

3. The circuit of claim 2, wherein, The analog switch (200) includes two MOSFETs connected in series and two transmission ports (NO, COM); The plurality of high-voltage signals include: power supply voltage signal (VS), high-voltage drive signal (VCP), and switch feedback signal (VMID). The high-voltage drive signal (VCP) is used to characterize the charge pump output voltage when the enable signal (EN) is at a high potential. The switch feedback signal (VMID) characterizes the reference voltage at the series node of the two MOS transistors. The plurality of low-voltage signals include ground signal (GS) and two port signals corresponding to the two transmission ports.

4. The circuit according to claim 2, wherein, The bias unit (116) further includes: A voltage regulator (118) is configured to limit the bias voltage (NG) output by the bias unit (116) within a preset voltage range.

5. The circuit according to claim 2, wherein, The potential conversion module (120) includes: An inverter (122) is configured to acquire the enable signal (EN) and invert it to output an inverted enable signal (ENB). A conversion unit (124), which is connected to the inverter (122) and the bias unit (116), is configured to selectively raise the potential of a first control signal (VC1) or a second control signal (VC2) according to the enable signal (EN), the inverting enable signal (ENB) and the bias voltage (NG).

6. The circuit of claim 5, wherein, The conversion unit (124) includes: A potential converter (126) is connected to the inverter (122) and configured to acquire the enable signal (EN) and the inverting enable signal (ENB), output a second high voltage signal (N2) when the enable signal (EN) is at a low potential, and output a first high voltage signal (N1) when the enable signal (EN) is at a high potential. A potential regulator (128), which is connected to the signal detection module (110) and the potential converter (126), is configured to raise the potential of the second control signal (VC2) based on the bias voltage (NG) when the potential converter (126) outputs a first high voltage signal (N1), or to raise the potential of the first control signal (VC1) when the potential converter (126) outputs a second high voltage signal (N2).

7. The circuit of claim 6, wherein, The potential converter (126) includes a first PMOS transistor (HP1) and a second PMOS transistor (HP2); The source of the first PMOS transistor (HP1) and the source of the second PMOS transistor (HP2) are both connected to the power supply voltage (VS). The gate of the first PMOS transistor (HP1) is connected to the inverter (122) to obtain the inverting enable signal (ENB), and the gate of the second PMOS transistor (HP2) is used to obtain the enable signal (EN). The body terminal of the first PMOS transistor (HP1) is shorted to its source, and the body terminal of the second PMOS transistor (HP2) is shorted to its source. When the enable signal (EN) is at a low potential, the first PMOS transistor (HP1) is turned off and the second PMOS transistor (HP2) is turned on, and the second high voltage signal (N2) is output through the drain of the second PMOS transistor (HP2); when the enable signal (EN) is at a high potential, the first PMOS transistor (HP1) is turned on and the second PMOS transistor (HP2) is turned off, and the first high voltage signal (N1) is output through the drain of the first PMOS transistor (HP1).

8. The circuit of claim 7, wherein, The potential regulator (128) includes a first NMOS transistor (HN1) and a second NMOS transistor (HN2); The gates of the first NMOS transistor (HN1) and the second NMOS transistor (HN2) are respectively connected to the signal detection module (110) to obtain the bias voltage (NG). The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor (HP1), and the drain of the second NMOS transistor (HN2) is connected to the drain of the second PMOS transistor (HP2). The body terminals of the first NMOS transistor (HN1) and the second NMOS transistor (HN2) are both connected to the power supply voltage (VS). The source of the first NMOS transistor (HN1) outputs the first control signal (VC1), and the source of the second NMOS transistor (HN2) outputs the second control signal (VC2). When the first PMOS transistor (HP1) outputs the first high voltage signal (N1), the potential of the first control signal (VC1) output from the source of the first NMOS transistor (HN1) is raised; when the second PMOS transistor (HP2) outputs the second high voltage signal (N2), the potential of the second control signal (VC2) output from the source of the second NMOS transistor (HN2) is raised.

9. The circuit of claim 5, wherein, The control module (130) includes: The control unit (132), which is connected to the low voltage comparison unit (114) and the conversion unit (124), is configured to selectively pull down the potential of the first control signal (VC1) or the second control signal (VC2) based on the lowest potential (VL).

10. The circuit of claim 9, wherein, The control unit (132) includes a third NMOS transistor (HN3) and a fourth NMOS transistor (HN4). The source of the third NMOS transistor (HN3) and the source of the fourth NMOS transistor (HN4) are both connected to the low-voltage comparator unit (114). The body terminals of the third NMOS transistor (HN3) and the fourth NMOS transistor (HN4) are both connected to the power supply voltage (VS). The gate of the third NMOS transistor (HN3) and the drain of the fourth NMOS transistor (HN4) are connected to the conversion unit (124) to obtain the second control signal (VC2) output by the conversion unit (124). The drain of the third NMOS transistor (HN3) and the gate of the fourth NMOS transistor (HN4) are connected to the conversion unit (124) to obtain the first control signal (VC1) output by the conversion unit (124). When the potential of the second control signal (VC2) is raised, the third NMOS transistor (HN3) is turned on to pull down the potential of the first control signal (VC1) based on the lowest potential (VL); when the potential of the first control signal (VC1) is raised, the fourth NMOS transistor (HN4) is turned on to pull down the potential of the second control signal (VC2) based on the lowest potential (VL).

11. The circuit according to claim 9, wherein, The control module (130) includes: A drive unit (134) is connected to the low-voltage comparator unit (114), the conversion unit (124), the control unit (132), and the analog switch (200), and is configured to acquire the lowest potential (VL), the first control signal (VC1), and the second control signal (VC2), and output the drive signal to the analog switch (200).

12. The circuit according to claim 11, wherein, The driving unit (134) includes a fifth NMOS transistor (HN5), and the driving signal includes a gate driving signal (VG_CTRL). The gate of the fifth NMOS transistor (HN5) is connected to the conversion unit (124) and the control unit (132) to acquire the first control signal (VC1). The source of the fifth NMOS transistor (HN5) is connected to the low-voltage comparator (114) to obtain the lowest potential (VL). The body terminal of the fifth NMOS transistor (HN5) is used to connect to the highest potential of the analog switch (200); The drain of the fifth NMOS transistor (HN5) is connected to the gate of the analog switch (200) and is used to output a gate drive signal (VG_CTRL) to the analog switch (200).

13. A switching control circuit (400) comprising: Inverter (122), first PMOS transistor (HP1), second PMOS transistor (HP2), first NMOS transistor (HN1), second NMOS transistor (HN2), third NMOS transistor (HN3) and fourth NMOS transistor (HN4); The input terminal of the inverter (122) is used to connect to the control signal input node (A). The gate of the first PMOS transistor (HP1) is connected to the output terminal of the inverter (122), and the gate of the second PMOS transistor (HP2) is used to connect to the control signal input node (A). The source of the first PMOS transistor (HP1) and the source of the second PMOS transistor (HP2) are both connected to the power supply voltage (VS). The body terminal of the first PMOS transistor (HP1) is shorted to its source, and the body terminal of the second PMOS transistor (HP2) is shorted to its source. The drain of the first PMOS transistor (HP1) is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor (HP2) is connected to the drain of the second NMOS transistor (HN2). The gates of the first NMOS transistor (HN1) and the second NMOS transistor (HN2) are used to acquire bias voltage signals. The body terminals of the first NMOS transistor (HN1) and the second NMOS transistor (HN2) are both connected to the power supply voltage (VS). The source of the first NMOS transistor (HN1) is connected to the drain of the third NMOS transistor (HN3) and the gate of the fourth NMOS transistor (HN4) via the target signal output node (B). The source of the second NMOS transistor (HN2) is connected to the gate of the third NMOS transistor (HN3) and the drain of the fourth NMOS transistor (HN4). The source of the third NMOS transistor (HN3) and the source of the fourth NMOS transistor (HN4) are both used to connect to the low-voltage signal input node (D).

14. The circuit according to claim 13, wherein, The circuit is applied to an analog switch (200), and the circuit also includes a fifth NMOS transistor (HN5); The gate of the fifth NMOS transistor (HN5) is connected to the target signal output node (B). The source of the fifth NMOS transistor (HN5) is used to connect to the low-voltage signal input node (D). The body terminal of the fifth NMOS transistor (HN5) is used to connect to the highest potential of the analog switch (200); The drain of the fifth NMOS transistor (HN5) is used to connect to the analog switch (200).

15. The circuit of claim 14, wherein, The circuit also includes: The bias unit (116) is used to connect the low-voltage signal input node (D), the high-voltage signal input node (C), the gate of the first NMOS transistor (HN1), and the gate of the second NMOS transistor (HN2).

16. An analog switch system comprising a switch control circuit (100) and an analog switch (200) according to any one of claims 1 to 15, for controlling the opening or closing of the analog switch (200) by the switch control circuit (100).

17. The system of claim 16, wherein, The analog switch (200) includes: First MOSFET (202), second MOSFET (204), first transmission port (NO), and second transmission port (COM); The first MOSFET (202) and the second MOSFET (204) are connected in series. The gate of the first MOSFET (202) and the gate of the second MOSFET (204) are both connected to the switch control circuit (100). The first transmission port (NO) is connected to the first MOSFET (202), and the second transmission port (COM) is connected to the second MOSFET (204). The first transmission port (NO) and the second transmission port (COM) are configured to transmit positive voltage signals or negative voltage signals.

18. A chip comprising a switch control circuit (100) according to any one of claims 1 to 15 or an analog switch system according to any one of claims 16 to 17.

Images