Schottky diode and semiconductor integrated device
By employing a long strip connection structure in the Schottky diode, the leakage problem caused by the circular through-hole connection is solved, the contact interface uniformity and circuit stability of the Schottky diode are improved, and the etching rate is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CSMC TECH FAB2 CO LTD
- Filing Date
- 2024-12-25
- Publication Date
- 2026-06-26
AI Technical Summary
In the manufacturing process of Schottky diodes, the circular through-hole connection method can easily cause the contact layer on the substrate surface to be penetrated during the etching process, which can damage the integrity of the Schottky junction and lead to leakage problems.
A long strip-shaped connection structure is adopted to ensure that the ratio of the first dimension to the second dimension of the connection structure is not less than 25, thereby reducing the etching rate, improving the uniformity of the contact interface, and preventing the contact layer from being etched through.
It effectively improves the leakage current phenomenon of Schottky diodes, enhances the uniformity of the contact interface between the connection structure and the contact layer, reduces the etching rate, and reduces energy loss and circuit instability.
Smart Images
Figure CN122294514A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a Schottky diode and semiconductor integrated device. Background Technology
[0002] In the field of modern electronics, diodes play a crucial role as fundamental electronic components. Schottky barrier diodes (SBDs), with their unique metal-semiconductor junction principle, exhibit significant advantages over traditional PN junction diodes. Their lower forward voltage drop and faster switching speed make them the preferred device for many high-speed electronic applications, such as high-frequency communication circuits, fast switching power supplies, and high-speed digital circuits, with broad application prospects.
[0003] However, current Schottky diode manufacturing processes face a challenging problem. Regarding the anode connection, circular vias are typically used to establish contact between the metal and the substrate, forming a Schottky barrier. While this via connection method is theoretically feasible, it exhibits significant drawbacks in practical manufacturing environments. For instance, due to limitations in process precision and various complex factors, circular vias are highly susceptible to penetrating the contact layer on the substrate surface during etching, thereby compromising the integrity of the Schottky junction and leading to leakage current issues. Summary of the Invention
[0004] Therefore, it is necessary to provide a Schottky diode and semiconductor integrated device to address the above problems.
[0005] To achieve the above objectives, in a first aspect, embodiments of this application provide a Schottky diode, comprising:
[0006] A substrate, wherein a first doped region and a first lead-out region are arranged at intervals within the substrate;
[0007] A first contact layer is disposed on the substrate, and the orthographic projection of the first contact layer on the substrate covers the first doped region.
[0008] A first dielectric layer is disposed on the first contact layer;
[0009] The cathode structure is electrically connected to the first lead-out area;
[0010] Multiple connection structures are disposed through the first dielectric layer and connected to the first contact layer; the multiple connection structures are arranged at intervals.
[0011] The anode is connected to the side of the plurality of connection structures away from the substrate;
[0012] Wherein, the orthographic projection of each of the connection structures on the substrate is a first orthographic projection, the dimension of the first orthographic projection along a first direction is a first dimension, and the dimension of the first orthographic projection along a second direction is a second dimension; the ratio of the first dimension to the second dimension is greater than or equal to 25; and the first direction and the second direction intersect.
[0013] The Schottky diode provided in this application embodiment has a long, narrow shape for the connection structure by ensuring that the ratio of the first and second dimensions of the orthographic projection of the connection structure is not less than 25. Compared to the traditional cylindrical connection structure, the connection structure in this application embodiment has a larger size, meaning the contact holes (used to fill the connection structure) in the first dielectric layer are larger. This allows for a slower etching rate during the etching of the first dielectric layer, mitigating the problem of the first contact layer being etched through due to excessively fast etching. This results in better uniformity of the contact interface between the connection structure and the first contact layer, which helps to improve the leakage current phenomenon of the Schottky diode.
[0014] In one embodiment, the first direction and the second direction are perpendicular;
[0015] And / or, the orthographic projection shape of each of the connection structures on the substrate is rectangular;
[0016] And / or, the ratio of the first dimension to the second dimension is less than or equal to 100.
[0017] In one embodiment, the plurality of connection structures are arranged at intervals along the second direction.
[0018] In one embodiment, the distance between the orthographic projections of any two adjacent connection structures onto the substrate is a first spacing.
[0019] The ratio of the second dimension to the first spacing is between 0.5 and 5.
[0020] In one embodiment, the dimension of the first doped region along the first direction is a third dimension, and the ratio of the third dimension to the first dimension is between 1.3 and 9.
[0021] In one embodiment, the plurality of connection structures are arranged in multiple rows along the first direction and in multiple columns along the second direction.
[0022] In one embodiment, the Schottky diode further includes:
[0023] The first buried doped region is disposed within the substrate and is located on the side of the first doped region and the first lead-out region away from the first contact layer;
[0024] The second doped region is disposed within the substrate and spaced apart from the first doped region, and the first lead-out region is disposed within the second doped region;
[0025] A first isolation region is disposed within the substrate and located between the second doped region and the first doped region; the first isolation region is connected to the first buried doped region, and a second lead-out region is provided within the first isolation region, and the cathode structure is electrically connected to the second lead-out region;
[0026] The second isolation region is disposed within the substrate and located on the side of the second doped region away from the first doped region; the second isolation region is connected to the first buried doped region, and a third lead-out region is provided within the second isolation region, and the cathode structure is electrically connected to the third lead-out region.
[0027] In one embodiment, the Schottky diode further includes:
[0028] The third doped region is disposed within the substrate and is located on the side of the second isolation region away from the first doped region;
[0029] The fourth lead-out region is located within the third doping region;
[0030] The substrate lead-out structure is electrically connected to the fourth lead-out region;
[0031] The voltage-resistant doped region is located on the side of the first isolation region closest to the first doped region.
[0032] Secondly, embodiments of this application provide a semiconductor integrated device, including:
[0033] The Schottky diode in any embodiment of the first aspect; and
[0034] A laterally diffused metal-oxide-semiconductor device is disposed on the substrate of the Schottky diode; the laterally diffused metal-oxide-semiconductor device includes a floating field plate, and the connection structure of the Schottky diode is disposed in the same layer as the floating field plate.
[0035] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes:
[0036] A drift region is provided within the substrate;
[0037] The body region is located within the drift region;
[0038] The source region is located within the body region;
[0039] The leakage area is located within the drift area;
[0040] A gate is disposed on the substrate;
[0041] A barrier layer is disposed on the substrate; the orthogonal projection of the barrier layer on the substrate covers a portion of the drift region; the floating field plate is disposed on the side of the barrier layer away from the substrate;
[0042] The source lead-out structure is electrically connected to the source region and the floating field plate.
[0043] The semiconductor integrated device provided in this application embodiment, by ensuring that the ratio of the first and second dimensions of the orthographic projection of the Schottky diode's connection structure is not less than 25, effectively makes the connection structure elongated. Compared to the traditional cylindrical connection structure, the connection structure in this application embodiment has a larger size, meaning the contact holes (used to fill the connection structure) in the first dielectric layer are larger. This allows for a lower etching rate during the etching of the first dielectric layer, mitigating the problem of the first contact layer being etched through due to excessively high etching rates. This results in better uniformity of the contact interface between the connection structure and the first contact layer, helping to improve the leakage current phenomenon of the Schottky diode. Furthermore, by placing the Schottky diode's connection structure and the floating field plate of the laterally diffused metal-oxide-semiconductor device in the same layer, the fabrication process of the connection structure can be compatible with existing floating field plate fabrication processes. That is, the connection structure and the floating field plate are fabricated simultaneously in the same process. Therefore, not only is there no need to add new photolithography steps, but there is also no need to adjust the etching menu, which helps reduce costs. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a schematic diagram of the cross-sectional structure of a Schottky diode provided in an embodiment of this application.
[0046] Figure 2 for Figure 1 The diagram shows a top view of the connection structure and the first doped region of the Schottky diode.
[0047] Figure 3 for Figure 1 The diagram shows another top view of the connection structure of the Schottky diode and the first doped region.
[0048] Figure 4 for Figure 1 The diagram shows another top view of the connection structure of the Schottky diode and the first doped region.
[0049] Figure 5 for Figure 1 The diagram shows another top view of the connection structure of the Schottky diode and the first doped region.
[0050] Figure 6 This is a schematic cross-sectional view of a laterally diffused metal-oxide-semiconductor device provided in an embodiment of this application.
[0051] Explanation of reference numerals in the attached figures:
[0052] 1. Schottky diode; 11. Substrate; 12. First contact layer; 13. Cathode structure; 14. Connection structure; 15. Anode; 16. Substrate lead-out structure; 171. First doped region; 172. First lead-out region; 173. First buried doped region; 174. Second doped region; 175. First isolation region; 176. Second lead-out region; 177. Second isolation region; 178. Third lead-out region; 179. Third doped region; 1710. Fourth lead-out region; 1711. Voltage-resistant doped region; 18. First isolation structure; 19. First dielectric layer;
[0053] 2. Laterally diffused metal-oxide-semiconductor device; 21. Floating field plate; 22. Gate; 23. Barrier layer; 24. Source lead-out structure; 25. Gate lead-out structure; 26. Drain lead-out structure; 271. Drift region; 272. Body region; 273. Source region; 274. Drain region; 275. Fifth lead-out region; 276. Second buried doped region; 277. Fourth doped region; 278. Fifth doped region; 279. Third isolation region; 2710. Sixth lead-out region; 28. Second isolation structure; 29. Second dielectric layer. Detailed Implementation
[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0057] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0058] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0059] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.
[0060] As described in the background section, in related technologies, circular vias are used to achieve contact between the metal and the substrate to form a Schottky barrier. However, due to the influence of process precision and various complex factors in the manufacturing process, circular vias are prone to penetrating the contact layer on the substrate surface during etching, thereby compromising the integrity of the Schottky junction and causing leakage current problems. This leakage current phenomenon not only reduces the operating efficiency of the Schottky diode and increases energy loss, but may also cause circuit instability, seriously affecting the overall performance and reliability of electronic devices or systems containing Schottky diodes. In today's increasingly demanding electronic device performance requirements, this leakage current problem caused by process structure has become a key bottleneck restricting the further widespread application and performance improvement of Schottky diodes. An innovative process improvement solution is urgently needed to solve this problem, in order to promote the continuous development and optimization of Schottky diodes in the field of electronic technology.
[0061] In view of this, embodiments of this application provide a Schottky diode and a semiconductor integrated device. By ensuring that the ratio of the first dimension and the second dimension of the orthographic projection of the connection structure of the Schottky diode is not less than 25, the connection structure is effectively elongated. Compared to the traditional cylindrical connection structure, the connection structure of this embodiment is larger, meaning the contact holes (used to fill the connection structure) in the first dielectric layer are larger. This allows for a slower etching rate during the etching of the first dielectric layer, mitigating the problem of the first contact layer being etched through due to excessively fast etching. This results in better uniformity of the contact interface between the connection structure and the first contact layer, which helps to improve the leakage current phenomenon of the Schottky diode.
[0062] Firstly, referring to Figures 1-5As shown, this application embodiment provides a Schottky diode 1, which includes a substrate 11, a first contact layer 12, a first dielectric layer 19, a cathode structure 13, a plurality of connection structures 14, and an anode 15. The substrate 11 has first doped regions 171 and first lead-out regions 172 arranged at intervals. The first contact layer 12 is disposed on the substrate 11, and its orthogonal projection on the substrate 11 covers the first doped regions 171. Specifically, the first contact layer 12 is disposed on the surface of the front side of the substrate 11. The first dielectric layer 19 is disposed on the first contact layer 12. The cathode structure 13 is electrically connected to the first lead-out region 172. The plurality of connection structures 14 pass through the first dielectric layer 19 and are connected to the first contact layer 12; further, the plurality of connection structures 14 are arranged at intervals. The anode 15 is connected to the side of the plurality of connection structures 14 away from the substrate 11; in other words, the anode 15 is disposed on the side of the first dielectric layer 19 away from the substrate 11 and is connected to the plurality of connection structures 14.
[0063] Among them, reference Figure 2 As shown, the orthographic projection of each connection structure 14 onto the substrate 11 is a first orthographic projection. The dimension of the first orthographic projection along the first direction X is a first dimension L1, and the dimension of the first orthographic projection along the second direction Y is a second dimension L2. The ratio of the first dimension L1 to the second dimension L2 is greater than or equal to 25. The first direction X and the second direction Y intersect. For example, the ratio of the first dimension L1 to the second dimension L2 can be 25, 30, 50, 60, 80, 90, 100, etc.
[0064] In one example, the first dimension L1 is the length of the first orthographic projection, and the second dimension L2 is the width of the first orthographic projection. Since the ratio of the first dimension L1 to the second dimension L2 is not less than 25, the connecting structure 14 appears elongated from a top view. It is understood that the first dielectric layer 19 has contact holes, and the connecting structure 14 passes through these contact holes. The shape of the contact holes matches the shape of the connecting structure 14; furthermore, from a top view, the contact holes also appear elongated.
[0065] It should be noted that the substrate 11 and the first lead-out region 172 are P-type, and the first doped region 171 is N-type.
[0066] The Schottky diode 1 provided in this application embodiment has an elongated shape for the connection structure 14. Compared to the conventional cylindrical connection structure 14, the elongated connection structure 14 has a larger size, meaning the contact holes in the first dielectric layer 19 are larger. This allows for a slower etching rate during the etching of the first dielectric layer 19, mitigating the problem of the first contact layer 12 being etched through due to excessively fast etching. This results in better uniformity of the contact interface between the connection structure 14 and the first contact layer 12, which helps to improve the leakage current phenomenon of the Schottky diode 1.
[0067] In one embodiment, the first direction X and the second direction Y are perpendicular.
[0068] It should be noted that the embodiments of this application do not impose special limitations on the first direction X and the second direction Y, as long as both the first direction X and the second direction Y are perpendicular to the thickness direction of the substrate 11. In one example, please refer to... Figure 2 As shown, the first direction X is Figure 2 The horizontal direction, the second direction Y is Figure 2 The vertical direction in the image. See another example. Figure 3 As shown, the first direction X is Figure 3 The vertical direction in the middle, the second direction Y is Figure 3 The horizontal direction in the middle.
[0069] In one embodiment, the orthographic projection of each connection structure 14 onto the substrate 11 is rectangular. This allows the connection structure 14 to have a more regular shape, and the openings on the mask are also more regular, which is beneficial for mask fabrication.
[0070] In one embodiment, the ratio of the first dimension L1 to the second dimension L2 is less than or equal to 100, that is, the ratio of the first dimension L1 to the second dimension L2 is not greater than 100. In this way, the ratio of the first dimension L1 to the second dimension L2 can be avoided from being too large, thereby increasing the photolithography precision and increasing the manufacturing difficulty.
[0071] In one embodiment, such as Figure 2 , Figure 3 and Figure 4 As shown, the multiple connection structures 14 are arranged at intervals along the second direction Y. This allows each connection structure 14 to be longer, resulting in a larger contact hole size, further reducing the etching rate and the risk of over-etching.
[0072] In one embodiment, such as Figure 2 and Figure 3 As shown, the first dimension L1 of each connecting structure 14 is equal. This ensures good dimensional consistency among all connecting structures 14, facilitating layout design.
[0073] In one embodiment, such as Figure 4 As shown, in all the connection structures 14, at least two connection structures 14 have different first dimensions L1. This allows designers to make differentiated designs according to the actual situation.
[0074] In one embodiment, such as Figures 2-5As shown, the second dimension L2 of each connecting structure 14 is equal. This ensures good dimensional consistency among all connecting structures 14, facilitating layout design.
[0075] In one embodiment, at least two of the connection structures 14 have unequal second dimensions L2. This allows designers to customize designs according to specific requirements.
[0076] In one embodiment, reference Figure 2 As shown, the distance between the orthographic projections of any two adjacent connection structures 14 onto the substrate 11 is the first spacing S, and the ratio of the second dimension L2 to the first spacing S is between 0.5 and 5. For example, the ratio of the second dimension L2 to the first spacing S can be 0.5, 1, 1.5, 2, 3, 4, 4.8, 5, or between any two of the above values.
[0077] If the ratio of the second dimension L2 to the first spacing S is less than 0.5, it indicates that the first spacing S is too large, resulting in a smaller number of connection structures 14 within a limited area, which in turn leads to a larger resistance between the anode 15 and the first contact layer 12. If the ratio of the second dimension L2 to the first spacing S is greater than 5, it indicates that the first spacing S is too small, which makes it easy for adjacent contact holes to connect during the etching process.
[0078] In one embodiment, such as Figure 2 As shown, the first doped region 171 has a third dimension L3 along the first direction X, and the ratio of the third dimension L3 to the first dimension L1 is between 1.3 and 9. For example, the ratio of the third dimension L3 to the first dimension L1 can be 1.3, 2, 3, 4.5, 6, 7.2, 8, 9 or between any two of the above values.
[0079] If the ratio of the third dimension L3 to the first dimension L1 is less than 1.3, it indicates that the first dimension L1 is too large. In the process of making the contact hole, the alignment accuracy of the mask and the area where the first doped region 171 is located needs to be high to ensure that the connection structure 14 can form effective contact. This places high demands on the process and increases the difficulty of manufacturing. If the ratio of the third dimension L3 to the first dimension L1 is greater than 9, it indicates that the first dimension L1 is too small. In this case, the overall size of the contact hole is too small, which is not conducive to reducing the etching rate.
[0080] In one embodiment, the plurality of connection structures 14 are arranged in multiple rows along a first direction X and in multiple columns along a second direction Y. Specifically, with Figure 5For example, all the connection structures 14 are arranged in at least two columns, each column including several connection structures 14. In this way, more connection structures 14 can be arranged in a limited area, and when a connection structure 14 fails or is damaged, the impact on the connection resistance between the anode 15 and the first contact layer 12 is small.
[0081] In one embodiment, such as Figure 1 As shown, the Schottky diode 1 also includes a first buried doped region 173, a second doped region 174, a first isolation region 175, a second isolation region 177, a second lead-out region 176, and a third lead-out region 178 disposed inside the substrate 11.
[0082] The first buried doped region 173 is located on the side of the first doped region 171 and the first lead-out region 172 away from the first contact layer 12. The second doped region 174 is spaced apart from the first doped region 171, and the first lead-out region 172 is located within the second doped region 174. The first isolation region 175 is located between the second doped region 174 and the first doped region 171. The first isolation region 175 is connected to the first buried doped region 173, and the second lead-out region 176 is located within the first isolation region 175. The cathode structure 13 is electrically connected to the second lead-out region 176. The second isolation region 177 is located on the side of the second doped region 174 away from the first doped region 171, and the second isolation region 177 is connected to the first buried doped region 173. The third lead-out region 178 is located within the second isolation region 177, and the cathode structure 13 is electrically connected to the third lead-out region 178.
[0083] Furthermore, the first buried doped region 173, the first isolation region 175, the second isolation region 177, the second lead-out region 176 and the third lead-out region 178 are all N-type, and the second doped region 174 is P-type.
[0084] In one embodiment, the Schottky diode 1 further includes a third doped region 179, a fourth lead-out region 1710, a substrate lead-out structure 16, and a voltage-resistant doped region 1711. The third doped region 179 is disposed within the substrate 11 and is located on the side of the second isolation region 177 opposite to the first doped region 171. The fourth lead-out region 1710 is disposed within the third doped region 179; the substrate lead-out structure 16 is electrically connected to the fourth lead-out region 1710. The voltage-resistant doped region 1711 is disposed on the side of the first isolation region 175 near the first doped region 171. The first buried doped region 173 is connected to the first doped region 171, the second doped region 174, and the third doped region 179, respectively.
[0085] Furthermore, the third doped region 179, the fourth lead-out region 1710, and the breakdown voltage doped region 1711 are P-type.
[0086] It should be noted that, viewed from the top of the substrate 11, the first isolation region 175, the second isolation region 177, the second doped region 174, the third doped region 179, and the voltage-resistant doped region 1711 can be annular in shape.
[0087] In one embodiment, the Schottky diode 1 further includes a plurality of first isolation structures 18, wherein, as shown in the figure... Figure 1 As shown, a first isolation structure 18 is provided on both sides of the first isolation region 175, a first isolation structure 18 is provided on both sides of the second doped region 174, a first isolation structure 18 is provided on both sides of the second isolation region 177, and a first isolation structure 18 is provided on both sides of the third doped region 179.
[0088] Secondly, such as Figure 6 As shown, this application provides a semiconductor integrated device, which includes a Schottky diode 1 and a laterally diffused metal-oxide-semiconductor device 2 as described in the first aspect embodiment. The laterally diffused metal-oxide-semiconductor device 2 and the Schottky diode 1 share the same substrate 11, that is, the laterally diffused metal-oxide-semiconductor device 2 is disposed on the substrate 11 of the Schottky diode 1. The laterally diffused metal-oxide-semiconductor device 2 includes a floating field plate 21, and the connection structure 14 of the Schottky diode 1 is disposed on the same layer as the floating field plate 21. It should be noted that the floating field plate 21 in this application embodiment can also be referred to as a contact floating plate.
[0089] The semiconductor integrated device provided in this application embodiment, by ensuring that the ratio of the first dimension and the second dimension of the orthographic projection of the connection structure 14 of the Schottky diode 1 is not less than 25, is equivalent to making the connection structure 14 elongated. Compared with the traditional cylindrical connection structure 14, the connection structure 14 of this application embodiment has a larger size, that is, the size of the contact hole in the first dielectric layer 19 is larger. Thus, during the etching process of the first dielectric layer 19, the etching rate can be reduced, which can improve the phenomenon that the first contact layer 12 is etched through due to an excessively fast etching rate. This results in better uniformity of the contact interface between the connection structure 14 and the first contact layer 12, which helps to improve the leakage current phenomenon of the Schottky diode 1. Furthermore, by setting the connection structure 14 of the Schottky diode 1 and the floating field plate 21 of the laterally diffused metal-oxide-semiconductor device 2 in the same layer, the fabrication process of the connection structure 14 can be made compatible with the existing fabrication process of the floating field plate 21. That is, the connection structure 14 and the floating field plate 21 are fabricated simultaneously in the same process. Therefore, not only is it unnecessary to add new photolithography steps, but it is also unnecessary to adjust the etching menu, which helps to reduce costs.
[0090] In one embodiment, the laterally diffused metal-oxide-semiconductor device 2 further includes a drift region 271, a body region 272, a source region 273, a drain region 274, a gate 22, a barrier layer 23, and a source lead-out structure 24. The drift region 271 is disposed within the substrate 11. The body region 272 is disposed within the drift region 271. The source region 273 is disposed within the body region 272. The drain region 274 is disposed within the drift region 271 and spaced apart from the body region 272. The gate 22 is disposed on the substrate 11. The barrier layer 23 is disposed on the substrate 11, and the orthogonal projection of the barrier layer 23 onto the substrate 11 covers a portion of the drift region 271. A floating field plate 21 is disposed on the side of the barrier layer 23 away from the substrate 11. The source lead-out structure 24 is electrically connected to the source region 273 and the floating field plate 21.
[0091] Furthermore, drift region 271, leak region 274, and source region 273 are N-type, while body region 272 is P-type.
[0092] In one embodiment, an oxide layer (not shown) is provided between the barrier layer 23 and the substrate 11.
[0093] In one embodiment, the substrate 11 further comprises a fourth doped region 277, a fifth doped region 278, and a fifth lead-out region 275. The fourth doped region 277 and the drift region 271 are spaced apart. The fifth doped region 278 is disposed within the fourth doped region 277, and the fifth lead-out region 275 is disposed within the fifth doped region 278. The source lead-out structure 24 is also electrically connected to the fifth lead-out region 275. Further, the substrate 11 also comprises a second buried doped region 276, a third isolation region 279, and a sixth lead-out region 2710. The third isolation region 279 is disposed on the side of the fourth doped region 277 away from the drift region 271. The sixth lead-out region 2710 is disposed within the third isolation region 279. The second buried doped region 276 is disposed at the bottom of the drift region 271, with a certain gap between the second buried doped region 276 and the drift region 271. The second buried doped region 276 is connected to both the fourth doped region 277 and the third isolation region 279.
[0094] Among them, the fourth doped region 277, the fifth doped region 278 and the fifth lead-out region 275 are P-type, and the second buried doped region 276, the third isolation region 279 and the sixth lead-out region 2710 are N-type.
[0095] Furthermore, the laterally diffused metal-oxide-semiconductor device 2 also includes a gate lead structure 25, a drain lead structure 26, a second isolation structure 28, and a second dielectric layer 29. The second dielectric layer 29 is disposed on the substrate 11. The source lead structure 24, the gate lead structure 25, and the drain lead structure 26 all penetrate the second dielectric layer 29. The gate lead structure 25 is electrically connected to the gate 22, and the drain lead structure 26 is electrically connected to the drain region 274 and the sixth lead region 2710. A second isolation structure 28 is provided on both sides of the fourth doped region 277, and a second isolation structure 28 is provided on both sides of the third isolation region 279.
[0096] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A Schottky diode, characterized in that, include: A substrate, wherein a first doped region and a first lead-out region are arranged at intervals within the substrate; A first contact layer is disposed on the substrate, and the orthographic projection of the first contact layer on the substrate covers the first doped region. A first dielectric layer is disposed on the first contact layer; The cathode structure is electrically connected to the first lead-out area; Multiple connection structures are disposed through the first dielectric layer and connected to the first contact layer; The plurality of connection structures are arranged at intervals; The anode is connected to the side of the plurality of connection structures away from the substrate; Wherein, the orthographic projection of each of the connecting structures on the substrate is a first orthographic projection, the dimension of the first orthographic projection along a first direction is a first dimension, and the dimension of the first orthographic projection along a second direction is a second dimension; The ratio of the first dimension to the second dimension is greater than or equal to 25; the first direction and the second direction intersect.
2. The Schottky diode according to claim 1, characterized in that, The first direction and the second direction are perpendicular; And / or, the orthographic projection shape of each of the connection structures on the substrate is rectangular; And / or, the ratio of the first dimension to the second dimension is less than or equal to 100.
3. The Schottky diode according to claim 1, characterized in that, The plurality of connection structures are arranged at intervals along the second direction.
4. The Schottky diode according to claim 1, characterized in that, The distance between the orthographic projections of any two adjacent connection structures onto the substrate is the first spacing; The ratio of the second dimension to the first spacing is between 0.5 and 5.
5. The Schottky diode according to claim 1, characterized in that, The dimension of the first doped region along the first direction is a third dimension, and the ratio of the third dimension to the first dimension is between 1.3 and 9.
6. The Schottky diode according to claim 1, characterized in that, The plurality of connection structures are arranged in multiple rows along the first direction and in multiple columns along the second direction.
7. The Schottky diode according to claim 1, characterized in that, The Schottky diode also includes: The first buried doped region is disposed within the substrate and is located on the side of the first doped region and the first lead-out region away from the first contact layer; The second doped region is disposed within the substrate and spaced apart from the first doped region, and the first lead-out region is disposed within the second doped region; A first isolation region is disposed within the substrate and located between the second doped region and the first doped region; the first isolation region is connected to the first buried doped region, and a second lead-out region is provided within the first isolation region, and the cathode structure is electrically connected to the second lead-out region; The second isolation region is disposed within the substrate and located on the side of the second doped region away from the first doped region; the second isolation region is connected to the first buried doped region, and a third lead-out region is provided within the second isolation region, and the cathode structure is electrically connected to the third lead-out region.
8. The Schottky diode according to claim 7, characterized in that, The Schottky diode also includes: The third doped region is disposed within the substrate and is located on the side of the second isolation region away from the first doped region; The fourth lead-out region is located within the third doping region; The substrate lead-out structure is electrically connected to the fourth lead-out region; The voltage-resistant doped region is located on the side of the first isolation region closest to the first doped region.
9. A semiconductor integrated device, characterized in that, include: The Schottky diode as described in any one of claims 1-8; as well as Laterally diffused metal-oxide-semiconductor device, disposed on the substrate of the Schottky diode; The laterally diffused metal-oxide-semiconductor device includes a floating field plate, and the connection structure of the Schottky diode is disposed on the same layer as the floating field plate.
10. The semiconductor integrated device according to claim 9, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes: A drift region is provided within the substrate; The body region is located within the drift region; The source region is located within the body region; The leakage area is located within the drift area; A gate is disposed on the substrate; A barrier layer is disposed on the substrate; the orthogonal projection of the barrier layer on the substrate covers a portion of the drift region; the floating field plate is disposed on the side of the barrier layer away from the substrate; The source lead-out structure is electrically connected to the source region and the floating field plate.