A semiconductor device, a manufacturing method thereof, and an electronic apparatus

Abstract

A semiconductor device and its manufacturing method, as well as an electronic device, are disclosed. The manufacturing method includes: providing a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate, and forming a metal gate structure in the interlayer dielectric layer; etching the top of the metal gate structure to form a groove in the interlayer dielectric layer located above the metal gate structure; performing a deposition process to deposit a metal material in the groove and on the interlayer dielectric layer; and removing the metal material on the interlayer dielectric layer and a portion of the metal material in the groove to obtain a metal capping layer composed of the remaining metal material. This invention uses a conventional deposition process to form the metal capping layer, is applicable to most metals, improves the feasibility and scalability of the process, significantly reduces the resistance of the metal gate structure, and improves the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] As semiconductor process nodes shrink, gate sizes continue to shrink, and gate resistance has become non-negligible. Covering the gate with a metal layer can significantly reduce resistance; the current approach involves selectively growing the metal directly on the gate. However, this approach is technically very challenging, and the types of metals available are limited. Summary of the Invention

[0003] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] To address the existing problems, one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0005] A semiconductor substrate is provided, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a metal gate structure is formed in the interlayer dielectric layer;

[0006] The top of the metal gate structure is etched to form a groove in the interlayer dielectric layer above the metal gate structure;

[0007] A deposition process is performed to deposit metallic material in the grooves and on the interlayer dielectric layer;

[0008] Remove the metal material on the interlayer dielectric layer and a portion of the metal material in the groove to obtain a metal overlay layer composed of the metal material covering the top of the metal gate structure.

[0009] In one embodiment, removing the metal material on the interlayer dielectric layer and a portion of the metal material in the groove includes:

[0010] Perform a chemical mechanical polishing process to remove the metallic material on the interlayer dielectric layer;

[0011] The metal material in the groove is etched back to remove a portion of the metal material in the groove.

[0012] In one embodiment, removing the metal material on the interlayer dielectric layer and a portion of the metal material in the groove includes:

[0013] The metal material is etched back to remove the metal material on the interlayer dielectric layer and a portion of the metal material in the groove.

[0014] In one embodiment, after forming the metal overlay, the method further includes:

[0015] A self-aligned contact hard mask layer that fills the groove is formed over the metal overlay.

[0016] In one embodiment, forming a self-aligned contact hard mask layer that fills the groove over the metal overlay includes:

[0017] A deposition process is performed to deposit a dielectric material in the grooves and on the interlayer dielectric layer;

[0018] A chemical mechanical polishing process is performed to remove the dielectric material on the interlayer dielectric layer, resulting in the self-aligned contact hard mask layer composed of the dielectric material filled in the grooves.

[0019] In one embodiment, a fin structure is formed on the semiconductor substrate, and a metal gate structure spans the fin structure.

[0020] In one embodiment, the metallic material comprises at least one of the following:

[0021] Tungsten, copper, cobalt, ruthenium, gold, aluminum.

[0022] In one embodiment, the deposition process includes at least one of the following:

[0023] Chemical vapor deposition, physical vapor deposition, and organometallic chemical vapor deposition.

[0024] A second aspect of the present invention provides a semiconductor device, which is manufactured using the method described above.

[0025] A third aspect of the present invention provides an electronic device, the electronic device comprising the semiconductor device described above.

[0026] The semiconductor device and its manufacturing method and electronic device provided by the present invention use a conventional deposition process to form a metal capping layer, which is applicable to most metals, improves the feasibility and scalability of the process, significantly reduces the resistance of the metal gate structure, and improves the performance of the semiconductor device. Attached Figure Description

[0027] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0028] In the attached image:

[0029] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0030] Figures 2A to 2G A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0032] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0034] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0036] Forming a metal capping layer on a metal gate structure can reduce the resistance of the metal gate. Currently, the method for forming the metal capping layer involves selectively growing metal layers on different materials within the metal gate structure. In one example, the materials of the metal gate structure include an interlayer dielectric layer (e.g., SiO2), a sidewall layer (e.g., Si3N4), a gate dielectric layer (e.g., HfO2), and a work function layer (e.g., TiN, TaN, TiAl). The selective growth ratio of the metal capping layer on these different materials is: SiO2:Si3N4:TiN:TaN:TiAl:HfO2 = 0:0:1:1:1:1. During selective growth, the incubation time of the precursors in different materials within the metal gate structure needs to be essentially the same to ensure the quality of the metal capping layer, making the actual process extremely challenging.

[0037] Furthermore, the aforementioned selective growth technology is not universally applicable: currently, the material for the metal capping layer is usually tungsten, and if the material for the metal capping layer is changed to other metals, the entire process needs to be redeveloped.

[0038] In view of the aforementioned technical problems, embodiments of the present invention propose a method for fabricating a semiconductor device. The following refers to... Figure 1 and Figures 2A to 2G The method for fabricating the semiconductor device according to embodiments of the present invention will be described in detail, wherein, Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. Figures 2A to 2G A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0039] First, execute step S101, as follows: Figure 2A As shown, a semiconductor substrate 201 is provided, an interlayer dielectric layer 204 is formed on the semiconductor substrate 201, and a metal gate structure 206 is formed in the interlayer dielectric layer 204.

[0040] The semiconductor substrate 201 is made of at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI).

[0041] In some embodiments, a fin structure is formed on the semiconductor substrate 201, and a metal gate structure 206 spans the fin structure. The method for forming the fin structure is not limited to any one method; one exemplary method includes: forming a hard mask layer on the semiconductor substrate 201; patterning the hard mask layer to form multiple separate hard mask patterns for etching the semiconductor substrate 201 to form fins thereon; in one embodiment, a self-aligned double-patterning process can be used to perform the patterning process; and finally, etching the semiconductor substrate 201 under the mask of the hard mask layer to form the fin structure thereon. Depending on the type of fin field-effect transistor to be formed, different types of dopant ions can be doped into the fin structure to adjust electrical parameters such as the threshold voltage of the fin field-effect transistor.

[0042] Exemplarily, a replacement metal gate (RMG) process (or post-gate process) can be used to form the metal gate structure. Specifically, a dummy gate structure is first formed sequentially on the fin structure, the dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode layer. The material of the dummy gate dielectric layer is, for example, silicon oxide. The material of the dummy gate electrode layer can include polysilicon, which can be formed using a chemical vapor deposition process. Exemplarily, a dummy gate hard mask layer is also formed on the dummy gate electrode layer, the dummy gate hard mask layer including a silicon nitride layer, a silicon oxide layer, or a stack of both. Next, the dummy gate electrode layer and the dummy gate dielectric layer are etched to form a dummy gate structure spanning the fin structure. Exemplarily, a patterned photoresist layer can be formed above the dummy gate hard mask layer, and the dummy gate hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer are sequentially etched using the photoresist layer as a mask to form the dummy gate structure.

[0043] Next, sidewall layers 205 are formed on both sides of the dummy gate structure. Exemplarily, a sidewall material layer covering the dummy gate structure is first deposited; then, the sidewall material layer is etched back until the top of the dummy gate hard mask layer is exposed, thereby forming the sidewall layer 205. The sidewall material layer includes, but is not limited to, a silicon nitride layer.

[0044] After forming the pseudo-gate structure, epitaxial source / drain structures 202 can be formed in the fin structures on both sides of the pseudo-gate structure. Specifically, the fin structure can be etched using dry etching or wet etching processes to form source / drain grooves; then, an epitaxial layer is grown in the source / drain grooves using an epitaxial process, and the epitaxial layer is doped to form the epitaxial source / drain structure 202. For example, the epitaxial source / drain structure 202 includes a SiGe layer.

[0045] A dielectric layer 204 is formed to cover the pseudo-gate structure. Exemplarily, a contact etch stop layer 203 is first formed to cover the pseudo-gate structure and the fin structure. Exemplarily, the contact etch stop layer (CESL) includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The contact etch stop layer 203 can be formed by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition processes. The interlayer dielectric layer 204 is formed above the contact etch stop layer. In some embodiments, the material of the interlayer dielectric layer includes tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophospho-silicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), or other suitable dielectric materials. The interlayer dielectric layer 204 can be deposited by PECVD or other suitable deposition processes.

[0046] Next, the dummy gate structure is removed to form a gate trench in the interlayer dielectric layer 204. This removal of the dummy gate structure can be achieved using either dry etching or wet etching processes, thereby forming the gate trench between the sidewall layers 205.

[0047] Finally, a metal gate structure 206 is formed in the gate recess. The metal gate structure 206 includes a gate dielectric layer 2061 formed on the bottom and sidewalls of the gate recess, and a metal gate stack formed on the gate dielectric layer 2061. The gate dielectric layer 2061 may be a high-k dielectric layer. Exemplarily, the material of the gate dielectric layer 2061 includes, for example, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxides of nitride (e.g., SiON), combinations thereof, or other suitable materials. For example, the gate dielectric layer 2061 can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), and thermal oxidation.

[0048] For example, the metal gate stack formed on the gate dielectric layer 2061 includes TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ti, Ag, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or combinations thereof.

[0049] Specifically, the metal gate stack may include a diffusion barrier layer 2062, a work function layer 2063, and a metal gate electrode layer 2064. The diffusion barrier layer 2062 comprises metal nitrides such as TiN and TaN, or metal carbonitrides such as titanium carbonitride. The diffusion barrier layer 2062 is used to block the diffusion effect between the gate dielectric layer 2061 and the work function layer 2063. The work function layer 2063 includes TiN, TiSiN, TiAlN, TiAl, TaAl, TaN, etc. The work function metal layer 2063 can be deposited using various deposition techniques such as ALD, PVD, CVD, PECVD, or other suitable techniques. The metal gate electrode layer 2064 includes Ti, Ag, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, and their alloys.

[0050] Next, proceed to step S102, as follows: Figure 2B As shown, the top of the metal gate structure 206 is etched to form a groove 207 in the interlayer dielectric layer 204 located above the metal gate structure 206.

[0051] In some embodiments, atomic layer etching (ALE), dry etching, wet etching, or a combination thereof can be used to etch the metal gate structure 206 back and forth. ALE uses an oxidizing agent for etching, such as ozone, hydrogen peroxide, or hydrogen fluoride. The etching gas for dry etching can include fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), argon, or combinations thereof. The etchant for wet etching includes ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), isopropanol (IPA), etc. Etching back the metal gate structure can also include a combination of various etching processes, for example, sequentially using dry etching and wet etching processes to etch back the metal gate structure. Specifically, a groove 207 is formed above the etched metal gate structure 206 and is located between the sidewall layers 205.

[0052] Next, proceed to step S103, as follows: Figure 2C As shown, a deposition process is performed to form a metallic material 208 in the groove 207 and on the interlayer dielectric layer 204.

[0053] The deposition process includes any suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), metal-organic CVD (MOCVD), and plasma-enhanced CVD (PECVD). In this embodiment of the invention, a non-selective deposition process can be used to deposit the metal material 208 to reduce process complexity. Because this embodiment of the invention uses a traditional non-selective deposition process, its process complexity is low, and there are no restrictions on the selection of the metal material 208. For example, the metal material 208 may include tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), gold (Au), aluminum (Al), etc.

[0054] Next, step S104 is performed to remove the metal material 208 located on the interlayer dielectric layer 204 and part of the metal material 208 in the groove 207, so as to obtain a metal cover layer composed of the metal material covering the top of the metal gate structure 206.

[0055] In one embodiment, firstly as Figure 2D As shown, chemical mechanical polishing (CMP) is used to remove the metal material 208 on the interlayer dielectric layer 204. CMP combines chemical reaction and mechanical polishing. During CMP, the polishing slurry undergoes a slight chemical reaction with the metal material 208 being polished, followed by mechanical polishing to remove the softened metal material 208, achieving global planarization. Performing CMP is beneficial for obtaining a flat surface morphology.

[0056] Next, as Figure 2E As shown, the metal material 208 inside the groove 207 is etched back to remove a portion of the metal material 208. Selective dry etching or wet etching processes can be used to etch back the metal material 208 inside the groove 207. For example, fluorine-based or chlorine-based gases can be used to selectively etch the metal material 208 without damaging the sidewall layers 205 and the interlayer dielectric layer 204. The remaining metal material 208 at the bottom of the groove ultimately forms a metal capping layer 208'.

[0057] In another embodiment, after the metal material 208 is formed in the groove 207 and on the interlayer dielectric layer 204, a back etching process can be directly performed to remove the metal material 208 on the interlayer dielectric layer 204 and a portion of the metal material 208 in the groove 207, thereby simplifying the process flow. Exemplarily, the back etching process may include dry etching, wet etching, or a combination of both.

[0058] For example, the metal capping layer 208' is formed only at the bottom of the groove 207 and on top of the metal gate structure 206, without completely filling the groove 207. After forming the metal capping layer 208', a self-aligned contact (SAC) hard mask layer can also be formed in the groove 207, meaning that the method of this embodiment is also compatible with the SAC process.

[0059] Specifically, the SAC process forms contact holes within a large pattern defined by photolithography by using different etching selectivity ratios for different materials. Isolation between the subsequently formed source / drain contact holes and the metal gate structure is primarily achieved through the gate sidewalls. However, as the pitch of the contact holes decreases, the source / drain contact holes formed on both sides of the metal gate structure are prone to misalignment, causing short circuits and reducing device yield. By forming a SAC hard mask layer above the metal gate structure, even if the source / drain contact holes are misaligned onto the metal gate structure, the presence of the SAC hard mask layer prevents short circuits.

[0060] For example, the step of forming a self-aligned contact hole hard mask layer includes: firstly, as shown in the figure... Figure 2F As shown, dielectric material 209 is deposited in the groove 207 above the metal capping layer 208' and on the interlayer dielectric layer 204. The dielectric material 209 exhibits etching selectivity with the interlayer dielectric layer 204, enabling the metal gate structure 206 to be protected when the interlayer dielectric layer 204 is etched to form source / drain contact vias. Exemplarily, the dielectric material 209 comprises silicon nitride.

[0061] Next, as Figure 2G As shown, a chemical mechanical polishing (CMP) process is performed to remove the dielectric material 209 on the interlayer dielectric layer 204, resulting in a self-aligned contact hard mask layer 209' composed of the dielectric material 209 filled in the groove 207.

[0062] For example, after forming the self-aligned contact hard mask layer 209', a zero-layer metal (MO) stack can be formed on the self-aligned contact hard mask layer 209' and the interlayer dielectric layer 204, and contact holes can subsequently be formed in the zero-layer metal stack. For example, the zero-layer metal stack includes an intermediate silicon nitride layer, a first PEOX (polyethylene oxide) layer, a titanium nitride hard mask layer, a second PEOX layer, and an amorphous silicon layer, etc.

[0063] Thus, the process steps of the semiconductor device manufacturing method according to the first aspect embodiment of the present invention are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0064] The semiconductor device manufacturing method provided by the embodiments of the present invention uses a conventional deposition process to form a metal capping layer, which is applicable to most metals, improves the feasibility and scalability of the process, significantly reduces the resistance of the metal gate structure, and improves the performance of the semiconductor device.

[0065] This invention also provides a semiconductor device that can be prepared by the methods described in the foregoing embodiments.

[0066] Below, for reference Figure 2G The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For a detailed explanation and description, please refer to the description in Embodiment 1.

[0067] Specifically, such as Figure 2G As shown, the semiconductor device of this embodiment includes: a semiconductor substrate 201, an interlayer dielectric layer 204 formed on the semiconductor substrate 201, a metal gate structure 206 formed in the interlayer dielectric layer 204, the top of the metal gate structure 206 being located below the surface of the interlayer dielectric layer 204; sidewall layers 205 formed on both sides of the metal gate structure 206, and a metal capping layer 208' covering the top of the metal gate structure 206 being formed between the two opposing sidewall layers 205.

[0068] Exemplarily, the upper surface of the metal capping layer 208' is located below the surface of the interlayer dielectric layer 204. A self-aligned contact hard mask layer 209' is also formed on the metal capping layer 208', located between two opposing sidewall layers 205. Exemplarily, the upper surface of the self-aligned contact hard mask layer 209' is flush with the surface of the interlayer dielectric layer 204.

[0069] The semiconductor device of the present invention is prepared by the above method, thus significantly reducing the resistance of the metal gate structure and improving the performance of the semiconductor device.

[0070] A third aspect of the present invention also provides an electronic device including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0071] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0072] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor substrate is provided, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a metal gate structure is formed in the interlayer dielectric layer; The top of the metal gate structure is etched to form a groove in the interlayer dielectric layer above the metal gate structure; A deposition process is performed to deposit metallic material in the grooves and on the interlayer dielectric layer; Remove the metal material on the interlayer dielectric layer and a portion of the metal material in the groove to obtain a metal capping layer composed of the remaining metal material.

2. The manufacturing method as described in claim 1, characterized in that, The removal of the metal material on the interlayer dielectric layer and a portion of the metal material in the groove includes: Perform a chemical mechanical polishing process to remove the metallic material on the interlayer dielectric layer; The metal material in the groove is etched back to remove a portion of the metal material in the groove.

3. The manufacturing method as described in claim 1, characterized in that, The removal of the metal material on the interlayer dielectric layer and a portion of the metal material in the groove includes: The metal material is etched back to remove the metal material on the interlayer dielectric layer and a portion of the metal material in the groove.

4. The manufacturing method as described in claim 1, characterized in that, After forming the metal coating, the method further includes: A self-aligned contact hard mask layer that fills the groove is formed over the metal overlay.

5. The manufacturing method as described in claim 4, characterized in that, The formation of a self-aligned contact hard mask layer filling the groove above the metal overlay includes: A deposition process is performed to deposit a dielectric material in the grooves and on the interlayer dielectric layer; A chemical mechanical polishing process is performed to remove the dielectric material on the interlayer dielectric layer, resulting in the self-aligned contact hard mask layer composed of the dielectric material filled in the grooves.

6. The manufacturing method as described in claim 1, characterized in that, A fin structure is formed on the semiconductor substrate, and a metal gate structure spans the fin structure.

7. The manufacturing method as described in claim 1, characterized in that, The metallic material includes at least one of the following: Tungsten, copper, cobalt, ruthenium, gold, aluminum.

8. The manufacturing method as described in claim 1, characterized in that, The deposition process includes at least one of the following: Chemical vapor deposition, physical vapor deposition, and organometallic chemical vapor deposition.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 9.

Images