Trench gate field effect transistor with low ron and method of manufacturing the same, smart electronic switch

Abstract

This application provides a trench gate field-effect transistor with low Ron, comprising: an N+ substrate, an N-type epitaxial layer, a first dielectric layer, an upper gate, a p-type substrate region, a source region, a drain, and a source. The N-type epitaxial layer and the p-type substrate region are sequentially disposed above the N+ substrate, and the drain is disposed below the N+ substrate. The first dielectric layer is located on the N-type epitaxial layer and passes through the p-type substrate region. The upper gate is disposed within the first dielectric layer and connected to the gate. The p-type substrate region, the source region, and the source are connected. The trench gate field-effect transistor further includes a lower gate and a first connecting portion. The lower gate and the first connecting portion are located within the first dielectric layer. The lower gate is located below the upper gate and is electrically connected to the upper gate through the first connecting portion. Embodiments of this application also provide a method for manufacturing a trench gate field-effect transistor and a smart electronic switch.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a low Ron trench gate field-effect transistor and its manufacturing method, and a smart electronic switch. Background Technology

[0002] Power MOSFETs, as power electronic switches, constantly switch between on and off states, generating conduction losses and switching losses. The on-resistance Ron affects conduction losses, while the gate-drain charge Qgd affects switching losses. On-resistance Ron and gate-drain charge Qgd are two important parameters characterizing the performance of power MOSFETs, and their product is called the figure of merit (FOM) of the power MOSFET.

[0003] Compared to planar gate field-effect transistors (FETs), trench gate field-effect transistors (TFETs) offer advantages such as higher device density and lower on-resistance Ron. An optimized structure of trench gate FETs is the shielded-gate trench FET, which achieves even lower on-resistance Ron and lower gate-drain charge Qgd by placing a shielded gate at the bottom of the trench. However, this comes at the cost of increased process and layout complexity, as the shielded gate needs to be led out from the terminal block to the device surface and connected to the source via a metal layer.

[0004] In low-frequency switching applications, such as intelligent electronic switches in automobiles, the switching frequency of the devices is low, and the conduction loss of the devices accounts for the majority of the losses. Therefore, reducing the on-resistance Ron of the power transistor will bring greater benefits. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of this application is to provide a low Ron trench gate field-effect transistor and its manufacturing method, which addresses the shortcomings of the prior art. The structure of this invention has a lower on-resistance than conventional trench gate field-effect transistors, has the same level of on-resistance as shielded gate field-effect transistors, and has fewer masks.

[0006] To address the aforementioned technical problems, the first aspect of this application provides a trench gate field-effect transistor with low Ron, comprising: an N+ substrate, an N-type epitaxial layer, a first dielectric layer, an upper gate, a p-type substrate region, a source region, a drain, and a source.

[0007] The N-type epitaxial layer and the p-type substrate region are sequentially disposed above the N+ substrate, the drain is disposed below the N+ substrate, the first dielectric layer is located on the N-type epitaxial layer and passes through the p-type substrate region, an upper gate is provided in the first dielectric layer, the upper gate is connected to the gate, and the p-type substrate region and the source region are connected to the source.

[0008] The trench gate field-effect transistor further includes a lower gate and a first connection portion. The lower gate and the first connection portion are located within the first dielectric layer. The lower gate is located below the upper gate and is electrically connected to the upper gate through the first connection portion.

[0009] Optionally, the upper gate includes a main body and a lower extension, the lower extension being formed by extending downward from the main body, and the lower extension partially overlapping the lower gate in the longitudinal direction;

[0010] The lower surface of the main body is higher than the lower surface of the p-type substrate region, and the lower surface of the lower extension is lower than the lower surface of the p-type substrate region.

[0011] Optionally, the first dielectric layer includes a field oxide layer, a gate oxide layer, and a spacer oxide layer, wherein the thickness of the field oxide layer is greater than the thickness of the gate oxide layer, the gate oxide layer is located on both sides of the upper gate, the spacer oxide layer is located between the upper gate and the lower gate, the field oxide layer is located between the lower gate and the N-type epitaxial layer, and the thickness of the gate oxide layer is less than the thickness of the field oxide layer.

[0012] Optionally, the trench gate field-effect transistor further includes a p-type contact region and a second connection portion. The p-type contact region is located within the p-type substrate region, and the source region is located above the p-type substrate region. The lower end of the second connection portion is connected to the p-type contact region, and the upper end of the second connection portion passes through the source region and is connected to the source electrode.

[0013] Optionally, the second connecting portion is formed simultaneously with the first connecting portion.

[0014] Optionally, the source region covers the p-type matrix region, and the second connecting portion is connected to the source region.

[0015] Optionally, the field-effect transistor further includes a second dielectric layer, which is located on the first dielectric layer and the source region. The source and the gate are located on the second dielectric layer, and the gate is connected to the upper gate via the first connection portion.

[0016] A second aspect of this application provides an intelligent electronic switch, including a power supply terminal, a power ground terminal, a load output terminal, and a switch control unit, wherein the power supply terminal is used to connect to the positive terminal of a power supply, the power ground terminal is used to connect to the negative terminal of a power supply, and the load output terminal is used to connect to a load.

[0017] It also includes the trench gate field-effect transistor mentioned above, wherein the drain of the trench gate field-effect transistor is connected to the power supply terminal or the load output terminal, its source is connected to the load output terminal or the power supply ground terminal, and its gate is connected to the switch control unit, which is used to control the trench gate field-effect transistor to turn on or turn off.

[0018] Optionally, the switch control unit is used to control the frequency at which the trench gate field-effect transistor is turned on or off to be less than or equal to 20 kHz.

[0019] A third aspect of this application provides a method for manufacturing a trench gate field-effect transistor, comprising:

[0020] An N+ substrate is provided, and an N-type epitaxial layer is formed on the N+ substrate;

[0021] The first deep trench was dug in the N-type epitaxial layer;

[0022] A first dielectric layer, a lower gate, and an upper gate are formed in the first deep trench;

[0023] A p-type matrix region is formed on the N-type epitaxial layer;

[0024] A source region is formed on the p-type matrix region;

[0025] A second dielectric layer is formed on the surface of the source region, and a second deep trench and a third deep trench are formed by trenching the second dielectric layer. The second deep trench extends downward from the surface of the second dielectric layer to the lower gate, and the third deep trench extends downward from the surface of the second dielectric layer to the p-type substrate region.

[0026] A p-type contact area, a first connecting part, and a second connecting part are formed;

[0027] A gate, source, and drain are formed, wherein the drain is located below the N+ substrate, and the gate and source are located above the N+ substrate.

[0028] Optionally, the steps of forming the p-type contact area, the first connecting portion, and the second connecting portion specifically include:

[0029] p-type impurities are simultaneously injected into the second and third deep trenches to form a p-type contact region within the p-type matrix region;

[0030] Conductive material is filled into the second deep trench and the third deep trench to form a first connection part and a second connection part respectively. The first connection part connects the lower gate to the upper gate and the upper end of the first connection part is exposed. The lower end of the second connection part is connected to the p-type contact area and the upper end of the second connection part passes through the source region and the second dielectric layer and is exposed.

[0031] Optionally, the steps of forming a first dielectric layer, a lower gate, and an upper gate in the first deep trench specifically include:

[0032] A first insulating layer is formed on the inner surface of the first deep trench and the upper surface of the N-type epitaxial layer;

[0033] A first conductive material is deposited on the surface of a first insulating layer, and the first conductive material and the first insulating layer are etched to form a lower gate and a field oxide layer, wherein the upper surface of the field oxide layer is lower than the upper surface of the lower gate.

[0034] A gate oxide layer is formed in the first deep trench, the gate oxide layer is located on the surface of the first deep trench that is not covered by the field oxide layer, and on the surface of the lower gate that is not covered by the field oxide layer, wherein the thickness of the gate oxide layer is less than the thickness of the field oxide layer;

[0035] The upper gate and gate protection layer are formed in the first deep trench.

[0036] In this embodiment, the trench gate field-effect transistor (FET) has a lower gate, an upper gate, and a first connection portion formed in the first dielectric layer. The first connection portion electrically connects the upper gate and the lower gate, with the lower gate located above the upper gate. Therefore, in this embodiment, the lower gate is equivalent to the shielding gate of a shielded gate FET, and the upper gate is equivalent to the control gate of a shielded gate FET. When the FET is turned off, both the lower gate and the shielding gate of the shielded gate FET in this embodiment have the same potential as the load output terminal. This results in better breakdown voltage performance, similar to a shielded gate FET. Consequently, the concentration of doped N-type material in the N-type epitaxial layer can be increased, thereby reducing the on-resistance and requiring fewer masks compared to a shielded gate FET. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1a This is a circuit diagram illustrating an application scenario of an intelligent electronic switch according to an embodiment of this application;

[0039] Figure 1b This is a circuit diagram illustrating an application scenario of a smart electronic switch according to another embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the structure of a trench gate field-effect transistor according to an embodiment of this application;

[0041] Figure 3a This is a manufacturing process diagram of a trench gate field-effect transistor according to an embodiment of this application;

[0042] Figure 3b yes Figure 3a Detailed flowchart of step S130;

[0043] Figures 4a-4n This is a schematic diagram of a method for manufacturing a trench gate field-effect transistor structure according to an embodiment of this application.

[0044] Figure 5a yes Figure 4n A top-view sectional view of the actual product along line A-A'.

[0045] Figure 5b yes Figure 5a A cross-sectional view along line B-B'.

[0046] Figure 5c yes Figure 5a A cross-sectional view along line C-C'. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] The terms "comprising" and "having," and any variations thereof, appearing in this application specification, claims, and drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses. Furthermore, the terms "first," "second," and "third," etc., are used to distinguish different objects and are not intended to describe a specific order. Connections in this application include direct connections and indirect connections; an indirect connection refers to a connection where other electronic components, pins, etc., may exist between the two connected components.

[0049] Please see Figure 1aThis application provides an intelligent electronic switch, which includes a power supply terminal VCC, a power ground terminal GND, and a load output terminal OUT. The power supply terminal VCC is connected to the positive terminal of a power supply 310, the power ground terminal GND is connected to the negative terminal of the power supply 310, and the load output terminal OUT is connected to one end of a load 320. The other end of the load 320 is connected to either the negative or positive terminal of the power supply 310. In other embodiments of this application, a reverse connection protection diode and a current-limiting resistor may be provided between the power ground terminal GND and the negative terminal of the power supply 310. The intelligent electronic switch of this application can be applied to automobiles, medical equipment, industrial automation equipment, aerospace equipment, etc.

[0050] In this embodiment, the power source 310 is generally a battery, typically a rechargeable battery, providing voltages such as 12V, 24V, 36V, 48V, and 60V. Other types of batteries or power sources are also possible. The load 320 includes at least one of resistive, inductive, and capacitive loads. Resistive loads include, for example, seat adjustment devices, auxiliary heating devices, window heating devices, light-emitting diodes (LEDs), rear lighting, or other resistive loads. Inductive loads include, for example, pumps, actuators, motors, anti-lock braking systems (ABS), electronic braking systems (EBS), fans, or other systems that include inductive loads for one or more wiper systems. Capacitive loads include, for example, lighting elements such as xenon arc lamps. In the illustration, load 320 is shown as a single element only; load 320 is typically a more complex load, such as a module or subsystem with numerous components.

[0051] In this embodiment, the intelligent electronic switch also includes a power switch M1 and a switch control unit 330. One end of the power switch M1 is connected in series with the load 320 via the load output terminal OUT, and the other end is connected to the power supply terminal VCC or the power ground terminal GND. Its control terminal is connected to the switch control unit 330, which is used to control whether the power switch M1 is turned on. Figure 1a In this embodiment, power switch M1 is connected as a high-side switch, which is a switch connected between the power supply terminal VCC and the load 320. However, this application is not limited to this; please refer to other embodiments of this application. Figure 1b Power switch M1 is connected as a low-side switch, which is the switch connected between load 320 and the power supply ground terminal GND. In this embodiment, the switching frequency of power switch M1 is relatively low, generally less than or equal to 20kHz, such as 20kHz, 10kHz, 5kHz, 3kHz, 1kHz, 800Hz, 600Hz, 500Hz, 300Hz, 100Hz, 60Hz, etc.

[0052] Please refer to the above. Figure 1a and Figure 2 In this embodiment, the power switch M1 is a trench gate field-effect transistor (VDMOS), which is a type of VDMOS (Vertical Double Diffused MOSFET). VDMOS can be, for example, NMOS or PMOS; NMOS is used as an example in the illustration. In this embodiment, the trench gate field-effect transistor includes an N+ substrate 110, an N-type epitaxial layer 120, a lower gate 152, an upper gate 160, a p-type substrate region 171, a source region 172, a p-type contact region 174, a first dielectric layer, a gate 183, a drain 182, and a source 181. The drain 182 is located below the N+ substrate 110, the N-type epitaxial layer 120 is located above the N+ substrate 110, the first dielectric layer extends from the upper surface of the N-type epitaxial layer 120 into the N-type epitaxial layer 120, the first dielectric layer is provided with a lower gate 152 and an upper gate 160, the upper gate 160 is located above the lower gate 152, the upper gate 160 and the lower gate 152 are electrically connected and are connected to the gate 183, the p-type substrate region 171 is located above the N-type epitaxial layer 120, the p-type substrate region 171 is formed with a p-type contact region 174 and a source region 172, wherein the source region 172 and the p-type contact region 174 are electrically connected to the source 181.

[0053] In this embodiment, the lower gate 152 and the upper gate 160 are made of conductive materials such as polysilicon. The trench gate field-effect transistor also includes a first connection portion 175, which is located in the first dielectric layer. The first connection portion 175 is used to electrically connect the upper gate 160 and the lower gate 152. The area of ​​the lower gate 152 projected onto the horizontal plane is larger than the area of ​​the upper gate 160 projected onto the horizontal plane. In this embodiment, the lower gate 152 is equivalent to the shielding gate of the shielded gate field-effect transistor, and the upper gate 160 is equivalent to the control gate of the shielded gate field-effect transistor. When the field-effect transistor is turned off, both the lower gate 152 and the shielding gate of the shielded gate field-effect transistor in this embodiment have the same potential as the load output terminal OUT. Therefore, the voltage withstand performance of this application is better. Similar to the shielded gate field-effect transistor, the concentration of doped N-type material in the N-type epitaxial layer 120 can be increased, thereby reducing the on-resistance and requiring fewer masks compared to the shielded gate field-effect transistor.

[0054] In this embodiment, the first dielectric layer is an insulating layer, such as SiO2 (silicon dioxide). In this embodiment, the first dielectric layer includes a field oxide layer 142, a gate oxide layer 143, and a spacer oxide layer 145. The field oxide layer 142 surrounds the lower gate electrode 152, the gate oxide layer 143 surrounds the upper gate electrode 160, and the spacer oxide layer 145 is located between the upper gate electrode 160 and the lower gate electrode 152. The thickness of the gate oxide layer 143 and the thickness of the spacer oxide layer 145 are less than the thickness of the field oxide layer 142. In this embodiment, the upper gate 160 includes a main body 161 and a lower extension 162. The main body 161 is located above the lower extension 162. The lower extension 162 is formed by extending downward from the main body 161. The lower extension 162 is a hollow ring. The upper surface of the lower extension 162 is higher than the lower surface of the p-type substrate region 171, and the lower surface of the lower extension 162 is lower than the lower surface of the p-type substrate region 171. The outer side of the lower extension 162 is surrounded by a gate oxide layer 143. The gate oxide layer 143 is thinner than the field oxide layer 142. Therefore, the turn-on voltage (Vth) of the trench gate field-effect transistor in this embodiment is the same as or similar to the turn-on voltage of the shielded gate field-effect transistor.

[0055] In this embodiment, the p-type contact region 174 is located inside the p-type substrate region 171. To connect the p-type contact region 174 to the source region 172, the trench gate field-effect transistor further includes a second connection portion 176. The second connection portion 176 has the same height as the first connection portion 175. The second connection portion 176 is used to connect the p-type contact region 174 to the source electrode 181. In this embodiment, the p-type contact region 174 is connected to the source region 172 via the second connection portion 176, and the source region 172 is connected to the source electrode 181. Alternatively, in other embodiments of this application, the p-type contact region 174 can also be connected to the source electrode 181 via the second connection portion 176. In this embodiment, the second connection portion 176 and the first connection portion 175 are formed through the same process, thereby saving on process costs such as mask fabrication. In this embodiment, the first connection portion 175 and the second connection portion 176 are made of conductive materials, such as tungsten.

[0056] This application also provides a method for manufacturing a trench gate field-effect transistor, which corresponds to the trench gate field-effect transistor structure described above. Please refer to [link to previous document]. Figures 2-4n The manufacturing method includes:

[0057] S110: Provide an N+ substrate 110, and form an N-type epitaxial layer 120 on the N+ substrate 110;

[0058] Please see Figure 4a In this embodiment, the doping concentration of the N-type epitaxial layer 120 is less than the doping concentration of the N+ substrate 110.

[0059] S120: Dig out the first deep trench 131 in the N-type epitaxial layer 120;

[0060] Please see Figure 4b In this embodiment, the first deep trench 131 extends downward from the upper surface of the N-type epitaxial layer 120 into the N-type epitaxial layer 120, and the first deep trench 131 does not penetrate the lower surface of the N-type epitaxial layer 120.

[0061] S130: A first dielectric layer, a lower gate 152, and an upper gate 160 are formed in the first deep trench 131;

[0062] Please see Figures 4c-4h In this embodiment, the lower gate 152 and the upper gate 160 are electrically insulated from each other by a first dielectric layer, i.e., they are electrically insulated from each other. In this embodiment, the first dielectric layer includes a field oxide layer 142, a gate oxide layer 143, a spacer oxide layer 145, and a gate protection layer 144. The field oxide layer 142 is located outside the lower gate 152, the gate oxide layer 143 is located between the upper gate 160 and the N-type epitaxial layer 120 (i.e., located on both sides of the upper gate 160), the spacer oxide layer 145 is located between the lower gate 152 and the upper gate 160, and the gate protection layer 144 is located above the upper gate 160.

[0063] In this embodiment, step S130 specifically includes:

[0064] S131: A first insulating layer 141 is formed on the inner surface of the first deep trench 131 and the upper surface of the N-type epitaxial layer 120;

[0065] Please see Figure 4c In this embodiment, a first insulating layer 141 is formed on the inner surface of the first deep trench 131 and the upper surface of the N-type epitaxial layer 120 by oxidation and / or deposition. The first insulating layer 141 is, for example, SiO2. The first insulating layer 141 itself is relatively thick, but the first insulating layer 141 itself does not fill the first deep trench 131.

[0066] S132: Deposit a first conductive material 151 on the surface of the first insulating layer 141, and etch the first conductive material 151 and the first insulating layer 141 to form a lower gate 152 and a field oxide layer 142, wherein the upper surface of the field oxide layer 142 is lower than the upper surface of the lower gate 152.

[0067] Please see Figures 4d-4fIn this embodiment, a first conductive material 151 is first deposited on the surface of the first insulating layer 141, filling the first deep trench 131. The first conductive material 151 is, for example, N-type polysilicon. Then, the first conductive material 151 is etched, and the first conductive material 151 located outside the first deep trench 131 is completely etched away. The first conductive material 151 in the first deep trench 131 is also partially etched away to form the first lower gate 152. Next, the first insulating layer 141 is etched, and the first insulating layer 141 located outside the first deep trench 131 is completely etched away. The first insulating layer 141 located inside the first deep trench 131 is partially etched away to form the field oxide layer 142. The upper surface of the field oxide layer 142 is lower than the upper surface of the lower gate 152. In the figure, there is no field oxide layer 142 on the left and right sides of the upper part of the lower gate 152 to form a groove. The depth of the groove can be set as needed.

[0068] S133: A gate oxide layer 143 and a spacer oxide layer 145 are formed in the first deep trench 131. The gate oxide layer 143 is located on the surface of the first deep trench 131 that is not covered by the field oxide layer 142, and the spacer oxide layer 145 is located on the surface of the lower gate 152 that is not covered by the field oxide layer 142.

[0069] Please see Figure 4g In this embodiment, a gate oxide layer 143 and a spacer oxide layer 145 are formed in the first deep trench 131 by oxidation. The gate oxide layer 143 is located on the exposed surface of the first deep trench 131, and the spacer oxide layer 145 is located on the exposed surface of the lower gate 152. That is, the gate oxide layer 143 is located on the surface of the first deep trench 131 that does not cover the field oxide layer 142, and the spacer oxide layer 145 is located on the surface of the lower gate 152 that does not cover the field oxide layer 142. The gate oxide layer 143 is present on both the left and right sides of the trench, but no gate oxide layer 143 is formed on the lower side of the trench. The gate oxide layer 143 itself is relatively thin. For example, the thickness of the gate oxide layer 143 is less than half the thickness of the field oxide layer 142. For example, the thickness of the gate oxide layer 143 is 1 / 4 to 1 / 10 of the thickness of the field oxide layer 142.

[0070] S134: An upper gate 160 and a gate protection layer 144 are formed in the first deep trench 131.

[0071] Please see Figure 4h In this embodiment, a second conductive material, such as N-type polysilicon, is filled into the first deep trench 131. Then, the second conductive material is etched to form an upper gate 160. The upper gate 160 is electrically insulated from the lower gate 152, and a gate oxide layer 143 is placed between them to insulate them. Next, a portion of the gate oxide layer 143 is etched away, and then a gate protection layer 144 is deposited to form the gate protection layer 144, which is located on top of the upper gate 160.

[0072] In this embodiment, the upper gate 160 includes a main body 161 and a lower extension 162. The lower extension 162 extends downward from the main body 161 and is located in a groove. A relatively thin gate oxide layer 143 exists between the lower extension 162 and the N-type epitaxial layer 120, and between the main body 161 and the N-type epitaxial layer 120. In this embodiment, the lower extension 162 is the portion where the upper gate 160 and the lower gate 152 overlap vertically; that is, the upper part of the lower gate 152 is located between the lower extensions 162 or within the annular region formed by the lower extensions 162.

[0073] S140: A p-type matrix region 171 is formed on the N-type epitaxial layer 120;

[0074] Please see Figure 4i In this embodiment, a p-type substrate region 171 is formed by doping the N-type epitaxial layer 120 with p-type impurities, such as trivalent elements like boron or indium. In this embodiment, the lower surface of the p-type substrate region 171 is lower than the upper surface of the lower gate 152, and the lower surface of the p-type substrate region 171 is higher than the lower surface of the lower extension portion 162. Specifically, the lower surface of the p-type substrate region 171 is located between the lower surface of the lower extension portion 162 and the lower surface of the main body portion 161. By setting the lower surface of the p-type substrate region 171 higher than the lower surface of the lower extension portion 162, and with a relatively thin gate oxide layer 143 and a relatively thick field oxide layer 142 between the lower extension portion 162 and the p-type substrate region 171, the turn-on voltage of the trench gate field-effect transistor in this embodiment is relatively small and not too large.

[0075] S150: Source region 172 is formed on p-type matrix region 171;

[0076] Please see Figure 4j In this embodiment, an n-type impurity is doped into the upper part of the p-type substrate region 171. The n-type impurity is, for example, a pentavalent element, such as phosphorus, arsenic, or antimony, to form a complete source region 172, which covers the epitaxial layer.

[0077] S160: A second dielectric layer 173 is formed on the surface of the source region 172, and a second deep trench 132 and a third deep trench 133 are formed by digging trenches in the second dielectric layer 173. The second deep trench 132 extends downward from the surface of the second dielectric layer 173 to the lower gate 152, and the third deep trench 133 extends downward from the surface of the second dielectric layer 173 to the p-type substrate region 171.

[0078] Please see Figure 4kIn this embodiment, a second dielectric layer 173 is formed on the surface of the source region 172. The second dielectric layer 173 is an insulating layer, such as SiO2 or Si3N4. Then, trenches are dug in the second dielectric layer 173 to form a second deep trench 132 and a third deep trench 133. The second deep trench 132 corresponds to the positions of the upper gate 160 and the lower gate 152. The third deep trench 133 is located between two adjacent upper gates 160. The number of second deep trenches 132 and third deep trenches 133 is set as needed. In this embodiment, the second deep trench 132 extends downward from the surface of the second dielectric layer 173 to the lower gate 152, extending either to the surface of the lower gate 152 or to a portion of its interior. The second deep trench 132 sequentially passes through the second dielectric layer 173, the gate protection layer 144, the upper gate 160, and the spacer oxide layer 145. The third deep trench 133 extends downward from the surface of the second dielectric layer 173 to the p-type substrate region 171, extending either to the upper surface of the p-type substrate region 171 or to a portion of its interior. The third deep trench 133 sequentially passes through the second dielectric layer 173 and the source region 172. In this embodiment, the third deep trench 133 and the second deep trench 132 are formed using the same mask, which helps save mask costs and process steps, and simplifies the manufacturing process.

[0079] S170: Forming a p-type contact area 174, a first connecting portion 175, and a second connecting portion 176;

[0080] Please see Figure 4l and Figure 4m In this embodiment, p-type impurities are simultaneously injected into the second deep trench 132 and the third deep trench 133 to form a p-type contact region 174 within the p-type substrate region 171. Then, a third conductive material is filled into the second deep trench 132 and the third deep trench 133 to correspondingly form a first connection portion 175 and a second connection portion 176. The third conductive material is, for example, tungsten. The first connection portion 175 completely fills the second deep trench 132, and the lower end of the first connection portion 175 is connected to the lower gate 152. 5 passes through the upper gate 160, thereby realizing the electrical connection between the upper gate 160 and the lower gate 152. The upper part of the first connection part 175 is exposed to facilitate the subsequent connection with the gate 183. The second connection part 176 fills the third deep trench 133. The lower end of the second connection part 176 is connected to the p-type contact region 174. The second connection part 176 passes through the source region 172, thereby realizing the connection between the source region 172 and the p-type contact region 174. The upper end of the second connection part 176 is exposed to facilitate the subsequent connection with the source 181.

[0081] S180: Forming a gate 183, a source 181, and a drain 182, wherein the drain 182 is located below the N+ substrate 110, and the gate 183 and the source 181 are located above the N+ substrate 110.

[0082] Please see Figure 4n In this embodiment, a fourth conductive material, such as aluminum or an alloy, is deposited on the second dielectric layer 173, the first connection portion 175, and the second connection portion 176. Then, etching is performed to form a gate 183 and a source 181. The gate 183 is connected to the first connection portion 175, and the source 181 is connected to the second connection portion 176. The gate 183 and the source 181 are separated and located above the N+ substrate 110. In this embodiment, a drain 182 is formed below the N+ substrate 110.

[0083] It should be noted that, for the sake of concise and intuitive illustration of the invention and process flow, the gate 183 and source 181, the first connection portion 175 and the second connection portion 176 in the above figures are drawn on the same cross-sectional view. In actual engineering, for ease of wiring, please refer to [the relevant documentation / reference]. Figure 5a The first connecting portion 175 and the second connecting portion 176, along with their gate 183 and source 181, are arranged in an alternating pattern in the direction perpendicular to the plane of the paper. Please refer to [reference needed]. Figure 5a and Figure 5b Along Figure 5a When the B-B' line is viewed in cross-section, the second connection portion 176 and the source 181 are not visible. The first connection portion 175 is connected through the entire gate 183. Please refer to [reference needed]. Figure 5a and Figure 5c Along Figure 5a When the C-C' line is viewed in cross-section, the first connection portion 175 and the gate 183 are not visible, and the second connection portion 176 is connected through the entire source 181. Of course, the actual layout and wiring method is not limited to this and can be determined according to engineering requirements. This is a technology known to those skilled in the art in the actual manufacturing process, and will not be elaborated here.

[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0085] It should be understood that "a plurality of" as used herein refers to two or more. Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0086] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0087] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A trench gate field-effect transistor with low Ron, characterized in that, Includes: N+ substrate, N-type epitaxial layer, first dielectric layer, upper gate, p-type substrate region, source region, drain, and source. The N-type epitaxial layer and the p-type substrate region are sequentially disposed above the N+ substrate, the drain is disposed below the N+ substrate, the first dielectric layer is located on the N-type epitaxial layer and passes through the p-type substrate region, an upper gate is provided in the first dielectric layer, the upper gate is connected to the gate, and the p-type substrate region and the source region are connected to the source. The trench gate field-effect transistor further includes a lower gate and a first connection portion. The lower gate and the first connection portion are located within the first dielectric layer. The lower gate is located below the upper gate and is electrically connected to the upper gate through the first connection portion.

2. The trench gate field-effect transistor according to claim 1, characterized in that, The upper gate includes a main body and a lower extension, the lower extension being formed by extending downward from the main body, and the lower extension partially overlapping the lower gate in the longitudinal direction; The lower surface of the main body is higher than the lower surface of the p-type substrate region, and the lower surface of the lower extension is lower than the lower surface of the p-type substrate region.

3. The trench gate field-effect transistor according to claim 2, characterized in that, The first dielectric layer includes a field oxide layer, a gate oxide layer, and a spacer oxide layer, wherein the thickness of the field oxide layer is greater than the thickness of the gate oxide layer, the gate oxide layer is located on both sides of the upper gate, the spacer oxide layer is located between the upper gate and the lower gate, the field oxide layer is located between the lower gate and the N-type epitaxial layer, and the thickness of the gate oxide layer is less than the thickness of the field oxide layer.

4. The trench gate field-effect transistor according to claim 1, characterized in that, The trench gate field-effect transistor further includes a p-type contact region and a second connection portion. The p-type contact region is located within the p-type substrate region, and the source region is located above the p-type substrate region. The lower end of the second connection portion is connected to the p-type contact region, and the upper end of the second connection portion passes through the source region and is connected to the source electrode.

5. The trench gate field-effect transistor according to claim 4, characterized in that, The second connecting portion is formed simultaneously with the first connecting portion.

6. The trench gate field-effect transistor according to claim 4, characterized in that, The source region covers the p-type matrix region, and the second connecting portion is connected to the source region.

7. The trench gate field-effect transistor according to any one of claims 1-6, characterized in that, The field-effect transistor further includes a second dielectric layer, which is located on the first dielectric layer and the source region. The source and the gate are located on the second dielectric layer, and the gate is connected to the upper gate via the first connection portion.

8. A smart electronic switch, characterized in that, It includes a power supply terminal, a power ground terminal, a load output terminal, and a switch control unit, wherein the power supply terminal is used to connect to the positive terminal of the power supply, the power ground terminal is used to connect to the negative terminal of the power supply, and the load output terminal is used to connect to the load. It also includes the trench gate field-effect transistor as described in any one of claims 1-7, wherein the drain of the trench gate field-effect transistor is connected to the power supply terminal or the load output terminal, its source is connected to the load output terminal or the power supply ground terminal, and its gate is connected to the switch control unit, wherein the switch control unit is used to control the trench gate field-effect transistor to turn on or turn off.

9. The intelligent electronic switch according to claim 8, characterized in that, The switch control unit is used to control the frequency at which the trench gate field-effect transistor is turned on or off to be less than or equal to 20 kHz.

10. A method for manufacturing a trench gate field-effect transistor, characterized in that, include: An N+ substrate is provided, and an N-type epitaxial layer is formed on the N+ substrate; The first deep trench was dug in the N-type epitaxial layer; A first dielectric layer, a lower gate, and an upper gate are formed in the first deep trench; A p-type matrix region is formed on the N-type epitaxial layer; A source region is formed on the p-type matrix region; A second dielectric layer is formed on the surface of the source region, and a second deep trench and a third deep trench are formed by trenching the second dielectric layer. The second deep trench extends downward from the surface of the second dielectric layer to the lower gate, and the third deep trench extends downward from the surface of the second dielectric layer to the p-type substrate region. A p-type contact area, a first connecting part, and a second connecting part are formed; A gate, source, and drain are formed, wherein the drain is located below the N+ substrate, and the gate and source are located above the N+ substrate.

11. The method for manufacturing a trench gate field-effect transistor according to claim 10, characterized in that, The steps for forming the p-type contact area, the first connecting part, and the second connecting part specifically include: p-type impurities are simultaneously injected into the second and third deep trenches to form a p-type contact region within the p-type matrix region; A third conductive material is filled into the second deep trench and the third deep trench to form a first connection portion and a second connection portion respectively. The first connection portion connects the lower gate to the upper gate and the upper end of the first connection portion is exposed. The lower end of the second connection portion is connected to the p-type contact area and the upper end of the second connection portion passes through the source region and the second dielectric layer and is exposed.

12. The method for manufacturing a trench gate field-effect transistor according to claim 10, characterized in that, The steps of forming a first dielectric layer, a lower gate, and an upper gate in the first deep trench specifically include: A first insulating layer is formed on the inner surface of the first deep trench and the upper surface of the N-type epitaxial layer; A first conductive material is deposited on the surface of a first insulating layer, and the first conductive material and the first insulating layer are etched to form a lower gate and a field oxide layer, wherein the upper surface of the field oxide layer is lower than the upper surface of the lower gate. A gate oxide layer and a spacer oxide layer are formed in a first deep trench. The gate oxide layer is located on the surface of the first deep trench that is not covered by the field oxide layer, and the spacer oxide layer is located on the surface of the lower gate that is not covered by the field oxide layer. The thickness of the gate oxide layer is less than the thickness of the field oxide layer. The upper gate and gate protection layer are formed in the first deep trench.

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