A SiC VDMOSFET based on a non-floating buried layer and its fabrication method

Abstract

This invention relates to a SiC VDMOSFET based on a non-floating buried layer and its fabrication method, comprising: an N+ substrate; an N-drift region located on the N+ substrate; a P-type non-floating buried layer extending from the surface of the N-drift region to its interior; an epitaxial N-region located on the N-drift region; a trench region extending from the surface of the epitaxial N-region to its interior, with its bottom separated from the P-type non-floating buried layer by a predetermined distance; a P+ source region extending from the bottom of the trench region until it overlaps with the P-type non-floating buried layer and is formed on the sidewall of the trench region; a Pwell region extending from the surface of the epitaxial N-region to its interior, contacting the P+ source region on the sidewall of the trench region; and an N+ source region extending from the surface of the Pwell region to its interior and contacting the P+ source region. This invention significantly improves the long-term gate oxide reliability and overall high-frequency switching performance of the device without sacrificing device symmetry or effective conduction area.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a SiCVD MOSFET based on a non-floating buried layer and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, exhibits significant advantages in high-power-density, high-frequency applications such as new energy vehicles, photovoltaic inverters, and high-voltage smart grids due to its high critical breakdown field strength, excellent thermal conductivity, and high electron saturation drift velocity. SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are currently the most promising fully controllable power switching devices, capable of significantly improving power conversion efficiency and reducing system size.

[0003] However, the long-term reliability of SiC MOSFETs has always been constrained by the intrinsic fragility of their gate oxide layer (SiO2). Traditional SiC vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) face a severe gate oxide reliability bottleneck in high-voltage applications. Due to the extremely high critical breakdown electric field of SiC (approximately 10 times that of silicon), the electric field in the drift region is extremely strong when the device is in a high-voltage blocking state. This high electric field easily penetrates the JFET region between the P-wells and couples directly to the bottom of the gate oxide layer. Because of the dielectric constant mismatch between SiC and SiO2, according to the principle of electrical displacement continuity at the interface, the gate oxide layer will experience extremely high oxygen field stress, several times higher than that in the bulk. The electric field that penetrates the JFET region and couples into the gate oxide layer will surge to more than 2.5 times that in the SiC bulk. This extremely fragile gate oxide interface is highly susceptible to microstructure damage under extreme additional electric field stress, leading to time-dependent breakdown (TDDB) of the gate dielectric layer and severely threatening the high-voltage reliability and lifespan of the device. Therefore, exploring device structures that can effectively shield high voltage and protect the gate oxide layer is a key technical challenge in the field of SiC power devices.

[0004] To shield the gate oxide layer from the impact of the high drain electric field, existing technologies typically introduce a P-type shield (P-Shield or buried layer) at the bottom of the JFET region below the gate oxide. However, in traditional symmetrical VDMOSFET structures, due to the physical limitations of ion implantation depth in SiC materials, the deep P-type shield often struggles to achieve effective electrical connection with the source, resulting in a "floating" state (i.e., a floating buried layer). This floating buried layer structure exhibits serious drawbacks in practical applications: First, during the dynamic process of high-frequency switching (high dV / dt conditions), the floating buried layer, lacking a charge discharge path, generates a large parasitic displacement current, easily causing severe fluctuations in the internal potential and even mis-triggering parasitic BJTs, leading to device failure. Second, the floating junction acts as a "charge trap" during the switching cycle, repeatedly capturing and releasing majority carriers in the depletion layer, causing severe degradation of the device's dynamic on-resistance (Ron) and significantly increasing the system's switching losses. In existing technologies, relying solely on multiple ultra-high energy ion implantations to achieve vertical connections is not only costly but also results in extremely low doping concentrations, making it impossible to form a low-impedance grounding path.

[0005] Therefore, existing structures cannot completely solve the reliable grounding problem of deep shielding layers without sacrificing device conductivity. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a SiCVDMOSFT based on a non-floating buried layer and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a SiC VDMOSFET based on a non-floating buried layer, comprising: N+ substrate; The N-drift region is located on the N+ substrate; The P-type non-floating buried layer extends from the surface of the N-drift region to the interior of the N-drift region; The epitaxial N-region is located on the N-drift region; The trench area extends from the surface of the epitaxial N region to the interior of the epitaxial N region, and its bottom is at a predetermined distance from the P-type non-floating buried layer. The P+ source region extends from the bottom of the trench region until it overlaps with the P-type non-floating buried layer and is formed on the sidewall of the trench region. The Pwell region extends from the surface of the epitaxial N region into the interior of the epitaxial N region and contacts the P+ source region on the sidewall of the trench region. The N+ source region extends from the surface of the Pwell region into the interior of the Pwell region and is in contact with the P+ source region; The P-type non-floating buried layer, trench region, P+ source region, Pwell region, and N+ source region each form two regions that are spaced apart; the projection of one region of the P-type non-floating buried layer covers the projection of the corresponding side region of the Pwell region, as well as the projection of the current path between the two regions of the Pwell region.

[0007] In one embodiment of the present invention, the junction depth of the P-type non-floating buried layer is 2~4 μm, and the doping concentration is 3e19~8e19 cm. -3 ; The doping concentration of the P+ source region is 1e19~5e19 cm⁻¹ -3 The junction depth of the P+ source region at the bottom of the trench is 0.8~1.0 μm; A high-concentration doped region is formed between the P-type non-floating buried layer and the P+ source region.

[0008] In one embodiment of the present invention, the width of the trench region is 2.0~2.4 μm and the depth is 1.0~1.4 μm; The distance between the bottom of the trench area and the top of the non-floating buried layer is 0.5~0.9μm.

[0009] In one embodiment of the present invention, the junction depth of the Pwell region is 0.4~0.8 μm, and the surface doping concentration is 3e16~5e16 cm. -3 The doping concentration in the bulk region is 1e18~5e18cm. -3 ; The junction depth of the N+ source region is 0.2~0.4 μm, and the doping concentration is 3e19~9e19 cm⁻¹. -3 .

[0010] In one embodiment of the present invention, the thickness of the N+ substrate is 300~400 μm, and the doping concentration is 4e18~6e18 cm⁻¹. -3 ; The thickness of the N-drift region is 10~14 μm, and the doping concentration is 7e15~1e16 cm⁻¹. -3 ; The thickness of the epitaxial N-region is 1.8~2.1 μm, and the doping concentration is 4e16~7e16 cm⁻¹. -3 .

[0011] In one embodiment of the present invention, it further includes: a gate oxide layer, which at least covers the surface of the current channel between the two regions of the Pwell region, the Pwell region and a portion of the N+ source region; A polysilicon gate is located on the gate oxide layer; An isolation medium covers the polysilicon gate and extends from the side of the polysilicon gate and the side of the gate oxide layer to the surface of the N+ source region. The source metal fills the trench region and covers part of the surface of the P+ source region and N+ source region on the sidewall of the trench region, as well as the isolation medium. The drain metal is located on the back side of the N+ substrate.

[0012] In one embodiment of the present invention, the thickness of the gate oxide layer is 50~60 nm; The thickness of the polysilicon gate is 0.5~1μm; The thickness of the isolation medium is 1~1.2 μm; The thickness of the source metal is 4~5 μm; The thickness of the drain metal is 4~5 μm.

[0013] Another embodiment of the present invention provides a method for fabricating a SiC VDMOSFET based on a non-floating buried layer, comprising the steps of: N-drift regions are grown on N+ substrates; Ion implantation is performed on the N-drift region to form a P-type non-floating buried layer; An epitaxial N-region is grown on the N-drift region; The epitaxial N-region is etched to form a trench region; the bottom of the trench region is a trench region at a predetermined distance from the P-type non-floating buried layer; Ion implantation is performed at the bottom and sidewalls of the trench region to form a P+ source region; the P+ source region at the bottom of the trench region overlaps with the P-type non-floating buried layer; Ion implantation is performed on the epitaxial N-region to form a Pwell region; the Pwell region is in contact with the P+ source region on the sidewall of the trench region; the P-type non-floating buried layer, the trench region, the P+ source region, the Pwell region, and the N+ source region each form two regions that are spaced apart; the projection of one region of the P-type non-floating buried layer covers the projection of one region of the Pwell region and the projection of the current channel between the two regions of the Pwell region; Ion implantation is performed on the Pwell region to form an N+ source region; the N+ source region extends from the surface of the Pwell region into the interior of the Pwell region and contacts the P+ source region.

[0014] In one embodiment of the present invention, ion implantation is performed on the N-drift region to form a P-type non-floating buried layer, comprising: sequentially performing ion implantation on the N-drift region using conventional ion implantation at an energy of 60-700k and channel ion implantation at an energy of 700k with an implantation angle deviation of -4°, wherein the implanted ions include aluminum ions, and the dose is 4e14-1e15 cm⁻¹. -3This forms a P-type non-floating buried layer; Etching the epitaxial N-region to form a trench region includes: using a silicon dioxide hard mask to etch the epitaxial N-region using an etching process to form a trench region; Ion implantation is performed at the bottom and sidewalls of the trench region to form a P+ source region. This includes: using a silicon dioxide hard mask, ion implantation is performed at the bottom and sidewalls of the trench region using an ion implantation process. The implanted ions include aluminum ions, with an energy of 60-700K and a dose of 4e14~1e15cm. -3 This forms the P+ source region; Ion implantation is performed on the epitaxial N-region to form a Pwell region, including: using a silicon dioxide hard mask, ion implantation is performed on the epitaxial N-region using an ion implantation process, the implanted ions include aluminum ions, the energy is 60-480K, and the dose is 1e12~2e14cm. -3 This forms the Pwell region; Ion implantation is performed on the Pwell region to form an N+ source region, including: using a silicon dioxide hard mask, ion implantation is performed on the Pwell region using an ion implantation process, the implanted ions include nitrogen ions, the energy is 35-160K, and the dose is 4e14~6e14cm. -3 This forms the N+ source region.

[0015] In one embodiment of the present invention, the step further includes: A gate oxide layer is grown on the surface of the current channel between the two regions of the Pwell region, the Pwell region, and part of the N+ source region. Polysilicon is deposited on the gate oxide layer, and a polysilicon gate is formed by an etching process. An isolation dielectric material is deposited on the sample surface, and a source contact hole is formed by an etching process to obtain the isolation dielectric; the isolation dielectric covers the polysilicon gate and extends from the side of the polysilicon gate and the side of the gate oxide layer to the surface of the N+ source region; Source metal is deposited in the trench region, on the P+ source region of the sidewall of the trench region, on a portion of the surface of the N+ source region, and on the isolation medium to form source metal; A drain metal is formed by depositing metal on the back side of the N+ substrate.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention forms a trench region in the epitaxial N-region, and combined with the P+ source region at the bottom of the trench, constructs an extremely low-impedance vertical charge discharge channel for the deep buried layer at the center of the device. This not only completely transforms the floating buried layer into a non-floating buried layer, allowing transient charge and discharge during high-frequency switching to be rapidly extracted by the source, but also significantly suppresses the parasitic capacitance charging and discharging effect and dynamic resistance degradation under high dV / dt conditions. At the same time, this non-floating buried layer structure can effectively shield the drain high voltage from the impact on the JFET region and the gate oxide layer, fundamentally reducing the high-voltage stress at the bottom of the gate oxide. Through the full overlap design of the P+ source region at the bottom of the trench and the P-type non-floating buried layer, an effective electrostatic shield is formed for the physical sharp corners at the bottom of the trench, perfectly avoiding the risk of local electric field distortion and premature breakdown introduced by the trench. Therefore, compared with traditional SiC MOSFETs, the structure of this invention significantly improves the long-term gate oxide reliability and overall high-frequency switching performance of the device without sacrificing device symmetry and effective conduction area. Attached Figure Description

[0017] Figure 1 A schematic diagram of a SiC VDMOSFET based on a non-floating buried layer is provided for an embodiment of the present invention; Figures 2a-2k This is a schematic diagram illustrating the process of fabricating a SiCVD MOSFET based on a non-floating buried layer, as provided in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of a SiC VDMOSFET based on a non-floating buried layer, provided for an embodiment of the present invention.

[0020] This embodiment of the SiC VDMOSFET based on a non-floating buried layer includes: an N+ substrate 1, an N- drift region 2, a P-type non-floating buried layer 3, an epitaxial N region 4, a trench region 5, a P+ source region 6, a Pwell region 7, an N+ source region 8, a gate oxide layer 9, a polysilicon gate 10, an isolation dielectric 11, a source metal 12, and a drain metal 13.

[0021] N-drift region 2 is located on N+ substrate 1; P-type non-floating buried layer 3 extends from the surface of N-drift region 2 to the interior of N-drift region 2; epitaxial N-region 4 is located on N-drift region 2; trench region 5 extends from the surface of epitaxial N-region 4 to the interior of epitaxial N-region 4, and its bottom is at a predetermined distance from P-type non-floating buried layer 3; P+ source region 6 extends from the bottom of trench region 5 until it overlaps with P-type non-floating buried layer 3, and is formed on the sidewall of trench region 5; Pwell region 7 extends from the surface of epitaxial N-region 4 to the interior of epitaxial N+ substrate 1. Inside region 4, it contacts the P+ source region 6 on the sidewall of trench region 5; N+ source region 8 extends from the surface of Pwell region 7 to the interior of Pwell region 7 and contacts P+ source region 6; P-type non-floating buried layer 3, trench region 5, P+ source region 6, Pwell region 7, and N+ source region 8 each form two regions that are spaced apart; the projection of one region of P-type non-floating buried layer 3 covers the projection of one region of Pwell region 7 and the projection of the current path between the two regions of Pwell region 7. The gate oxide layer 9 partially covers the current channel between the two regions of Pwell region 7, the surface of Pwell region 7 and part of N+ source region 8; the polysilicon gate 10 is located on the gate oxide layer 9; the isolation dielectric 11 covers the polysilicon gate 10 and extends from the side of the polysilicon gate 10 and the side of the gate oxide layer 9 to the surface of N+ source region 8; the source metal 12 fills the trench region 5 and covers part of the surface of P+ source region 6 and N+ source region 8 on the sidewall of the trench region 5 and the isolation dielectric 11; the drain metal 13 is located on the back side of the N+ substrate 1.

[0022] Specifically, the N+ substrate 1 serves as the drain layer of the device. The N- drift region 2 is the first epitaxial N-region, used to bear the main withstand voltage of the device under high voltage blocking conditions. The epitaxial N-region 4 is the second epitaxial N-region, which forms the basis for the formation of the Pwell region 7 and the trench region 5.

[0023] The P-type non-floating buried layer 3 is formed inside the N-drift region 2 by ion implantation, and it forms two regions spaced apart along the first direction: a first sub-buried layer and a second sub-buried layer.

[0024] The trench region 5 is formed in the epitaxial N region 4 by etching process. It forms two regions distributed at intervals along the first direction: a first sub-trench and a second sub-trench. The projections of the two regions of the trench region 5 overlap with the projections of the two regions of the P-type non-floating buried layer 3. That is, the projection of the first sub-trench overlaps with the projection of the first sub-buried layer, and the projection of the second sub-trench overlaps with the projection of the first sub-trench.

[0025] P+ source region 6 is formed at the bottom and sidewalls of trench region 5, and forms two regions spaced apart along the first direction: a first sub-P+ source region and a second sub-P+ source region. The first sub-P+ source region is formed at the bottom and sidewalls of the first sub-trench and overlaps with the first sub-buried layer at its bottom. The second sub-P+ source region is formed at the bottom and sidewalls of the second sub-P+ trench and overlaps with the second sub-buried layer at its bottom. The overlapping regions form a high-concentration doped region connection, thereby constructing a vertical charge discharge channel with extremely low impedance.

[0026] Pwell region 7 is formed in the epitaxial N region 4, which forms two regions spaced apart along the first direction: a first sub-Pwell region and a second sub-Pwell region. The side of the first sub-Pwell region is in contact with the first sub-source region, and the side of the second sub-Pwell region is in contact with the side of the second sub-source region.

[0027] N+ source region 8 is formed in Pwell region 7, which forms two regions spaced apart along the first direction, and the sides of the two regions are in contact with the two regions of P+ source region 6.

[0028] The channels between the two regions of the P-type non-floating buried layer 3, the two regions of the trench region 5, the two regions of the P+ source region 6, and the two regions of the Pwell region 7 are interconnected, forming a vertical conductive path between the source and drain of the device. Furthermore, the projection of one region of the P-type non-floating buried layer 3 covers the projection of the corresponding region of the Pwell region 7, and also covers the projection of the current path between the two Pwell regions 7, ensuring that the P-type non-floating buried layer 3 can effectively shield the high-voltage electric field from the drain, preventing it from penetrating the JFET region and coupling to the bottom of the gate oxide layer.

[0029] In one specific embodiment, the junction depth of the P-type non-floating buried layer 3 is 2~4 μm, and the doping concentration is 3e19~8e19 cm. -3 The doping concentration of P+ source region 6 is 1e19~5e19cm. -3 The junction depth of the P+ source region 6 at the bottom of the trench region 5 is 0.8~1.0μm. A high-concentration doped region is formed between the P-type non-floating buried layer 3 and the P+ source region 6. Through the effective connection of the high-concentration doped region, the current path from the P-type non-floating buried layer 3 to the source metal 12 has extremely low resistance, thereby realizing rapid charge discharge and effectively suppressing high-frequency parasitic effects.

[0030] For example, the junction depth of the P-type non-floating buried layer 3 is 3.5 μm, and the doping concentration is 5e19 cm⁻¹. -3 The doping concentration of P+ source region 6 is 3e19cm. -3 The junction depth of the P+ source region 6 at the bottom of trench region 5 is 0.9 μm.

[0031] In one specific embodiment, the trench region 5 has a width of 2.0~2.4μm and a depth of 1.0~1.4μm. The distance between the bottom of the trench region 5 and the top of the non-floating buried layer 3 is 0.5~0.9μm. This distance ensures that there is sufficient N-type epitaxial material between the bottom of the trench region 5 and the P-type non-floating buried layer 3 to maintain the device's withstand voltage capability, and also ensures that the P+ source region 6 formed by subsequent ion implantation can fully overlap with the P-type non-floating buried layer 3 to form a reliable electrical connection.

[0032] For example, the trench region 5 has a width of 2.2 μm and a depth of 1.2 μm. The distance between the bottom of the trench region 5 and the top of the non-floating buried layer 3 is 0.7 μm.

[0033] In one specific embodiment, the junction depth of Pwell region 7 is 0.4~0.8 μm, and the surface doping concentration is 3e16~5e16 cm⁻¹. -3 The doping concentration in the bulk region is 1e18~5e18cm. -3 The junction depth of the N+ source region 8 is 0.2~0.4 μm, and the doping concentration is 3e19~9e19 cm⁻¹. -3 The low doping concentration of Pwell region 7 facilitates the formation of an enhancement-mode channel, ensuring the device is off at zero gate voltage; while the high doping concentration in the remaining regions helps reduce bulk resistance and improve latch-up resistance. The high doping concentration of N+ source region 8 ensures good ohmic contact characteristics.

[0034] For example, the junction depth of Pwell region 7 is 0.4 μm, and the surface doping concentration is 4e16 cm⁻¹. -3 The bulk doping concentration is 1e18cm. -3 The junction depth of N+ source region 8 is 0.3 μm, and the doping concentration is 6e19cm. -3 .

[0035] In one specific embodiment, the thickness of the N+ substrate 1 is 300~400 μm, and the doping concentration is 4e18~6e18 cm⁻¹. -3 The thickness of N-drift region 2 is 10~14 μm, and the doping concentration is 7e15~1e16 cm⁻¹. -3 The thickness of epitaxial N-region 4 is 1.8~2.1 μm, and the doping concentration is 4e16~7e16 cm⁻¹. -3 .

[0036] For example, the N+ substrate 1 has a thickness of 330 μm and a doping concentration of 5e18 cm⁻¹. -3 The thickness of N-drift region 2 is 11 μm, and the doping concentration is 7e15cm. -3 The thickness of epitaxial N-region 4 is 2 μm, and the doping concentration is 6e16cm. -3 .

[0037] In one specific embodiment, the thickness of the gate oxide layer 9 is 50~60nm; the thickness of the polysilicon gate 10 is 0.5~1μm; the thickness of the isolation dielectric 11 is 1~1.2μm; the thickness of the source metal 12 is 4~5μm; and the thickness of the drain metal 13 is 4~5μm.

[0038] For example, the thickness of the gate oxide layer 9 is 60 nm; the thickness of the polysilicon gate 10 is 0.5 μm; the thickness of the isolation dielectric 11 is 1 μm; the thickness of the source metal 12 is 4 μm; and the thickness of the drain metal 13 is 4 μm.

[0039] The SiC VDMOSFET cell structure based on the non-floating buried layer of this invention can be a strip, square, hexagonal symmetrical cell structure, or an asymmetrical cell structure, to adapt to different device design and application requirements.

[0040] This invention forms a trench region in the epitaxial N-region, combined with the P+ source region at the bottom of the trench, creating an extremely low-impedance vertical charge discharge channel for the deep buried layer at the center of the device. This not only completely transforms the floating buried layer into a non-floating buried layer, allowing transient charge and discharge during high-frequency switching to be rapidly extracted by the source, but also significantly suppresses parasitic capacitance charging and discharging effects and dynamic resistance degradation under high dV / dt conditions. Simultaneously, this non-floating buried layer structure effectively shields the drain high voltage from impacting the JFET region and gate oxide layer, fundamentally reducing high-voltage stress at the bottom of the gate oxide. Through the full overlap design of the P+ source region at the bottom of the trench and the P-type non-floating buried layer, effective electrostatic shielding is formed for the physical sharp corners at the bottom of the trench, perfectly avoiding the risk of local electric field distortion and premature breakdown introduced by the trench. Therefore, compared with traditional SiC MOSFETs, this invention significantly improves the long-term gate oxide reliability and overall high-frequency switching performance of the device without sacrificing device symmetry or effective conduction area.

[0041] Example 2 Based on Example 1, this example provides a method for fabricating SiC VDMOSFETs based on non-floating buried layers.

[0042] Please see Figures 2a-2k , Figures 2a-2k This is a schematic diagram illustrating the fabrication process of a SiCVD MOSFET based on a non-floating buried layer, as provided in an embodiment of the present invention. The fabrication method includes the following steps: S1. An N- drift region 2 is grown on an N+ substrate 1.

[0043] Specifically, a doping concentration of 7e15~1e16cm is grown on N+ substrate 1 with a thickness of 10~14μm. -3 N-drift region 2, such as Figure 2a As shown.

[0044] S2. Ion implantation is performed on the N-drift region 2 to form a P-type non-floating buried layer 3.

[0045] Specifically, a silicon dioxide (SiO2) hard mask was used. In the N-drift region 2, conventional ion implantation with an energy of 60-700K and channel ion implantation with an energy of 700K and an implantation angle deviation of -4° were performed sequentially. The implanted ions included aluminum ions, with a dose of 4e14~1e15cm. -3 The junction depth is 2~4μm and the doping concentration is 3e19~8e19cm. -3 P-type non-floating buried layer 3, such as Figure 2b As shown, the P-type non-floating buried layer 3 forms two laterally separated regions, with an N-type region reserved between them as a current channel.

[0046] S3. Grow epitaxial N-region 4 on N-drift region 2.

[0047] Specifically, 4e16~7e16 cm² further grows on N-drift region 2. -3 The 1.8~2.1μm epitaxial layer N-region 4 is used as the N-drift region, such as... Figure 2c As shown.

[0048] S4. Etch the epitaxial N region 4 to form a trench region 5; the bottom of the trench region 5 is at a preset distance from the P-type non-floating buried layer 3.

[0049] Specifically, using a silicon dioxide hard mask, an etching process is employed to etch the epitaxial N-region 4, forming a deep contact trench region 5 with a width of 2.0~2.4μm and a depth of 1.0~1.4μm. The etching depth needs to be 0.5~0.9μm away from the top of the P-type non-floating buried layer 3 to facilitate the connection of the high-concentration doped regions. Figure 2d As shown.

[0050] S5. Ion implantation is performed at the bottom and sidewalls of trench region 5 to form P+ source region 6; the P+ source region 6 at the bottom of trench region 5 overlaps with the P-type non-floating buried layer 3.

[0051] Specifically, using a silicon dioxide hard mask, aluminum ions are implanted into the bottom and sidewalls of trench region 5 using a conventional ion implantation dose of 4e14~1e15 cm⁻³ at an energy of 60~700K, forming a junction depth of 0.8~1.0 μm and a doping concentration of 1e19~5e19 cm⁻³. -3 The P+ source region 6, and the bottom of the P+ source region 6 must be connected to the P-type non-floating buried layer 3 to form a sufficiently high-concentration doped region, thereby establishing a deep grounding path with extremely low impedance, such as... Figure 2eAs shown, both trench region 5 and P+ source region 6 form two laterally separated regions, with an N-type region reserved between them as a current path.

[0052] S6. Ion implantation is performed on the epitaxial N-region 4 to form Pwell region 7. Pwell region 7 is in contact with P+ source region 6 on the sidewall of trench region 5. P-type non-floating buried layer 3, trench region 5, P+ source region 6, Pwell region 7, and N+ source region 8 each form two regions that are spaced apart. The projection of one region of P-type non-floating buried layer 3 covers the projection of one region of Pwell region 7 and the projection of the current channel between the two regions of Pwell region 7.

[0053] Specifically, using a silicon dioxide hard mask, ion implantation is performed on the epitaxial N-region 4. The implanted ions include aluminum ions, with an energy of 60-480K and a dose of 1e12~2e14cm. -3 The junction depth is 0.4~0.8μm, and the surface doping concentration is 3e16~5e16cm. -3 The doping concentration in the bulk region is 1e18~5e18cm. -3 Pwell area 7, such as Figure 2f As shown, Pwell region 7 forms two horizontally separated regions, with an N-type region reserved between them as a current path. Together with the N-type region reserved between the two regions of P-type non-floating buried layer 3, trench region 5, and P+ source region 6, they form the device current path.

[0054] S7. Ion implantation is performed on Pwell region 7 to form N+ source region 8; N+ source region 8 extends from the surface of Pwell region 7 to the interior of Pwell region 7 and contacts P+ source region 6.

[0055] Specifically, using a silicon dioxide hard mask, ion implantation was performed on Pwell region 7. The implanted ions included nitrogen ions, with an energy of 35-160K and a dose of 4e14~6e14cm. -3 The junction depth is 0.2~0.4μm, and the doping concentration is 3e19~9e19cm. -3 N+ source region 8, such as Figure 2g As shown.

[0056] After all ion implantation processes are completed, the entire device is subjected to a high-temperature annealing process at 1700°C for 10 minutes to activate impurities in each implanted region and repair lattice damage caused by ion implantation.

[0057] S8. A gate oxide layer 9 is grown on the surface of the current channel between the two regions of Pwell region 7, Pwell region 7 and part of the N+ source region 8.

[0058] Specifically, an oxide layer of 50-60 nm is grown on the silicon carbide surface using a thermal oxidation process to form a gate oxide layer 9 as the gate thick dielectric layer, such as... Figure 2h As shown.

[0059] S9. Polysilicon is deposited on the gate oxide layer 9, and a polysilicon gate 10 is formed by etching process.

[0060] Specifically, a deposition process is used to deposit 0.5~1.0μm of polysilicon above the gate oxide layer 9, and an etching process is used to form the polysilicon gate 10, such as... Figure 2i As shown.

[0061] S10. An isolation dielectric material is deposited on the sample surface, and a source contact hole is formed by etching process to obtain an isolation dielectric 11. The isolation dielectric 11 covers the polysilicon gate 10 and extends from the side of the polysilicon gate 10 and the side of the gate oxide layer 9 to the surface of the N+ source region 8.

[0062] Specifically, through a deposition process, a 1-1.2 μm thick isolation dielectric 11 is deposited above and on both sides of the polysilicon gate 10 as an interlayer dielectric. Then, through an etching process, excess material on both sides of the isolation dielectric 11 is etched to form source contact holes, such as... Figure 2j As shown; S11. Metal is deposited in the trench region 5, on the P+ source region 6 on the sidewall of the trench region 5, on part of the surface of the N+ source region 8, and on the isolation medium 11 to form source metal 12; metal is deposited on the back side of the N+ substrate 1 to form drain metal 13.

[0063] Specifically, after an ohmic contact process at 1200±100℃ for 3-5 minutes, a deposition process is used to deposit 4-5 μm thick source metal 12 on the P+ source region 6, N+ source region 8, and isolation dielectric 11, respectively, and to deposit 4-5 μm thick drain metal 13 on the bottom of the device. Figure 2k As shown.

[0064] In the fabrication method of this embodiment, the etching process for the deep contact trench includes, but is not limited to, single-pass deep trench etching, multi-step deep trench etching, and other implementation methods. The high-dose ion implantation process at the bottom of the trench includes, but is not limited to, single or multiple implantations, to ensure that a sufficient high-concentration doping overlap is formed between the P+ source region 6 and the P-type non-floating buried layer 3.

[0065] To achieve reliable grounding of the buried layer and eliminate the aforementioned high-frequency dynamic parasitic effects, this embodiment employs a deep trench etching process combined with a high-dose P+ implantation at the bottom. Deep contact trenches are formed by etching downwards at the conventional P+ source region, and high-concentration ion implantation is performed at the bottom of the trenches. This constructs a highly doped, extremely low-resistance P+ charge discharge channel directly reaching the buried layer, physically and with low resistance, directly interconnecting the previously isolated buried layer with the source, transforming it into a non-floating buried layer. During the transient processes of high-voltage blocking and high-frequency switching, charge carriers within the depletion layer and around the buried layer can be rapidly extracted by the source along the high-concentration, low-resistance P+ region, thereby completely eliminating potential fluctuations and parasitic effects caused by the floating junction, while simultaneously providing stable shielding against the high-voltage, strong electric field beneath the gate oxide.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A SiC VDMOSFET based on a non-floating buried layer, characterized in that, include: N+ substrate (1); The N-drift region (2) is located on the N+ substrate (1); The P-type non-floating buried layer (3) extends from the surface of the N-drift region (2) to the interior of the N-drift region (2); The extended N region (4) is located on the N-drift region (2); The trench area (5) extends from the surface of the epitaxial N region (4) to the interior of the epitaxial N region (4), and its bottom is at a preset distance from the P-type non-floating buried layer (3); The P+ source region (6) extends from the bottom of the trench region (5) until it overlaps with the P-type non-floating buried layer (3) and is formed on the sidewall of the trench region (5). The Pwell region (7) extends from the surface of the epitaxial N region (4) into the interior of the epitaxial N region (4) and contacts the P+ source region (6) of the sidewall of the trench region (5); The N+ source region (8) extends from the surface of the Pwell region (7) into the interior of the Pwell region (7) and is in contact with the P+ source region (6); The P-type non-floating buried layer (3), trench region (5), P+ source region (6), Pwell region (7), and N+ source region (8) each form two regions that are spaced apart; the projection of one region of the P-type non-floating buried layer (3) covers the projection of the corresponding side region of the Pwell region (7) and the projection of the current path between the two regions of the Pwell region (7).

2. The SiC VDMOSFET based on a non-floating buried layer according to claim 1, characterized in that, The junction depth of the P-type non-floating buried layer (3) is 2~4 μm, and the doping concentration is 3e19~8e19 cm. -3 ; The doping concentration of the P+ source region (6) is 1e19~5e19 cm⁻¹ -3 The junction depth of the P+ source region (6) at the bottom of the trench region (5) is 0.8~1.0 μm; A high-concentration doped region is formed between the P-type non-floating buried layer (3) and the P+ source region (6).

3. The SiC VDMOSFET based on a non-floating buried layer according to claim 1, characterized in that, The width of the trench area (5) is 2.0~2.4 μm and the depth is 1.0~1.4 μm; The distance between the bottom of the trench area (5) and the top of the non-floating buried layer (3) is 0.5~0.9μm.

4. The SiC VDMOSFET based on a non-floating buried layer according to claim 1, characterized in that, The junction depth of the Pwell region (7) is 0.4~0.8 μm, and the surface doping concentration is 3e16~5e16 cm. -3 The doping concentration in the bulk region is 1e18~5e18cm. -3 ; The junction depth of the N+ source region (8) is 0.2~0.4 μm, and the doping concentration is 3e19~9e19 cm⁻¹. -3 .

5. The SiC VDMOSFET based on a non-floating buried layer according to claim 1, characterized in that, The N+ substrate (1) has a thickness of 300~400 μm and a doping concentration of 4e18~6e18 cm⁻¹. -3 ; The thickness of the N-drift region (2) is 10~14 μm, and the doping concentration is 7e15~1e16 cm. -3 ; The thickness of the epitaxial N-region (4) is 1.8~2.1 μm, and the doping concentration is 4e16~7e16 cm⁻¹. -3 .

6. The SiC VDMOSFET based on a non-floating buried layer according to claim 1, characterized in that, Also includes: The gate oxide layer (9) covers at least the surface of the current channel between the two regions of the Pwell region (7), the Pwell region (7), and part of the N+ source region (8); A polysilicon gate (10) is located on the gate oxide layer (9); An isolation medium (11) covers the polysilicon gate (10) and extends from the side of the polysilicon gate (10) and the side of the gate oxide layer (9) to the surface of the N+ source region (8); Source metal (12) fills the trench region (5) and covers part of the surface of the P+ source region (6) and N+ source region (8) on the sidewall of the trench region (5) as well as the isolation medium (11); Drain metal (13) is located on the back side of the N+ substrate (1).

7. The SiC VDMOSFET based on a non-floating buried layer according to claim 6, characterized in that, The thickness of the gate oxide layer (9) is 50~60 nm; The thickness of the polysilicon gate (10) is 0.5~1μm; The thickness of the isolation medium (11) is 1~1.2 μm; The thickness of the source metal (12) is 4~5 μm; The thickness of the drain metal (13) is 4~5 μm.

8. A method for fabricating a SiC VDMOSFET based on a non-floating buried layer, characterized in that, Including the following steps: An N- drift region (2) is grown on an N+ substrate (1); Ion implantation is performed on the N-drift region (2) to form a P-type non-floating buried layer (3); An epitaxial N-region (4) is grown on the N-drift region (2); The epitaxial N region (4) is etched to form a trench region (5); the bottom of the trench region (5) is a trench region (5) at a preset distance from the P-type non-floating buried layer (3); Ion implantation is performed at the bottom and sidewalls of the trench region (5) to form a P+ source region (6); the P+ source region (6) at the bottom of the trench region (5) overlaps with the P-type non-floating buried layer (3); Ion implantation is performed on the epitaxial N region (4) to form a Pwell region (7); the Pwell region (7) is in contact with the P+ source region (6) on the sidewall of the trench region (5); the P-type non-floating buried layer (3), the trench region (5), the P+ source region (6), the Pwell region (7), and the N+ source region (8) each form two regions that are spaced apart; the projection of one region of the P-type non-floating buried layer (3) covers the projection of one region of the Pwell region (7) and the projection of the current channel between the two regions of the Pwell region (7); Ion implantation is performed on the Pwell region (7) to form an N+ source region (8); the N+ source region (8) extends from the surface of the Pwell region (7) into the interior of the Pwell region (7) and is in contact with the P+ source region (6).

9. The method for fabricating a SiC VDMOSFET based on a non-floating buried layer according to claim 8, characterized in that, Ion implantation is performed on the N-drift region (2) to form a P-type non-floating buried layer (3), including: sequentially performing conventional ion implantation with an energy of 60~700k and channel ion implantation with an energy of 700k and an implantation angle deviation of -4° on the N-drift region (2), the implanted ions including aluminum ions, and the dose is 4e14~1e15 cm. -3 , forming a P-type non-floating buried layer (3); Etching the epitaxial N-region (4) to form a trench region (5) includes: using a silicon dioxide hard mask to etch the epitaxial N-region (4) using an etching process to form a trench region (5); Ion implantation is performed on the bottom and sidewalls of the trench region (5) to form a P+ source region (6), including: using a silicon dioxide hard mask, ion implantation is performed on the bottom and sidewalls of the trench region (5) using an ion implantation process, the implanted ions include aluminum ions, the energy is 60-700K, and the dose is 4e14~1e15cm. -3 , forming a P+ source region (6); Ion implantation is performed on the epitaxial N-region (4) to form a Pwell region (7), including: using a silicon dioxide hard mask, ion implantation is performed on the epitaxial N-region (4) using an ion implantation process, the implanted ions include aluminum ions, the energy is 60-480K, and the dose is 1e12~2e14cm. -3 This forms the Pwell region (7); Ion implantation is performed on the Pwell region (7) to form an N+ source region (8), including: using a silicon dioxide hard mask, ion implantation is performed on the Pwell region (7) using an ion implantation process, the implanted ions include nitrogen ions, the energy is 35-160K, and the dose is 4e14~6e14cm. -3 This forms the N+ source region (8).

10. The method for fabricating a SiC VDMOSFET based on a non-floating buried layer according to claim 8, characterized in that, It also includes the following steps: A gate oxide layer (9) is grown on the surface of the current channel between the two regions of Pwell region (7), Pwell region (7) and part of N+ source region (8); Polysilicon is deposited on the gate oxide layer (9), and a polysilicon gate (10) is formed by etching process; An isolation dielectric material is deposited on the sample surface, and a source contact hole is formed by etching process to obtain an isolation dielectric (11); the isolation dielectric (11) covers the polysilicon gate (10) and extends from the side of the polysilicon gate (10) and the side of the gate oxide layer (9) to the surface of the N+ source region (8). Metal is deposited in the trench region (5), on the P+ source region (6) of the sidewall of the trench region (5), on part of the surface of the N+ source region (8), and on the isolation medium (11) to form source metal (12); A drain metal (13) is formed by depositing metal on the back side of the N+ substrate (1).

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