A semiconductor structure and a method of fabricating the same

Abstract

This application relates to a semiconductor structure and its fabrication method, comprising the following steps: providing a substrate; forming a gate structure on one side of the substrate, the gate structure including a gate dielectric layer and a gate layer sequentially stacked along a first direction; forming a buffer material layer covering the gate structure; forming an etching control material layer covering the buffer material layer, the etching control material layer including a first portion located on both sides of the gate layer along a second direction and a second portion covering the top and sidewalls of the gate layer, the first portion including a preset implantation region near the gate layer; implanting control ions into the first portion based on the preset implantation region to form a first implantation region near the gate layer and a second implantation region away from the gate layer, wherein the concentration of control ions in the first implantation region is greater than that in the second implantation region; forming a protective material layer; etching the protective material layer, the etching control material layer, and the buffer material layer to expose the gate dielectric layer and form a sidewall structure. The above improves the uniformity of the gate dielectric layer thickness and enhances device performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As the feature size of semiconductor devices continues to shrink, the size control of the gate structure and its adjacent sidewall structure has an increasingly significant impact on device performance. In advanced logic device manufacturing processes, the sidewall structure is typically achieved by sequentially forming dielectric material layers on the surface of the gate structure and then performing anisotropic etching. The sidewall structure not only defines the formation location of the source and drain regions but also has a significant impact on subsequent ion implantation and device electrical characteristics.

[0003] In existing semiconductor manufacturing processes for high-voltage (HV) devices based on the 90nm process platform, the formation of sidewall structures typically involves the deposition of multiple layers of dielectric materials and a uniform etching process. However, during sidewall etching, due to the loading effect inherent in the etching process formulation, the distribution of etching plasma is not uniform across different regions. In particular, the plasma concentration is relatively high in the region near the gate polysilicon structure, resulting in a significantly faster etching rate in this region compared to the region farther from the gate.

[0004] The non-uniformity of the etching rate results in a thinner residual oxide layer near the gate structure and a thicker residual oxide layer further away from the gate structure after sidewall etching. This creates micro-trench structures with localized depressions near the gate structure. This micro-trench phenomenon causes non-uniformity in the sidewall structure profile, which in turn affects the shielding and limiting effect of the sidewalls on subsequent processes.

[0005] Furthermore, in subsequent ion implantation processes, due to the difference in dielectric layer thickness between the micro-trench region and the non-micro-trench region, the energy attenuation and distribution of implanted ions differ in different regions, resulting in differences in ion implantation concentration between the region near the gate and the region far from the gate. This implantation inhomogeneity ultimately causes fluctuations in device electrical parameters, such as inconsistent threshold voltage, increased leakage current, or decreased reliability, thereby reducing device consistency and yield.

[0006] Therefore, there is an urgent need in the existing technology for a semiconductor structure fabrication method that can improve the problem of uneven etching rate during sidewall etching, suppress the micro trench phenomenon, and further improve the uniformity of subsequent ion implantation and the stability of device electrical performance. Summary of the Invention

[0007] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem in the prior art where microgrooves appear in the sidewall region due to differences in plasma loading effects during etching, which in turn causes uneven distribution of implanted ion concentration and affects the electrical performance of the device.

[0008] To achieve the above objectives, this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0009] Provide substrate;

[0010] A gate structure is formed on one side of the substrate, the gate structure comprising a gate dielectric layer and a gate layer sequentially stacked along a first direction;

[0011] A buffer material layer covering the gate structure is formed;

[0012] An etching control material layer is formed covering the buffer material layer, wherein the etching control material layer includes a first part and a second part connected to each other, the first part is located on both sides of the gate layer along the second direction, the second part covers the top and sidewalls of the gate layer, and the first part includes a preset implantation region located on the side close to the gate layer, the first direction intersecting the second direction;

[0013] Based on the preset implantation region, regulating ions are implanted in the first part to form a first implantation region and a second implantation region in the first part. The first implantation region is located on the side close to the gate layer, and the second implantation region is located on the side away from the gate layer. The concentration of regulating ions in the first implantation region is greater than the concentration of regulating ions in the second implantation region.

[0014] A protective material layer is formed covering the etching control material layer;

[0015] The protective material layer, the etching control material layer, and the buffer material layer are etched to expose the gate dielectric layer. The etched protective material layer, the etching control material layer, and the buffer material layer serve as the protective layer, the etching control layer, and the buffer layer, respectively, and the protective layer, the etching control layer, and the buffer layer constitute the sidewall structure.

[0016] In one embodiment, injecting regulating ions into the first part based on the preset injection region includes:

[0017] Based on the preset implantation region, at least two doses of the modulating ion are implanted in the first part to obtain the first implantation region and the second implantation region. The first implantation region is located on the side close to the gate layer and is the region where at least one dose of the modulating ion is implanted. The second implantation region is located on the side away from the gate layer and is the region where at least two doses of the modulating ion are implanted.

[0018] In one embodiment, the preset implantation region includes a first preset implantation region and a second preset implantation region, wherein the first preset implantation region and the second preset implantation region are respectively located in the first portion on both sides of the gate structure along the second direction, and the step of implanting the regulating ions at least twice in the first portion based on the preset implantation region includes:

[0019] Based on the first preset injection area, the first injection angle is obtained;

[0020] The first part is injected with the modulating ions at least once along the first injection angle;

[0021] Based on the second preset injection region, a second injection angle is obtained, and the first injection angle and the second injection angle correspond to different directions on both sides of the gate structure, respectively.

[0022] The first part is implanted with the regulating ions at least once along the second implantation angle, wherein the region having both the regulating ions implanted along the first implantation angle and the regulating ions implanted along the second implantation angle is designated as the second implantation region, and the region having only the regulating ions implanted along the first implantation angle or the region having only the regulating ions implanted along the second implantation angle is designated as the first implantation region.

[0023] In one embodiment, the first injection angle is obtained based on the sum of the width of the first preset injection region in the second direction and the thickness of the gate structure, the buffer material layer, and the etching control material layer in the first direction;

[0024] The second injection angle is obtained based on the width of the second preset injection region in the second direction and the sum of the thicknesses of the gate structure, the buffer material layer, and the etching control material layer in the first direction.

[0025] In one embodiment, the etching control material layer is a dielectric material with covalent bonds, and the controlling ion is an ion that can weaken the covalent bond strength within the etching control material layer.

[0026] In one embodiment, the regulating ion includes fluoride ions; the material of the etching control material layer includes silicon nitride.

[0027] In one embodiment, the implantation dose of the modulated ions ranges from 1 × 10⁻⁶. 14 ~1×10 16 cm -2 The implantation energy of the regulating ions is 5keV~50keV.

[0028] In one embodiment, the sidewall structure further includes a first isolation layer and a second isolation layer, and before forming the buffer material layer covering the gate structure, it further includes:

[0029] A first isolation layer and a second isolation layer are formed, wherein the first isolation layer covers the sidewalls of the gate layer on both sides in the second direction, and the second isolation layer covers the sidewalls of the first isolation layer away from the gate layer.

[0030] In one embodiment, the etching process on the protective material layer, the etching control material layer, and the buffer material layer includes:

[0031] The protective material layer, the etching control material layer, and the buffer material layer are etched sequentially so that the etched protective material layer, the etching control material layer, and the buffer material layer are located on both sides of the gate layer along the second direction to form the protective layer, the etching control layer, and the buffer layer, thereby obtaining the sidewall structure.

[0032] This application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in any of the above embodiments.

[0033] The aforementioned semiconductor structure and its fabrication method have the following beneficial effects: By implanting regulating ions into the first part based on a preset implantation region near the gate layer, a first implantation region and a second implantation region are formed in the first part. The first implantation region is located near the gate layer, and the second implantation region is located away from the gate layer. The concentration of regulating ions in the first implantation region is greater than that in the second implantation region. During the subsequent etching process of the protective material layer, etching control material layer, and buffer material layer to expose the gate dielectric layer, the etching rate of the etching control material in the first and second implantation regions differs, which effectively regulates the etching behavior near the gate layer. This compensates for the etching unevenness caused by the microchannel effect at the preset implantation region. As a result, after the sidewall structure is formed, the gate dielectric layer thickness corresponding to the preset implantation region can be consistent with the gate dielectric layer thickness corresponding to other regions in the first part, improving the morphological consistency and cross-sectional uniformity of the gate dielectric layer, thereby improving the electrical consistency and overall performance of the device. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 SEM images of semiconductor structures in the prior art;

[0036] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0037] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the gate structure is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0038] Figure 4 This is a schematic cross-sectional view of the semiconductor structure after the buffer material layer is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0039] Figure 5 This is a schematic diagram of the cross-sectional structure after forming an etching control material layer in a semiconductor structure fabrication method provided in one embodiment;

[0040] Figure 6 This is a schematic diagram of the cross-sectional structure after ion implantation with an adjusted first implantation angle in a semiconductor structure fabrication method provided in one embodiment.

[0041] Figure 7 This is a schematic diagram of the cross-sectional structure after ion implantation with adjusted ions along the second implantation angle in a semiconductor structure fabrication method provided in one embodiment.

[0042] Figure 8 This is a schematic cross-sectional view of the semiconductor structure after the protective material layer is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0043] Figure 9 This is a schematic diagram of the cross-sectional structure after the sidewall structure is formed in the semiconductor structure fabrication method provided in one embodiment.

[0044] Explanation of reference numerals in the attached figures:

[0045] 10-Microchannel region, 1-Substrate, 2-Gate structure, 21-Gate dielectric layer, 22-Gate layer, 3-Buffer material layer, 4-Etching control material layer, 41-First part, 411-Preset implantation region, 411a-First preset implantation region, 411b-Second preset implantation region, 412-First implantation region, 413-Second implantation region, 42-Second part, 5-Protective material layer, 6-Buffer layer, 7-Etching control layer, 8-Protective layer, 9-Sidewall structure, 91-First isolation layer, 92-Second isolation layer. Detailed Implementation

[0046] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0051] As mentioned in the background section, in existing technologies, anisotropic etching is typically performed directly after forming the various material layers of the sidewall structure to form the sidewall structure. However, please refer to... Figure 1 The image shows a SEM image of a semiconductor structure in the prior art. In the gate dielectric layer near the gate layer, due to the electric field concentration effect and ion reflection effect of the plasma in the region near the gate structure during the etching process, the etching rate in the region near the bottom of the gate layer sidewall is higher than that in the region far away from the gate layer, thus producing a local over-etching phenomenon in this region, forming a microchannel region 10.

[0052] In the microchannel region 10, the gate dielectric layer is significantly thinner than in other regions, weakening its ability to block implanted ions. This can lead to abnormal penetration or lateral diffusion of ions near the gate structure, causing a shift in the implantation distribution and affecting the channel length control accuracy and junction distribution uniformity. Furthermore, the non-uniformity of the local electric field distribution may further amplify electrical fluctuations after ion implantation, leading to threshold voltage drift or increased leakage current, thus affecting device consistency and reliability.

[0053] To resolve the above issues, please refer to [link / reference]. Figure 2 This application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0054] Step S1: Provide substrate 1;

[0055] Step S2: A gate structure 2 is formed on one side of the substrate 1. The gate structure 2 includes a gate dielectric layer 21 and a gate layer 22 stacked sequentially along the first direction.

[0056] Step S3: Form a buffer material layer 3 covering the gate structure 2;

[0057] Step S4: Form an etching control material layer 4 covering the buffer material layer 3, wherein the etching control material layer 4 includes a first part 41 connected to the second part 42, the first part 41 being located on both sides of the gate layer 22 along the second direction, the second part 42 covering the top and sidewalls of the gate layer 22, and the first part 41 including a preset implantation region 411, the first direction intersecting the second direction.

[0058] Step S5: Based on the preset implantation region 411, conditioning ions are implanted into the first part 41 to form a first implantation region 412 and a second implantation region 413 in the first part 41. The first implantation region 412 is located on the side close to the gate layer 22, and the second implantation region 413 is located on the side of the first implantation region 412 away from the gate layer 22. The concentration of conditioning ions in the second implantation region 413 is greater than the concentration of conditioning ions in the first implantation region 412.

[0059] Step S6: Form a protective material layer 5 covering the etching control material layer 4;

[0060] Step S7: Etch the protective material layer 5, the etching control material layer 4, and the buffer material layer 3 to expose the gate dielectric layer 21. The etched protective material layer 5, the etching control material layer 4, and the buffer material layer 3 serve as the protective layer 8, the etching control layer 7, and the buffer layer 6, respectively. The protective layer 8, the etching control layer 7, and the buffer layer 6 constitute the sidewall structure 9.

[0061] In the above example, conditioning ions are implanted into the first part 41 based on a preset implantation region 411 near the gate layer 22, so that a first implantation region 412 and a second implantation region 413 are formed in the first part 41. The first implantation region 412 is located near the gate layer 22, and the second implantation region 413 is located away from the gate layer 22. The concentration of conditioning ions in the first implantation region 412 is greater than the concentration of conditioning ions in the second implantation region 413. In the subsequent etching process of the protective material layer 5, the etching control material layer 4, and the buffer material layer 3 to expose the gate dielectric layer 21. In this process, due to the difference in etching rates between the etching control materials in the first injection region 412 and the second injection region 413, the etching behavior near the gate layer 22 is effectively regulated, thereby compensating for the uneven etching problem caused by the microchannel effect in the preset injection region 411. As a result, after the sidewall structure 9 is formed, the thickness of the gate dielectric layer 21 corresponding to the preset injection region 411 can be consistent with the thickness of the gate dielectric layer 21 corresponding to other regions in the first part 41, improving the morphological consistency and cross-sectional uniformity of the gate dielectric layer 21, and thus improving the electrical consistency and overall performance of the device.

[0062] Specifically, please refer to Figure 3 Steps S1 to S2 are performed to provide a substrate 1; a gate structure 2 is formed on one side of the substrate 1. The gate structure 2 includes a gate dielectric layer 21 and a gate layer 22 stacked sequentially along a first direction, wherein the first direction is the thickness direction of the gate structure 2.

[0063] In one embodiment, substrate 1 is used to carry and support the device structure formed thereon, and serves as the basic structural layer of the semiconductor device. Substrate 1 also includes an active region, which can be used to form an active device structure.

[0064] In this embodiment, the material of substrate 1 may include, but is not limited to, silicon (Si) substrate, germanium (Ge) substrate, silicon germanide (SiGe) substrate, silicon-on-insulator (SOI) substrate, and germanium-on-insulator (GOI) substrate.

[0065] In one embodiment, the substrate 1 may also be a stacked structure, such as a silicon / silicon germanium stacked structure, a multilayer semiconductor stacked structure, or other composite substrate structures suitable for semiconductor device manufacturing.

[0066] It should be noted that the size, doping type, and doping concentration of substrate 1 can be selected according to the specific device type and process requirements, and are not specifically limited in this specification.

[0067] In one embodiment, such as Figure 3As shown, a gate structure 2 is formed on one side of the substrate 1, including:

[0068] A gate dielectric layer 21 is formed on one side of the substrate 1. The method for forming the gate dielectric layer 21 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the gate dielectric layer 21 includes silicon dioxide or other suitable dielectric materials. The gate dielectric layer 21 is used to isolate the gate layer 22 from the substrate 1 and to control the electrical characteristics of the device in subsequent processes.

[0069] A gate layer 22 is formed on the side of the gate dielectric layer 21 away from the substrate 1. The method for forming the gate layer 22 includes chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the gate layer 22 includes polysilicon, metal material or other suitable material. The gate layer 22 is used to form the gate electrode to realize the gate control function of the device.

[0070] It should be noted that both the gate dielectric layer 21 and the gate layer 22 have been patterned to meet actual design requirements.

[0071] In one embodiment, the orthogonal projection of the gate layer 22 on the substrate 1 is located within the orthogonal projection region of the gate dielectric layer 21 on the substrate 1, thereby providing positioning and shielding functions for subsequent formation of sidewall structures and ion implantation.

[0072] Specifically, please refer to Figure 4 Step S3 is executed to form a buffer material layer 3 covering the gate structure 2.

[0073] In one embodiment, the sidewall structure 9 further includes a first isolation layer 91 and a second isolation layer 92, and before forming the buffer material layer 3 covering the gate structure 2, it further includes:

[0074] A first isolation layer 91 and a second isolation layer 92 are formed. The first isolation layer 91 covers the sidewalls of the gate layer 22 on both sides in the second direction, and the second isolation layer 92 covers the sidewalls of the first isolation layer 91 away from the gate layer 22.

[0075] The first isolation layer 91 is made of silicon dioxide or other suitable dielectric material. The first isolation layer 91 isolates the sidewalls of the gate layer 22 and provides subsequent sidewall protection. Methods for forming the first isolation layer 91 include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0076] The second isolation layer 92 is made of silicon nitride or other suitable materials, and serves to enhance sidewall protection and block subsequent ion implantation. Methods for forming the second isolation layer 92 include thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0077] In one embodiment, such as Figure 4As shown, the method for forming the buffer material layer 3 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. The material of the buffer material layer 3 includes silicon dioxide and can be formed using TEOS. The buffer material layer 3 is used to provide protection and thickness control between the gate structure 2 and the subsequent etching control material layer.

[0078] Specifically, please refer to Figure 5 Step S4 is executed to form an etching control material layer 4 covering the buffer material layer 3. The etching control material layer 4 includes a first part 41 connected to each other. The first part 41 is located on both sides of the gate layer 22 along the second direction. The second part 42 covers the top and sidewalls of the gate layer 22. The first part 41 includes a preset implantation region 411. The first direction intersects with the second direction.

[0079] In one embodiment, the method for forming the etching control material layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. The material of the etching control material layer 4 includes silicon nitride. The first part 41 is used for subsequent ion implantation adjustment and is the main region for adjusting the etching rate.

[0080] The preset implantation region 411 is located near the gate layer 22. Through process analysis, the applicant discovered that during the sidewall etching process of the prior art, due to the effect of etching loading, the etching rate in the region near the gate layer 22 is relatively high, which reduces the thickness of the gate dielectric layer in this region, thereby forming a microchannel region 10 near the gate layer 22.

[0081] Therefore, the size of the preset implantation region 411 corresponds to the size of the microchannel region 10 mentioned above, and the preset implantation region 411 is a region with abnormal etching rate during the sidewall etching process. By adjusting ion implantation within this preset implantation region 411, the etching rate in this region can be specifically controlled, thereby improving the problem of uneven gate dielectric layer thickness after sidewall etching.

[0082] Specifically, please refer to Figures 6 to 7 In step S5, based on the preset implantation region 411, regulating ions are implanted into the first part 41 to form a first implantation region 412 and a second implantation region 413 in the first part 41. The first implantation region 412 is located on the side close to the gate layer 22, and the second implantation region 413 is located on the side of the first implantation region 412 away from the gate layer 22. The concentration of regulating ions in the second implantation region 413 is greater than the concentration of regulating ions in the first implantation region 412.

[0083] In one embodiment, injecting modulating ions into the first part 41 based on a preset injection region 411 includes:

[0084] Based on the preset implantation region 411, at least two controlled ion implantations are performed in the first part 41 to obtain a first implantation region 412 and a second implantation region 413. The first implantation region 412 is located on the side close to the gate layer 22 and is the region where one controlled ion implantation is performed. The second implantation region 413 is located on the side away from the gate layer 22 and is the region where at least two controlled ion implantations are performed.

[0085] In one embodiment, such as Figure 6 and Figure 7 As shown, the preset implantation region 411 includes a first preset implantation region 411a and a second preset implantation region 411b. The first preset implantation region 411a and the second preset implantation region 411b are respectively located in the first part 41 on both sides of the gate structure 2 along the second direction. Based on the preset implantation region 411, at least two controlled ion implantations are performed in the first part 41, including:

[0086] Based on the first preset injection area 411a, the first injection angle is determined;

[0087] At least one controlled ion is implanted into the first part 41 along the first injection angle;

[0088] Based on the second preset injection region 411b, the second injection angle is determined. The first injection angle and the second injection angle correspond to different injection directions on both sides of the gate structure 2, respectively.

[0089] At least one adjustment ion is implanted into the first part 41 along the second injection angle, wherein the region having adjustment ions implanted along both the first injection angle and the second injection angle is designated as the second injection region 413; and the region having only adjustment ions implanted along the first injection angle or only adjustment ions implanted along the second injection angle is designated as the first injection region 412.

[0090] In one embodiment, the first injection angle is obtained based on the sum of the width of the first preset injection region 411a in the second direction and the thickness of the gate structure 2, the buffer material layer 3, and the etching control material layer 4 in the first direction; the second injection angle is obtained based on the sum of the width of the second preset injection region 411b in the second direction and the thickness of the gate structure 2, the buffer material layer 3, and the etching control material layer 4 in the first direction.

[0091] Specifically, the sum of the thicknesses of the gate structure 2, the buffer material layer 3, and the etching control material layer 4 in the first direction is L, and the width of the first preset implantation region 411a in the second direction is S1. Therefore, the first implantation angle θ1 satisfies θ1 = arctan(L / S1). Similarly, the width of the second preset implantation region 411b in the second direction is S2, and the second implantation angle θ2 satisfies θ2 = arctan(L / S2). The widths of the first preset implantation region 411a and the second preset implantation region 411b in the second direction are known parameters. Specifically, the widths of the first preset implantation region 411a and the second preset implantation region 411b in the second direction correspond to the equivalent widths of the microchannel regions 10 on both sides of the gate structure 2, respectively. These equivalent widths can be obtained by the applicant in the preceding process steps. Figure 1 The width of the microchannel region 10 in the SEM image was measured. It should be noted that the thickness of the gate structure 2, buffer material layer 3, and etching control material layer 4 in the first direction, the width of the first preset injection region 411a in the second direction, the width of the second preset injection region 411b in the second direction, and the specific values ​​of the first injection angle and the second injection angle can be selected according to the actual situation, and are not limited here.

[0092] When ion implantation is adjusted based on the first implantation angle, the region near the gate layer 22 on the side opposite to the first implantation angle is blocked by the gate structure 2 and cannot be implanted; when ion implantation is adjusted based on the second implantation angle, the region near the gate layer 22 on the side opposite to the second implantation angle is also blocked by the gate structure 2. Through the above-mentioned blocking effect, a first implantation region 412 and a second implantation region 413 with different implantation times are formed in the first part 41.

[0093] In this embodiment, regulating ions are implanted twice at symmetrical angles, that is, the first implantation angle and the second implantation angle are the same in magnitude but opposite in direction, and regulating ion implantation is performed on both sides of the gate structure 2. The first implantation region 412 is implanted with regulating ions only once, while the second implantation region 413 is implanted with regulating ions twice. Therefore, the concentration of regulating ions in the second implantation region 413 is greater than the concentration of regulating ions in the first implantation region 412.

[0094] The range of the implantation dose for the aforementioned ion regulation is 1×10⁻⁶. 14 ~1×10 16 cm -2 In this embodiment, the ion implantation dose is adjusted to 1×10⁻⁶. 15 cm -2The ion implantation energy is adjusted to be between 5 keV and 50 keV. When the implantation energy is below 5 keV, the ion implantation depth is too shallow, making it difficult to effectively adjust the etching characteristics; when the implantation energy is above 50 keV, the ion implantation is too deep, which may damage the underlying structure. In this embodiment, the ion implantation energy is adjusted to be between 10 keV and 30 keV.

[0095] Furthermore, in one embodiment, the etching control material layer 4 is a dielectric material with a covalent bond structure, and the regulating ion is an ion that can weaken the covalent bond strength inside the etching control material layer 4.

[0096] For example, the regulating ions include fluoride ions, and the material of the etching control material layer 4 includes silicon nitride.

[0097] By introducing regulating ions into the etching control material layer 4 of silicon nitride, the regulating ions form new chemical bond structures with the silicon elements in silicon nitride, weakening the original silicon-nitrogen covalent bond strength. This makes the etching control material layer 4 more likely to react with the etchant during subsequent etching, thereby increasing the etching rate of the etching control material layer 4. This, in turn, compensates for the insufficient etching of the micro-trench region caused by the etching loading effect, improves the morphological consistency of the sidewall structure, reduces the effective oxide layer thickness difference during subsequent ion implantation, and enhances the electrical consistency and reliability of the device.

[0098] In one embodiment, the thickness of the second isolation layer 92 is less than the thickness of the etching control material layer 4, so that the etching control material layer 4 acts as the main influencing layer of the etching rate during the sidewall etching process.

[0099] Specifically, please refer to Figure 8 Step S6 is executed to form a protective material layer 5 covering the etching control material layer 4.

[0100] In one embodiment, the method for forming the protective material layer 5 covering the etching control material layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0101] The protective material layer 5 is made of silicon dioxide, silicon nitride, or other dielectric materials with a high etching selectivity, and is used to provide etching protection and morphology constraints for the underlying etching control material layer 4 during subsequent etching processes.

[0102] Specifically, please refer to Figure 9 Step S7 is executed to etch the protective material layer 5, the etching control material layer 4 and the buffer material layer 3 to expose the gate dielectric layer 21. The etched protective material layer 5, the etching control material layer 4 and the buffer material layer 3 serve as the protective layer 8, the etching control layer 7 and the buffer layer 6, respectively. The protective layer 8, the etching control layer 7 and the buffer layer 6 constitute the sidewall structure 9.

[0103] In one embodiment, etching is performed on the protective material layer 5, the etching control material layer 4, and the buffer material layer 3, including:

[0104] The protective material layer 5, the etching control material layer 4, and the buffer material layer 3 are etched sequentially so that the etched protective material layer 5, the etching control material layer 4, and the buffer material layer 3 are located on both sides of the gate layer 22 along the second direction, forming the protective layer 8, the etching control layer 7, and the buffer layer 6, thereby obtaining the sidewall structure 9. The etching method for the protective material layer 5, the etching control material layer 4, and the buffer material layer 3 includes anisotropic dry etching, with etching conditions set to have a predetermined etching selectivity ratio for different materials to ensure controllable morphology of the sidewall structure 9.

[0105] During the etching process, since there are a first implantation region 412 and a second implantation region 413 in the first part 41 of the etching control material layer 4, and the doping concentration of the control ions in the first implantation region 412 and the second implantation region 413 is different, the first part 41 has different etching rate compensation effects in the region close to the gate structure 2 and the region far away from the gate structure 2.

[0106] Therefore, after etching is completed, the thickness distribution of the gate dielectric layer 21 exposed on both sides of the gate structure 2 tends to be consistent, effectively suppressing the problem of excessive or insufficient local etching caused by the micro-trench effect.

[0107] In one embodiment, after etching the protective material layer 5, the etching control material layer 4, and the buffer material layer 3, the method further includes:

[0108] Ion implantation is performed in the active region of substrate 1 to form device structure regions such as well region, source region, and drain region.

[0109] The above-described semiconductor structure fabrication method introduces ion implantation regions with spatially differentiated distributions into the first part 41 of the etching control material layer 4, and utilizes the compensation effect of different etching rates in subsequent etching processes to effectively control the micro-trench regions on both sides of the gate structure 2. This reduces the etching non-uniformity caused by plasma loading during sidewall etching, ensuring consistent exposed thickness of the gate dielectric layer 21 at different locations. Consequently, it reduces the impact of ion distribution differences during subsequent ion implantation on the device's electrical performance, improving device consistency and reliability.

[0110] In one embodiment, please continue reading Figure 9 This application also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method of any of the above embodiments, and the semiconductor structure includes:

[0111] The substrate 1, gate structure 2, and sidewall structure 9 are provided. The gate structure 2 is located on one side of the substrate 1, and the sidewall structure 9 is located on both sides of the gate structure 2. The sidewall structure 9 includes a buffer layer 6, an etching control layer 7, and a protective layer 8 arranged sequentially.

[0112] In one embodiment, the sidewall structure 9 further includes a first isolation layer 91 and a second isolation layer 92, the first isolation layer 91 covering the sidewalls of the gate layer 22 on both sides in the second direction, and the second isolation layer 92 covering the sidewalls of the first isolation layer 91 away from the gate layer 22.

[0113] In one embodiment, the active region of substrate 1 further includes device structure regions such as well region, source region, and drain region.

[0114] For specific details regarding the above semiconductor structure, please refer to the embodiments of the above semiconductor structure preparation method for understanding, and will not be repeated here.

[0115] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0116] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; A gate structure is formed on one side of the substrate, the gate structure comprising a gate dielectric layer and a gate layer sequentially stacked along a first direction; A buffer material layer covering the gate structure is formed; An etching control material layer is formed covering the buffer material layer, wherein the etching control material layer includes a first part and a second part connected to each other, the first part is located on both sides of the gate layer along the second direction, the second part covers the top and sidewalls of the gate layer, and the first part includes a preset implantation region located on the side close to the gate layer, the first direction intersecting the second direction; Based on the preset implantation region, regulating ions are implanted in the first part to form a first implantation region and a second implantation region in the first part. The first implantation region is located on the side close to the gate layer, and the second implantation region is located on the side away from the gate layer. The concentration of regulating ions in the first implantation region is greater than the concentration of regulating ions in the second implantation region. A protective material layer is formed covering the etching control material layer; The protective material layer, the etching control material layer, and the buffer material layer are etched to expose the gate dielectric layer. The etched protective material layer, the etching control material layer, and the buffer material layer serve as the protective layer, the etching control layer, and the buffer layer, respectively, and the protective layer, the etching control layer, and the buffer layer constitute the sidewall structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The injection of regulating ions into the first part based on the preset injection region includes: Based on the preset implantation region, at least two doses of the modulating ion are implanted in the first part to obtain the first implantation region and the second implantation region. The first implantation region is located on the side close to the gate layer and is the region where at least one dose of the modulating ion is implanted. The second implantation region is located on the side away from the gate layer and is the region where at least two doses of the modulating ion are implanted.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The preset implantation region includes a first preset implantation region and a second preset implantation region. The first preset implantation region and the second preset implantation region are respectively located in the first part on both sides of the gate structure along the second direction. The step of implanting the regulating ions at least twice in the first part based on the preset implantation region includes: Based on the first preset injection area, the first injection angle is obtained; The first part is injected with the modulating ions at least once along the first injection angle; Based on the second preset injection region, a second injection angle is obtained, and the first injection angle and the second injection angle correspond to different directions on both sides of the gate structure, respectively. The first part is implanted with the regulating ions at least once along the second implantation angle, wherein the region having both the regulating ions implanted along the first implantation angle and the regulating ions implanted along the second implantation angle is designated as the second implantation region, and the region having only the regulating ions implanted along the first implantation angle or the region having only the regulating ions implanted along the second implantation angle is designated as the first implantation region.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The first injection angle is obtained based on the width of the first preset injection region in the second direction and the sum of the thicknesses of the gate structure, the buffer material layer, and the etching control material layer in the first direction; The second injection angle is obtained based on the width of the second preset injection region in the second direction and the sum of the thicknesses of the gate structure, the buffer material layer, and the etching control material layer in the first direction.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching control material layer is a dielectric material with covalent bonds, and the regulating ion is an ion that can weaken the covalent bond strength inside the etching control material layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The regulating ion includes fluoride ions; the material of the etching control material layer includes silicon nitride.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The range of the implantation dose of the regulating ions is 1×10. 14 ~1×10 16 cm -2 The implantation energy of the regulating ions is 5keV~50keV.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sidewall structure further includes a first isolation layer and a second isolation layer, and before forming the buffer material layer covering the gate structure, it further includes: A first isolation layer and a second isolation layer are formed, wherein the first isolation layer covers the sidewalls of the gate layer on both sides in the second direction, and the second isolation layer covers the sidewalls of the first isolation layer away from the gate layer.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching process for the protective material layer, the etching control material layer, and the buffer material layer includes: The protective material layer, the etching control material layer, and the buffer material layer are etched sequentially so that the etched protective material layer, the etching control material layer, and the buffer material layer are located on both sides of the gate layer along the second direction to form the protective layer, the etching control layer, and the buffer layer, thereby obtaining the sidewall structure.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method as described in any one of claims 1 to 9.

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