A GaN power device packaging structure and a preparation method thereof

Abstract

This invention relates to the semiconductor field and discloses a GaN power device packaging structure and its fabrication method. The GaN power device packaging structure includes a leadframe base island, a gate, drain, and source of the GaN power device, connecting ribs, a MOS chip, and a GaN chip. The gate, drain, and source of the GaN power device are sequentially distributed along a first direction relative to the leadframe base island, and at least two of the three gates, drain, and source of the GaN power device are separated from the leadframe base island. The gate, drain, and source of the GaN power device each have an extension in a direction away from the leadframe base island, and each extension is connected to a connecting rib. The MOS chip and the GaN chip are disposed on the leadframe base island and are electrically connected to the gate, drain, and source of the GaN power device respectively. This invention enables GaN power devices that can directly replace MOS / IGBT devices pin-to-pin.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a GaN power device packaging structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) is a third-generation wide-bandgap semiconductor material. Its semiconductor device characteristics are superior to Si-based semiconductor devices in applications requiring high temperature, high voltage, and high frequency. GaN FET devices currently mainly have depletion mode (D-mode) and enhancement mode (E-mode) structures. Cascode (common gate, common source) structures (such as...) Figure 1 The device shown is composed of a high-voltage depletion-mode GaN power transistor and a low-voltage enhancement-mode Si MOSFET (metal-oxide-semiconductor field-effect transistor). From the structure, it can be seen that when the device has no gate voltage and the drain-source voltage is greater than zero, it operates in the forward blocking mode; when the gate voltage is greater than the threshold voltage of the Si MOSFET, the device conducts in the forward direction; once the Si MOSFET conducts in the reverse direction, the device will operate in the reverse conduction mode.

[0003] Given that GaN power devices have superior switching frequencies, fast response times, and advantages such as better heat dissipation and lower losses, many product, equipment, and system upgrades and performance optimizations require the replacement of existing MOS / IGBT devices with GaN power devices.

[0004] However, GaN power devices are generally packaged in three-pin packages with GSD (gate-source-drain) electrode pins (e.g., Figure 2 As shown), while the commonly used MOS / IGBT devices in the market are all packaged with three-pin GDS (gate-drain-source) electrode pins (such as...). Figure 3 As shown in the diagram, this specifically involves commonly used devices in the market, such as TO-220F, TO-220, TO-247, TO-252, DFN5*6-2L, and DFN8*8-2L packages. Because GaN power devices and MOS / IGBT devices have different electrode pin configurations, replacing similar MOS / IGBT devices with GaN power devices is difficult, costly, and hinders the widespread adoption of GaN power devices.

[0005] The above background information is provided only to assist in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this patent application, nor does it necessarily provide technical teaching. In the absence of clear evidence that the above information was disclosed before the filing date of this patent application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0006] The purpose of this invention is to provide a GaN power device packaging structure and its fabrication method, which can directly replace MOS / IGBT and other devices pin-to-pin.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A GaN power device packaging structure includes a lead frame base island, a gate of the GaN power device, a drain of the GaN power device, a source of the GaN power device, a connecting bar, a MOS chip, and a GaN chip.

[0009] The gate, drain, and source of the GaN power device are distributed sequentially along a first direction relative to the lead frame base island, and at least two of the three electrodes of the GaN power device are separated from the lead frame base island.

[0010] The gate, drain, and source of the GaN power device are each provided with an insulated extension in the direction away from the lead frame base island, and the extensions of the gate, drain, and source of the GaN power device are respectively connected to the connecting rib.

[0011] Both the MOS chip and the GaN chip are disposed on the lead frame base island, and the gate of the MOS chip is electrically connected to the gate of the GaN power device, and the source of the MOS chip is electrically connected to the source of the GaN power device.

[0012] The drain of the GaN chip is electrically connected to the drain of the GaN power device, the gate of the GaN chip is electrically connected to the source of the GaN power device, and the source of the GaN chip is electrically connected to the drain of the MOS chip.

[0013] Furthermore, based on any or a combination of the aforementioned technical solutions, the source of the GaN power device and the lead frame base island are an integral structure interconnected, and a first conductive region is provided on the lead frame base island, which is electrically connected to the source of the GaN power device.

[0014] The extension of the source of the GaN power device has an increased width at the connection between the source of the GaN power device and the lead frame base island.

[0015] Furthermore, in accordance with any or a combination of the aforementioned technical solutions, the substrate is further included, wherein a second conductive area is provided on the front side of the substrate, the back side of the substrate is insulated, and the back side of the substrate is bonded and connected to the lead frame base island.

[0016] The drain of the MOS chip is disposed on the back side, and the source and gate of the MOS chip are disposed on the front side.

[0017] The MOS chip is disposed on the substrate, and the back side of the MOS chip is bonded to the front side of the substrate. The drain of the MOS chip is electrically connected to the second conductive region.

[0018] The GaN chip has an insulated back side, and its gate, source, and drain are disposed on the front side. The back side of the GaN chip is bonded to the lead frame base island, and the source of the GaN chip is electrically connected to the second conductive region.

[0019] Furthermore, based on any or a combination of the aforementioned technical solutions, the MOS chip and the GaN chip are in a stacked structure;

[0020] The GaN chip has an insulated back side and a gate, a drain, and a source window on its front side. Any point within the source window is configured as the source of the GaN chip.

[0021] The drain of the MOS chip is disposed on the back side, and the source and gate of the MOS chip are disposed on the front side.

[0022] The MOS chip is disposed within the source window, and the drain of the MOS chip is attached to and electrically connected to the source window. The source of the MOS chip is electrically connected to the first conductive region, and the source of the MOS chip is electrically connected to the gate of the GaN chip.

[0023] Furthermore, following any or a combination of the aforementioned technical solutions, the MOS chip and the GaN chip are directly disposed on the lead frame base island, wherein the source of the MOS chip is disposed on the back side, and the gate and drain of the MOS chip are disposed on the front side.

[0024] The GaN chip has an insulated back side, and its gate, drain, and source are disposed on the front side.

[0025] The source on the back of the MOS chip is attached to and electrically connected to the first conductive region; the gate of the MOS chip is electrically connected to the gate of the GaN power device; and the drain of the MOS chip is electrically connected to the source of the GaN chip.

[0026] The gate of the GaN chip is electrically connected to the first conductive region, and the drain of the GaN chip is electrically connected to the drain of the GaN power device.

[0027] Furthermore, following any or a combination of the aforementioned technical solutions, the MOS chip and the GaN chip are directly disposed on the lead frame base island, wherein the back side of the MOS chip is insulated, and the front side of the MOS chip has its source, gate, and drain.

[0028] The GaN chip has an insulated back side, and its gate, drain, and source are disposed on the front side.

[0029] The back side of the MOS chip is bonded to the lead frame base island, and the gate of the MOS chip is electrically connected to the gate of the GaN power device, and the source of the MOS chip is electrically connected to the first conductive region.

[0030] The back side of the GaN chip is bonded to the lead frame base island, and the gate of the GaN chip is electrically connected to the first conductive region, the drain of the GaN chip is electrically connected to the drain of the GaN power device, and the source of the GaN chip is electrically connected to the drain of the MOS chip.

[0031] Furthermore, in accordance with any one or a combination of the aforementioned technical solutions, any one of the three electrodes of the GaN power device—the gate, the drain, and the source—and the lead frame base island are all separate structures.

[0032] It also includes an outer frame, through which the outer side of the lead frame base island is connected to the extension portions of the three electrodes of the GaN power device: the gate, the drain, and the source.

[0033] Furthermore, in accordance with any one or a combination of the aforementioned technical solutions, the substrate is further included, wherein a first accommodating area and a second accommodating area are provided on the front side of the substrate, the first accommodating area is provided with a second conductive area, the back side of the substrate is insulated, and the back side of the substrate is bonded and connected to the lead frame base island.

[0034] The drain of the MOS chip is disposed on the back side, and the source and gate of the MOS chip are disposed on the front side.

[0035] The MOS chip is disposed on the substrate, and the back side of the MOS chip is attached to the first accommodating area, and the drain of the MOS chip is electrically connected to the second conductive area.

[0036] The GaN chip is disposed on the substrate, and the back side of the GaN chip is attached to the second accommodating region, and the source of the GaN chip is electrically connected to the second conductive region.

[0037] Furthermore, in accordance with any or a combination of the aforementioned technical solutions, the gate of the GaN power device and the lead frame base island are an integral structure interconnected, and a third conductive region is provided on the lead frame base island, which is electrically connected to the gate of the GaN power device.

[0038] The extension of the gate of the GaN power device to the connection between the gate of the GaN power device and the lead frame base island has an increased width.

[0039] Furthermore, following any one or a combination of the aforementioned technical solutions, the electrode connected to the lead frame base island is configured as the first electrode;

[0040] The width of the first electrode at its connection with the lead frame base island is at least twice the width of the extension of the first electrode.

[0041] Furthermore, in accordance with any or a combination of the aforementioned technical solutions, the connecting rib is in the form of a strip, and the width of the strip is 4mm to 6mm.

[0042] Furthermore, following any one or a combination of the aforementioned technical solutions, the minimum distance between the electrode that is separated from the lead frame base island among the three electrodes of the GaN power device (gate, drain, and source) and the lead frame base island is 2mm to 6mm.

[0043] Furthermore, based on any or a combination of the aforementioned technical solutions, the gate, drain, and source extensions of the GaN power device are integrated with the connecting rib.

[0044] Furthermore, in accordance with any or a combination of the aforementioned technical solutions, the GaN power device packaging structure is configured with a packaging area, the packaging area is configured to be packaged with a packaging material, and the connecting ribs are disposed on the outside of the packaging area.

[0045] After the GaN power device package structure is encapsulated, the connecting ribs are removed.

[0046] According to another aspect of the present invention, a GaN power device packaging structure is provided, including a lead frame base island, a gate of the GaN power device, a drain of the GaN power device, a source of the GaN power device, connecting ribs, and a GaN chip.

[0047] The gate, drain, and source of the GaN power device are distributed sequentially along a first direction relative to the lead frame base island, and at least two of the three electrodes of the GaN power device are separated from the lead frame base island.

[0048] The gate, drain, and source of the GaN power device are each provided with an insulated extension in the direction away from the lead frame base island, and the extensions of the gate, drain, and source of the GaN power device are respectively connected to the connecting rib.

[0049] The drain of the GaN chip is electrically connected to the source of the GaN power device, the gate of the GaN chip is electrically connected to the gate of the GaN power device, and the source of the GaN chip is electrically connected to the drain of the GaN power device.

[0050] Furthermore, following any one or a combination of the aforementioned technical solutions, the source of the GaN power device and the lead frame base island are an integral structure interconnected. A fourth conductive region is provided on the lead frame base island, and the fourth conductive region is electrically connected to the source of the GaN power device. The drain of the GaN chip is electrically connected to the fourth conductive region. The extension of the source of the GaN power device to the connection between the source of the GaN power device and the lead frame base island has an increasing width.

[0051] According to another aspect of the present invention, a method for fabricating a GaN power device packaging structure is provided, comprising the following steps:

[0052] A leadframe is designed and fabricated, comprising a leadframe base island, a gate of a GaN power device, a drain of a GaN power device, a source of a GaN power device, and connecting ribs. The gate, drain, and source of the GaN power device are sequentially distributed relative to the leadframe base island along a first direction, and at least two of the three electrodes (gate, drain, and source) are separated from the leadframe base island. Each of the GaN power device's gate, drain, and source has an insulating extension portion in a direction away from the leadframe base island, and these extension portions are connected to the connecting ribs.

[0053] A GaN chip and a MOS chip are disposed on the lead frame base island, and the gate of the MOS chip is electrically connected to the gate of the GaN power device, and the source of the MOS chip is electrically connected to the source of the GaN power device; the drain of the GaN chip is electrically connected to the drain of the GaN power device, the gate of the GaN chip is electrically connected to the source of the GaN power device, and the source of the GaN chip is electrically connected to the drain of the MOS chip.

[0054] According to another aspect of the present invention, a method for fabricating a GaN power device packaging structure is provided, comprising the following steps:

[0055] A leadframe is designed and fabricated, comprising a leadframe base island, a gate of a GaN power device, a drain of a GaN power device, a source of a GaN power device, and connecting ribs. The gate, drain, and source of the GaN power device are sequentially distributed relative to the leadframe base island along a first direction, and at least two of the three electrodes (gate, drain, and source) are separated from the leadframe base island. Each of the GaN power device's gate, drain, and source has an insulating extension portion in a direction away from the leadframe base island, and these extension portions are connected to the connecting ribs.

[0056] A GaN chip is disposed on the lead frame base island, and the drain of the GaN chip is electrically connected to the source of the GaN power device; the gate of the GaN chip is electrically connected to the gate of the GaN power device, and the source of the GaN chip is electrically connected to the drain of the GaN power device.

[0057] According to another aspect of the present invention, a method for fabricating a lead frame is provided, the lead frame being suitable for fabricating GaN power devices with an electrode arrangement of gate-drain-source, the method comprising the following steps:

[0058] Design and fabricate a leadframe, which includes a leadframe base island, a gate of the GaN power device, a drain of the GaN power device, a source of the GaN power device, and connecting ribs.

[0059] The gate, drain, and source of the GaN power device are distributed sequentially along a first direction relative to the lead frame base island, and at least two of the three electrodes of the GaN power device are separated from the lead frame base island.

[0060] The gate, drain, and source of the GaN power device are each provided with an insulated extension in the direction away from the lead frame base island, and the extensions of the gate, drain, and source of the GaN power device are respectively connected to the connecting rib.

[0061] The beneficial effects of the technical solution provided by this invention are as follows:

[0062] a. The GaN power device packaging structure provided by this invention, by redesigning its lead frame base island and the three electrodes of the GaN power device, namely the gate, drain and source, to obtain a GaN power device with a GDS (gate-drain-source) electrode arrangement, is suitable for direct pin-to-pin replacement with commonly used MOS / IGBT devices on the market. This not only solves the bottleneck of application and promotion of GaN power devices and reduces their promotion costs, but also simplifies the upgrade and optimization of products involving MOS / IGBT devices, reduces costs and improves efficiency.

[0063] b. The present invention connects the gate, drain and source of GaN power devices by connecting ribs, and sets the width of the connecting ribs to 4-6mm. For the electrodes connected to the lead frame base island, the connection part of the electrode extension to the lead frame base island is designed as a horn structure with increased width, which can improve the stability of the overall connection structure of the lead frame and ensure the stability and good operability of the lead frame during transmission and use.

[0064] c. This invention provides a variety of GaN power device packaging structures with GDS (gate-drain-source) electrode arrangements, which can produce a variety of GaN power device products that can be directly replaced with MOS / IGBT devices by pin to pin, thus expanding the application scenarios;

[0065] d. The present invention provides a GaN power device packaging structure in which the lead frame base island is insulated and separated from the three electrodes, forming an internally insulated packaging structure product, which has better electrical performance and can meet the stringent practical requirements of GaN power devices in specific electrical environments;

[0066] e. The GaN power device packaging structure provided by this invention adopts a GaN-MOS with a stacked die interconnect structure, which can fabricate smaller GaN power devices. It only requires four electrical connections by bonding wires, and the wires are short. This not only simplifies the process, but also greatly reduces the parasitic parameters of the device and improves the high-frequency performance and voltage withstand performance of the device. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 A schematic diagram of the circuit principle of the GaN power device package structure with Cascode structure in the prior art;

[0069] Figure 2 This is a schematic diagram showing the pin arrangement of the electrode pins in a GaN power device in the prior art.

[0070] Figure 3 This is a schematic diagram showing the pin arrangement of a MOS device in the prior art.

[0071] Figure 4 A schematic diagram of the structure of a GaN chip provided as an exemplary embodiment of the present invention;

[0072] Figure 5 A schematic diagram of the structure of a first type of MOS chip provided as an exemplary embodiment of the present invention;

[0073] Figure 6 A schematic diagram of the structure of a substrate provided in an exemplary embodiment of the present invention;

[0074] Figure 7 A schematic diagram of the lead frame provided in an exemplary embodiment of the present invention;

[0075] Figure 8 A circuit connection diagram of a GaN power device provided for an exemplary embodiment of the present invention;

[0076] Figure 9 A schematic diagram of the packaged and cut GaN power device provided as an exemplary embodiment of the present invention;

[0077] Figure 10 This is a schematic diagram of the structure of the substrate provided in Exemplary Embodiment 2 of the present invention;

[0078] Figure 11 This is a schematic diagram of the lead frame structure provided in Exemplary Embodiment 2 of the present invention;

[0079] Figure 12 A circuit connection diagram of a GaN power device provided for an exemplary embodiment two of the present invention;

[0080] Figure 13 A schematic diagram of the packaged and cut GaN power device provided as an exemplary embodiment 2 of the present invention;

[0081] Figure 14 A circuit connection diagram of a GaN power device provided for an exemplary embodiment three of the present invention;

[0082] Figure 15 A schematic diagram of the structure of a second MOS chip provided as an exemplary embodiment of the present invention;

[0083] Figure 16 A circuit connection diagram of a GaN power device provided for an exemplary embodiment four of the present invention;

[0084] Figure 17 A schematic diagram of the structure of a third MOS chip provided as an exemplary embodiment of the present invention;

[0085] Figure 18 A circuit connection diagram of a GaN power device provided for Exemplary Example 5 of the present invention;

[0086] Figure 19This is a circuit connection diagram of a GaN power device provided for an exemplary embodiment six of the present invention.

[0087] The reference numerals in the accompanying drawings include: 1-lead frame base, 14-gate of GaN power device, 15-drain of GaN power device, 16-source of GaN power device, 17-packaging material, 18-connecting rib, 19-speaker structure, 2-adhesive, 30-substrate, 31-second conductive region, 32-second accommodating region, 5-MOS chip, 51-gate of MOS chip, 52-drain of MOS chip, 53-source of MOS chip, 7-GaN chip, 71-gate of GaN chip, 72-drain of GaN chip, 73-source of GaN chip, 8-first bonding lead, 9-second bonding lead, 10-third bonding lead, 11-fourth bonding lead, 13-sixth bonding lead, and 14-seventh bonding lead. Detailed Implementation

[0088] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0089] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0090] Because GaN power devices and MOS / IGBT devices have different electrode pin configurations, GaN power devices cannot be used for pin-to-pin replacement of MOS / IGBT devices. This not only hinders the widespread adoption of GaN power devices but also affects the upgrade and optimization of existing products involving MOS / IGBT devices. Specifically, in some applications that require replacing MOS / IGBT devices with GaN power devices, an adapter board is needed to replace the existing MOS / IGBT devices with GaN power devices. This process is complex and costly, and may not be feasible for products with limited installation space.

[0091] In view of the shortcomings of the prior art, the present invention aims to provide a GaN power device packaging structure that is suitable for fabricating GaN power devices with GDS (gate-drain-source) electrode arrangement, and thus suitable for direct pin-to-pin replacement with commercially available MOS / IGBT devices. This not only solves the bottleneck in the application and promotion of GaN power devices and reduces their promotion costs, but also simplifies the upgrading and optimization of products involving MOS / IGBT devices, reduces costs, and improves efficiency.

[0092] In one embodiment of the present invention, a GaN power device packaging structure is disclosed, suitable for fabricating GaN power devices with GDS gate-drain-source electrode arrangement. See [link to relevant documentation]. Figures 4 to 9 The GaN power device package structure includes a lead frame base island 1, a gate 14 of the GaN power device, a drain 15 of the GaN power device, a source 16 of the GaN power device, a connecting rib 18, a MOS chip 5, and a GaN chip 7.

[0093] The gate 14, drain 15, and source 16 of the GaN power device are sequentially distributed relative to the lead frame base island 1 along a first direction. Preferably, the first direction is the direction of one side of the lead frame base island 1, and at least two of the three electrodes of the GaN power device (gate 14, drain 15, and source 16) are separated from the lead frame base island 1.

[0094] The gate 14, drain 15, and source 16 of the GaN power device are each provided with an insulated extension in the direction away from the lead frame base island 1. The extensions of the gate 14, drain 15, and source 16 of the GaN power device are respectively connected to the connecting rib 18.

[0095] Both the MOS chip 5 and the GaN chip 7 are disposed on the lead frame base island 1, and the gate of the MOS chip 5 is electrically connected to the gate 14 of the GaN power device, and the source of the MOS chip 5 is electrically connected to the source 16 of the GaN power device.

[0096] The drain of the GaN chip 7 is electrically connected to the drain 15 of the GaN power device, the gate of the GaN chip 7 is electrically connected to the source 16 of the GaN power device, and the source of the GaN chip 7 is electrically connected to the drain of the MOS chip 5.

[0097] To increase the connection strength between the lead frame base island 1 and the pin terminals, and to achieve the stability of the overall connection structure of the lead frame, ensuring the stability and good operability of the lead frame during transmission and use, the lead frame is a frame connecting the lead frame base island and the three electrical terminals (i.e., the gate 14, drain 15, and source 16 of the GaN power device). This invention proposes the following improvements:

[0098] (1) The electrode connected to the lead frame base island 1 is configured as a first electrode; the width of the first electrode at its connection with the lead frame base island 1 is greater than the width of the extension of the first electrode, preferably at least twice the width of the extension of the first electrode, that is, the connection part between the first electrode terminal and the lead frame base island has a widened and thickened horn structure 19, such as... Figures 7 to 9 As shown;

[0099] (2) The connecting rib 18 is strip-shaped, and the width of the strip is 4mm to 6mm. More preferably, the extending direction of the connecting rib 18 is consistent with the first direction;

[0100] (3) The extension of the gate 14, drain 15, and source 16 of the GaN power device, together with the connecting rib 18 and the lead frame base island 1, form an integral structure.

[0101] (4) The minimum distance between the electrode that is separated from the lead frame base island 1 among the three electrodes of the GaN power device (gate 14, drain 15, and source 16) and the lead frame base island 1 is 2 mm to 6 mm; more preferably, the minimum distance is 3 mm to 5 mm.

[0102] The GaN power device packaging structure described above is configured with a packaging area, which is configured to be encapsulated using packaging material 17, and the connecting rib 18 is disposed on the outside of the packaging area; after the GaN power device packaging structure is encapsulated, the connecting rib 18 is removed, thereby forming a GaN power device with a GDS structure, such as... Figure 19 As shown.

[0103] Example 1

[0104] In this embodiment, see Figures 6 to 9 The source 16 of the GaN power device and the lead frame base island 1 are an integral structure interconnected. A first conductive region is provided on the lead frame base island 1, and the first conductive region is electrically connected to the source 16 of the GaN power device. The extension of the source 16 of the GaN power device, to the connection point between the source 16 and the lead frame base island 1, has an increasing width, such as... Figure 7 As shown.

[0105] In this embodiment, the GaN power device packaging structure further includes a substrate 30, and a second conductive region 31 is disposed on the front side of the substrate 30 (e.g., Figure 6 As shown, the back side of the substrate 30 is insulated.

[0106] like Figure 8 As shown, the back surface of the substrate 30 is bonded to the lead frame base island 1. Figure 5 As shown, the drain of the MOS chip 5 is disposed on its back side, and the source 53 and the gate 51 of the MOS chip 5 are disposed on its front side. The MOS chip 5 is disposed on the substrate 30, and the back side of the MOS chip 5 is bonded to the front side of the substrate 30. The drain of the MOS chip 5 is electrically connected to the second conductive region 31.

[0107] like Figure 4 As shown, the back side of the GaN chip 7 is insulated, and the front side of the GaN chip 7 is provided with its gate, drain, and source (Gate 71, Drain 72, and Source 73 of the GaN chip). The back side of the GaN chip 7 is attached to the lead frame base island 1, and the source of the GaN chip 7 is electrically connected to the second conductive region 31.

[0108] The method for fabricating the GaN power device packaging structure provided in this embodiment includes the following steps:

[0109] Design and tape-out of high-performance GaN chips (such as...) Figure 4 As shown), the MOS chip (such as...) Figure 5 (as shown) and the DPC substrate (e.g.) Figure 6 The GaN chip has an insulated back side / substrate and is a non-electrical electrode, whose main function is heat dissipation; the DPC substrate has an insulated back side and is a non-electrical electrode, which is mainly used for heat dissipation and realizing electrode switching of the MOS chip; a second conductive area is provided on the front side of the DPC substrate; it should be noted that existing GaN chips and MOS chips can also be used.

[0110] Design precision leadframes (such as) Figure 7 The GaN power device's gate 14 (Pin1-G electrode), drain 15 (Pin2-D electrode), and source 16 (Pin3-S electrode) are arranged sequentially along the long side of the lead frame base island 1 to achieve the GDS electrical performance arrangement of the GaN HMET device's pin terminals. The Pin1-G and Pin2-D electrodes are not directly connected to the lead frame base island. Pin3-S is connected to the lead frame base island, and a first conductive region electrically connected to Pin3-S is provided on the lead frame base island. The connection between Pin3-S and the lead frame base island has a horn-shaped structure, and each pin terminal is supported and fixed by connecting ribs.

[0111] The back side of the DPC substrate is attached to the lead frame base island using high-precision adhesive pads with thermally conductive, low-stress adhesive on both sides.

[0112] The back side of the MOS chip is attached to the front side of the DPC substrate using a high-precision adhesive with thermally conductive and low-stress adhesive on both sides, and the drain of the back side of the MOS chip is electrically connected to the second conductive area.

[0113] The back of the GaN chip is attached to the lead frame base island using a high-precision adhesive pad with thermally conductive, low-stress adhesive on both sides.

[0114] After the adhesive cures, the MOS chip, GaN chip, DPC substrate, etc., are electrically connected to the lead frame base island and each pin terminal via WB bonding leads. See [link to documentation]. Figure 8 ,include:

[0115] The gate of the MOS chip and the gate 14 of the GaN power device are electrically connected using a first bonding lead 8 via a thermo-ultrasonic bonding process.

[0116] The drain of the GaN chip is electrically connected to the drain of the GaN power device using a second bonding lead 9 via a thermo-ultrasonic bonding process.

[0117] The gate of the GaN chip is electrically connected to the first conductive region of the lead frame base island using a third bonding lead 10 via a thermo-ultrasonic bonding process.

[0118] The source of the GaN chip is electrically connected to the second conductive region by using a fourth bonding lead 11 through a thermo-ultrasonic bonding process, thereby realizing the electrical connection between the source of the GaN chip and the drain of the MOS chip.

[0119] The source of the MOS chip is electrically connected to the first conductive region of the lead frame base island using a fifth bonding wire 12 via a thermo-ultrasonic bonding process. Since the first conductive region of the lead frame base island is directly electrically connected to the source 16 of the GaN power device, the source of the MOS chip is electrically connected to the source of the GaN power device.

[0120] The molding process is adopted to encapsulate and protect the GaN power device packaging structure (the packaging area includes the die and wire, as well as the lead frame base island, excluding the connecting ribs) with EMC resin to achieve the device's electrical and heat dissipation functions.

[0121] The excess parts, such as the outer lead frame and the connecting ribs, are cut off and separated using electroplating and cutting processes to obtain a single GaN power device.

[0122] Each GaN power device undergoes visual inspection and electrical performance testing to eliminate defective products, thus obtaining GaN power devices that meet both electrical performance and appearance standards.

[0123] This invention utilizes advanced packaging to achieve the product's structure and electrical functions by employing key and core components and materials such as "precision lead frame Pin3-S electrode connection base island structure, MOS core, GaN core, DPC substrate core, high thermal conductivity and low stress adhesive, wire, low stress, low water absorption and low halogen EMC".

[0124] This invention utilizes technologies such as GaN Die, MOS Die, precision lead frame, high-precision surface mount, thermo-ultrasonic bonding, and molding to achieve GDS functionality at the pin of Cascode structure GaN power devices. This avoids the Si-based GaN chip substrate coming into contact with high voltage, enabling the replacement of GaN power devices with commercially available MOS / IGBT devices in a pin-to-pin manner. It possesses advanced technology, high economic value, and practical value.

[0125] Example 2

[0126] In this embodiment, see Figures 10 to 13The gate 14, drain 15, and source 16 of the GaN power device are all separate from the lead frame base island 1. The lead frame base island 1 is made of insulating material and is an insulator. An outer frame is also included, through which the outer side of the lead frame base island 1 is connected to the extension portions of the three electrodes: the gate 14, drain 15, and source 16 of the GaN power device.

[0127] The GaN power device packaging structure also includes a substrate 30, such as Figure 10 As shown, a first accommodating area and a second accommodating area 32 are provided on the front side of the substrate 30. The first accommodating area is provided with a second conductive area 31. The back side of the substrate 30 is insulated, and the back side of the substrate 30 is attached to the lead frame base island 1.

[0128] In this embodiment, the structures of the MOS chip and the GaN chip are the same as those described in Embodiment 1. Unlike Embodiment 1, the MOS chip 5 is disposed on the substrate 30, and the back surface of the MOS chip 5 is bonded to the first accommodating region, while the drain of the MOS chip 5 is electrically connected to the second conductive region 31. The GaN chip 7 is disposed on the substrate 30, and the back surface of the GaN chip 7 is bonded to the second accommodating region 32, while the source of the GaN chip 7 is electrically connected to the second conductive region 31.

[0129] The GaN power device packaging structure provided in this embodiment features an insulated lead frame base island that is separated from the three electrodes, forming an internally insulated packaging structure. This structure offers superior electrical performance and can meet the stringent practical requirements of GaN power devices in specific electrical environments, demonstrating its advanced nature.

[0130] The method for fabricating the GaN power device packaging structure provided in this embodiment includes the following steps:

[0131] Design and tape-out of high-performance GaN chips (such as...) Figure 4 As shown), the MOS chip (such as...) Figure 5 (as shown) and the DPC substrate (e.g.) Figure 10 (as shown); wherein, the back side / substrate of the GaN chip is insulated and is a non-electrical electrode, and its main function is heat dissipation; the back side of the DPC substrate is insulated and is a non-electrical electrode, and its main functions are heat dissipation and realizing electrode switching of the MOS chip; the front side of the DPC substrate is provided with a first accommodating area and a second accommodating area, and a second conductive area is provided in the first accommodating area.

[0132] Design precision leadframes (such as) Figure 11The GaN power device has a gate 14 (Pin1-G electrode), a drain 15 (Pin2-D electrode), and a source 16 (Pin3-S electrode) arranged sequentially along the long side of the lead frame base island 1 to achieve the GDS electrical performance arrangement of the Pin terminals of the GaN HMET device. The Pin1-G, Pin2-D, and Pin3-S electrodes are not directly connected to the lead frame base island; they are reinforced by connecting ribs, and are connected to the lead frame base island via an outer frame.

[0133] The back side of the DPC substrate is attached to the lead frame base island using high-precision adhesive pads with thermally conductive, low-stress adhesive on both sides.

[0134] The back side of the MOS chip is attached to the first accommodating area on the front side of the DPC substrate using a high-precision adhesive with thermally conductive and low-stress adhesive on both sides, and the drain of the back side of the MOS chip is electrically connected to the second conductive area of ​​the first accommodating area.

[0135] The back side of the GaN chip is attached to the second accommodating area on the front side of the DPC substrate using a high-precision adhesive pad with thermally conductive and low-stress adhesive on both sides.

[0136] After the adhesive cures, the MOS chip, GaN chip, DPC substrate, etc., are electrically connected to the lead frame base island and each pin terminal via WB bonding wires. See [link to documentation]. Figure 12 ,include:

[0137] The gate of the MOS chip and the gate 14 of the GaN power device are electrically connected by the first bonding lead 8.

[0138] The drain of the GaN chip is electrically connected to the drain of the GaN power device using a second bonding lead 9.

[0139] The source of the MOS chip and the source of the GaN power device are electrically connected using the sixth bonding lead 13.

[0140] The source of the GaN chip is electrically connected to the second conductive region by the fourth bonding lead 11, thereby realizing the electrical connection between the source of the GaN chip and the drain of the MOS chip.

[0141] Using the seventh bonding lead 14 to electrically connect the gate of the GaN chip and the source of the MOS chip can reduce device parasitic parameters and improve device performance.

[0142] The molding process is adopted to encapsulate and protect the GaN power device packaging structure (the packaging area includes the die and wire, as well as the lead frame base island, excluding the connecting ribs) with EMC resin to achieve the device's electrical and heat dissipation functions.

[0143] The excess parts, such as the outer lead frame and the connecting ribs, are cut off and separated using electroplating and cutting processes to obtain a single GaN power device.

[0144] Each GaN power device undergoes visual inspection and electrical performance testing to eliminate defective products, thus obtaining GaN power devices that meet both electrical performance and appearance standards.

[0145] Example 3

[0146] In this embodiment, see Figure 14 The structure and connection method of the lead frame base island 1, the gate 14 (Pin1-G electrode) of the GaN power device, the drain 15 (Pin2-D) of the GaN power device, the source 16 (Pin3-S) of the GaN power device, and the connecting ribs are the same as in Embodiment 1.

[0147] The difference between this embodiment and Embodiment 1 is that the MOS chip 5 and the GaN chip 7 are stacked. Specifically, the back side of the GaN chip 7 is insulated, and the front side of the GaN chip 7 has its gate, drain, and a source window, with any point within the source window being configured as the source of the GaN chip 7.

[0148] The structure of the MOS chip 5 is as follows: Figure 5 As shown, the drain of the MOS chip 5 is disposed on its back side, and the source and gate of the MOS chip 5 are disposed on its front side. In this embodiment, the MOS chip 5 is disposed within the source window, and the drain of the MOS chip 5 is attached to and electrically connected to the source window. The source of the MOS chip 5 is electrically connected to the first conductive region, and the source of the MOS chip 5 is electrically connected to the gate 73 of the GaN chip 7.

[0149] The method for fabricating the GaN power device packaging structure provided in this embodiment includes the following steps:

[0150] Design and fabrication of high-performance GaN chips and MOS chips (such as...) Figure 5 (as shown); wherein, the back / substrate of the GaN chip is insulated and is a non-electrical terminal, and its back side mainly functions as heat dissipation; the front side of the GaN chip is provided with the source window, and the size of the source window is not smaller than the size of the MOS chip; it should be noted that existing GaN chips and MOS chips can also be used;

[0151] Design precision leadframes (such as) Figure 7 The GaN power device's gate 14 (Pin1-G electrode), drain 15 (Pin2-D electrode), and source 16 (Pin3-S electrode) are arranged sequentially along the long side of the lead frame base island 1 to achieve the GDS electrical performance arrangement of the GaN HMET device's pin terminals. The Pin1-G and Pin2-D electrodes are not directly connected to the lead frame base island. Pin3-S is connected to the lead frame base island, and a first conductive region electrically connected to Pin3-S is provided on the lead frame base island. The connection between Pin3-S and the lead frame base island has a horn-shaped structure, and each pin terminal is supported and fixed by connecting ribs.

[0152] The back side of the GaN chip is attached to the lead frame base island using a high-precision adhesive pad with thermally conductive, low-stress adhesive on both sides.

[0153] The back side of the MOS chip is attached to the source window on the front side of the GaN chip using a high-precision adhesive with thermally conductive and low-stress adhesive on both sides, and the drain on the back side of the MOS chip is electrically connected to the source of the GaN chip.

[0154] After the adhesive cures, MOS chips, GaN chips, etc., are electrically connected to the lead frame base island and each pin terminal via WB bonding leads. See [link to documentation]. Figure 14 ,include:

[0155] The gate of the MOS chip and the gate 14 of the GaN power device are electrically connected by bonding leads;

[0156] The source of the MOS chip and the first conductive region of the lead frame base island are electrically connected by bonding wires. Since the first conductive region of the lead frame base island is electrically connected to the source 16 of the GaN power device, the source of the MOS chip and the source 16 of the GaN power device are electrically connected.

[0157] The drain of the GaN chip is electrically connected to the drain 15 of the GaN power device via bonding wires.

[0158] The gate of the GaN chip is electrically connected to the source of the MOS chip via bonding wires.

[0159] The molding process is adopted to encapsulate and protect the GaN power device packaging structure (the packaging area includes the die and wire, as well as the lead frame base island, excluding the connecting ribs) with EMC resin to achieve the device's electrical and heat dissipation functions.

[0160] The excess parts, such as the outer lead frame and the connecting ribs, are cut off and separated using electroplating and cutting processes to obtain a single GaN power device.

[0161] Each GaN power device undergoes visual inspection and electrical performance testing to eliminate defective products, thus obtaining GaN power devices that meet both electrical performance and appearance standards.

[0162] The GaN power device provided in this embodiment requires only four electrical connections via bonding wires, which not only simplifies the manufacturing process but also significantly reduces parasitic parameters and improves high-frequency and voltage withstand performance. Furthermore, this embodiment provides a GaN-MOS with a stacked die interconnect structure, enabling the fabrication of smaller GaN power devices.

[0163] Example 4

[0164] In this embodiment, see Figure 16 The structure and connection method of the lead frame base island 1, the gate 14 (Pin1-G electrode) of the GaN power device, the drain 15 (Pin2-D) of the GaN power device, the source 16 (Pin3-S) of the GaN power device, and the connecting ribs are the same as in Embodiment 1. The structure of the GaN chip 7 is also the same as in Embodiment 1.

[0165] The difference between this embodiment and Embodiment 1 is that the structure of the MOS chip 5 is different from that in Embodiment 1, and this embodiment does not include a substrate; the MOS chip 5 and the GaN chip 7 are directly disposed on the lead frame base island 1. The MOS chip 5 is as follows: Figure 16 The image shows an LDMOS chip, with a source electrode on its back side and a gate 51 and a drain 52 on its front side.

[0166] In this embodiment, the MOS chip 5 and the GaN chip 7 are directly disposed on the lead frame base island 1. The source electrode on the back side of the MOS chip 5 is bonded and electrically connected to the first conductive region. The gate electrode of the MOS chip 5 is electrically connected to the gate 14 of the GaN power device, and the drain electrode of the MOS chip 5 is electrically connected to the source electrode of the GaN chip 7. The gate electrode of the GaN chip 7 is electrically connected to the first conductive region, and the drain electrode of the GaN chip 7 is electrically connected to the drain 15 of the GaN power device. This embodiment can form a GaN power device with a Cascode structure and GDS pin performance.

[0167] The method for fabricating the GaN power device packaging structure provided in this embodiment includes the following steps:

[0168] Design and tape-out of high-performance GaN chips (such as...) Figure 4As shown), the MOS chip (such as...) Figure 16 (as shown); wherein, the back / substrate of the GaN chip is insulated and is a non-electrical terminal, and its main function on the back is heat dissipation, and its source, gate and drain are arranged on its front; the back of the MOS chip is the source, and its gate and drain are arranged on its front.

[0169] Design precision leadframes (such as) Figure 7 The GaN power device's gate 14 (Pin1-G electrode), drain 15 (Pin2-D electrode), and source 16 (Pin3-S electrode) are arranged sequentially along the long side of the lead frame base island 1 to achieve the GDS electrical performance arrangement of the GaN HMET device's pin terminals. The Pin1-G and Pin2-D electrodes are not directly connected to the lead frame base island. Pin3-S is connected to the lead frame base island, and a first conductive region electrically connected to Pin3-S is provided on the lead frame base island. The connection between Pin3-S and the lead frame base island has a horn-shaped structure, and each pin terminal is supported and fixed by connecting ribs.

[0170] The GaN chip and MOS chip are respectively attached to the lead frame base island by high-precision adhesive with thermally conductive and low-stress adhesive on both sides. Preferably, the GaN chip is located at the position of the drain 15 of the GaN power device directly opposite the lead frame base island, and the MOS chip is located at the position of the gate 14 of the GaN power device directly opposite the lead frame base island. This can reduce the length of the bonding wire, reduce the impurity inductance of the device, and improve the electrical performance of the product.

[0171] After the adhesive cures, MOS chips, GaN chips, etc., are electrically connected to the lead frame base island and each pin terminal via WB bonding leads. See [link to documentation]. Figure 16 ,include:

[0172] The gate of the MOS chip and the gate 14 of the GaN power device are electrically connected by bonding leads;

[0173] The drain of the MOS chip and the source of the GaN chip are electrically connected by bonding wires.

[0174] The gate of the GaN chip is electrically connected to the first conductive region by bonding wires, and then electrically connected to the source of the MOS chip and the source 16 of the GaN power device.

[0175] The drain of the GaN chip is electrically connected to the drain 15 of the GaN power device via bonding wires.

[0176] The molding process is adopted to encapsulate and protect the GaN power device packaging structure (the packaging area includes the die and wire, as well as the lead frame base island, excluding the connecting ribs) with EMC resin to achieve the device's electrical and heat dissipation functions.

[0177] The excess parts, such as the outer lead frame and the connecting ribs, are cut off and separated using electroplating and cutting processes to obtain a single GaN power device.

[0178] Each GaN power device undergoes visual inspection and electrical performance testing to eliminate defective products, thus obtaining GaN power devices that meet both electrical performance and appearance standards.

[0179] The GaN power device provided in this embodiment is a GaN power device with a Cascode structure and GDS pins. It only needs to be electrically connected in four places by bonding wires, which not only simplifies the process, but also greatly reduces the parasitic parameters of the device and improves the high-frequency performance and voltage withstand performance of the device.

[0180] Example 5

[0181] In this embodiment, see Figure 17 and Figure 18 The structure and connection method of the lead frame base island 1, the gate 14 (Pin1-G electrode) of the GaN power device, the drain 15 (Pin2-D) of the GaN power device, the source 16 (Pin3-S) of the GaN power device, and the connecting ribs are the same as in Embodiment 1. The structure of the GaN chip 7 is also the same as in Embodiment 1.

[0182] The difference between this embodiment and Embodiment 1 is that the structure of the MOS chip 5 is different from that in Embodiment 1, and this embodiment does not include a substrate; the MOS chip 5 and the GaN chip 7 are directly disposed on the lead frame base island 1. The MOS chip 5 is as follows: Figure 17 The image shows an LDMOS chip with its back side insulated and its front side having a gate 51, a drain 52, and a source 53.

[0183] In this embodiment, the MOS chip 5 and the GaN chip 7 are directly disposed on the lead frame base island 1. The back side of the MOS chip 5 is attached to the lead frame base island 1, and the gate of the MOS chip 5 is electrically connected to the gate 14 of the GaN power device. The source of the MOS chip 5 is electrically connected to the first conductive region.

[0184] The back side of the GaN chip 7 is bonded to the lead frame base island 1, and the gate of the GaN chip 7 is electrically connected to the first conductive region, the drain of the GaN chip 7 is electrically connected to the drain 15 of the GaN power device, and the source of the GaN chip 7 is electrically connected to the drain of the MOS chip 5. This embodiment can form a GaN power device with a Cascode structure and GDS pin performance.

[0185] The method for fabricating the GaN power device packaging structure provided in this embodiment includes the following steps:

[0186] Design and tape-out of high-performance GaN chips (such as...) Figure 4 As shown), the MOS chip (such as...) Figure 17 (as shown); wherein, the GaN chip has an insulated back / substrate and is a non-electrical terminal, and its main function on the back is heat dissipation, and its source, gate and drain are provided on the front; the MOS chip has an insulated back / substrate and is a non-electrical terminal, and its gate, drain and source are provided on the front.

[0187] Design precision leadframes (such as) Figure 7 The GaN power device's gate 14 (Pin1-G electrode), drain 15 (Pin2-D electrode), and source 16 (Pin3-S electrode) are arranged sequentially along the long side of the lead frame base island 1 to achieve the GDS electrical performance arrangement of the GaN HMET device's pin terminals. The Pin1-G and Pin2-D electrodes are not directly connected to the lead frame base island. Pin3-S is connected to the lead frame base island, and a first conductive region electrically connected to Pin3-S is provided on the lead frame base island. The connection between Pin3-S and the lead frame base island has a horn-shaped structure, and each pin terminal is supported and fixed by connecting ribs.

[0188] The GaN chip and MOS chip are respectively attached to the lead frame base island by high-precision adhesive with thermally conductive and low-stress adhesive on both sides. Preferably, the GaN chip is located at the position of the drain 15 of the GaN power device directly opposite the lead frame base island, and the MOS chip is located at the position of the gate 14 of the GaN power device directly opposite the lead frame base island. This can reduce the length of the bonding wire, reduce the impurity inductance of the device, and improve the electrical performance of the product.

[0189] After the adhesive cures, MOS chips, GaN chips, etc., are electrically connected to the lead frame base island and each pin terminal via WB bonding leads. See [link to documentation]. Figure 16 ,include:

[0190] The gate of the MOS chip and the gate 14 of the GaN power device are electrically connected by bonding leads;

[0191] The drain of the MOS chip and the source of the GaN chip are electrically connected by bonding wires.

[0192] The source of the MOS chip and the first conductive region are electrically connected by bonding wires, and then electrically connected to the source 16 of the GaN power device.

[0193] The gate of the GaN chip is electrically connected to the first conductive region by bonding wires, and then electrically connected to the source of the MOS chip and the source 16 of the GaN power device.

[0194] The drain of the GaN chip is electrically connected to the drain 15 of the GaN power device via bonding wires.

[0195] The molding process is adopted to encapsulate and protect the GaN power device packaging structure (the packaging area includes the die and wire, as well as the lead frame base island, excluding the connecting ribs) with EMC resin to achieve the device's electrical and heat dissipation functions.

[0196] The excess parts, such as the outer lead frame and the connecting ribs, are cut off and separated using electroplating and cutting processes to obtain a single GaN power device.

[0197] Each GaN power device undergoes visual inspection and electrical performance testing to eliminate defective products, resulting in GaN power devices that meet both electrical performance and visual quality standards. Example Six

[0198] This embodiment provides a GaN power device that does not include a MOS chip. See [link to documentation]. Figure 19 The GaN power device package structure includes a lead frame base island 1, a gate 14 of the GaN power device, a drain 15 of the GaN power device, a source 16 of the GaN power device, a connecting rib 18, and a GaN chip 7.

[0199] The gate 14, drain 15, and source 16 of the GaN power device are sequentially distributed along a first direction relative to the lead frame base island 1. The source 16 of the GaN power device and the lead frame base island 1 are an integrally connected structure. A fourth conductive region is provided on the lead frame base island 1, and the fourth conductive region is electrically connected to the source 16 of the GaN power device.

[0200] The gate 14, drain 15, and source 16 of the GaN power device each have an insulating extension portion in the direction away from the lead frame base island 1. These extension portions are connected to the connecting rib 18. The extension portion of the source 16 of the GaN power device has an increasing width from the point of connection between the source 16 and the lead frame base island 1. This forms an E-Mode GaN chip package structure with GDS pin performance.

[0201] like Figure 19 As shown, the GaN chip 7 is disposed on the lead frame base island 1. The drain of the GaN chip 7 is electrically connected to the fourth conductive region through bonding leads, thereby achieving electrical connection with the source 16 of the GaN power device. The gate of the GaN chip 7 is electrically connected to the gate 14 of the GaN power device through bonding leads, and the source of the GaN chip 7 is electrically connected to the drain 15 of the GaN power device through bonding leads.

[0202] The method for fabricating the GaN power device packaging structure provided in this embodiment includes the following steps:

[0203] Design and tape-out of high-performance GaN chips (such as...) Figure 4 (as shown); wherein, the back / substrate of the GaN chip is insulated and is a non-electrical terminal, and its main function is heat dissipation; the front side of the GaN chip is provided with its gate, source and drain.

[0204] Design precision leadframes (such as) Figure 7 The GaN power device's gate 14 (Pin1-G electrode), drain 15 (Pin2-D electrode), and source 16 (Pin3-S electrode) are arranged sequentially along the long side of the lead frame base island 1 to achieve the GDS electrical performance arrangement of the GaN HMET device's pin terminals. The Pin1-G and Pin2-D electrodes are not directly connected to the lead frame base island. Pin3-S is connected to the lead frame base island, and a first conductive region electrically connected to Pin3-S is provided on the lead frame base island. The connection between Pin3-S and the lead frame base island has a horn-shaped structure, and each pin terminal is supported and fixed by connecting ribs.

[0205] The back of the GaN chip is attached to the lead frame base island using a high-precision adhesive pad with thermally conductive, low-stress adhesive on both sides.

[0206] After the adhesive cures, the GaN chip is electrically connected to the leadframe base island and each pin terminal via WB bonding wires. See [link to documentation]. Figure 19 ,include:

[0207] The drain of the GaN chip 7 is electrically connected to the fourth conductive region by bonding wires, thereby achieving electrical connection with the source 16 of the GaN power device;

[0208] The gate of the GaN chip 7 is electrically connected to the gate 14 of the GaN power device by bonding wires.

[0209] The source of the GaN chip 7 is electrically connected to the drain of the GaN power device 15 by bonding wires.

[0210] The molding process is adopted to encapsulate and protect the GaN power device packaging structure (the packaging area includes the die and wire, as well as the lead frame base island, excluding the connecting ribs) with EMC resin to achieve the device's electrical and heat dissipation functions.

[0211] The excess parts, such as the outer lead frame and the connecting ribs, are cut off and separated using electroplating and cutting processes to obtain a single GaN power device.

[0212] Each GaN power device undergoes visual inspection and electrical performance testing to eliminate defective products, thus obtaining GaN power devices that meet both electrical performance and appearance standards.

[0213] It should be noted that the lead frame in this invention includes at least the lead frame base island, the gate 14 of the GaN power device, the drain 15 of the GaN power device, the source 16 of the GaN power device, and the connecting rib 18. For a structure in which all three electrode pins (i.e., the gate, source, and drain of the GaN power device) are separated from the lead frame base island, the lead frame also includes at least an outer frame for connecting the lead frame base island and the three electrodes. For a structure in which one electrode is connected to the lead frame base island, based on the reinforcing rib structure proposed in this invention, the lead frame may include the outer frame or may not include the outer frame. Excluding the outer frame saves more cost.

[0214] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0215] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A GaN power device package structure, characterized by, It includes a lead frame base island (1), a gate (14) of a GaN power device, a drain (15) of a GaN power device, a source (16) of a GaN power device, a connecting rib (18), a MOS chip (5) and a GaN chip (7); The gate (14), drain (15), and source (16) of the GaN power device are distributed sequentially along a first direction relative to the lead frame base island (1), and at least two of the three electrodes of the GaN power device (gate (14), drain (15), and source (16) are separated from the lead frame base island (1). The gate (14), drain (15), and source (16) of the GaN power device are each provided with an insulating extension in a direction away from the lead frame base island (1). The extensions of the gate (14), drain (15), and source (16) of the GaN power device are respectively connected to the connecting rib (18). The MOS chip (5) and the GaN chip (7) are both disposed on the lead frame base island (1), and the gate of the MOS chip (5) is electrically connected to the gate (14) of the GaN power device, and the source of the MOS chip (5) is electrically connected to the source (16) of the GaN power device. The drain of the GaN chip (7) is electrically connected to the drain (15) of the GaN power device, the gate of the GaN chip (7) is electrically connected to the source (16) of the GaN power device, and the source of the GaN chip (7) is electrically connected to the drain of the MOS chip (5).

2. The GaN power device package structure of claim 1, wherein, The source (16) of the GaN power device and the lead frame base island (1) are an integral structure connected to each other. A first conductive region is provided on the lead frame base island (1), and the first conductive region is electrically connected to the source (16) of the GaN power device. The extension of the source (16) of the GaN power device to the connection between the source (16) of the GaN power device and the lead frame base island (1) has an increased width structure.

3. The GaN power device packaging structure according to claim 2, characterized in that, It also includes a substrate (30), on the front side of which a second conductive area (31) is provided, the back side of which is insulated, and the back side of which is attached to the lead frame base island (1). The drain of the MOS chip (5) is disposed on the back side, and the source and gate of the MOS chip (5) are disposed on the front side. The MOS chip (5) is disposed on the substrate (30), and the back side of the MOS chip (5) is attached to the front side of the substrate (30). The drain of the MOS chip (5) is electrically connected to the second conductive region (31). The back side of the GaN chip (7) is insulated, and the front side of the GaN chip (7) is provided with its gate, source and drain. The back side of the GaN chip (7) is attached to the lead frame base island (1), and the source of the GaN chip (7) is electrically connected to the second conductive region (31).

4. The GaN power device packaging structure according to claim 2, characterized in that, The MOS chip (5) and the GaN chip (7) are stacked. The GaN chip (7) is insulated on the back side, and the GaN chip (7) has a gate (81), a drain (82) and a source window on the front side. Any point in the source window is configured as the source of the GaN chip (7). The drain of the MOS chip (5) is disposed on the back side, and the source and gate of the MOS chip (5) are disposed on the front side. The MOS chip (5) is disposed within the source window, and the drain of the MOS chip (5) is attached to and electrically connected to the source window. The source of the MOS chip (5) is electrically connected to the first conductive region, and the source of the MOS chip (5) is electrically connected to the gate (73) of the GaN chip (7).

5. The GaN power device packaging structure according to claim 2, characterized in that, The MOS chip (5) and the GaN chip (7) are directly disposed on the lead frame base island (1), wherein the back side of the MOS chip (5) is provided with its source, and the front side of the MOS chip (5) is provided with its gate and drain. The back side of the GaN chip (7) is insulated, and the front side of the GaN chip (7) is provided with its gate, drain and source. The source of the MOS chip (5) on the back side is attached to and electrically connected to the first conductive region. The gate of the MOS chip (5) is electrically connected to the gate (14) of the GaN power device. The drain of the MOS chip (5) is electrically connected to the source of the GaN chip (7). The gate of the GaN chip (7) is electrically connected to the first conductive region, and the drain of the GaN chip (7) is electrically connected to the drain (15) of the GaN power device.

6. The GaN power device packaging structure according to claim 2, characterized in that, The MOS chip (5) and the GaN chip (7) are directly disposed on the lead frame base island (1), wherein the back side of the MOS chip (5) is insulated, and the front side of the MOS chip (5) is provided with its source, gate and drain. The back side of the GaN chip (7) is insulated, and the front side of the GaN chip (7) is provided with its gate, drain and source. The back side of the MOS chip (5) is attached to the lead frame base island (1), and the gate of the MOS chip (5) is electrically connected to the gate (14) of the GaN power device. The source of the MOS chip (5) is electrically connected to the first conductive region. The back side of the GaN chip (7) is attached to the lead frame base island (1), and the gate of the GaN chip (7) is electrically connected to the first conductive region. The drain of the GaN chip (7) is electrically connected to the drain (15) of the GaN power device, and the source of the GaN chip (7) is electrically connected to the drain of the MOS chip (5).

7. The GaN power device packaging structure according to claim 1, characterized in that, The gate (14), drain (15), and source (16) of the GaN power device are all separate from the lead frame base island (1). It also includes an outer frame, through which the outer side of the lead frame base island (1) is connected to the extension portions of the three electrodes of the GaN power device: the gate (14), the drain (15), and the source (16).

8. The GaN power device packaging structure according to claim 7, characterized in that, It also includes a substrate (30), on the front side of the substrate (30) are provided a first accommodating area and a second accommodating area (32), the first accommodating area is provided with a second conductive area (31), the back side of the substrate (30) is insulated, and the back side of the substrate (30) is attached to the lead frame base island (1). The drain of the MOS chip (5) is disposed on the back side, and the source and gate of the MOS chip (5) are disposed on the front side. The MOS chip (5) is disposed on the substrate (30), and the back side of the MOS chip (5) is attached to the first accommodating area, and the drain of the MOS chip (5) is electrically connected to the second conductive area (31). The GaN chip (7) is disposed on the substrate (30), and the back side of the GaN chip (7) is attached to the second accommodating region (32), and the source of the GaN chip (7) is electrically connected to the second conductive region (31).

9. The GaN power device packaging structure according to claim 2, characterized in that, The electrode connected to the lead frame base island (1) is configured as the first electrode; The width of the first electrode at its connection with the lead frame base island (1) is at least twice the width of the extension of the first electrode.

10. The GaN power device packaging structure according to any one of claims 1 to 5, characterized in that, The connecting rib (18) is in the shape of a strip, and the width of the strip is 4mm to 6mm.

11. The GaN power device packaging structure according to claim 1, characterized in that, The minimum distance between the electrode that is separated from the lead frame base island (1) among the three electrodes of the GaN power device (gate (14), drain (15) and source (16) is 2 mm to 6 mm.

12. The GaN power device packaging structure according to claim 1, characterized in that, The extensions of the gate (14), drain (15), and source (16) of the GaN power device are integral with the connecting rib (18).

13. The GaN power device packaging structure according to claim 1, characterized in that, The GaN power device packaging structure is configured with a packaging area, which is configured to be packaged with a packaging material, and the connecting rib (18) is disposed on the outside of the packaging area. After the GaN power device package structure is packaged, the connecting rib (18) is cut off.

14. A GaN power device packaging structure, characterized in that, It includes a lead frame base island (1), a gate (14) of a GaN power device, a drain (15) of a GaN power device, a source (16) of a GaN power device, a connecting rib (18) and a GaN chip (7); The gate (14), drain (15), and source (16) of the GaN power device are distributed sequentially along a first direction relative to the lead frame base island (1), and at least two of the three electrodes of the GaN power device (gate (14), drain (15), and source (16) are separated from the lead frame base island (1). The gate (14), drain (15), and source (16) of the GaN power device are each provided with an insulating extension in a direction away from the lead frame base island (1). The extensions of the gate (14), drain (15), and source (16) of the GaN power device are respectively connected to the connecting rib (18). The drain of the GaN chip (7) is electrically connected to the source (16) of the GaN power device, the gate of the GaN chip (7) is electrically connected to the gate (14) of the GaN power device, and the source of the GaN chip (7) is electrically connected to the drain (15) of the GaN power device.

15. The GaN power device packaging structure according to claim 14, characterized in that, The source (16) of the GaN power device and the lead frame base island (1) are an integral structure connected to each other. A fourth conductive region is provided on the lead frame base island (1). The fourth conductive region is electrically connected to the source (16) of the GaN power device. The drain of the GaN chip (7) is electrically connected to the fourth conductive region. The extension of the source (16) of the GaN power device to the connection between the source (16) of the GaN power device and the lead frame base island (1) has a structure with increasing width.

16. A method for fabricating a GaN power device packaging structure, characterized in that, Includes the following steps: A leadframe is designed and fabricated, comprising a leadframe base island, a gate of a GaN power device, a drain of a GaN power device, a source of a GaN power device, and connecting ribs. The gate, drain, and source of the GaN power device are sequentially distributed relative to the leadframe base island along a first direction, and at least two of the three electrodes (gate, drain, and source) are separated from the leadframe base island. Each of the GaN power device's gate, drain, and source has an insulating extension portion in a direction away from the leadframe base island, and these extension portions are connected to the connecting ribs. A GaN chip and a MOS chip are disposed on the lead frame base island, and the gate of the MOS chip is electrically connected to the gate of the GaN power device, and the source of the MOS chip is electrically connected to the source of the GaN power device. The method involves electrically connecting the drain of the GaN chip to the drain of the GaN power device, electrically connecting the gate of the GaN chip to the source of the GaN power device, and electrically connecting the source of the GaN chip to the drain of the MOS chip.

17. A method for fabricating a GaN power device packaging structure, characterized in that, Includes the following steps: A leadframe is designed and fabricated, comprising a leadframe base island, a gate of a GaN power device, a drain of a GaN power device, a source of a GaN power device, and connecting ribs. The gate, drain, and source of the GaN power device are sequentially distributed relative to the leadframe base island along a first direction, and at least two of the three electrodes (gate, drain, and source) are separated from the leadframe base island. Each of the GaN power device's gate, drain, and source has an insulating extension portion in a direction away from the leadframe base island, and these extension portions are connected to the connecting ribs. A GaN chip is disposed on the lead frame base island, and the drain of the GaN chip is electrically connected to the source of the GaN power device; the gate of the GaN chip is electrically connected to the gate of the GaN power device, and the source of the GaN chip is electrically connected to the drain of the GaN power device.

18. A method for fabricating a lead frame, characterized in that, The lead frame is suitable for fabricating GaN power devices with an electrode arrangement of gate-drain-source. The fabrication method of the lead frame includes the following steps: Design and fabricate a leadframe, which includes a leadframe base island, a gate of the GaN power device, a drain of the GaN power device, a source of the GaN power device, and connecting ribs. The gate, drain, and source of the GaN power device are distributed sequentially along a first direction relative to the lead frame base island, and at least two of the three electrodes of the GaN power device are separated from the lead frame base island. The gate, drain, and source of the GaN power device are each provided with an insulated extension in the direction away from the lead frame base island, and the extensions of the gate, drain, and source of the GaN power device are respectively connected to the connecting rib.

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