An integrated method of self-curling passive elements

Abstract

This invention provides an integration method for self-curling passive components. The wafer-level front-end process for the self-curling component begins with the deposition of metal thin films on both the front and back of the substrate. Next, a dual-frequency silicon nitride strain layer is deposited via plasma chemical vapor deposition. A first positive photolithography step followed by inductively coupled plasma dry etching is used to pattern the mesa. Four negative photolithography steps are then used to progressively pattern and deposit a metal step layer, a copper metal layer, a gold electrode layer, and an etching window layer. An oriented protective layer is deposited using atomic force deposition. Finally, a xenon difluoride dry etching process is used to etch the sacrificial layer, releasing the film stress from the dual-frequency silicon nitride strain layer and triggering curling to obtain a self-curling inductor. A modified layer consisting of voids, a high dislocation density layer, and cracks is generated inside the wafer using a specific wavelength laser. The wafer is then cleaved starting from this modified layer. Finally, UV desolventizing is used to obtain separable, micron-scale independent inductors.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an integration method for self-rolling passive components. In particular, it relates to a three-dimensional self-rolling micro / nano fabrication technology proposed to meet the miniaturization and high-performance heterogeneous integration requirements of passive inductor components in microwave RF integrated circuits. Background Technology

[0002] Microwave integrated circuits play a central role in modern communication systems. The development of next-generation mobile communication technologies has placed higher demands on radio frequency transceiver systems, necessitating the integration of more functional components into microwave chips. Miniaturization and multifunctionality of devices have become the main research directions. Microwave integrated circuits (ICs), such as low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and power amplifiers (PAs), typically contain various passive components, such as capacitors, varactor diodes, resistors, inductors, transformers, and transmission lines. These passive components play a crucial role in circuits, primarily for impedance matching, resonance, filtering, and biasing functions. Especially in the Sub-6GHz and millimeter-wave bands, the quality factor (Q value), self-resonant frequency, and power capacity of passive components directly determine the linearity, efficiency, and noise figure of the transceiver link.

[0003] In radio frequency integrated circuits operating below 10 GHz, the performance of passive components determines the overall circuit performance, especially since the RF characteristics of active devices (such as transistors) are primarily manifested at higher frequencies. In this frequency band, designers must fully utilize the characteristics of passive components to ensure signal quality and system reliability. However, traditional planar spiral inductors, limited by substrate losses, metal resistance, and proximity effects, typically have a Q value between 10 and 30, and are prone to self-resonance due to parasitic capacitance in the GHz band, becoming a bottleneck in system performance.

[0004] A significant trend in microwave integrated circuits is the adoption of miniaturized lumped components. Advances in photolithography and thin-film technology have led to a significant reduction in the size of lumped components (such as capacitors and inductors), and an increase in applicable frequency bands. This allows designers to create smaller, more efficient circuits to meet the needs of modern communication systems. However, planar integration technology is approaching its physical limits; further miniaturization will lead to increased conductor losses, reduced power handling capabilities, and crosstalk problems caused by electromagnetic coupling.

[0005] Integrating lumped elements on a dielectric substrate with chip-form semiconductor devices provides an innovative approach to microwave integrated circuits. This heterogeneous integration not only improves the integration density of devices but also enhances the versatility of circuit functions. Therefore, developing miniaturized and lightweight capacitors suitable for microwave frequencies has become a crucial issue that urgently needs to be addressed in mobile communication technologies. This research is essential for improving the overall performance and integration density of microwave integrated circuit chips.

[0006] The emergence of self-scrolling technology has provided a new direction for miniaturization. By fabricating devices vertically, this technology achieves heterogeneous integration while effectively reducing chip area and power consumption. This approach not only expands the development space of integrated circuits but also provides new ideas for extending Moore's Law. The continuation of Moore's Law depends on the continuous improvement of integration density and functionality, and self-scrolling technology is the key to achieving this goal.

[0007] Therefore, this invention proposes a self-curling passive component integration method to solve the above-mentioned technical problems. Summary of the Invention

[0008] The purpose of this invention is to provide an integration method for self-curling passive components, which can not only effectively reduce the chip area, but also achieve heterogeneous integration continuity, providing a new approach to Moore's Law.

[0009] To address the aforementioned technical problems, this invention provides a method for integrating self-curling passive components, the method comprising: Step 1: Dry and wet methods are combined to pre-treat the dielectric substrate, wherein the substrate includes sapphire and glass; When the substrate is silicon, a silicon dioxide insulating layer needs to be grown on the surface to achieve electrical isolation; Step 2: A titanium shielding layer is formed on the back side of the substrate and a germanium sacrificial layer is deposited on the front side using electron beam deposition technology; Step 3: Deposit dual-frequency silicon nitride strained layers sequentially using plasma-enhanced chemical vapor deposition; The dual-frequency silicon nitride strain layer includes a low-frequency silicon nitride thin film and a high-frequency silicon nitride thin film. In step 4, a positive photolithography process is used to pattern the mesa, and an inductively coupled plasma dry etching process is used to define the stress platform. The etching depth needs to be shallow enough to reach the substrate surface. Step 5: Deposit a directional protective layer using atomic layer deposition (ALD). Step 6: The first negative photolithography patterning of the step pattern is formed by electron beam deposition to form a metal step layer, mainly made of titanium. Step 7: The metal layer pattern is patterned by negative photolithography in the second step, and copper metal is deposited by electron beam to form a conductive layer. The main materials are titanium and copper. Step 8: The electrode layer pattern is patterned by negative photolithography for the third time, and the gold electrode layer is deposited by electron beam deposition. The main materials are titanium and gold. Step 9: The fourth negative photolithography patterning etching window is opened by inductively coupled plasma dry etching and etched to the surface of the sacrificial layer. Step 10: Selectively remove the Ge sacrificial layer by dry etching with xenon difluoride to trigger stress release of the dual-frequency silicon nitride strain layer and obtain a self-rolling inductor with two or more rolls. Step 11: Wafer-level components are fixed by attaching them to a blue film or a UV film; Step 12: The laser performs local deformation modification to obtain a modified layer composed of pores, a high dislocation density layer, and cracks; Step 13: Using the modified layer as the starting point for wafer dicing and cracking, use a cleaver to cleave the wafer into dicing slabs. Step 14: De-adhesion of the UV film to obtain a separable micron-scale self-rolling inductor; Step 15: Bake the silver paste to fix the chip; Step 16: Gold wire bonding or flip-chip bonding to interconnect the chip and the self-rolling inductor; Step 17: Surface mount packaging to achieve heterogeneous integration of the self-rolling inductor.

[0010] As a further improvement to the present invention, step 1 further includes, Step 1.1: Soak in acetone and sonicate, then soak in isopropanol and sonicate, and finally rinse with deionized water and dry with nitrogen. Step 1.2, then proceed with dry treatment, using a plasma cleaner to clean for 5 minutes at 100 W power in an oxygen environment; Step 4 also includes, Step 4.1: Before the positive photolithography process, the wafer surface is pretreated using a special oven treated with HMDS (Hexamethyldisilazane). This involves turning on the vacuum pump to create a vacuum, and once the vacuum level reaches a certain high level, nitrogen gas is introduced. After reaching a certain low vacuum level, the process of vacuuming and nitrogen introduction is repeated. After the set number of nitrogen introductions is reached, the process is held for a period of time to allow the wafer to be fully heated and reduce surface moisture. Then, vacuuming and HMDS gas introduction are started again. After the set time is reached, HMDS introduction is stopped, and the wafer enters a holding phase to allow the wafer surface to fully react with HMDS. After the set holding time is reached, vacuuming and HMDS gas introduction are started again to complete the entire process. The reaction mechanism of HMDS with silicon wafers is as follows: First, heat to 100 ℃–200 ℃ to remove the moisture on the wafer surface. Then, HMDS reacts with the -OH groups on the surface to form silyl ether bonds on the wafer surface, eliminating hydrogen bonding and thus transforming the polar surface into a non-polar surface. Step 4.2: After HMDS pretreatment, positive photoresist is spin-coated; using a photolithography machine, the photoresist portion that needs to be retained is blocked, and the mesa pattern on the first set of photomasks is transferred to the surface of the upper stress layer. After exposure and development, a patterned positive photoresist layer is obtained on the stress layer; the positive photoresist layer includes spaced and uniformly distributed square photoresist blocks, i.e., stress-relieved mesa patterns; Step 4.3, Inductively Coupled Plasma Dry Etching: Using an ICP dry etching apparatus, the dual-frequency silicon nitride stress layer and germanium sacrificial layer not covered by the positive photoresist layer are etched away, and a shallow layer is etched downwards onto the substrate. Step 4.4, wet cleaning: remove the barrier layer of the remaining positive photoresist layer, retain the stress layer and germanium sacrificial layer below the positive photoresist layer, and obtain the patterned region module.

[0011] As a further improvement of the present invention, step 6.1, spin coating, exposure, and development Spin-coating negative photoresist and pre-baking; using a photolithography machine, aligning and exposing the second set of photomasks; then post-baking, and finally development, to map the solid pattern in the second set of photomasks onto the stage. Step 6.2: On the wafer obtained in step 4.1, use a plasma cleaning device to clean it and remove any residual photoresist that has not been completely developed; use a high-vacuum electron beam evaporation device to deposit a stepped metal thin film layer in a vacuum environment. Step 6.3: Prepare a wafer with a metal step layer, and use acetone or resist remover to completely remove the first negative photoresist layer. The step metal layer on the first negative photoresist layer is then removed to obtain the metal step layer of the second mask.

[0012] As a further improvement of the present invention, step 7.1, second negative photolithography; step 7.2, plasma cleaning and electron beam deposition process to deposit a copper metal layer; Step 7.3: The patterned metal film is obtained by wet peeling with acetone or a desizing liquid.

[0013] As a further improvement of the present invention, step 8.1, the third negative photolithography, includes coating, pre-baking, exposure, post-baking and development; Step 8.2, plasma cleaning and electron beam deposition process to deposit a gold electrode layer; Step 8.3: The patterned gold film is obtained by wet peeling with acetone or a desizing liquid.

[0014] As a further improvement of the present invention, step 9 includes: Step 9.1, the fourth negative photolithography, includes coating, pre-baking, exposure, post-baking and development; Step 9.2: Use plasma cleaning pretreatment, then use ICP dry etching to etch away the alumina orientation layer, dual-frequency silicon nitride stress layer and germanium sacrificial layer not covered by the negative photoresist layer, and shallowly etch to a certain depth towards the substrate. Step 9.3: On the wafer obtained in the previous step, wet etching of the photoresist barrier layer is performed using a resist remover to obtain a metal layer, an aluminum oxide orientation layer, a dual-frequency silicon nitride layer, and a germanium sacrificial layer protected by negative photoresist.

[0015] As a further improvement of the present invention, step 11 includes: fixing the wafer, using a laser with a wavelength of 1064nm to focus on the inside of the wafer through a transmission mirror to generate a local deformation layer, namely a modified layer, which is mainly composed of holes, a high dislocation density layer and cracks; the modified layer is the starting point for subsequent wafer dicing and cracking.

[0016] As a further improvement of the present invention, in step 1, when the substrate material is silicon, a silicon dioxide insulating layer needs to be grown on the silicon surface to achieve electrical isolation between layers; In step 2, the thickness of the germanium sacrificial layer is configured to be 30 nm to 150 nm; In step 3, the thickness of the low-frequency silicon nitride film is 20 nm to 50 nm; the thickness of the high-frequency silicon nitride film is 20 nm to 50 nm. In step 3, a low-frequency silicon nitride thin film, i.e., the lower stress layer, is first deposited on the germanium sacrificial layer using plasma-enhanced chemical vapor deposition, and then a high-frequency silicon nitride thin film, i.e., the upper stress layer, is deposited as the stretching layer.

[0017] As a further improvement of the present invention, in step 10, the germanium sacrificial layer is etched through the etching window using dry etching or wet etching, so that the upper stress layer and the lower stress layer, namely the dual-frequency silicon nitride, are displaced and rolled towards the electrode end with the planar inductor to obtain an on-chip micro-nanotube-shaped self-rolling inductor; the inner diameter of the self-rolling inductor is 10~200 μm, and the number of rolls is two or more.

[0018] As a further improvement of the present invention, in step 16, gold wire bonding provides excellent electrical connection to ensure stable signal transmission; while flip-chip bonding achieves efficient thermal management and smaller package size through micro-bumps, improving overall performance and integration.

[0019] The beneficial technical effects of this invention are reflected in the following aspects: The self-rolling passive component integration method compatible with integrated circuit technology provided by this invention has significant and diverse beneficial technical effects compared with existing planar inductor technology and other three-dimensional integration schemes, specifically reflected in the following aspects: 1. The most intuitive and prominent effect of this invention lies in its breakthrough reduction in the planar area occupied by inductor components. By extending the power transmission path from a two-dimensional plane to three-dimensional space through self-curling technology, the area occupied by traditional planar spiral inductors is successfully reduced by less than 35%. This order-of-magnitude reduction in size frees up enormous space for integrating more functional units (whether passive components or active circuits) per unit chip area, greatly improving the chip's integration and functional density. For mobile terminals, wearable devices, and IoT nodes where space is extremely valuable, this invention means that RF front-end modules can be made smaller and thinner, providing unprecedented flexibility in product design, while directly contributing to reducing overall system power consumption.

[0020] 2. The self-curved three-dimensional inductor prepared by this invention achieves a qualitative improvement in key radio frequency performance indicators compared to traditional planar inductors. Its three-dimensional tubular coil, after release, is entirely suspended above the substrate, effectively blocking the diffusion path of magnetic field lines to the damaged substrate and fundamentally suppressing substrate loss. Simultaneously, using a glass substrate as the main conductor platform not only further weakens the negative impact of the substrate on the electromagnetic field but also significantly reduces the overall manufacturing cost. The synergistic effect of these structural advantages significantly improves the inductor's quality factor (Q value). The increased Q value directly leads to lower transmission loss, a steeper filter roll-off, a better low-noise amplifier noise figure, and lower voltage-controlled oscillator phase noise, thereby comprehensively improving the linearity and efficiency of the radio frequency system. Furthermore, because the coil is entirely suspended, the parasitic capacitance between it and the substrate is significantly reduced, resulting in a significant increase in the inductor's self-resonant frequency (SRF), with an improvement of over 20%. Thanks to its higher Q value and higher SRF, the self-curved inductor of this invention can operate stably and efficiently in the high-frequency bands required for 5G / 6G communication such as millimeter waves, significantly expanding the available bandwidth of the inductor and overcoming the technical bottleneck that traditional planar inductors cannot be used in high-frequency scenarios due to their low self-resonant frequency.

[0021] 3. The entire process flow adopted in this invention, including its core equipment (such as PECVD, ALD, ICP, electron beam evaporation, lithography machine, etc.) and basic materials (such as SiN...). x Materials such as Al2O3, Cu, and Ge are standard components on modern 8-inch and even 12-inch standard integrated circuit manufacturing lines. This high degree of compatibility means that the technology can be quickly integrated into existing semiconductor manufacturing systems for large-scale, highly consistent mass production without the need for expensive production line modifications or the purchase of specialized equipment. This characteristic greatly reduces the technical barriers, time costs, and financial risks associated with moving three-dimensional passive components from the laboratory to industrial applications, enabling rapid commercialization and economic benefits.

[0022] 4. This invention, through precise design and optimization of multilayer thin-film stress engineering and the introduction of a rigid Al2O3 protective layer, ensures that the self-rolled structure reaches a stable state with the lowest energy after release, and its three-dimensional tubular structure itself also possesses excellent mechanical strength. The self-rolled inductor prepared by this method can withstand the challenges posed by subsequent chip packaging processes (such as stress generated by molding compound injection) and harsh operating environments, exhibiting excellent structural stability and long-term operational reliability.

[0023] 5. One of the greatest advantages of this invention is that it shifts the performance tuning of self-curling inductors from the complex and difficult-to-control material physics level (such as controlling the intrinsic stress of the thin film) to the flexible, precise, and mature patterned design level. Researchers can fabricate a family of inductors with different inductance values ​​and Q-SRF characteristic curves under the same stable and mature process conditions simply by changing the design of the photomask (such as adjusting the pattern, linewidth, and spacing of the two-dimensional planar coils, and designing the cross-sectional shape of the metal layer). This meets the application requirements of diverse circuits, from low-frequency Bluetooth to high-frequency millimeter waves. This significantly shortens the product development cycle, reduces the cost and complexity of customized development for different applications, and provides RF integrated circuit designers with great flexibility and freedom.

[0024] 6. This invention enables the integration of the high-Q, small-size self-rolling inductor prepared according to this invention with high-performance active circuits (such as power amplifiers and low-noise amplifiers) based on different materials such as silicon, gallium arsenide, and gallium nitride into a single package using advanced packaging technology. This allows system designers to select the most suitable materials and technologies for each function, thereby constructing more powerful, smaller, and more efficient RF front-end modules, which can be widely used in high-end fields such as future 5G / 6G base stations, autonomous driving radar, and satellite internet terminals.

[0025] 7. This invention achieves high-precision, low-damage separation of micron-scale self-curling inductors through wafer-level laser modification and cleaving processes. The modified layer, composed of pores, high dislocation density regions, and microcracks, serves as the starting point for precise control of the cleaving path. Combined with UV debonding, this yields individual inductor units with neat edges and intact structures. This approach avoids the mechanical stress damage to the self-curling structure caused by traditional mechanical cutting, ensuring that the curling morphology and electrical performance are unaffected by the cutting process. Simultaneously, it significantly improves mass production efficiency, providing a reliable guarantee for large-scale industrial applications.

[0026] 8. This invention effectively solves the problem of chemical erosion of the silicon nitride stress layer by the wet process by introducing an oriented protective layer in the mid-process. This protective layer not only provides reverse pressure matching the strain layer, ensuring controllable curling of the structure along a preset axis during stress release, but also blocks the penetration of chemical reagents such as electroplating solutions and resist removers in subsequent processes through its dense and conformal properties, maintaining the stability of the film stress. This design balances process compatibility and structural reliability, and is a key technical support for achieving high-yield fabrication of self-curling inductors.

[0027] 9. This invention is compatible with both wire bonding and flip-chip bonding in back-end processes, allowing for flexible adaptation to different application scenarios. Wire bonding is suitable for conventional packaging requirements with low parasitic inductance and low thermal impact, ensuring that the inductor's rolled structure is not mechanically damaged by optimizing ultrasonic power, pressure, and thermal parameters. Flip-chip bonding, on the other hand, achieves even lower parasitic parameters and higher heat dissipation efficiency through tiny ball-shaped contacts, making it particularly suitable for high-frequency, high-performance scenarios such as millimeter-wave circuits and 5G / 6G front-end modules. The integration of these two solutions expands the applicability of self-rolling inductors in different RF systems and enhances the engineering practicality of the technology.

[0028] 10. This invention is compatible with a variety of semiconductor substrate materials, allowing for the selection of low-cost or high-frequency, low-loss substrates depending on the application scenario. In particular, the silicon substrate solution effectively blocks parasitic capacitive coupling between the inductor and the substrate through thermal oxidation growth of a SiO2 layer larger than 500nm (step 1.1), further improving the self-resonant frequency (SRF) and quality factor (Q value), while maintaining full compatibility with existing silicon-based integrated circuit processes, providing a more flexible substrate selection scheme for heterogeneous integration.

[0029] This invention not only completely solves the inherent contradiction between performance and size in traditional planar inductors, but also overcomes many problems in process compatibility, performance controllability and mechanical reliability of existing three-dimensional inductor technologies. It provides a practical and feasible technical path to high-performance, miniaturized and highly integrated RF microsystems with prospects for large-scale industrialization, and has significant technical, economic and strategic value. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the bare wafer structure of the present invention.

[0031] Figure 2 for Figure 1 A schematic diagram of the structure with titanium deposited on the back and germanium deposited on the front.

[0032] Figure 3 for Figure 2 A schematic diagram of the structure of deposited dual-frequency silicon nitride.

[0033] Figure 4This is a schematic diagram of the patterned countertop structure in this invention.

[0034] Figure 5 This is a schematic diagram of the atomic layer deposition of alumina in this invention.

[0035] Figure 6 This is a schematic diagram of the structure of the deposited metal conductive layer in this invention.

[0036] Figure 7 This is a schematic diagram of the window patterning structure in this invention.

[0037] Figure 8 A schematic diagram of the self-curling structure in this invention.

[0038] Figure 9 A schematic diagram of the structure of the self-rolling passive element in the wafer-level array of this invention.

[0039] Figure 10 A schematic diagram of the structure of the self-curling passive element after independent cutting in this invention.

[0040] Figure 11 A schematic diagram of the gold wire bonding structure of the self-curling passive element in this invention.

[0041] Figure 12 A schematic diagram of the flip-chip bonding structure of the self-curling passive element in this invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0044] This invention provides a method for integrating self-curling passive components, comprising the following end-to-end process steps: Step 1: Dry and wet methods are combined to pre-treat the dielectric substrate, wherein the substrate includes sapphire and glass; When the substrate is silicon, a silicon dioxide insulating layer needs to be grown on the surface to achieve electrical isolation; In addition to sapphire and glass substrates, dielectric substrates can also be made of materials such as borosilicate glass, quartz glass, aluminum nitride (AlN), and silicon carbide (SiC).

[0045] Step 2: A titanium shielding layer is formed on the back side of the substrate and a germanium sacrificial layer is deposited on the front side using electron beam deposition technology; Step 3: Deposit dual-frequency silicon nitride strained layers sequentially using plasma-enhanced chemical vapor deposition; The dual-frequency silicon nitride strain layer includes a low-frequency silicon nitride thin film and a high-frequency silicon nitride thin film. In step 4, a positive photolithography process is used to pattern the mesa, and an inductively coupled plasma dry etching process is used to define the stress platform. The etching depth needs to be shallow enough to reach the substrate surface. Step 5: Deposit a directional protective layer using atomic layer deposition (ALD). Step 6: The first negative photolithography patterning of the step pattern is formed by electron beam deposition to form a metal step layer, mainly made of titanium. Step 7: The metal layer pattern is patterned by negative photolithography in the second step, and copper metal is deposited by electron beam to form a conductive layer. The main materials are titanium and copper. Step 8: The electrode layer pattern is patterned by negative photolithography for the third time, and the gold electrode layer is deposited by electron beam deposition. The main materials are titanium and gold. Here, an additional gold conductive layer is plated, which not only protects the copper surface from oxidation, but also provides a contact surface for subsequent bonding.

[0046] Step 9: The fourth negative photolithography patterning etching window is opened by inductively coupled plasma dry etching and etched to the surface of the sacrificial layer. Step 10: Selectively remove the Ge sacrificial layer by dry etching with xenon difluoride to trigger stress release of the dual-frequency silicon nitride strain layer and obtain a self-rolling inductor with two or more rolls. Step 11: Wafer-level components are fixed by attaching them to a blue film or a UV film; Step 12: The laser performs local deformation modification to obtain a modified layer composed of pores, a high dislocation density layer, and cracks; Step 13: Using the modified layer as the starting point for wafer dicing and cracking, use a cleaver to cleave the wafer into dicing slabs. Step 14: De-adhesion of the UV film to obtain a separable micron-scale self-rolling inductor; Step 15: Bake the silver paste to fix the chip; Step 16: Gold wire bonding or flip-chip bonding to interconnect the chip and the self-rolling inductor; Step 17: Surface mount packaging to achieve heterogeneous integration of the self-rolling inductor.

[0047] Step 1 also includes, Step 1.1: Soak in acetone and sonicate, then soak in isopropanol and sonicate, and finally rinse with deionized water and dry with nitrogen. Step 1.2, then proceed with dry treatment, using a plasma cleaner to clean for 5 minutes at 100 W power in an oxygen environment; Step 4 also includes, Step 4.1: Before the positive photolithography process, the wafer surface is pretreated using a special oven treated with HMDS (Hexamethyldisilazane). This involves turning on the vacuum pump to create a vacuum, and once the vacuum level reaches a certain high level, nitrogen gas is introduced. After reaching a certain low vacuum level, the process of vacuuming and nitrogen introduction is repeated. After the set number of nitrogen introductions is reached, the process is held for a period of time to allow the wafer to be fully heated and reduce surface moisture. Then, vacuuming and HMDS gas introduction are started again. After the set time is reached, HMDS introduction is stopped, and the wafer enters a holding phase to allow the wafer surface to fully react with HMDS. After the set holding time is reached, vacuuming and HMDS gas introduction are started again to complete the entire process. The reaction mechanism of HMDS with silicon wafers is as follows: First, heat to 100 ℃–200 ℃ to remove the moisture on the wafer surface. Then, HMDS reacts with the -OH groups on the surface to form silyl ether bonds on the wafer surface, eliminating hydrogen bonding and thus transforming the polar surface into a non-polar surface. Step 4.2: After HMDS pretreatment, positive photoresist is spin-coated; using a photolithography machine, the photoresist portion that needs to be retained is blocked, and the mesa pattern on the first set of photomasks is transferred to the surface of the upper stress layer. After exposure and development, a patterned positive photoresist layer is obtained on the stress layer; the positive photoresist layer includes spaced and uniformly distributed square photoresist blocks, i.e., stress-relieved mesa patterns; Step 4.3, Inductively Coupled Plasma Dry Etching: Using an ICP dry etching apparatus, the dual-frequency silicon nitride stress layer and germanium sacrificial layer not covered by the positive photoresist layer are etched away, and a shallow layer is etched downwards onto the substrate. Step 4.4, wet cleaning: remove the barrier layer of the remaining positive photoresist layer, retain the stress layer and germanium sacrificial layer below the positive photoresist layer, and obtain the patterned region module.

[0048] Step 6.1: Spin coat, expose, develop Spin-coating negative photoresist and pre-baking; using a photolithography machine, aligning and exposing the second set of photomasks; then post-baking, and finally development, to map the solid pattern in the second set of photomasks onto the stage. Step 6.2: On the wafer obtained in step 4.1, use a plasma cleaning device to clean it and remove any residual photoresist that has not been completely developed; use a high-vacuum electron beam evaporation device to deposit a stepped metal thin film layer in a vacuum environment. Step 6.3: Prepare a wafer with a metal step layer, and use acetone or resist remover to completely remove the first negative photoresist layer. The step metal layer on the first negative photoresist layer is then removed to obtain the metal step layer of the second mask.

[0049] Step 7.1, Second negative photolithography; Step 7.2, Perform plasma cleaning and electron beam deposition to deposit a copper metal layer; Step 7.3: The patterned metal film is obtained by wet peeling with acetone or a desizing liquid.

[0050] Step 8.1, the third negative photolithography, includes coating, pre-baking, exposure, post-baking and development; Step 8.2, plasma cleaning and electron beam deposition process to deposit a gold electrode layer; Step 8.3: The patterned gold film is obtained by wet peeling with acetone or a desizing liquid.

[0051] Step 9 includes: Step 9.1, the fourth negative photolithography, includes coating, pre-baking, exposure, post-baking and development; Step 9.2: Use plasma cleaning pretreatment, then use ICP dry etching to etch away the alumina orientation layer, dual-frequency silicon nitride stress layer and germanium sacrificial layer not covered by the negative photoresist layer, and shallowly etch to a certain depth towards the substrate. Step 9.3: On the wafer obtained in the previous step, wet etching of the photoresist barrier layer is performed using a resist remover to obtain a metal layer, an aluminum oxide orientation layer, a dual-frequency silicon nitride layer, and a germanium sacrificial layer protected by negative photoresist.

[0052] Step 11 includes: fixing the wafer, using a laser with a wavelength of 1064 nm to focus on the inside of the wafer through a transmission mirror to generate a local deformation layer, namely a modified layer. This layer is mainly composed of holes, a high dislocation density layer and cracks; this modified layer is the starting point for subsequent wafer dicing and cracking.

[0053] In step 1, when the substrate material is silicon, a silicon dioxide insulating layer needs to be grown on the silicon surface to achieve electrical isolation between layers; In step 2, the thickness of the germanium sacrificial layer is configured to be 30 nm to 150 nm; In step 3, the thickness of the low-frequency silicon nitride film is 20 nm to 50 nm; the thickness of the high-frequency silicon nitride film is 20 nm to 50 nm. In step 3, a low-frequency silicon nitride thin film, i.e., the lower stress layer, is first deposited on the germanium sacrificial layer using plasma-enhanced chemical vapor deposition, and then a high-frequency silicon nitride thin film, i.e., the upper stress layer, is deposited as the stretching layer.

[0054] In step 10, the germanium sacrificial layer is etched through the etching window using dry or wet etching, causing the upper and lower stress layers, i.e., the dual-frequency silicon nitride, to roll up towards the electrode end along with the planar inductor, thus obtaining an on-chip micro-nanotube-shaped self-rolling inductor; the inner diameter of the self-rolling inductor is 10~200 μm, and the number of rolls is two or more.

[0055] In step 16, gold wire bonding provides excellent electrical connection to ensure stable signal transmission; while flip-chip bonding achieves efficient thermal management and smaller package size through micro-bumps, improving overall performance and integration.

[0056] Example 1: A complete fabrication, performance tuning, and heterogeneous integration method for self-rolling inductors based on silicon substrates. This embodiment aims to provide a detailed description of a method for implementing a high-performance self-curling inductor that is fully compatible with standard integrated circuit processes.

[0057] Step 1: Substrate Pretreatment and Insulating Layer Growth First, a 2-inch high-resistivity silicon substrate is provided (sapphire and glass substrates can be used directly). The high-resistivity silicon substrate is chosen to minimize high-frequency signal loss within the substrate. Since the substrate material is silicon, a silicon dioxide (SiO2) insulating layer must first be grown on its surface to achieve electrical isolation. The silicon wafer is placed in a thermal oxidation furnace and treated in a dry oxygen environment at 1000°C for 120 minutes to grow a silicon dioxide layer with a thickness of approximately 500 nm. This insulating layer effectively prevents parasitic capacitive coupling between the self-curling inductor and the substrate during operation, thereby improving the device's self-resonant frequency and quality factor. See [link to relevant documentation]. Figure 1 .

[0058] Step 2: Deposition of back metal shielding layer and front germanium sacrificial layer After the substrate was prepared, double-sided metallization was performed. First, a 100 nm thick titanium (Ti) film was deposited on the back side of the substrate using an electron beam evaporation apparatus as an electromagnetic shielding layer to reduce interference from external noise to sensitive inductive components. Next, the wafer was flipped, and a germanium sacrificial layer was deposited on the silicon dioxide insulating layer on the front side using the same electron beam evaporation apparatus. The thickness of the germanium sacrificial layer was crucial and was optimized to 80 nm. During the deposition process, the vacuum level was maintained at 7 × 10⁻⁶. - Below 5 Pa, the deposition rate is controlled at 0.5. / s, to ensure good film density and surface smoothness, providing an ideal platform for subsequent stress layer deposition, see [link / s]. Figure 2 .

[0059] Step 3: Plasma-enhanced chemical vapor deposition (PECVD) of dual-frequency silicon nitride strained layer This step is crucial for forming the self-curling driving force. A dual-frequency silicon nitride strain layer is sequentially deposited on the germanium sacrificial layer using a PECVD system.

[0060] Low-frequency silicon nitride deposition: First, low-frequency silicon nitride is deposited as a compression layer. Process parameters are set as follows: substrate temperature 300℃, RF power low frequency (380kHz), and power density 0.3W / cm². 2 The reaction gases consist of 5% silane (SiH4, diluted with argon) and ammonia (NH3), with a SiH4 / NH3 flow rate ratio of 1:4 and a chamber pressure of 300 mTorr. Under these conditions, the deposited silicon nitride film exhibits a compressive stress of approximately -300 MPa, with a thickness precisely controlled at 30 nm. High-frequency silicon nitride deposition: Without breaking the vacuum, switching the RF power to a high frequency increases the power density to 0.8 W / cm². 2 The flow rate ratio of silane to ammonia was adjusted to 1:2, the chamber pressure was increased to 500 mTorr, and the deposition temperature was maintained at 300°C. Under these conditions, the deposited silicon nitride film exhibited a tensile stress of approximately +800 MPa, with the thickness also controlled at 30 nm. Thus, the stress stack composed of 30 nm compressive stress silicon nitride and 30 nm tensile stress silicon nitride had a net stress of approximately +500 MPa, providing a strong and controllable driving force for subsequent roll-up. See also Figure 3 .

[0061] Step 4: First photolithography and inductively coupled plasma (ICP) dry etching to define the mesa This step aims to divide a continuous thin film layer into independent unit regions.

[0062] HMDS Pretreatment and Positive Photoresist Spin Coating: The wafer was placed in a dedicated oven for HMDS (hexamethyldisilazane) vapor phase pretreatment. The process was as follows: First, the oven was evacuated to 2 Pa, then high-purity nitrogen was introduced to atmospheric pressure. This evacuation-nitrogen purging process was repeated three times to thoroughly remove moisture from the chamber. Then, the temperature was raised to 150°C and held for 10 minutes to further remove adsorbed water from the wafer surface. Afterward, the oven was evacuated again, and HMDS vapor was introduced. The temperature was maintained at 150°C for 5 minutes to allow the HMDS to fully react with the silanol groups on the wafer surface to form a hydrophobic silyl ether layer. After the pretreatment, positive photoresist was spin-coated at 5000 rpm on a spin coater and pre-baked on a 100°C hot plate for 90 seconds to form a photoresist layer with a thickness of approximately 1.4 μm. Exposure and Development: Using an i-line lithography machine, a first photomask (containing multiple 80μm x 80μm square mesa patterns) is used for contact exposure. After exposure, it is developed in a developer for 45 seconds to remove the photoresist in the exposed areas, thus clearly transferring the mesa patterns onto the photoresist layer. ICP Dry Etching: The wafer is placed in an ICP etching machine, and etching is performed using a BCl3 / Ar mixed gas. The process parameters are: ICP power 120W, bias power 120W, chamber pressure 2Pa, and BCl3 and Ar gas flow rates of 25sccm and 6sccm, respectively. The etching process continues until the unprotected alumina protective layer, dual-frequency silicon nitride layer, and germanium sacrificial layer are completely etched away, and approximately 20nm of the underlying silicon dioxide insulating layer is slightly etched in, thus forming an isolated mesa structure. Photoresist stripping and cleaning: Ultrasonic cleaning with acetone and isopropanol thoroughly removes residual photoresist, resulting in a clean, clearly patterned unit substrate. See also Figure 4 .

[0063] Step 5: Atomic Layer Deposition (ALD) of Alumina Protective Layer To protect the chemically sensitive silicon nitride stress layer during subsequent wet processes, a high-quality alumina (Al₂O₃) protective layer was grown on dual-frequency silicon nitride using atomic layer deposition (ALD). Trimethylaluminum (TMA) and water (H₂O) were used as precursors, and the deposition temperature was set to 250°C. Through 168 ALD cycles, an extremely dense alumina film with a thickness of approximately 20 nm and excellent conformability was grown. This protective layer effectively blocks potential erosion of the silicon nitride layer by subsequent resist strippers and electroplating solutions. See also... Figure 5 .

[0064] Steps 6 to 8: Multilayer metallization achieved by three negative photolithography and electron beam evaporation A stepped metal layer, main conductive layer, and electrode layer are sequentially constructed through three negative photolithography and lift-off processes. The second photolithography process forms the titanium stepped metal layer: negative photoresist is spin-coated onto the wafer surface and pre-baked. Exposure, post-baking, and development are performed using a second mask (patterned with connector pads and lead areas). Subsequently, the surface is lightly cleaned with oxygen plasma to remove development residue. Then, a 10 nm thick titanium (Ti) layer is deposited in a high-vacuum electron beam evaporation apparatus as an adhesion layer and simultaneously as the stepped metal layer. The titanium layer structure significantly improves the coverage of the subsequent copper main conductive layer at the steps, preventing wire breakage due to excessive step height. Finally, lift-off is performed in acetone to remove the photoresist and its overlying metal, forming the stepped metal pattern. The third photolithography process forms the copper conductive layer: negative photoresist is repeatedly coated, and exposure and development are performed using a third mask. Then, a 300 nm thick copper (Cu) film is deposited by electron beam evaporation, forming the main conductive path of the inductor. Copper is preferred due to its low resistivity and excellent electromigration properties. After lift-off, a clearly defined copper coil pattern is obtained. A fourth photolithography step is performed to form the gold electrode layer: negative photolithography is performed again, using a fourth mask for patterning. Subsequently, an electron beam evaporation deposition layer of 150 nm thick gold (Au) is formed. Gold possesses excellent oxidation resistance and contact properties, making it an ideal material for the top electrode. After lift-off, the gold electrode for subsequent gold wire bonding is formed. See also... Figure 6 .

[0065] Step Nine: Fourth Photolithography and ICP Etching - Defining the Etching Window A negative photoresist is spin-coated again onto the wafer surface, and exposure and development are performed using a fifth mask. Then, ICP dry etching is performed using a BCl3 / Cl2-based chemical gas to precisely etch away the gold electrode, copper conductive layer, aluminum oxide protective layer, and dual-frequency silicon nitride layer within the window area until the underlying germanium sacrificial layer is exposed, forming the etched window. See also Figure 7 .

[0066] Step 10: XeF2 dry etching releases the sacrificial layer and triggers self-curl. This is the most critical step in the entire process. The prepared wafer is placed in a specially designed XeF2 dry etching apparatus. XeF2 gas is an isotropic, highly selective etchant for silicon and germanium. At room temperature, XeF2 gas is introduced into the chamber, reacting with the exposed germanium sacrificial layer to generate volatile GeF4 gas, thereby selectively removing the sacrificial layer. As the sacrificial layer is hollowed out, the multilayer film composed of high-frequency SiNx, low-frequency SiNx, and Al2O3 metals is released due to its inherent stress mismatch, generating a huge bending moment that drives the entire structure to rotate and curl inward around a predetermined axis, starting from the etching window. After etching, the sacrificial layer is completely removed, and the two-dimensional planar structure is finally curled into a three-dimensional tubular micro / nano inductor structure. See also Figure 8 .

[0067] Steps 11 to 16: Laser-modified cutting and chip separation This stage facilitates the transition from wafer-level processing to chip-level products. First, the entire 2-inch wafer is temporarily bonded to a UV adhesive film. This film has appropriate adhesion, which decreases to near zero under certain UV irradiation. The bonding process is performed in a vacuum laminator at a pressure of 0.5 MPa and a temperature of 80°C, ensuring no air bubbles between the wafer and the film. Laser cutting utilizes an infrared picosecond laser (wavelength 1064 nm, pulse width 10 ps, ​​repetition frequency 100 kHz). The laser beam is focused onto the wafer through a focusing lens and scans along a pre-set cutting path. By precisely controlling the focal point, a modified layer consisting of micropores, high dislocation density regions, and microcracks is formed within the material, while the wafer surface remains intact. After laser scanning, the UV film with the wafer bonded is fixed to an expansion ring. The film is then mechanically stretched uniformly, causing the wafer to neatly split along the internal modified layer, separating into individual components. Finally, the entire device is placed in a UV irradiation chamber and irradiated for 30 seconds to remove the UV film's adhesiveness, allowing for easy picking up of individual micron-scale self-curling inductor components. This process achieves a yield of over 95%, producing clean, undamaged chip edges. See also... Figure 9 and Figure 10 .

[0068] Steps 17 to 19: Heterogeneous Integration Heterogeneous integration is key to the practical application of self-curling inductors. First, conductive silver is applied to designated locations using a high-precision dispensing machine. Then, the CMOS RF chip is picked up using a vacuum pen, precisely positioned under a microscope, and placed on the silver paste. It is then baked on a 150°C heating plate for 30 minutes to cure the silver paste, achieving mechanical fixation and electrical grounding of the CMOS RF chip. Interconnection employs gold wire bonding and flip-chip bonding technologies, using 25μm diameter high-purity gold wire. The bonding parameters are: first solder joint (inductor gold electrode) temperature 150°C, pressure 0.5N, time 20ms; second solder joint (CMOS chip pad) temperature 120°C, pressure 0.3N, time 15ms. After bonding, a standard fishtail-shaped solder joint is formed. Pull-stretch tests show a bonding strength greater than 0.2N, meeting reliability requirements. (See [link to relevant documentation]). Figure 11 .

[0069] Flip-chip bonding uses a wire bonding machine. First, gold wire is melted into a gold ball at the pads of the self-curling inductor. Then, a flip-chip nozzle is used to hold the back of the self-curling inductor and precisely position it onto the chip pads for flip-chip interconnection. Finally, a final cleaning and curing process is performed on a heated stage. Integration complete. See [link to documentation]. Figure 12 .

[0070] In summary, this invention provides an integration method for self-curling passive components. The wafer-level front-end process for the self-curling component begins with the deposition of metal thin films on both the front and back of the substrate; then, a dual-frequency silicon nitride strain layer is deposited via plasma chemical vapor deposition; a first positive photolithography and inductively coupled plasma dry etching are used to pattern the mesa; a metal step layer, a copper metal layer, a gold electrode layer, and an etching window layer are deposited through four negative photolithography steps; an orientation protective layer is deposited using atomic force deposition; finally, a xenon difluoride dry etching is used to etch the sacrificial layer, releasing the film stress caused by the dual-frequency silicon nitride strain layer and triggering curling to obtain a self-curling inductor. A modified layer consisting of holes, a high dislocation density layer, and cracks is generated inside the wafer using a specific wavelength laser; the wafer is then cleaved starting from the modified layer; finally, UV desolventizing is used to obtain separable micron-scale independent inductors. This invention not only completely solves the inherent contradiction between performance and size in traditional planar inductors, but also overcomes many problems in process compatibility, performance controllability and mechanical reliability of existing three-dimensional inductor technologies. It provides a practical and feasible technical path to high-performance, miniaturized and highly integrated RF microsystems with prospects for large-scale industrialization, and has significant technical, economic and strategic value.

Claims

1. A method for integrating self-curling passive components, characterized in that, The method includes: Step 1: Dry and wet methods are combined to pre-treat the dielectric substrate, wherein the substrate includes sapphire and glass; Step 2: A titanium shielding layer is formed on the back side of the substrate and a germanium sacrificial layer is deposited on the front side using electron beam deposition technology; Step 3: Deposit dual-frequency silicon nitride strained layers sequentially using plasma-enhanced chemical vapor deposition; The dual-frequency silicon nitride strain layer comprises a low-frequency silicon nitride thin film and a high-frequency silicon nitride thin film; Step 4: Pattern the mesa using positive photolithography and define the stress platform using inductively coupled plasma dry etching; the etching depth needs to be shallow enough to reach the substrate surface. Step 5: Deposit a directional protective layer using atomic layer deposition (ALD). Step 6: The first negative photolithography patterning of the step pattern is formed by electron beam deposition to form a metal step layer, mainly made of titanium. Step 7: The metal layer pattern is patterned by negative photolithography in the second step, and copper metal is deposited by electron beam to form a conductive layer. The main materials are titanium and copper. Step 8: The electrode layer pattern is patterned by negative photolithography for the third time, and the gold electrode layer is deposited by electron beam deposition. The main materials are titanium and gold. Step 9: The fourth negative photolithography patterning etching window is opened by inductively coupled plasma dry etching and etched to the surface of the sacrificial layer. Step 10: Selectively remove the Ge sacrificial layer by dry etching with xenon difluoride to trigger stress release of the dual-frequency silicon nitride strain layer and obtain a self-rolling inductor with two or more rolls. Step 11: Wafer-level components are fixed by attaching them to a blue film or a UV film; Step 12: The laser performs local deformation modification to obtain a modified layer composed of pores, a high dislocation density layer, and cracks; Step 13: Using the modified layer as the starting point for wafer dicing and cracking, use a cleaver to cleave the wafer into dicing slabs. Step 14: De-adhesion of the UV film to obtain a separable micron-scale self-rolling inductor; Step 15: Bake the silver paste to fix the chip; Step 16: Gold wire bonding or flip-chip bonding to interconnect the chip and the self-rolling inductor; Step 17: Surface mount packaging to achieve heterogeneous integration of the self-rolling inductor.

2. The integration method for a self-curling passive component according to claim 1, characterized in that, Step 1 also includes, Step 1.1: Soak in acetone and sonicate, then soak in isopropanol and sonicate, and finally rinse with deionized water and dry with nitrogen. Step 1.2, then proceed with dry treatment, using a plasma cleaner to clean for 5 minutes at 100 W power in an oxygen environment; Step 4 also includes, Step 4.1: Before the positive photolithography process, the wafer surface is pretreated using a special oven treated with HMDS (Hexamethyldisilazane). This involves turning on the vacuum pump to create a vacuum, and once the vacuum level reaches a certain high level, nitrogen gas is introduced. After reaching a certain low vacuum level, the process of vacuuming and nitrogen introduction is repeated. After the set number of nitrogen introductions is reached, the process is held for a period of time to allow the wafer to be fully heated and reduce surface moisture. Then, vacuuming and HMDS gas introduction are started again. After the set time is reached, HMDS introduction is stopped, and the wafer enters a holding phase to allow the wafer surface to fully react with HMDS. After the set holding time is reached, vacuuming and HMDS gas introduction are started again to complete the entire process. The reaction mechanism of HMDS with silicon wafers is as follows: First, heat to 100 ℃–200 ℃ to remove the moisture on the wafer surface. Then, HMDS reacts with the -OH groups on the surface to form silyl ether bonds on the wafer surface, eliminating hydrogen bonding and thus transforming the polar surface into a non-polar surface. Step 4.2: After HMDS pretreatment, positive photoresist is spin-coated. Using a photolithography machine, the photoresist portion that needs to be retained is blocked, and the mesa pattern on the first set of photomasks is transferred to the surface of the upper stress layer. After exposure and development, a patterned positive photoresist layer is obtained on the stress layer. The positive photoresist layer includes spaced and uniformly distributed square photoresist blocks, i.e., stress-relieved mesa patterns. Step 4.3, Inductively Coupled Plasma Dry Etching: Using an ICP dry etching apparatus, the dual-frequency silicon nitride stress layer and germanium sacrificial layer not covered by the positive photoresist layer are etched away, and a shallow layer is etched downwards onto the substrate. Step 4.4, wet cleaning: remove the barrier layer of the remaining positive photoresist layer, retain the stress layer and germanium sacrificial layer below the positive photoresist layer, and obtain the patterned region module.

3. The integration method for a self-curling passive component according to claim 1, characterized in that: Step 6.1: Spin coat, expose, develop Spin-coat negative photoresist and perform pre-baking treatment; Using a lithography machine, the second set of photomasks is used for overlay alignment and exposure; then post-baking is performed, and finally development is carried out to map the solid pattern in the second set of photomasks onto the stage. Step 6.2: On the wafer obtained in step 4.1, use a plasma cleaning device to clean it and remove any residual photoresist that has not been completely developed; use a high-vacuum electron beam evaporation device to deposit a stepped metal thin film layer in a vacuum environment. Step 6.3: Prepare a wafer with a metal step layer, and use acetone or resist remover to completely remove the first negative photoresist layer. The step metal layer on the first negative photoresist layer is then removed to obtain the metal step layer of the second mask.

4. The integration method of a self-curling passive component according to claim 1, characterized in that: Step 7.1, Second negative photolithography; Step 7.2, Perform plasma cleaning and electron beam deposition to deposit a copper metal layer; Step 7.3: The patterned metal film is obtained by wet peeling with acetone or a desizing liquid.

5. The integration method of a self-curling passive component according to claim 1, characterized in that: Step 8.1, the third negative photolithography, includes coating, pre-baking, exposure, post-baking and development; Step 8.2, plasma cleaning and electron beam deposition process to deposit a gold electrode layer; Step 8.3: The patterned gold film is obtained by wet peeling with acetone or a desizing liquid.

6. The integration method for a self-curling passive component according to claim 1, characterized in that, Step 9 includes: Step 9.1, the fourth negative photolithography, includes coating, pre-baking, exposure, post-baking and development; Step 9.2: Use plasma cleaning pretreatment, then use ICP dry etching to etch away the alumina orientation layer, dual-frequency silicon nitride stress layer and germanium sacrificial layer not covered by the negative photoresist layer, and shallowly etch to a certain depth towards the substrate. Step 9.3: On the wafer obtained in the previous step, wet etching of the photoresist barrier layer is performed using a resist remover to obtain a metal layer, an aluminum oxide orientation layer, a dual-frequency silicon nitride layer, and a germanium sacrificial layer protected by negative photoresist.

7. The integration method for a self-curling passive component according to claim 1, characterized in that, Step 11 includes: fixing the wafer, using a laser with a wavelength of 1064 nm to focus on the inside of the wafer through a transmission mirror to generate a local deformation layer, namely a modified layer. This layer is mainly composed of holes, a high dislocation density layer and cracks; this modified layer is the starting point for subsequent wafer dicing and cracking.

8. The integration method of a self-curling passive component according to claim 1, characterized in that: In step 1, when the substrate material is silicon, a silicon dioxide insulating layer needs to be grown on the silicon surface to achieve electrical isolation between layers; In step 2, the thickness of the germanium sacrificial layer is configured to be 30 nm to 150 nm; In step 3, the thickness of the low-frequency silicon nitride film is 20 nm to 50 nm; the thickness of the high-frequency silicon nitride film is 20 nm to 50 nm. In step 3, a low-frequency silicon nitride thin film, i.e., the lower stress layer, is first deposited on the germanium sacrificial layer using plasma-enhanced chemical vapor deposition, and then a high-frequency silicon nitride thin film, i.e., the upper stress layer, is deposited as the stretching layer.

9. The integration method of a self-curling passive component according to claim 1, characterized in that: In step 10, the germanium sacrificial layer is etched through the etching window using dry or wet etching, causing the upper and lower stress layers, i.e., the dual-frequency silicon nitride, to roll up towards the electrode end along with the planar inductor, thus obtaining an on-chip micro-nanotube-shaped self-rolling inductor; the inner diameter of the self-rolling inductor is 10~200 μm, and the number of rolls is two or more.

10. The integration method of a self-curling passive component according to claim 1, characterized in that: In step 16, gold wire bonding provides excellent electrical connection to ensure stable signal transmission; while flip-chip bonding achieves efficient thermal management and smaller package size through micro-bumps, improving overall performance and integration.

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