A new type of MOS tube circuit, chip and method for resisting RF interference of TFT_LCD display chip

Abstract

This invention provides a novel MOS transistor circuit for RF interference suppression in TFT-LCD display chips, comprising a MOS transistor. The key feature is that an injection layer is disposed in the DPW layer of the MOS transistor, the injection layer being connected to IOVCC, and the DNW layer of the MOS transistor being left floating. The injection layer, DNW layer, and DPW layer form a newly added parasitic NPN transistor, wherein the DPW layer is connected to VSS. A TFT-LCD display chip and a corresponding control method are also provided. When the chip is subjected to RF signal interference, this technology can effectively reduce the conduction of parasitic transistors inside the chip and the injection of charge into the substrate without increasing chip area or production costs. Furthermore, it is applicable to different manufacturing processes.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, particularly semiconductor chip technology, and is especially applied to TFT-LCD display chips and other related technologies. Specifically, it relates to a novel MOS transistor circuit for RF interference suppression in TFT-LCD display chips, as well as the corresponding display chip and control method. Background Technology

[0002] RF interference refers to signal distortion caused by electromagnetic radiation in electronic devices or communication systems. I / O circuits used in TFT-LCD displays may experience screen flickering under RF interference, affecting display quality. The main reason for this flickering is that electromagnetic waves are converted into instantaneous current through the antenna. This instantaneous current generates momentary positive and negative voltage changes through the parasitic resistance of the I / O interface. This voltage change causes the parasitic transistor inside the MOSFET to conduct, injecting charge into the substrate of the entire display chip, resulting in abnormal voltages and thus affecting the display.

[0003] Current solutions primarily focus on reducing this issue through circuit design or optimized layout. Common solutions include: 1. Optimizing layout: Properly arranging circuits susceptible to RF signal interference, reducing signal transmission path length, and minimizing mutual interference; 2. Adding filtering circuits: Including adding filtering circuits at input ports to filter out higher harmonics and minimize RF interference; 3. Optimizing power and ground lines: Good ground and power line layout helps reduce interference caused by ground return current; 4. Signal shielding: Strengthening the shielding design of circuits susceptible to RF interference to reduce external interference.

[0004] The RF interference suppression techniques described above all require increased circuit area, leading to higher production costs. Through... Figures 1 to 3 To more clearly describe the technical problems encountered in the existing technology: Figure 1This is a cross-sectional view of a 110nm process device, with the potentials connected to each port matching the actual situation. Taking a PMOS transistor as an example, the third PNP transistor Q3 is a parasitic PNP transistor composed of P+ (Vout is subject to RF interference), MVNW (IOVCC), and DPW (VSS). Under normal operation, the third PNP transistor Q3 is in the cutoff region. However, when there is positive RF interference at P+ (Vout), Vout will couple a transient positive voltage pulse ∆V. When ∆V - IOVCC > Vbe (pnp), the third PNP transistor Q3 enters the amplification region from the cutoff region. At this time, Vout injects charge into DPW (VSS) through the third PNP transistor Q3, causing the DPW (VSS) voltage to rise. Meanwhile, DPW(VSS), DNW(IOVCC), and Psub(VGL) constitute another parasitic PNP transistor, namely the fourth PNP transistor Q4. Under normal circumstances, this fourth PNP transistor is also in the cutoff region. However, as DPW(VSS) rises to IOVCC+Vbe(pnp), this parasitic PNP transistor, namely the fourth PNP transistor Q4, moves from the cutoff region into the amplification region. The raised local DPW(VSS) injects charge into the substrate Psub(VGL) through the fourth PNP transistor Q4. Since VGL is built into the chip, its driving force is generally only tens to hundreds of microamps, and the voltage regulator capacitor is very small. For a current in the milliamp range, the VGL voltage will be pulled up rapidly, which will lead to abnormal display.

[0005] The above Figure 1 The corresponding parasitic PNP transistors are shown in the diagrams below. Figure 2 , Figure 3 As shown, where Figure 2 A schematic diagram of the equivalent circuit of a parasitic transistor on a PMOS substrate is shown. Figure 3 A schematic diagram of the equivalent circuit of a parasitic transistor on an NMOS substrate is shown.

[0006] Specifically, with Figure 2Taking the NMOS transistor shown as an example, the first NPN transistor Q1 is a parasitic NPN transistor composed of N+ (Vout is subject to RF interference), MVPW (VSS), and DNW (IOVCC). Under normal operation, the first NPN transistor Q1 is in the cutoff region. However, when there is negative RF interference at N+ (Vout), Vout will couple a transient negative voltage pulse ∆V. When VSS - ∆V > Vbe (npn), the first NPN transistor Q1 enters the amplification region from the cutoff region. At this time, N+ (Vout) draws charge from DNW (IOVCC) through Q1, causing the potential of DNW (IOVCC) to drop from IOVCC. At the same time, MVPW (VSS), DNW (IOVCC), and Psub (VGL) constitute another parasitic PNP transistor, namely the second PNP transistor Q2. Under normal circumstances, the parasitic PNP transistor, namely the second PNP transistor Q2, is also in the cutoff region. However, as the DNW (IOVCC) voltage drops below Vbe (pnp), the PNP transistor moves from the cutoff region into the amplification region. The pulled-down IOVCC injects charge into Psub (VGL) through the second PNP transistor Q2, causing an abnormal VGL voltage, which in turn affects the display.

[0007] Due to the existence of the above-mentioned technical problems, a solution is needed to solve the existing technical problems, namely, to provide a new type of MOS transistor circuit for TFT-LCD display chips to resist RF interference and a corresponding control method. Summary of the Invention

[0008] To address the technical deficiencies of existing technologies, the present invention aims to provide a novel MOS transistor circuit for TFT-LCD display chips to resist RF interference, comprising a MOS transistor, characterized in that an injection layer is provided in the DPW of the MOS transistor, the injection layer is connected to IOVCC, and the DNW of the MOS transistor is left floating, the injection layer, DNW layer, and DPW layer form a newly added parasitic NPN transistor, wherein the DPW layer is connected to VSS.

[0009] Preferably, the MOS transistor is an NMOS transistor, and the NMOS transistor includes at least a first NPN transistor Q1 and a second PNP transistor Q2, and the newly added parasitic NPN transistor Q5 is connected to the first NPN transistor Q1 and the second PNP transistor Q2.

[0010] Preferably, the MOS transistor is a PMOS transistor, and the PMOS transistor includes at least a third PNP transistor Q3 and a fourth PNP transistor Q4, and the newly added parasitic NPN transistor Q6 is connected to the third PNP transistor Q3 and the fourth PNP transistor Q4.

[0011] Preferably, the implanted layer is composed of +5 valent phosphorus ions.

[0012] Preferably, the injection layer material is the same material as the DNW layer of the MOS transistor.

[0013] According to another aspect of the present invention, a TFT-LCD display chip is provided for RF interference suppression, characterized in that it includes the novel MOS transistor circuit for RF interference suppression described above.

[0014] According to another aspect of the present invention, a control method for the novel MOS transistor circuit and / or the TFT-LCD display chip described above, is provided, characterized by comprising the following steps: a. When the output voltage Vout of the novel MOS transistor circuit is subjected to negative RF interference, the first NPN transistor Q1 enters the amplification region from the cutoff region and injects charge into the floating DNW layer, thereby pulling down the node voltage of the DNW layer; b. When the node voltage of the DNW layer is pulled down to below -Vbe, the fifth NPN transistor of the newly added parasitic NPN transistor is turned on. IOVCC injects charge into the floating DNW layer through the newly added parasitic NPN transistor, thereby suppressing the drop in the voltage of the DNW layer and the turn-on of the second PNP transistor Q2, thus avoiding abnormal VGL voltage.

[0015] Preferably, the above control method further includes the following steps: c. When the output voltage Vout of the novel MOS transistor circuit is subjected to positive RF interference, the third PNP transistor Q3 enters the amplification region from the cutoff region and injects charge into the DPW layer, causing the corresponding voltage of the DPW to rise; d. As the DPW layer gradually rises, the newly added parasitic NPN transistor moves from the cutoff region to the amplification region and eventually to the saturation region. IOVCC injects charge into the floating DNW layer through the newly added parasitic PNP transistor Q6, raising the potential of the DNW layer and suppressing the conduction of the fourth PNP transistor Q4, thereby avoiding abnormal VGL voltage.

[0016] The control circuit and TFT-LCD display chip provided by this invention can effectively reduce the conduction of parasitic transistors inside the chip and the injection of charge into the substrate when the chip is subjected to RF signal interference, without increasing chip area or production costs. Furthermore, it is applicable to various processes. This technical solution is efficient, has low implementation cost, is easy to apply, and can be easily and effectively promoted compared to existing technologies. Attached Figure Description

[0017] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A cross-sectional schematic diagram of an NMOS transistor and a PMOS transistor in the prior art is shown; Figure 2 The corresponding Figure 1 A schematic diagram of the equivalent circuit of a parasitic transistor on a PMOS substrate in the prior art; Figure 3 The corresponding Figure 1 A schematic diagram of the equivalent circuit of a parasitic transistor on an NMOS substrate in the prior art; Figure 4 A schematic diagram of a novel MOS transistor circuit structure for RF interference suppression applied to a TFT-LCD display chip according to a first embodiment of the present invention is shown. Figure 5 An application according to the first embodiment of the present invention is shown. Figure 4 The circuit structure diagram of the equivalent circuit of the PMOS substrate parasitic transistor in the novel MOS transistor circuit shown; and Figure 6 The application according to the first embodiment of the present invention is shown. Figure 4 The circuit structure diagram of the equivalent circuit of the NMOS substrate parasitic transistor of the novel MOS transistor circuit is shown. Detailed Implementation

[0018] To better illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings.

[0019] refer to Figures 4 to 6 The embodiments shown are as understood by those skilled in the art. Figure 4 This is a cross-sectional view of the improved 110nm process device. The potentials connected to each port are consistent with the actual process conditions.

[0020] Those skilled in the art will understand that the preferred embodiment improved by the technical solution provided by the present invention is as follows: an N+ injection layer is added to the DPW of the PMOS and NMOS transistors and connected to 10VCC, while the original DNW layer connected to 10VCC is left floating. The mechanism for suppressing charge injection into the substrate is as follows: Figure 4 As shown.

[0021] refer to Figure 5 As will be understood by those skilled in the art in the illustrated embodiment, taking a PMOS transistor as an example, the addition of an N+ layer (IOVCC), DNW (floating), and DPW (VSS) constitutes a new parasitic NPN transistor, i.e. Figure 5The designation Q6 represents the new parasitic NPN transistor Q6. Specifically, the newly added N+ layer (IOVCC) serves as the collector of the new parasitic NPN transistor Q6; DNW (floating) serves as the emitter of the new parasitic NPN transistor Q6 and is connected to the base of the fourth PNP transistor Q4; and DPW (VSS) serves as the base of the new NPN transistor Q6 and is connected to the collector of the third PNP transistor Q3 and the emitter of the fourth PNP transistor Q4.

[0022] When P+(Vout) is subjected to positive RF interference, the third PNP transistor Q3 enters the amplification region from the cutoff region and injects charge into DPW(VSS), causing the DPW(VSS) voltage to rise. As DPW(VSS) gradually increases from 0V, the newly added parasitic NPN transistor Q6 enters the amplification region from the cutoff region and eventually enters the saturation region. At this time, IOVCC injects charge into the DNW (floating) layer through the newly added parasitic NPN transistor Q6, raising the DNW (floating) potential. Since the main charge carrier of NPN transistors is electrons, they have stronger conduction capability than PNP transistors. As the DNW (floating) potential rises, it suppresses the conduction of the fourth PNP transistor Q4, thereby preventing DPW(VSS) from injecting charge into Psub(VGL) through the fourth PNP transistor Q4. The improved parasitic transistor structure is as follows. Figure 5 : refer to Figure 5 As will be understood by those skilled in the art in the illustrated embodiment, taking an NMOS transistor as an example, the addition of an N+ layer (IOVCC), DPW (VSS), and DNW (floating) constitutes a new parasitic NPN transistor, in order to interact with... Figure 5 The contents shown are distinguished by the label Q5. Specifically, the newly added N+ layer (IOVCC) serves as the collector of the newly added parasitic NPN transistor Q5; DPW (VSS) serves as the base of the newly added parasitic NPN transistor Q5 and is connected to the base of the first NPN transistor Q1 and the emitter of the second PNP transistor Q2; DNW (floating) serves as the emitter of the newly added parasitic NPN transistor Q5 and is connected to the base of the second PNP transistor Q2 and the collector of the first NPN transistor Q1.

[0023] When P+(Vout) is subjected to negative RF interference, the first NPN transistor Q1 enters the amplification region from the cutoff region and injects charge into DNW (floating), pulling the DNW (floating) node voltage down. When pulled down below -Vbe(npn), the newly added parasitic NPN transistor Q5 turns on, and IOVCC injects charge into DNW (floating) through the newly added parasitic NPN transistor Q5, thereby suppressing the drop in DNW (floating) voltage and the conduction of the second PNP transistor Q2. That is, it suppresses DPW (VSS) from injecting charge into Psub (VGL) through the second PNP transistor Q2, avoiding abnormal VGL voltage and thus affecting the display.

[0024] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A novel MOSFET circuit for RF interference suppression in a TFT-LCD display chip, comprising a MOSFET, characterized in that, An injection layer is provided in the DPW of the MOS transistor, the injection layer is connected to IOVCC, and the DNW of the MOS transistor is left floating. The injection layer, DNW layer and DPW layer form a new parasitic NPN transistor, wherein the DPW layer is connected to VSS.

2. The novel MOSFET circuit for RF interference suppression according to claim 1, characterized in that, The MOS transistor is an NMOS transistor, which includes at least a first NPN transistor (Q1) and a second PNP transistor (Q2). The newly added parasitic NPN transistor is connected to the first NPN transistor (Q1) and the second PNP transistor (Q2).

3. The novel MOSFET circuit for resisting RF interference according to claim 1, characterized in that, The MOS transistor is a PMOS transistor, which includes at least a third PNP transistor (Q3) and a fourth PNP transistor (Q4). The newly added parasitic NPN transistor is connected to the third PNP transistor (Q3) and the fourth PNP transistor (Q4).

4. The novel MOSFET circuit for RF interference suppression according to any one of claims 1 to 3, characterized in that, The implanted layer is composed of +5 valent phosphorus ions.

5. The novel MOSFET circuit for resisting RF interference according to claim 4, characterized in that, The injection layer material is the same as the DNW layer of the MOS transistor.

6. A TFT-LCD display chip for RF interference suppression, characterized in that, Includes the novel MOSFET circuit for RF interference suppression according to any one of claims 1 to 5.

7. A control method for a novel RF interference-resistant MOS transistor circuit according to any one of claims 1 to 5, characterized in that, Includes the following steps: a. When the output voltage Vout of the novel MOS transistor circuit is subjected to negative RF interference, the first NPN transistor (Q1) enters the amplification region from the cutoff region and injects charge into the floating DNW layer, thereby pulling down the node voltage of the DNW layer; b. When the node voltage of the DNW layer is pulled down to below -Vbe, the fifth NPN of the newly added parasitic NPN transistor is turned on. IOVCC injects charge into the floating DNW layer through the newly added parasitic NPN transistor, thereby suppressing the drop in the voltage of the DNW layer and the turn-on of the second PNP transistor (Q2), thus avoiding abnormal VGL voltage.

8. The control method according to claim 7, characterized in that, It also includes the following steps: i. When the output voltage Vout of the novel MOS transistor circuit is subjected to positive RF interference, the third PNP transistor (Q3) enters the amplification region from the cutoff region and injects charge into the DPW layer, causing the corresponding voltage of the DPW to rise; ii. As the DPW layer gradually rises, the newly added parasitic NPN transistor moves from the cutoff region to the amplification region and eventually to the saturation region. IOVCC injects charge into the floating DNW layer through the newly added parasitic PNP transistor, raising the potential of the DNW layer and suppressing the conduction of the fourth PNP transistor (Q4), thereby avoiding abnormal VGL voltage.

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