Display device

Abstract

This disclosure provides a display device including a plurality of light-emitting elements disposed on a substrate, and capable of preventing or reducing optical sensor failures by including the following structure, wherein at least one of the plurality of light-emitting elements includes a first electrode disposed on the substrate, a hole transport layer disposed on the first electrode, an electron blocking layer disposed on the hole transport layer, an emitting layer disposed on the electron blocking layer and having a width greater than that of the electron blocking layer, and a second electrode disposed on the emitting layer.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0195693, filed on December 24, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0002] This disclosure relates to electronic devices, and more specifically to display devices. Background Technology

[0003] With advancements in display technology, display devices have been developed to provide additional functionalities, such as image capture, sensing, and image display. To provide these functions, display devices are equipped with optoelectronic devices, such as cameras, sensors for detecting images, sensors for detecting light, and light receiving devices.

[0004] To effectively receive light passing through the front surface of a display device, it may be desirable for such optoelectronic devices to be located in an area of ​​the display device where they can receive and detect more of the incident light passing through the front surface. Considering this, a typical display device employs a structure in which the optoelectronic devices are located at the front of the display device to allow them to be effectively exposed to incident light. To mount such optoelectronic devices, such as cameras or sensors, in a display device with this structure, the bezel of the display device may be increased, or it may be necessary to form notches or holes in the display area of ​​the display panel to accommodate the optoelectronic devices.

[0005] According to this configuration, since optical electronic devices (such as cameras, sensors, etc.) used to receive or detect light incident through the front surface and perform the intended function are included in the display device, the size of the front bezel of the display device may be increased, or substantial limitations may be imposed on the design of the front of the display device. Summary of the Invention

[0006] To address these issues, one or more aspects of this disclosure may provide a display device including a light-transmitting structure that enables at least one optical electronic device disposed below or at the bottom of a display panel to normally receive light (e.g., visible light, infrared light, ultraviolet light, etc.) without being exposed in front of the display device.

[0007] One or more aspects of this disclosure may provide a display device including at least one optoelectronic device configured to overlap with and be located below the display area of ​​a display panel, and capable of achieving full-screen display by using all display areas as a display screen.

[0008] One or more aspects of this disclosure may provide a display device including a structure forming a hole movement path in a light-emitting element, and capable of preventing or reducing the presence of residual light.

[0009] One or more aspects of this disclosure may provide a display device including a structure forming a hole movement path in a light-emitting element, and capable of preventing or reducing failure of one or more optical sensors.

[0010] One or more aspects of this disclosure may provide a display device including a structure forming a hole movement path in a light-emitting element, and capable of improving the sensing efficiency of one or more optical sensors by means of external light.

[0011] One or more aspects of this disclosure may provide a display device that can improve the reliability of light-emitting elements by reducing brightness degradation and shortening the lifespan of light-emitting elements in the display area.

[0012] The aspects, examples, and embodiments provided in this disclosure are not limited to the foregoing description, and additional aspects, examples, and embodiments provided in this disclosure will become apparent to those skilled in the art from the following description.

[0013] According to one or more example embodiments of this disclosure, a display device may be provided, comprising a plurality of light-emitting elements disposed on a substrate. In one or more aspects, at least one of the plurality of light-emitting elements may include a first electrode disposed on the substrate, a hole transport layer disposed on the first electrode, an electron blocking layer disposed on the hole transport layer, an emitting layer disposed on the electron blocking layer and having a width greater than that of the electron blocking layer, and a second electrode disposed on the emitting layer.

[0014] According to one or more aspects of this disclosure, a display device may be provided, the display device including a light-transmitting structure that enables at least one optical electronic device disposed below or at the bottom of a display panel to normally receive light (e.g., visible light, infrared light, ultraviolet light, etc.) without being exposed in front of the display device.

[0015] According to one or more aspects of this disclosure, a display device may be provided that can achieve full-screen display by using the entire display area of ​​a display panel as a display screen through a structure including at least one optical electronic device configured to overlap with and be located below the display area.

[0016] According to one or more aspects of this disclosure, a display device may be provided that is capable of preventing or reducing the presence of residual light by including a structure that forms a hole movement path in the light-emitting element.

[0017] According to one or more aspects of this disclosure, a display device may be provided that is capable of preventing or reducing failure of one or more optical sensors by including a structure that forms a hole movement path in a light-emitting element.

[0018] According to one or more aspects of this disclosure, a display device may be provided that can improve the sensing efficiency of one or more optical sensors for external light by including a structure that forms a hole movement path in a light-emitting element.

[0019] According to one or more aspects of this disclosure, a display device may be provided that can improve the reliability of the light-emitting element by reducing brightness degradation and shortening the lifespan of the light-emitting element in the display area.

[0020] According to one or more aspects of this disclosure, a display device may be provided that can achieve high efficiency, increased lifespan, and low power consumption by reducing brightness degradation in the display area and shortening the lifespan of the light-emitting elements.

[0021] The effects or advantages derived from the aspects, examples and embodiments described herein are not limited thereto, and additional effects or advantages will become apparent to those skilled in the art from the following description. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated into and constitute a part of this disclosure, illustrate various aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure. Therefore, it should be understood that the aspects, examples, and embodiments described herein are not limited to the illustrations in the drawings. In the drawings:

[0023] Figure 1 An example configuration of a display device according to various aspects of this disclosure is shown;

[0024] Figure 2 An example system configuration of a display device according to various aspects of this disclosure is shown;

[0025] Figure 3 An example configuration of a display panel is shown according to various aspects of this disclosure;

[0026] Figure 4 An example configuration of three regions, including a display area of ​​a display device, is shown according to various aspects of this disclosure;

[0027] Figure 5 An example cross-sectional view is shown of an optical region defined in a display panel according to various aspects of this disclosure;

[0028] Figure 6 An example cross-sectional view of a common light-emitting element is shown;

[0029] Figure 7 These are example cross-sectional views and band diagrams of a common light-emitting element;

[0030] Figure 8 It was applied Figure 7 An example cross-sectional view of a conventional display device with light-emitting elements shown;

[0031] Figure 9 These are example cross-sectional views and band diagrams of light-emitting elements based on various aspects of this disclosure;

[0032] Figure 10 It was applied Figure 9 An example cross-sectional view of a display device with the light-emitting element shown;

[0033] Figure 11 This is an example cross-sectional view used to compare a light-emitting element according to various aspects of this disclosure with a conventional light-emitting element;

[0034] Figure 12 These are example cross-sectional views and band diagrams of light-emitting elements based on various aspects of this disclosure;

[0035] Figure 13 It was applied Figure 12 An example cross-sectional view of a display device with the light-emitting element shown;

[0036] Figure 14 These are example cross-sectional views and band diagrams of light-emitting elements based on various aspects of this disclosure;

[0037] Figure 15 It was applied Figure 14 An example cross-sectional view of a display device with the light-emitting element shown;

[0038] Figure 16 This is an example cross-sectional view used to compare a light-emitting element according to various aspects of this disclosure with a conventional light-emitting element;

[0039] Figure 17 It was applied Figure 14 Another example cross-sectional view of the display device with the light-emitting element shown; and

[0040] Figure 18 and Figure 19It is a graph showing example characteristics of brightness and off in a display device and a general display device according to various aspects of this disclosure. Detailed Implementation

[0041] Reference will now be made in detail to exemplary embodiments of this disclosure, examples or aspects of which may be illustrated in the accompanying drawings. In the following description, the structures, implementations, methods, and operations described herein are not limited to the specific examples, aspects, and embodiments set forth herein, and may be varied as is known in the art, unless otherwise stated. Unless otherwise stated, the same reference numerals always denote the same elements. The names of the corresponding elements used in the following explanation are chosen solely for ease of writing and may therefore differ from those used in actual products. The advantages and features of this disclosure and methods of implementation thereof will be elucidated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and complete enough to assist those skilled in the art in fully understanding the scope of this disclosure. Furthermore, the scope of protection of this disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of relevant known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of this disclosure. The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the accompanying drawings. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0042] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0043] When referring to the first element as "connected or coupled to" the second element, "contacting" the second element, or "overlapping" with the second element, it should be interpreted as meaning that not only is the first element "directly connected or coupled to" the second element, "directly contacting" the second element, or "directly overlapping" with the second element, but a third element may also be "inserted" between the first and second elements, or the first and second elements may be "connected or coupled," "contacting," or "overlapping" with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled," "contacting," or "overlapping" with each other.

[0044] When describing positional relationships, such as when using terms like "on," "above," "over," "above," "below," "next to," or "adjacent" to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when an element or layer is positioned "on" another element or layer, a third element or layer may be inserted between them. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "upper," "lower," etc., refer to any frame of reference.

[0045] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical or corresponding information of an element or feature (e.g., level, range, etc.) includes tolerances or error ranges that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even when no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "may".

[0046] In the following description, various exemplary aspects of this disclosure are described in detail with reference to the accompanying drawings. Reference numerals for elements in each drawing may indicate the same element in other drawings, and unless otherwise stated, the same reference numerals may refer to the same element. Identical or similar elements may be represented by the same reference numerals, even if they are depicted in different drawings. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from the actual scale, dimensions, size, and thickness, and therefore, aspects of this disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0047] Figure 1 An example configuration of a display device 100 according to various aspects of this disclosure is shown.

[0048] refer to Figure 1In one or more example embodiments, the display device 100 may include a display panel 110 for displaying images, and one or more optoelectronic devices (11 and / or 12). Hereinafter, the optoelectronic devices may be referred to as light detectors, light receivers, or light sensing devices. The optoelectronic devices may include one or more of a camera, camera lens, sensor, sensor for detecting images, etc.

[0049] The display panel 110 may include a display area DA that can display one or more images and a non-display area NDA that does not display images.

[0050] Multiple subpixels can be set in the display area DA, and several types of signal lines used to drive the multiple subpixels can be set therein.

[0051] The non-display area NDA can refer to the area outside the display area DA, or the area around the outer edge of the display area DA. Several types of signal lines can be disposed in the non-display area NDA, and several types of drive circuits can be connected to or located in the non-display area NDA. At least a portion of the non-display area NDA can be bent and thus not visible from the front surface of the display device 100, or covered by the housing or enclosure (not shown) of the display device 100. The non-display area NDA can also be referred to as an active area, a bezel, or a bezel area.

[0052] refer to Figure 1 In one or more aspects, one or more optoelectronic devices (11 and / or 12) may be prepared as devices separate from the display panel 110 and subsequently included in the display device 100. For example, one or more optoelectronic devices (11 and / or 12) may be located below or on the lower part of the display panel 110 (on the side opposite to its viewing surface).

[0053] Light can enter the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optoelectronic devices (11 and / or 12) located below or on the lower part of the display panel 110 (opposite to the viewing surface). The light passing through the display panel 110 may include, for example, visible light, ultraviolet light, etc.

[0054] One or more optoelectronic devices (11 and / or 12) may be devices capable of receiving or detecting light passing through the display panel 110 and performing a predetermined function based on the received light. For example, one or more optoelectronic devices (11 and / or 12) may include one or more of the following: image capture devices such as cameras, image sensors, etc.; or sensors such as proximity sensors, illuminance sensors, etc. For example, the sensor may be an infrared sensor capable of performing a predetermined operation using infrared light.

[0055] Reference Figure 1 In one or more aspects, the display area DA of the display panel 110 may include one or more optical areas (OA1 and / or OA2) and a general area NA. In this document, the term "general area" NA can be an area that, when present in the display area DA, does not overlap with one or more optoelectronic devices (11 and / or 12), and may also be referred to as a non-optical area. The one or more optical areas (OA1 and / or OA2) can be one or more areas that, in a cross-sectional view of the display panel 110, respectively overlap with one or more optoelectronic devices (11 and / or 12).

[0056] In one or more aspects, although Figure 1 The diagram illustrates a display device 100 comprising two optical regions (OA1, OA2), but aspects of this disclosure are not limited thereto. For example, the display device 100 may include a first optical region (OA1 or OA2) and a general region NA. In these configurations, at least a portion of the first optical region OA1 may overlap with a first optoelectronic device 11.

[0057] In one or more aspects, it may be desirable for one or more optical regions (OA1 and / or OA2) to include both image display structures and light-transmitting structures. For example, since one or more optical regions (OA1 and / or OA2) are included in the display area DA, it may be desirable for the corresponding light-emitting regions of the subpixels used to display the image to be located in one or more optical regions (OA1 and / or OA2). Furthermore, in order for one or more optoelectronic devices (11 and / or 12) to fully receive light, it may be desirable for one or more optical regions (OA1 and / or OA2) to include light-transmitting structures.

[0058] In the following discussion, for ease of description, an example in which the first optoelectronic device 11 is a camera and the second optoelectronic device 12 is a sensor is provided. However, it should be understood that the scope of this disclosure includes examples in which the first optoelectronic device 11 is a sensor and the second optoelectronic device 12 is a camera. A camera may be, for example, a camera lens, an image sensor, or a unit that includes at least one of a camera lens and an image sensor.

[0059] The display area DA includes a general area NA and one or more optical areas (OA1 and / or OA2), which can be areas where images can be displayed. It should be noted that the general area NA can be an area that does not require a light-transmitting structure, while the one or more optical areas (OA1 and / or OA2) can be areas that require a light-transmitting structure.

[0060] Therefore, one or more optical regions (OA1 and / or OA2) may have a transmittance greater than or equal to a predetermined level, i.e., relatively high transmittance, and the ordinary region NA may have a transmittance less than the predetermined level or no transmittance.

[0061] For example, one or more optical regions (OA1 and / or OA2) may have different resolutions, subpixel arrangements, number of subpixels per unit area, electrode structures, line structures, electrode arrangements, line arrangements, etc., than ordinary regions NA.

[0062] In one or more aspects, the number of subpixels per unit area in one or more optical regions (OA1 and / or OA2) may be less than the number of subpixels per unit area in a normal region NA. For example, the resolution of one or more optical regions (OA1 and / or OA2) may be lower than the resolution of the normal region NA. Here, the number of subpixels per unit area may be expressed in the same way as resolution, pixel density, or pixel integration. For example, the number of subpixels per unit area may be expressed as pixels per inch (PPI), which represents the number of pixels in one inch.

[0063] The first optical region OA1 can have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. The second optical region OA2 can also have various shapes, such as circular, elliptical, quadrilateral, hexagonal, octagonal, etc. The first optical region OA1 and the second optical region OA2 can have the same, substantially or nearly the same, or different shapes. In the following description, for ease of reference to the shapes of the optical regions (OA1 and OA2), each of the first optical region OA1 and the second optical region OA2 is considered to have a circular shape. However, it should be understood that the scope of this disclosure includes examples where at least one of the first optical region OA1 and the second optical region OA2 has a shape other than a circular shape.

[0064] In this document, a display device 100 having a structure in which a first optical electronic device 11 (such as a camera) is located below or under the display panel 110 and is not exposed to the outside can be referred to as a display in which under-display camera (UDC) technology is implemented.

[0065] According to this structure, the display device 100 can provide the advantage of preventing a reduction in the size of the display area DA, because it is not necessary to form a notch or camera hole in the display panel 110 for exposing the camera. In fact, since it is not necessary to form a notch or camera hole in the display panel 110 for camera exposure, the display device 100 can provide the following further advantages: a reduction in the size of the bezel area, and improved design freedom due to the elimination of this limitation on the design.

[0066] In this document, a display device 100 having a structure in which a second electronic device 12 (e.g., a sensor such as a proximity sensor, illuminance sensor, infrared sensor, etc.) is located below or under the display panel 110 and is not exposed to the outside can be referred to as a display that applies under-display infrared (UDIR) technology.

[0067] Although one or more optoelectronic devices (11 and / or 12) are located below or under the display panel 110 of the display device 100 (e.g., hidden or not exposed to the outside), one or more optoelectronic devices (11 and / or 12) need to properly receive or detect light in order to perform predefined functions.

[0068] Furthermore, although one or more optoelectronic devices (11 and / or 12) in the display device 100 are located below or at the bottom of the display panel 110 to be hidden and positioned to overlap with the display area DA, it is generally necessary to perform image display in one or more optical areas (OA1 and / or OA2) that overlap with the one or more optoelectronic devices (11 and / or 12) in the display area DA. Therefore, in one or more aspects, even if one or more optoelectronic devices (11 and / or 12) are located on the back of the display panel, images can be displayed in a normal manner (e.g., without degrading image quality) in one or more optical areas (OA1 and / or OA2) that overlap with the one or more optoelectronic devices (11 and / or 12) in the display area DA.

[0069] It should be understood that, since the first optical region OA1 is designed as a transparent region, the image display characteristics in the first optical region OA1 may differ from the image display characteristics in the ordinary region NA.

[0070] Furthermore, when the first optical region OA1 is designed to improve image display characteristics, the transmittance of the first optical region OA1 may decrease.

[0071] To address these issues, in one or more aspects, a display device may be provided comprising a structure that can improve the transmittance of the first optical region OA1 without causing a difference in image quality between the first optical region OA1 and the ordinary region NA.

[0072] In addition, in one or more aspects, a display device may be provided, the display device including a structure of a second optical region OA2 wherein the image quality and light transmittance of the second optical region OA2 can be improved.

[0073] Furthermore, in one or more aspects, although the first optical region OA1 and the second optical region OA2 included in the display device 100 are light-transmitting regions with similar functions, the first optical region OA1 and the second optical region OA2 can be used in different applications. Therefore, the first optical region OA1 and the second optical region OA2 included in the display device 100 can be designed to have different structures from each other.

[0074] Figure 2 An example system configuration of a display device 100 according to various aspects of this disclosure is shown. In the following... Figure 2 In the discussion of the configuration, for the sake of brevity, the references are omitted or briefly described. Figure 1 Discussion of features and configurations that are equal, substantially equal, or similar.

[0075] Reference Figure 2 In one or more example embodiments, the display device 100 may include a display panel 110 and at least one display driving circuit as components for displaying one or more images.

[0076] The display driving circuit may be a circuit for driving the display panel 110, and includes a data driving circuit DDC, a gate driving circuit GDC, a display controller DTCR, and other circuit components.

[0077] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. The display panel 110 may also include several types of signal lines to drive the plurality of sub-pixels SP.

[0078] In one or more aspects, the display device 100 herein may be a liquid crystal display device or the like, or a self-emissive display device that emits light from the display panel 110 itself. In the example where the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP included in the display panel 110 may include a light-emitting element.

[0079] For example, the display device 100 according to various aspects of this disclosure may be an organic light-emitting display device that uses organic light-emitting diodes (OLEDs) to realize the light-emitting elements. In another example, the display device 100 according to various aspects of this disclosure may be an inorganic light-emitting display device that uses light-emitting diodes based on inorganic materials to realize the light-emitting elements. In yet another embodiment, the display device 100 according to various aspects of this disclosure may be a quantum dot display device that uses quantum dots to realize the light-emitting elements, wherein quantum dots are self-emitting semiconductor crystals.

[0080] The structure of each of the plurality of subpixels SP may be configured or designed differently depending on the type of display device 100. For example, in an example where the display device 100 is a self-emitting display device including self-emitting subpixels SP, each subpixel SP may include a self-emitting light-emitting element, one or more transistors, and one or more capacitors.

[0081] In one or more aspects, the signal lines provided in the display device 100 may include, for example, multiple data lines DL for transmitting data signals (which may be referred to as data voltage or image signals), multiple gate lines GL for transmitting gate signals (which may be referred to as scan signals), etc.

[0082] Multiple data lines DL and multiple gate lines GL may intersect each other. Each of the multiple data lines DL may extend in a first direction. Each of the multiple gate lines GL may extend in a second direction different from the first direction. For example, the first direction may be a column or vertical direction, and the second direction may be a row or horizontal direction. In another example, the first direction may be a row or horizontal direction, and the second direction may be a column or vertical direction.

[0083] The data drive circuit DDC can be used to drive multiple data lines DL and can provide data signals to the multiple data lines DL. The gate drive circuit GDC can be used to drive multiple gate lines GL and can provide gate signals to the multiple gate lines GL.

[0084] The display controller DCTR can be a device for controlling the data drive circuit DDC and the gate drive circuit GDC, and can control the driving time of multiple data lines DL and multiple gate lines GL.

[0085] The display controller DCTR can provide a data drive control signal DCS to the data drive circuit DDC to control the data drive circuit DDC, and a gate drive control signal GCS to the gate drive circuit GDC to control the gate drive circuit GDC.

[0086] The display controller DCTR can receive input image data from the host system HSYS and provide the data driver circuit DDC with image data DATA that is readable by the data driver circuit DDC based on the input image data.

[0087] The data drive circuit DDC can receive digital image data DATA from the display controller DCTR, convert the received image data DATA into analog data signals, and output the obtained analog data signals to multiple data lines DL.

[0088] The gate drive circuit GDC can receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage, as well as various gate drive control signals GCS, generate a gate signal, and provide the generated gate signal to multiple gate lines GL.

[0089] In one or more aspects, the data drive circuit DDC can be connected to the display panel 110 via tape auto-bonding (TAB) technology, or to conductive pads of bonding pads such as the display panel 110 via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 110 via chip-on-film (COF) technology.

[0090] In one or more aspects, the gate drive circuit GDC can be connected to the display panel 110 via tape-on-buck (TAB) technology, or to conductive pads such as bonding pads of the display panel 110 via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 110 via chip-on-film (COF) technology. In one or more aspects, the gate drive circuit GDC can be disposed in the non-active region NDA of the display panel 110 via gate-in-panel (GIP) technology. The gate drive circuit GDC can be disposed on the substrate or connected to the substrate. In an example where the gate drive circuit GDC is implemented via GIP technology, the gate drive circuit GDC can be disposed in the non-display region NDA of the substrate. In examples where the gate drive circuit GDC is implemented via chip-on-glass (COG) technology, chip-on-film (COF) technology, etc., the gate drive circuit GDC can be connected to the substrate.

[0091] In one or more aspects, at least one of the data driving circuit DDC and the gate driving circuit GDC may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit DDC and the gate driving circuit GDC may be configured not to overlap with the sub-pixel SP, or to overlap with one or more or all of the sub-pixels SP, or to overlap with at least one or more corresponding portions of one or more sub-pixels SP.

[0092] In one or more aspects, the data driving circuit DDC may be disposed and / or electrically connected to, but not limited to, only one side or one edge (e.g., the upper or lower part) of the display panel 110. In one or more aspects, depending on the driving scheme, panel design scheme, etc., the data driving circuit DDC may be located and / or electrically connected to, but not limited to, both sides or two edges (e.g., the upper and lower parts) of the display panel 110 or at least two of the four sides or four edges (e.g., the upper, lower, left, and right portions) of the display panel 110.

[0093] In one or more aspects, the gate drive circuit GDC may be located and / or electrically connected to, but not limited to, one side or one edge (e.g., the left or right portion) of the display panel 110. In one or more aspects, depending on the driving scheme, panel design, etc., the gate drive circuit GDC may be located and / or electrically connected to, but not limited to, at least two of the four sides or four edges (e.g., the left and right portions) of the panel 110 or the four sides or four edges (e.g., the upper, lower, left, and right portions) of the panel 110.

[0094] The display controller DCTR can be implemented in a separate component from the data drive circuit DDC, or integrated with the data drive circuit DDC, so that the display controller DCTR and the data drive circuit DDC can be implemented in a single integrated circuit.

[0095] The display controller DCTR can be a timing controller used in common display technologies, or a controller or control device capable of performing control functions other than those of a common timing controller. In one or more aspects, the display controller DCTR can be a controller or control device different from a timing controller, or a circuit system or component included in a controller or control device. The display controller DCTR can be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0096] The display controller DCTR can be mounted on printed circuit boards, flexible printed circuits, etc., and can be electrically connected to the data drive circuit DDC and the gate drive circuit GDC through printed circuit boards, flexible printed circuits, etc.

[0097] The display controller DCTR can send signals to and receive signals from the data drive circuit DDC via one or more predefined interfaces. For example, such interfaces may include Low Voltage Differential Signaling (LVDS), Embedded Clock Point-to-Point Interface (EPI), Serial Peripheral Interface (SPI), etc.

[0098] In one or more aspects, to further provide touch sensing and image display functions, the display device 100 may include at least one touch sensor and a touch sensing circuit, which is capable of detecting whether a touch event is caused by a touch object such as a finger or a pen, or is capable of detecting the corresponding touch position by sensing the touch sensor.

[0099] The touch sensing circuit may include a touch driver circuit (TDC) capable of generating and providing touch sensing data by driving and sensing a touch sensor, a touch controller (TCTR) capable of using the touch sensing data to detect the occurrence of a touch event or to detect the touch position (or touch coordinates), and one or more other components.

[0100] A touch sensor may include multiple touch electrodes. The touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes to a touch driver circuit (TDC).

[0101] The touch sensor can be disposed on the exterior of the display panel 110 in the form of a touch panel, or it can be disposed inside the display panel 110. In the example where the touch sensor is implemented as a touch panel outside the display panel 110, such a touch sensor can be referred to as an additional type. In the example where the additional type touch sensor is disposed in the display device 100, the touch panel and the display panel 110 can be manufactured and combined separately during the assembly process. The additional type touch panel may include a touch panel substrate and a plurality of touch electrodes disposed on the touch panel substrate.

[0102] In an example where the touch sensor is integrated inside the display panel 110, the touch sensor can be formed on the substrate SUB along with the display driving-related signal lines and electrodes during the manufacturing process of the display panel 110.

[0103] The touch driving circuit TDC can provide a touch driving signal to at least one of a plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0104] Touch sensing circuits can perform touch sensing using self-capacitance sensing technology or mutual capacitance sensing technology.

[0105] In an example where the touch sensing circuit performs touch sensing using self-capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between one or more touch electrodes and an object such as a finger or pen. According to self-capacitance sensing technology, each of the multiple touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit TDC can drive all or one or more of the multiple touch electrodes and sense all or one or more of the multiple touch electrodes.

[0106] In an example where the touch sensing circuit performs touch sensing using mutual capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to mutual capacitance sensing technology, multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit TDC can drive the driving touch electrodes and sense the sensing touch electrodes.

[0107] In one or more aspects, the touch driver circuit TDC and the touch controller TCTR included in the touch sensing circuit can be implemented in separate devices or in a single device. In one or more aspects, the touch driver circuit TDC and the data driver circuit DDC can be implemented in separate devices or in a single device.

[0108] The display device 100 may also include a power supply circuit for providing several types of power to the display driving circuit and / or touch sensing circuit.

[0109] In one or more aspects, the display device 100 can be a mobile terminal such as a smartphone, tablet computer, etc., or a monitor, television (TV), etc. Furthermore, the display device 100 can be configured with various types, sizes, and shapes to display information or images. For example, the display device 100 can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, stretchable devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation devices, car navigation devices, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc.

[0110] Figure 3 An example configuration of the display panel 110 according to various aspects of this disclosure is shown. In the following... Figure 3 In the discussion of the configuration, for simplicity, descriptions of references are omitted or briefly described. Figure 1 and Figure 2 Discussion of features and configurations that are equal, substantially equal, or similar.

[0111] Reference Figure 3 The display panel 110 may include a substrate SUB on which a plurality of sub-pixels SP are disposed, and an encapsulation layer ENCAP located on the substrate SUB. The encapsulation layer may also be referred to as an encapsulation substrate or an encapsulation portion.

[0112] Reference Figure 3 In one or more example embodiments, when the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP disposed on the substrate SUB may include an emitting element ED and a sub-pixel circuit SPC for driving the emitting element ED.

[0113] Reference Figure 3The subpixel circuit (SPC) may include multiple transistors and at least one capacitor for driving the light-emitting element (ED). The SPC drives the ED by providing a drive current to the ED at a predetermined timing. The ED emits light by being driven by the drive current.

[0114] The multiple transistors may include a driving transistor DT for driving the light-emitting element ED and a scanning transistor ST configured to be turned on or off according to the scanning signal SC.

[0115] The driving transistor DT can provide driving current to the light-emitting element ED.

[0116] The scanning transistor ST can be configured to control the electrical state of the corresponding node in the sub-pixel circuit SPC, or to control the state or operation of the driving transistor DT.

[0117] At least one capacitor may include a storage capacitor Cst, which is configured to maintain a constant voltage level during a display frame or a period of a display frame.

[0118] To drive at least one sub-pixel SP, at least one data signal VDATA as an image signal and at least one scan signal SC as a gate signal can be applied to at least one sub-pixel SP. Furthermore, to drive one or more sub-pixels SP, at least one common driving voltage, including a first common driving voltage VDD and a second common driving voltage VSS, can be applied to one or more sub-pixels SP.

[0119] The light-emitting element (ED) may include a first electrode AE, a second electrode CE, and an intermediate layer EL. The intermediate layer EL may be disposed between the first electrode AE ​​and the second electrode CE.

[0120] For example, the first electrode AE ​​can be an electrode provided for each sub-pixel SP, and the second electrode CE can be an electrode commonly provided in all or some of the multiple sub-pixels SP. For example, the first electrode AE ​​can be an anode electrode, and the second electrode CE can be a cathode electrode. In another example, the first electrode AE ​​can be a cathode electrode, and the second electrode CE can be an anode electrode. In the following discussion, for ease of explanation, the example of the first electrode AE ​​being an anode electrode and the second electrode CE being a cathode electrode can be used as a basis for explanation.

[0121] In an example where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL may include an emitter layer EML, a first common intermediate layer COM1 between the first electrode AE ​​and the emitter layer EML, and a second common intermediate layer COM2 between the emitter layer EML and the second electrode CE. The layer including the first common intermediate layer COM1 and the second common intermediate layer COM2 may be referred to as the common intermediate layer EL_COM.

[0122] In one or more aspects, an emission layer EML can be set for each subpixel SP, and a common intermediate layer EL_COM can be set on all or some of the multiple subpixel SPs.

[0123] The Emitting Layer (EML) can be set in each emitting region, and the common Intermediate Layer (EL_COM) can be set in all or some of the multiple emitting regions and all or some of the multiple non-emitting regions.

[0124] In one or more aspects, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transfer layer HTL. The second common intermediate layer COM2 may include an electron transport layer ETL and an electron injection layer EIL.

[0125] The hole injection layer (HIL) injects holes from the first electrode (AE) into the hole transport layer (HTL), and the hole transport layer (HTL) transports holes to the emitter layer (EML). The electron injection layer injects electrons from the second electrode (CE) into the electron transport layer, and the electron transport layer transports electrons to the emitter layer (EML).

[0126] For example, the second electrode CE can be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS can be applied to the second electrode CE through the second common driving voltage line VSSL. The first electrode AE ​​can be electrically connected directly or indirectly (via another transistor) to the first node N1 of the corresponding driving transistor DT of each sub-pixel SP. In this document, the second common driving voltage VSS can also be referred to as the "reference voltage", and the second common driving voltage line VSSL can also be referred to as the "low power supply voltage line", "low voltage line", or "reference voltage line".

[0127] Each light-emitting element (ED) can be configured by overlapping a first electrode AE, an emissive layer EML in the intermediate layer EL, and a second electrode CE. Each ED can form a corresponding light-emitting region. For example, the corresponding light-emitting region of each ED may include the area where the first electrode AE, the emissive layer EML in the intermediate layer EL, and the second electrode CE overlap.

[0128] In one or more aspects, each or at least one of the plurality of light-emitting elements ED included in the display panel 110 or display device 100 may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot (QD) light-emitting element, a micro light-emitting diode, a miniature light-emitting diode, etc. In an example where each light-emitting element ED is an organic light-emitting diode (OLED), the intermediate layer EL of the corresponding light-emitting element ED may be a layer comprising organic material.

[0129] The driving transistor DT can be a transistor configured to provide drive current to the light-emitting element ED. The driving transistor DT can be connected between the first common drive voltage line VDDL and the light-emitting element ED.

[0130] The driving transistor DT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light-emitting element ED. The data signal VDATA may be applied to the second node N2. The first common driving voltage VDD transmitted through the first common driving voltage line VDDL may be applied to the third node N3.

[0131] In the driving transistor DT, the second node N2 can be the gate node, the first node N1 can be the source node or the drain node, and the third node N3 can be the drain node or the source node. In the following discussion, for ease of explanation only, examples are provided based on the scenario where the first, second, and third nodes (N1, N2, and N3) of the driving transistor DT are the source, gate, and drain nodes (or electrodes), respectively. However, aspects of this disclosure are not limited thereto.

[0132] Included Figure 3 The scanning transistor ST in the sub-pixel circuit SPC shown can be a switching transistor, used to allow the data signal VDATA, which is the image signal, to be provided to the second node N2, which is the gate node of the driving transistor DT.

[0133] The scan transistor ST can be turned on or off by the scan signal SC, and controls the electrical connection between the second node N2 of the drive transistor DT and the data line DL. The scan signal SC is a type of gate signal applied through the scan line SCL, which is a type of gate line GL. The drain or source electrode of the scan transistor ST can be electrically connected to the data line DL. The source or drain electrode of the scan transistor ST can be electrically connected to the second node N2 of the drive transistor DT. The gate electrode of the scan transistor ST can be electrically connected to the scan line SCL.

[0134] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst can include a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[0135] The storage capacitor Cst can be an external capacitor that is intentionally designed to be located outside the driving transistor DT, and thus different from an internal capacitor such as a parasitic capacitor (e.g., Cgs, Cgd) that can be formed between the first node N1 and the second node N2 of the driving transistor DT.

[0136] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0137] The display panel 110 may have a top-emitting structure or a bottom-emitting structure.

[0138] In the example where the display panel 110 has a top-emitting structure, at least a portion of the sub-pixel circuit SPC can overlap with at least a portion of the light-emitting element ED in the vertical direction. In this configuration, the area or size of the corresponding light-emitting region can be increased, and the corresponding aperture ratio can be increased.

[0139] In the example of the display panel 110 having a bottom emission structure, the sub-pixel circuit SPC can be designed not to overlap with the light-emitting element ED in the vertical direction.

[0140] like Figure 3 As shown, the subpixel circuit SPC can have a 2T (transistor) 1C (capacitor) structure comprising two transistors (DT and ST) and one capacitor (Cst). In one or more aspects, the subpixel circuit SPC may also include one or more transistors or one or more capacitors in the 2T 1C structure.

[0141] For example, a subpixel circuit SPC can have an 8T1C structure comprising 8 transistors and 1 capacitor. In another example, a subpixel circuit SPC can have a 6T2C structure comprising 6 transistors and 2 capacitors. In yet another example, a subpixel circuit SPC can have a 7T1C structure comprising 7 transistors and 1 capacitor. However, aspects of this disclosure are not limited to such specific structures.

[0142] The type and number of gate signals supplied to the sub-pixel SP and / or the type and number of gate lines connected to the sub-pixel SP can vary depending on the structure of the corresponding sub-pixel circuit SPC. Furthermore, the type and number of common driving voltages supplied to the sub-pixel SP can vary depending on the structure of the corresponding sub-pixel circuit SPC.

[0143] Reference Figure 3Since circuit elements (e.g., light-emitting elements ED in each sub-pixel SP, such as organic light-emitting diodes (OLEDs) that include organic materials) may be easily damaged by external moisture or oxygen, an encapsulation layer ENCAP may be provided in the display panel 110 to prevent external moisture or oxygen from penetrating the circuit elements (e.g., light-emitting elements ED).

[0144] The encapsulation layer ENCAP can be configured in various shapes or shapes to prevent the light-emitting element (ED) from contacting moisture or oxygen. For example, the encapsulation layer ENCAP may comprise two or more layers, wherein one or more organic layers and one or more inorganic layers are stacked alternately, but aspects of this disclosure are not limited thereto.

[0145] Reference Figure 3 In one or more aspects, in order to sense a user's touch, the display device 100 may include: a touch sensor layer including a plurality of sensor electrodes; a touch driving circuit configured to sense the plurality of sensor electrodes; and a touch controller configured to determine whether a touch is applied or the location of the touch (e.g., touch coordinates) based on the sensing results (e.g., touch sensing data) of the touch driving circuit.

[0146] The touch sensor layer can be embedded in the display panel 110. For example, the touch sensor layer can be disposed on the encapsulation layer ENCAP of the display panel 110.

[0147] The display panel 110 may include multiple touchpads electrically connected to the touch driving circuit, and multiple touch wirings, which are used to electrically connect multiple sensor electrodes included in the touch sensor layer to the multiple touchpads connected to the touch driving circuit 220.

[0148] Figure 4 The following illustrates a configuration of three example regions (NA, OA1, and OA2) included in the display area DA of a display device 100, according to various aspects of this disclosure. Figure 4 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 3 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0149] Reference Figure 4 In one or more example embodiments, a plurality of sub-pixels SP may be disposed in each of the ordinary region NA, the first optical region OA1 and the second optical region OA2 included in the display region DA.

[0150] Multiple subpixels SP may include, for example, at least one red subpixel (red SP) that emits red light, at least one green subpixel (green SP) that emits green light, and at least one blue subpixel (blue SP) that emits blue light.

[0151] Therefore, each of the ordinary region NA, the first optical region OA1, and the second optical region OA2 may include the light-emitting region EA of the red sub-pixel (red SP), the light-emitting region EA of the green sub-pixel (green SP), and the light-emitting region EA of the blue sub-pixel (blue SP).

[0152] Reference Figure 4 The ordinary region NA may not include the light-transmitting structure, but may include the light-emitting region EA.

[0153] In this configuration, it may be desirable for the optical regions (OA1 and OA2) to include not only the light-emitting region EA, but also the light-transmitting structure. The optical regions (OA1 and OA2) may include transmission regions (TA1 and TA2) and a low-transmission region LTA. For example, the first optical region OA1 may include at least one first transmission region TA1 and a low-transmission region LTA, and the second optical region OA2 may include at least one second transmission region TA2 and a low-transmission region LTA.

[0154] In each of the optical regions (OA1 and OA2), the low-transmission region LTA, excluding the transmission region (TA1 or TA2), may include multiple luminescent regions EA. Thus, in one or more aspects, the first optical region OA1 may include luminescent region EA and a first transmission region TA1, and the second optical region OA2 may include luminescent region EA and a second transmission region TA2.

[0155] In one or more aspects, the low-transmission region LTA and the transmission regions (TA1 and TA2) can differ depending on whether light transmission is permitted. For example, the low-transmission region LTA may be a region that allows light to transmit at a low transmittance (or less than a predetermined level of transmittance) or does not allow light transmission, and the transmission regions (TA1 and TA2) may be regions that allow light transmission or allow light to transmit at a transmittance greater than or equal to a predetermined level.

[0156] In one or more aspects, the low-transmission region LTA and the transmission regions (TA1 and TA2) may also differ depending on whether a specific metal layer is included. For example, a second electrode layer CE may be formed in the low-transmission region LTA, and the second electrode layer CE may not be formed in the transmission regions (TA1 and TA2). For example, a light-shielding layer LSL may be formed in the low-transmission region LTA, and the light-shielding layer LSL may not be formed in the transmission regions (TA1 and TA2).

[0157] In one or more aspects, the multiple pixel circuits (SPCs) for driving multiple light-emitting elements (EDs) can be arranged in the low-transmission region (LTA).

[0158] The low-transmittance region LTA in the optical regions (OA1 and OA2) can be, for example, a region that does not allow light transmission. In another example, the low-transmittance region LTA and the transmission regions (TA1 and TA2) can be regions that allow light to transmit at a low transmittance (e.g., less than a predetermined level of transmittance). The transmittance of the low-transmittance region LTA in the optical regions (OA1 and OA2) can be less than the transmittance of the transmission region TA. However, the transmittance of the low-transmittance region LTA in the optical regions (OA1 and OA2) can be greater than the transmittance of the normal region NA.

[0159] According to the light-transmitting structure, since the first optical region OA1 includes the first transmission region TA1 and the second optical region OA2 includes the second transmission region TA2, the first optical region OA1 and the second optical region OA2 can be regions where light can be transmitted.

[0160] In one or more aspects, the transmittance (transmittance) of the first optical region OA1 and the transmittance (transmittance) of the second optical region OA2 can be substantially the same. In this paper, taking into account slight differences due to errors in the process, substantially the same can mean the same degree.

[0161] In this configuration, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 may have substantially the same shape or size as each other. In one or more aspects, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have different shapes or sizes, the ratio of the first transmission region TA1 to the first optical region OA1 and the ratio of the second transmission region TA2 to the second optical region OA2 may be substantially the same as each other.

[0162] However, the aspects of this disclosure are not limited thereto. For example, the transmittance of the first optical region OA1 and the transmittance of the second optical region OA2 may be different from each other.

[0163] In this configuration, the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 may have different shapes or sizes from each other. In one or more aspects, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have different shapes or sizes, the ratio of the first transmission region TA1 to the first optical region OA1 and the ratio of the second transmission region TA2 to the second optical region OA2 may be substantially the same as each other.

[0164] In one or more aspects, in an example where a first optical electronic device 11 overlapping with a first optical region OA1 is a camera and a second optical electronic device 12 overlapping with a second optical region OA2 is a sensor for detecting an image, the camera may require a larger amount of light than the sensor.

[0165] Therefore, the transmittance of the first optical region OA1 can be greater than that of the second optical region OA2.

[0166] For example, at least one first transmission region TA1 of the first optical region OA1 may have a larger size than at least one second transmission region TA2 of the second optical region OA2. In one or more aspects, even when the first transmission region TA1 of the first optical region OA1 and the second transmission region TA2 of the second optical region OA2 have substantially the same size as each other, the ratio of the first transmission region TA1 to the first optical region OA1 may be greater than the ratio of the second transmission region TA2 to the second optical region OA2.

[0167] In one or more aspects, such as Figure 4 As shown, the first transmission region TA1 of the first optical region OA1 may have a circular shape in the plan view, but the structure of the first transmission region TA1 in the plan view according to various aspects of this disclosure is not limited to this.

[0168] For example, the shape of the first transmission region TA1 of the first optical region OA1 can be octagonal in a plan view, and in another example, it can be formed as an ellipse or a polygon.

[0169] In one or more aspects, the area or size of the light-emitting area of ​​the first optical region OA1 can be adjusted by changing the shape of the first transmission region TA1 and adjusting the transmittance of the first transmission region TA1.

[0170] In the following discussion, for ease of description, an example is provided based on the fact that the transmittance of the first optical region OA1 is greater than that of the second optical region OA2.

[0171] Furthermore, the transmissive regions (TA1 and TA2) can be referred to as the transparent regions, and the term transmittance can be referred to as transparency.

[0172] Furthermore, in the following discussion, it is assumed that the first optical region OA1 and the second optical region OA2 are located at the upper edge of the display region DA of the display panel 110 and are arranged adjacent to each other in a direction from left to right or from right to left.

[0173] Reference Figure 4The horizontal display area provided with the first optical region OA1 and the second optical region OA2 can be referred to as the first horizontal display area HA1, and the other horizontal display area not provided with the first optical region OA1 and the second optical region OA2 can be referred to as the second horizontal display area HA2.

[0174] Reference Figure 4 The first horizontal display area HA1 may include a portion of the ordinary area NA, the first optical area OA1, and the second optical area OA2.

[0175] Figure 5 An example cross-sectional view is shown of optical regions (e.g., a first optical region OA1 and / or a second optical region OA2) defined in a display panel 110 according to various aspects of this disclosure. In the following... Figure 5 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 4 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0176] Reference Figure 5 The first light-emitting element ED1 and the second light-emitting element ED2 can be disposed in the optical regions (OA1 and / or OA2). The corresponding region where the first light-emitting element ED1 and / or the second light-emitting element ED2 are disposed is a low-transmission region LTA, and a transmission region TA can be disposed between the first light-emitting element ED1 and the second light-emitting element ED2. For example, the transmission region TA can be disposed between the first light-emitting region EA1 formed by the first light-emitting element ED1 and the second light-emitting region EA2 formed by the second light-emitting element ED2.

[0177] Reference Figure 5 The pixel circuit SPC can be configured to drive the first light-emitting element ED1 and is configured to overlap all or part of the first light-emitting element ED1 in the optical region (OA1 and / or OA2). Another pixel circuit SPC can be configured to drive the second light-emitting element ED2 and is configured to overlap all or part of the second light-emitting element ED2 in the optical region (OA1 and / or OA2).

[0178] The pixel circuit SPC for driving the first light-emitting element ED1 may include a first driving transistor DT1, a first scanning transistor ST1, and a first storage capacitor Cst1. The pixel circuit SPC for driving the second light-emitting element ED2 may include a second driving transistor DT2, a second scanning transistor ST2, and a second storage capacitor Cst2. Since the pixel circuit SPC for driving the first light-emitting element ED1 and the pixel circuit SPC for driving the second light-emitting element ED2 include substantially the same components, for ease of description, the discussion will focus on the pixel circuit SPC for driving the first light-emitting element ED1.

[0179] Reference Figure 5 In terms of the stacked structure, the display panel 110 may include a transistor forming portion, a light-emitting element forming portion, and an encapsulation portion.

[0180] The transistor forming portion may include a substrate SUB, a first buffer layer BUF1 on the substrate SUB, and various transistors (DT, ST), a storage capacitor Cst, and various electrodes or signal lines disposed on the first buffer layer BUF.

[0181] The lower shielding metal BSM can be disposed on the substrate SUB. The lower shielding metal BSM can be located below the first active layer ACT1s of the first scan transistor ST1.

[0182] The first buffer layer BUF1 can be a single layer or multiple layers. When the first buffer layer BUF1 is in the form of multiple layers, it can include a multi-buffer layer MBUF and an active buffer layer ABUF.

[0183] Various transistors (DT1, ST1), at least one storage capacitor Cst, and various electrodes or signal lines can be disposed on the first buffer layer BUF1.

[0184] For example, transistors (DT1, ST1) disposed on the first buffer layer BUF1 may comprise the same material and reside together in one or more layers. In another example, such as Figure 5 As shown, in transistors (DT1, ST1), the first driving transistor DT1 and the first scanning transistor ST1 may include different materials and are located in different layers.

[0185] The first driving transistor DT1 and the first scanning transistor ST1 can be formed in the following example configuration.

[0186] The first scanning transistor ST1 may include a first active layer ACT1s, a first gate electrode G1s, a first source electrode S1s, and a first drain electrode D1s.

[0187] The first driving transistor DT1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0188] The first active layer ACT1 of the first driving transistor DT1 can be located at a position higher than the first active layer ACT1s of the first scanning transistor ST1.

[0189] The first buffer layer BUF1 can be disposed below the first active layer ACT1 of the first scanning transistor ST1, and the second buffer layer BUF2 can be disposed below the first active layer ACT1 of the first driving transistor DT1.

[0190] For example, the first active layer ACT1 of the first scanning transistor ST1 can be located on the first buffer layer BUF1, and the first active layer ACT1 of the first driving transistor DT1 can be located on the second buffer layer BUF2. For example, the second buffer layer BUF2 can be located above the first buffer layer BUF1.

[0191] The first active layer ACT1s of the first scanning transistor ST1 can be located on the first buffer layer BUF1, and the first gate insulating layer GI1 can be disposed on the first active layer ACT1s of the first scanning transistor ST1. The first gate electrode G1s of the first scanning transistor ST1 can be disposed on the first gate insulating layer GI1, and the first interlayer insulating layer ILD1 can be disposed on the first gate electrode G1s of the first scanning transistor ST1.

[0192] The first active layer ACT1s of the first scanning transistor ST1 may include a first channel region overlapping with the first gate electrode G1s, a first source connection region on one side of the first channel region, and a first drain connection region on the other side of the first channel region.

[0193] The second buffer layer BUF2 can be placed on the first interlayer insulation layer ILD1.

[0194] The first active layer ACT1 of the first driving transistor DT1 can be disposed on the second buffer layer BUF2, and the second gate insulating layer GI2 can be disposed on the first active layer ACT1. The first gate electrode G1 of the first driving transistor DT1 can be disposed on the second gate insulating layer GI2, and the second interlayer insulating layer ILD2 can be disposed on the first gate electrode G1.

[0195] The first active layer ACT1 of the first driving transistor DT1 may include a second channel region overlapping with the first gate electrode G1, a second source connection region located on one side of the second channel region, and a second drain connection region located on the other side of the second channel region.

[0196] The first source electrode S1s and the first drain electrode D1s of the first scanning transistor ST1 can be disposed on the second interlayer insulating layer ILD2. Similarly, the first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 can be disposed on the second interlayer insulating layer ILD2.

[0197] The first source electrode S1s and the first drain electrode D1s of the first scanning transistor ST1 can be connected to the first source connection region and the first drain connection region of the first active layer ACT1s through the holes of the second interlayer insulating layer ILD2, the second gate insulating layer GI2, the second buffer layer BUF2, the first interlayer insulating layer ILD1, and the first gate insulating layer GI1, respectively.

[0198] The first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 can be connected to the second source connection region and the second drain connection region of the first active layer ACT1 through the holes of the second interlayer insulating layer ILD2 and the second gate insulating layer GI2, respectively.

[0199] Reference Figure 5 The first storage capacitor Cst1 included in the first pixel circuit SPC1 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0200] The first capacitor electrode PLT1 can be electrically connected to the first gate electrode G1 of the first driving transistor DT1, and the second capacitor electrode PLT2 can be electrically connected to the first source electrode S1 of the first driving transistor DT1.

[0201] Reference Figure 5 The lower metal layer BML can be disposed below the first active layer ACT1 of the first driving transistor DT1. The lower metal layer BML can overlap with all or part of the first active layer ACT1.

[0202] For example, the lower metal BML can be electrically connected to the first gate electrode G1. In another example, the lower metal BML can be used as a light shield to block light entering from the layer below it. In this configuration, the lower metal BML can be electrically connected to the first source electrode S1.

[0203] The first driving transistor DT1 and the first scanning transistor ST1 can be located in the low-transmission region LTA.

[0204] Reference Figure 5 The display panel 110 may include at least one planarization layer PLN disposed on the first driving transistor DT1 and the first scanning transistor ST1.

[0205] For example, refer to Figure 5At least one planarization layer PLN may include a first planarization layer PLN1. The first planarization layer PLN1 may be disposed on the first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1, and the first source electrode S1s and the first drain electrode D1s of the first scanning transistor ST1.

[0206] Reference Figure 5 A first relay electrode RE1 can be disposed on the first planarization layer PLN1.

[0207] For example, the first relay electrode RE1 can be an electrode used to relay the electrical connection between the first source electrode S1 of the first driving transistor DT1 and the first electrode AE1 of the first light-emitting element ED1. The first relay electrode RE1 can be electrically connected to the first source electrode S1 of the first driving transistor DT1 through the holes of the first planarization layer PLN1.

[0208] Reference Figure 5 The first relay electrode RE1 can be set in the low-transmission region LTA.

[0209] Reference Figure 5 The planarization layer PLN disposed in the display panel 110 may further include a second planarization layer PLN2 located on the first planarization layer PLN1. For example, the second planarization layer PLN2 may be configured such that it covers the first relay electrode RE1 located on the first planarization layer PLN1.

[0210] Figure 5 The diagram shows a planarization layer PLN comprising a first planarization layer PLN1 and a second planarization layer PLN2, but aspects of this disclosure are not limited thereto. For example, the planarization layer PLN may also comprise one or more planarization layers.

[0211] Reference Figure 5 The light-emitting element can be located on the second planarization layer PNL2.

[0212] Reference Figure 5 The light-emitting element forming portion may include a first light-emitting element ED1 and a second light-emitting element ED2 disposed on the second planarization layer PNL2. The first light-emitting element ED1 and the second light-emitting element ED2 may be disposed in the low-transmission region TLA.

[0213] Reference Figure 5 The first light-emitting element ED1 can be disposed in the region where the first electrode AE1, the intermediate layer EL, and the second electrode CE overlap with each other.

[0214] Reference Figure 5The first electrode AE1 can be disposed on the second planarization layer PLN2. The first electrode AE1 can be connected to the first relay electrode RE1 through the holes in the second planarization layer PLN2.

[0215] Reference Figure 5 A dam portion BK can be formed on the first electrode AE1. The dam portion BK may include a plurality of dam holes, and a portion of the first electrode AE1 may be exposed through one or at least one of the corresponding dam holes. For example, at least one of the plurality of dam holes formed in the dam portion BK may overlap with a portion of the first electrode AE1.

[0216] Reference Figure 5 The intermediate layer EL can be disposed on the embankment BK. The intermediate layer EL can contact corresponding portions of the first electrode AE ​​(e.g., AE1 and AE2) through multiple embankment holes.

[0217] Reference Figure 5 At least one spacer SPCR can be disposed between the intermediate layer EL and the embankment BK.

[0218] Reference Figure 5 The second electrode CE may be disposed on the intermediate layer EL. The cathode electrode CE may or may not include multiple cathode holes CH. In the example where the cathode electrode CE includes multiple cathode holes CH, the multiple cathode holes CH of the cathode electrode CE may be positioned to correspond to the transmission region TA in the optical region (OA1 and / or OA2).

[0219] The embankment hole of the embankment BK may not overlap with the cathode hole CH.

[0220] The upper surface of the embankment BK located below the multiple cathode holes CH can be flat and not recessed or etched. For example, the embankment BK may not be recessed or perforated at the location of the cathode holes CH. Therefore, at the location of the cathode holes CH, the second planarization layer PLN2 and the first planarization layer PLN1 located below the embankment BK may also not be recessed or perforated.

[0221] Because the upper surface of the embankment BK located below the multiple cathode holes CH is formed to be flat, one or more insulating layers, one or more metal patterns (electrodes, lines, etc.) or emitter layers EL located below the cathode electrode CE will not be damaged by the process of forming multiple cathode holes CH in the cathode electrode CE.

[0222] The process of forming multiple cathode holes CH in a cathode electrode CE is briefly described below. After depositing a specific mask pattern at the locations where multiple cathode holes CH are to be formed, cathode electrode material can be deposited on it. Therefore, cathode electrode material can be deposited only in areas where the specific mask pattern is not present, thereby forming a cathode electrode CE with multiple cathode holes CH. For example, the specific mask pattern may include an organic material. The cathode electrode material may include a magnesium-silver ((Mg-Ag) alloy.

[0223] After forming a cathode electrode CE with multiple cathode holes CH, the display panel 110 may be in a state where a particular mask pattern is completely removed, or in a state where a particular mask pattern is at least partially retained.

[0224] Reference Figure 5 The encapsulation portion may be located on the second electrode CE. The encapsulation portion may include an encapsulation layer ENCAP disposed on the second electrode CE.

[0225] Reference Figure 5 The encapsulation layer ENCAP can be a layer disposed below the encapsulation layer ENCAP to prevent moisture or oxygen from penetrating into the light-emitting elements (ED1 and ED2). In particular, the encapsulation layer ENCAP can prevent moisture or oxygen from penetrating into the intermediate layer EL, which may include an organic layer. For example, the encapsulation layer ENCAP can be in the form of a single layer or multiple layers.

[0226] Reference Figure 5 The encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0227] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 can be inorganic layers, and the second encapsulation layer PCL can be an organic layer. Since the second encapsulation layer PCL includes an organic layer, it can also serve as a planarization layer.

[0228] In one or more aspects, the display panel 110 may include a touch sensor embedded in the display panel 110. In this configuration, the display panel 110 may include a touch sensor layer TSL disposed on the encapsulation layer ENCAP.

[0229] Reference Figure 5 The touch sensor layer (TSL) may include a touch sensor metal (TSM) and a bridging metal (BRG), and may also include insulating layers such as a sensor buffer layer (S-BUF), an interlayer insulating layer (S-ILD), and a sensor protective layer (S-PAC). The interlayer insulating layer (S-ILD) may be in the form of one or more insulating layers.

[0230] The sensor buffer layer S-BUF can be disposed on the encapsulation layer ENCAP. The bridging metal BRG can be disposed on the sensor buffer layer S-BUF, and the sensor interlayer insulating layer S-ILD can be disposed on the bridging metal BRG.

[0231] The touch sensor metal (TSM) can be disposed on the interlayer insulating layer (S-ILD). One or more touch sensor metal (TSMs) can be connected to one or more corresponding bridging metals (BRGs) through one or more holes in the S-ILD.

[0232] Reference Figure 5 The touch sensor metal TSM and bridging metal BRG can be set in the optical frame area OBA. The touch sensor metal TSM and bridging metal BRG can be set so as not to overlap with the light-emitting areas (EA1 and EA2) of the low-transmission area LTA.

[0233] Multiple touch sensor metal TSMs can form a touch electrode (or a touch electrode line (or array)) and are arranged in a grid to be electrically connected to each other. One or more touch sensor metals in the touch sensor metal TSMs and the remaining one or more touch sensor metal TSMs can be electrically connected to each other through at least one bridging metal BRG to form a touch electrode (or a touch electrode line (or array)).

[0234] The sensor protective layer S-PAC can be configured to cover the touch sensor metal TSM and the bridging metal BRG.

[0235] In one or more aspects, in the example where the touch sensor is embedded in the display panel 110, a corresponding portion of at least one touch sensor metal in the touch sensor metal TSM located on the encapsulation layer ENCAP in the display area DA may extend along the outer inclined surface of the encapsulation layer ENCAP and be electrically connected to a pad positioned further outward than the outer inclined surface of the encapsulation layer ENCAP. For example, the pad may be located in the non-display area NDA and may be a metal pattern to which the touch driving circuit TDC is electrically connected.

[0236] In one or more aspects, the display panel 110 may include a substrate SUB, a first buffer layer BUF1 disposed between the substrate SUB and the first scanning transistor ST1, and a second buffer layer BUF2 disposed between the first scanning transistor ST1 and the first driving transistor DT1.

[0237] The first active layer ACT1s of the first scanning transistor ST1 and the first active layer ACT1 of the first driving transistor DT1 may include different semiconductor materials.

[0238] For example, the first active layer ACT1 of the first driving transistor DT1 may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), cadmium oxide (CdO), indium oxide (InO), zinc tin oxide (ZTO), zinc indium tin oxide (ZITO), etc.

[0239] For example, the first active layer ACT1s of the first scanning transistor ST1 may include a semiconductor material different from the first active layer ACT1 of the first driving transistor DT1. For example, the first active layer ACT1s of the first scanning transistor ST1 may include a silicon-based semiconductor material. For example, the silicon-based semiconductor material may include low-temperature polycrystalline silicon (LTPS), etc.

[0240] Reference Figure 5 The second driving transistor DT2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0241] The second light-emitting element ED2 can be disposed in the region where the first electrode AE2, the intermediate layer EL, and the second electrode CE overlap.

[0242] The second source electrode S2 of the second driving transistor DT2 can be connected to the first electrode AE2 via the second relay electrode RE2.

[0243] The second storage capacitor Cst2 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0244] The second source electrode S2 of the second driving transistor DT2 can be connected to the second capacitor electrode PLT2 of the second storage capacitor Cst2.

[0245] The second gate electrode G2 of the second driving transistor DT2 can be connected to the first capacitor electrode PLT1 of the second storage capacitor Cst2.

[0246] The active layer ACT2s of the second scanning transistor ST2 can be located on the first buffer layer BUF1 and at a position lower than the second active layer ACT2 of the second driving transistor DT2.

[0247] The semiconductor material included in the active layer ACT2s of the second scanning transistor ST2 may be different from the semiconductor material included in the second active layer ACT2 of the second driving transistor DT2. For example, the semiconductor material included in the second active layer ACT2 of the second driving transistor DT2 may be an oxide semiconductor material, and the semiconductor material included in the active layer ACT2s of the second scanning transistor ST2 may be a silicon-based semiconductor material (e.g., low-temperature polycrystalline silicon (LTPS)).

[0248] Reference Figure 5 The optical regions (OA1 and / or OA2) may overlap with one or more optoelectronic devices. The one or more optoelectronic devices overlapping with the optical regions (OA1 and / or OA2) may be a first optoelectronic device 11 and / or a second optoelectronic device 12. For example, the one or more optoelectronic devices may include a camera, an infrared sensor, an ultraviolet sensor, etc. For example, the one or more optoelectronic devices may be one or more devices capable of receiving or detecting visible light to perform a predefined operation, or one or more devices capable of receiving or detecting light other than visible light (e.g., infrared light, ultraviolet light, etc.) to perform a predefined operation.

[0249] Reference Figure 5 The cross-sectional structure of the normal region NA can be the same as that of the low-transmission region LTA.

[0250] Reference Figure 5 Two or more light-emitting elements (EDs) may be disposed in the optical regions (OA1 and / or OA2). For example, two or more light-emitting elements (EDs) may be disposed in the low-transmission region (LTA) of the optical regions (OA1 and / or OA2). In one or more aspects, transistors (DT, ST) and storage capacitors (Cst) may be disposed in the optical regions (OA1 and / or OA2). For example, transistors (DT, ST) and storage capacitors (Cst) may be disposed in the low-transmission region (LTA) of the optical regions (OA1 and / or OA2).

[0251] Figure 6 An example cross-sectional view of a common light-emitting element is shown. In the following... Figure 6 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 5 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0252] Reference Figure 6The display device may include sub-pixels that emit light of different colors, including a red sub-pixel Red SP that emits red light, a green sub-pixel Green SP that emits green light, and a blue sub-pixel Blue SP that emits blue light. The red sub-pixel Red SP may include a light-emitting element containing a red emitting layer REML, the green sub-pixel Green SP may include a light-emitting element containing a green emitting layer GEML, and the blue sub-pixel Blue SP may include a light-emitting element containing a blue emitting layer BEML.

[0253] Each light-emitting element may include a first electrode AE ​​as an anode electrode. The first electrode AE ​​may include a conductive material having a relatively large work function value. For example, the first electrode AE ​​may include a transparent or semi-transparent conductive material that can transmit light. For example, the first electrode AE ​​may include a transparent conductive oxide (TCO) selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide, and tin oxide. For example, the first electrode AE ​​may include a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0254] For example, the first electrode AE ​​may include a metallic material with high reflectivity. For example, the first electrode AE ​​may include a highly reflective metallic material, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), a stacked structure of silver and ITO (ITO / Ag / ITO), a stacked structure of molybdenum-titanium (MoTi) and ITO (ITO / MoTi / ITO), a stacked structure of IZO, MoTi, and ITO (IZO / MoTi / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). An APC alloy represents an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0255] Light-emitting elements typically include a hole transport layer (HTL) on a first electrode AE. The hole transport layer (HTL) can be a layer used to accelerate and transport holes from the first electrode AE ​​to the emitting layer. The hole transport layer (HTL) can be commonly disposed in sub-pixels. Although Figure 6 Although not shown, the light-emitting element may include a hole injection layer HIL for injecting holes from the first electrode AE ​​into the emitting layer. The hole injection layer may be disposed between the first electrode AE ​​and the hole transport layer HTL.

[0256] Considering the wavelength of light emitted from the emitting layer and the hole mobility, the light-emitting element of a sub-pixel can include hole-assisted layers (R'HTL, G'HTL, etc.) with different heights. Although Figure 6Not shown, but the light-emitting element of the blue sub-pixel Blue SP may also include a hole auxiliary layer. Each hole auxiliary layer can control the mobility of holes from the hole transport layer (HTL) to the corresponding emission layer and control the optical distance according to the wavelength of light.

[0257] Light-emitting elements typically include a hole transport layer (HTL) and an electron blocking layer (EBL) on a hole auxiliary layer (R'HTL, G'HTL, etc.). The electron blocking layer (EBL) can be a layer used to block the movement of electrons flowing into the emitter layer and to retain electrons in the emitter layer. For example, the electron blocking layer (EBL) can prevent electrons flowing into the emitter layer from moving to the hole transport layer (HTL), thereby preventing electrons and holes from combining in the hole transport layer (HTL).

[0258] The red emission layer REML, green emission layer GEML, and blue emission layer BEML, respectively included in the light-emitting element of the sub-pixel, can be disposed on the electron blocking layer EBL. Electrons and holes can combine in each emission layer, thereby emitting light of the corresponding color. For example, light can be emitted when an exciton formed by combining a hole injected from the first electrode AE ​​and an electron injected from the second electrode CE in the emission layer returns from an excited state (unstable state) to a ground state (stable state). Each emission layer may include a body corresponding to the corresponding sub-pixel (e.g., Figure 7 GH in the middle) and dopants (e.g., Figure 7 (GD in the middle).

[0259] Light-emitting elements typically include a hole blocking layer (HBL) located on the emitter layer (REML, GEML, and BEML). The hole blocking layer (HBL) can be a layer used to block the movement of holes flowing into the emitter layer and to allow the holes to remain in the emitter layer. For example, the hole blocking layer (HBL) can prevent holes flowing into the emitter layer from moving to the electron transport layer (ETL), thereby preventing electrons and holes from combining in the electron transport layer (ETL).

[0260] Light-emitting elements typically include an electron transport layer (ETL) on a hole-blocking layer (HBL). The ETL can be a layer used to accelerate and transport electrons from the second electrode (CE) to the emitter layer. The ETL can be commonly disposed within sub-pixels. Although... Figure 6 Not shown, but the light-emitting element may include an electron injection layer for injecting electrons from the second electrode CE into the emitting layer. The electron injection layer may be disposed between the electron transport layer ETL and the second electrode CE.

[0261] The light-emitting element may include a second electrode CE on the electron transport layer (ETL). The second electrode CE may include a conductive material with a relatively low work function value. For example, the second electrode may include a metallic material with high reflectivity. For example, the second electrode CE may include highly reflective metallic materials such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), a stacked structure of silver and ITO (ITO / Ag / ITO), a stacked structure of molybdenum titanium (MoTi) and ITO (ITO / MoTi / ITO), a stacked structure of IZO, MoTi and ITO (IZO / MoTi / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0262] For example, the second electrode CE may include a transparent conductive oxide (TCO) selected from the group consisting of ITO, IZO, ITZO, zinc oxide, and tin oxide. For example, the second electrode CE may include a semi-transparent conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0263] Figure 7 These are example cross-sectional views and band diagrams of a common light-emitting element. The following are examples of such elements. Figure 7 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 6 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0264] Reference Figure 7 The light-emitting element (ED) may include a first electrode AE, a hole transport layer HTL, a hole auxiliary layer G'HTL, an electron blocking layer EBL, an emitter layer GEML, a hole blocking layer HBL, an electron transport layer ETL, and a second electrode CE. For example, Figure 7 The light-emitting element ED shown can be a green light-emitting element that emits green light.

[0265] Figure 7 The band structure diagram shown illustrates the band structure between the hole transport layer (HTL) and the emitter layer (GEML). Figure 7 In the band structure diagram, the upper side of the square band can represent the lowest unoccupied molecular orbital (LUMO) level of each layer, and the lower side can represent the highest occupied molecular orbital (HOMO) level of each layer.

[0266] Reference Figure 7 Since the electron blocking layer EBL is disposed between the emitter layer GEML and the hole auxiliary layer G'HTL, the emitter layer GEML and the hole auxiliary layer G'HTL can be disconnected from each other. For example, the emitter layer GEML and the hole auxiliary layer G'HTL may not be in direct contact with each other.

[0267] When the light-emitting element is turned on, holes injected from the first electrode AE ​​can move through the hole transport layer HTL, the hole auxiliary layer G'HTL, and the electron blocking layer EBL, and reach the emitter layer GEML. Similarly, electrons injected from the second electrode CE can move through the electron transport layer ETL and the hole blocking layer HBL, and reach the emitter layer GEML. When the light-emitting element is turned off, holes and electrons in the emitter layer GEML can return to the first electrode AE ​​and the second electrode CE, respectively. Each layer included in the light-emitting element can comprise a material with an appropriate bandgap energy, allowing holes and electrons to be injected and transported to the emitter layer GEML.

[0268] For example, when the difference in HOMO energy levels between the hole transport layer HTL, the hole auxiliary layer G'HTL, the electron blocking layer EBL, and the emitter layer GEML is not large, holes can move rapidly from the hole transport layer HTL to the emitter layer GEML when the light-emitting element is turned on, and holes can also move rapidly from the emitter layer GEML to the hole transport layer HTL even when the light-emitting element is turned off.

[0269] In this case, when the energy at which the difference between HOMO energy levels between layers is the largest (i.e., the HOMO threshold energy ΔHTH) is small, light may be emitted in the off state due to leakage current generated in adjacent sub-pixels, and holes may leak as a result.

[0270] To prevent this phenomenon, such as Figure 7 As shown, an electron blocking layer (EBL) with a relatively low (deep) HOMO energy level can be set adjacent to an emitter layer (GEML), which leads to an increase in the magnitude of the HOMO threshold energy.

[0271] Here, ΔHTH can be represented as |H2-H3|, where H2 is the HOMO level of the electron blocking layer EBL and H3 is the HOMO level of the hole-assisted layer G'HTL.

[0272] In this structure, when the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitting layer GEML cannot move to the first electrode AE ​​relatively quickly, but may move slowly.

[0273] In other words, although the energy difference ΔGH between the HOMO level of the emitting layer GEML and the HOMO level of the electron blocking layer is less than the HOMO threshold energy ΔHTH, holes may move relatively slowly when the light-emitting element is turned off, and therefore residual light may remain on the surface of the display device. Specifically, as... Figure 5 As shown, residual light may reduce sensing sensitivity when it remains in the optical area (OA1 and / or OA2) of one or more optoelectronic devices such as cameras and detection sensors.

[0274] Here, ΔGH can be expressed as ΔGH=|H1-H2|, and H1 represents the HOMO energy level of the emitter layer GEML.

[0275] Figure 7 The energy levels in the band diagram shown are as follows.

[0276] The HOMO level H2 of the electron blocking layer (EBL) can be lower than the HOMO level H1 of the emitter layer (GEML), the HOMO level H3 of the hole-assisted layer (G'HTL), and the HOMO level H4 of the hole transport layer (HTL). The HOMO level H1 of the emitter layer (GEML) can be lower than the HOMO level H3 of the hole-assisted layer (G'HTL) and the HOMO level H4 of the hole transport layer (HTL). The HOMO level H3 of the hole-assisted layer (G'HTL) can be lower than the HOMO level H4 of the hole transport layer (HTL).

[0277] The energy difference ΔGH' between the HOMO level of the emitter GEML and the HOMO level of the hole-assisted layer can be expressed as |H1-H3|, and the energy difference ΔGH'' between the HOMO level of the emitter GEML and the HOMO level of the hole transport layer can be expressed as |H1-H4|. The relationship of the HOMO level differences can be represented by the following equations 1 and 2.

[0278] Equation 1: |H1-H2|>|H1-H4|

[0279] Equation 2: |H1-H2|>|H1-H3|

[0280] Figure 8 It was applied Figure 7 The diagram shows an example cross-sectional view of a common display device with a light-emitting element. In the following section... Figure 8 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 7 Discussion of features and examples that are equal to, substantially equal to, or similar to those described.

[0281] Reference Figure 8 A typical display device may include a planarization layer PLN, a first electrode AE, a dam BK, a hole transport layer HTL, a hole auxiliary layer G'HTL, an electron blocking layer EBL, an emitter layer GEML, a hole blocking layer HBL, an electron transport layer ETL, and a second electrode CE.

[0282] In the open region of the dam section BK, the first electrode AE, hole transport layer HTL, hole auxiliary layer G'HTL, electron blocking layer EBL, emitter layer GEML, hole blocking layer HBL, electron transport layer ETL, and second electrode CE can overlap and contact each other. In this configuration, the open region of the dam section BK can be used as a light-emitting region.

[0283] The hole transport layer HTL, electron blocking layer EBL, and electron transport layer ETL can be commonly disposed in two or more sub-pixels SP and can span two or more emitting and non-emitting regions. The hole auxiliary layer G'HTL and the emission layer GEML can be patterned and configured as separate layers corresponding to each of the sub-pixels SP, and disposed in and around the opening region of the embankment BK, which corresponds to a portion of the emitting region and the non-emitting region. The width of the emission layer GEML can be represented as W1, and the width of the hole auxiliary layer G'HTL can be represented as W2. In this configuration, the hole auxiliary layer G'HTL and the emission layer GEML can be formed by a fine mask with apertures of the same size. The electron blocking layer EBL can have the same width as the hole transport layer HTL, the hole blocking layer, and the electron transport layer ETL, and is formed by an opening mask with apertures larger than those of the fine mask. The width of the electron blocking layer EBL can be represented as W3.

[0284] Reference Figure 7 and Figure 8 When the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitter layer GEML can move sequentially to the electron blocking layer EBL, the hole auxiliary layer G'HTL, and the hole transport layer HTL, and be emitted to the first electrode AE. Therefore, the movement speed of the holes may be relatively slow.

[0285] Figure 9 These are example cross-sectional views and band diagrams of light-emitting elements based on various aspects of this disclosure. The following are examples of such cross-sectional views and band diagrams for light-emitting elements. Figure 7 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 8 Discussion of features and examples that are equal to, substantially equal to, or similar to those described.

[0286] Reference Figure 9 In one or more example embodiments, the light-emitting element (ED) may include an electron blocking layer (EBL) disposed between the emitting layer GEML and the hole auxiliary layer G'HTL. The emitting layer GEML may have a structure that directly contacts the hole transport layer HTL. For example, the emitting layer GEML may directly contact the hole transport layer HTL without being disconnected by the electron blocking layer EBL. In this structure, the hole transport layer HTL, the hole auxiliary layer G'HTL, the electron blocking layer EBL, and the emitting layer GEML may be stacked in this order in the light-emitting region of the ED, and the emitting layer GEML and the hole transport layer HTL may be configured to directly contact each other in the non-light-emitting region.

[0287] Reference Figure 9As shown in the band structure diagram, the HOMO level H1 of the emitter layer GEML can be lower than the HOMO level H4 of the hole transport layer HTL, and the difference ΔGH'' between the HOMO level H1 of the emitter layer GEML and the HOMO level H4 of the hole transport layer can be relatively small. Therefore, when the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitter layer GEML can quickly and directly move to the hole transport layer HTL.

[0288] Figure 10 It was applied Figure 9 The diagram shows an example cross-sectional view of a display device 100 with a light-emitting element (ED). The following section addresses... Figure 10 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 9 Discussion of features and examples that are equal to, substantially equal to, or similar to those described.

[0289] Reference Figure 10 In one or more example embodiments, the display device 100 may include a planarization layer PLN, a first electrode AE, a dam BK, a hole transport layer HTL, a hole auxiliary layer G'HTL, an electron blocking layer EBL, an emitter layer GEML, a hole blocking layer HBL, an electron transport layer ETL, and a second electrode CE.

[0290] Reference Figure 10 The width W1 of the emitter layer GEML can be greater than the width W2 of the hole-assist layer G'HTL and the width W3 of the electron-blocking layer EBL. That is, the electron-blocking layer EBL, which is commonly disposed in each sub-pixel SP, can be patterned and configured to correspond to each sub-pixel SP. For example, the width W2 of the hole-assist layer G'HTL can have the same size as the width W3 of the electron-blocking layer EBL.

[0291] Reference Figure 10 The emitter layer GEML can be configured to contact the hole transport layer HTL. For example, the emitter layer GEML can be configured to cover the electron blocking layer EBL and contact the hole transport layer HTL. The emitter layer GEML can be configured to cover the upper surface and at least one side surface of the electron blocking layer EBL and contact the hole transport layer HTL. In this configuration, the emitter layer GEML can be configured to cover at least one side surface of the electron blocking layer EBL and contact the hole transport layer HTL.

[0292] Furthermore, the emitter layer GEML can be configured to cover the electron blocking layer EBL and the hole assist layer G'HTL, and to contact the hole transport layer HTL. For example, the emitter layer GEML can be configured to cover the upper surface and at least one side surface of the electron blocking layer EBL and at least one side surface of the hole assist layer G'HTL, and to contact the hole transport layer HTL. In this configuration, the emitter layer GEML can be configured to cover at least one corresponding side surface of the electron blocking layer EBL and the hole assist layer G'HTL, and to contact the hole transport layer HTL.

[0293] The emitter layer GEML can contact a portion of the upper surface of the hole transport layer HTL at the upper surface of the dam BK. For example, the emitter layer GEML can contact a portion of the upper surface of the hole transport layer HTL in a non-emitting region surrounding the opening region of the dam BK.

[0294] refer to Figure 9 and Figure 10 The hole transport layer HTL, hole auxiliary layer G'HTL, electron blocking layer EBL, and emitter layer GEML can be stacked in this order in the opening region of the luminescent area of ​​the dam BK, and the emitter layer GEML can be configured to be disconnected from the hole transport layer HTL and the hole auxiliary layer G'HTL in the opening region. In the non-luminescent area surrounding the opening region of the dam BK, the emitter layer GEML and the hole transport layer HTL can be configured to be in direct contact with each other.

[0295] With this structure, when the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitter layer GEML can be directly moved to the hole transport layer HTL. Therefore, the movement speed of the holes emitted to the first electrode AE ​​can be quickly controlled.

[0296] Figure 11 This is an example cross-sectional view used to compare a light-emitting element (ED) according to various aspects of this disclosure with a conventional light-emitting element. Below, regarding... Figure 11 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 10 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0297] Reference Figure 11Under normal conditions, when the display device is turned on, holes (h) can move from the first electrode AE ​​to the emitter layer GEML via a first path, and electrons (e) can move from the second electrode CE to the emitter layer GEML via a first path. Light can be emitted through the combination of holes (h) and electrons (e) in the emitter layer GEML. Subsequently, when the display device is turned off, holes (h) can move from the emitter layer GEML to the first electrode AE ​​via the first path, and electrons (e) can move from the emitter layer GEML to the second electrode CE via the first path. That is, under normal conditions, when the display device is turned off, due to the difference ΔGH between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the electron blocking layer, holes (h) can slowly move from the emitter layer GEML to the first electrode AE.

[0298] Conversely, when the display device 100 according to various aspects of this disclosure is turned off, holes h can move from the emitter layer GEML to the first electrode AE ​​via the third and fourth paths. That is, when the display device 100 is turned off, due to the difference ΔGH'' between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the hole transport layer, holes h can move relatively quickly from the emitter layer GEML to the first electrode AE. The difference ΔGH'' between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the hole transport layer can be smaller than the difference ΔGH between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the electron blocking layer. Therefore, a hole movement path that allows for rapid hole movement can be formed between the emitter layer GEML and the hole transport layer HTL, allowing holes h to move rapidly sequentially to the emitter layer GEML, the hole transport layer HTL, and the first electrode AE.

[0299] Reference Figure 11 The hole-assist layer G'HTL and the electron-blocking layer EBL can be formed using the first mask MASK1, the emitter layer GEML can be formed using the second mask MASK2, and other layers can be formed using the third mask MASK3. The apertures in the first mask MASK1 can have smaller dimensions than the apertures in the second mask MASK2.

[0300] Figure 12 Examples of cross-sectional views and band diagrams of light-emitting elements (EDs) based on various aspects of this disclosure are shown below. Figure 12 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 11 Discussion of features and examples that are equal to, substantially equal to, or similar to those described.

[0301] Reference Figure 12In one or more example embodiments, the light-emitting element (ED) may include an electron blocking layer (EBL) disposed between the emitting layer GEML and the hole auxiliary layer G'HTL. The emitting layer GEML may have a structure that directly contacts the hole transport layer HTL and the hole auxiliary layer G'HTL. For example, the emitting layer GEML may directly contact the hole transport layer HTL and the hole auxiliary layer G'HTL without being disconnected by the electron blocking layer EBL. In this configuration, the hole transport layer HTL, the hole auxiliary layer G'HTL, the electron blocking layer EBL, and the emitting layer GEML may be stacked in this order in the light-emitting region of the light-emitting element ED, and the emitting layer GEML may be configured to directly contact the hole transport layer HTL and the hole auxiliary layer G'HTL in the non-light-emitting region.

[0302] Reference Figure 12 As shown in the band structure diagram, the HOMO level H1 of the emitter layer GEML can be lower than the HOMO level H3 of the hole-assisted layer G'HTL and the HOMO level H4 of the hole transport layer HTL, and the HOMO level H3 of the hole-assisted layer G'HTL can be lower than the HOMO level H4 of the hole transport layer HTL. Furthermore, the energy difference ΔGH' between the HOMO level H1 of the emitter layer GEML and the HOMO level H3 of the hole-assisted layer G'HTL, and the energy difference ΔGH” between the HOMO level H1 of the emitter layer GEML and the HOMO level H4 of the hole transport layer can be relatively small. Therefore, when the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitter layer GEML can quickly and directly move to the hole-assisted layer G'HTL and the hole transport layer HTL.

[0303] Figure 13 It was applied Figure 12 The example cross-sectional view of the display device 100 with light-emitting elements (ED) is shown below. Figure 13 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 12 Discussion of features and examples that are equal to, substantially equal to, or similar to those described.

[0304] Reference Figure 13 In one or more example embodiments, the display device 100 may include a planarization layer PLN, a first electrode AE, a dam BK, a hole transport layer HTL, a hole auxiliary layer G'HTL, an electron blocking layer EBL, an emitter layer GEML, a hole blocking layer HBL, an electron transport layer ETL, and a second electrode CE.

[0305] Reference Figure 13The width W1 of the emitter layer GEML can be greater than the width W2 of the hole-assisted layer G'HTL and the width W3 of the electron-blocking layer EBL. For example, the width W2 of the hole-assisted layer G'HTL can be greater than the width W3 of the electron-blocking layer EBL.

[0306] Reference Figure 13 The emitter layer GEML can be configured to contact the hole auxiliary layer G'HTL and the hole transport layer HTL. For example, the emitter layer GEML can be configured to cover the electron blocking layer EBL and contact the hole transport layer HTL. The emitter layer GEML can be configured to cover the upper surface and at least one side surface of the electron blocking layer EBL and contact the hole transport layer HTL. In this configuration, the emitter layer GEML can be configured to cover at least one side surface of the electron blocking layer EBL and contact the hole transport layer HTL.

[0307] Furthermore, the emitter layer GEML can be configured to cover the electron blocking layer EBL and the hole assist layer G'HTL, and contact the hole transport layer HTL. For example, the emitter layer GEML can be configured to cover the upper surface and at least one side surface of the electron blocking layer EBL and a portion of the upper surface and at least one side surface of the hole assist layer G'HTL, and contact the hole transport layer HTL. In this configuration, the emitter layer GEML can be configured to cover at least one side surface of the electron blocking layer EBL and at least one side surface of the hole assist layer G'HTL, and contact the hole transport layer HTL.

[0308] The emitter layer GEML can contact the upper surface of the hole transport layer HTL at the upper surface of the dam BK. The emitter layer GEML can also contact a portion of the upper surface of the hole auxiliary layer G'HTL at the upper surface of the dam BK. For example, the emitter layer GEML can contact the upper surfaces of the hole auxiliary layer G'HTL and the upper surfaces of the hole transport layer HTL in a non-emitting region surrounding the opening region of the dam BK.

[0309] Reference Figure 12 and Figure 13 The hole transport layer HTL, hole auxiliary layer G'HTL, electron blocking layer EBL, and emitter layer GEML can be stacked in this order in the opening region of the luminescent area of ​​the dam BK, and the emitter layer GEML can be configured to be disconnected from the hole transport layer HTL and the hole auxiliary layer G'HTL in the opening region. In the non-luminescent area surrounding the opening region of the dam BK, the emitter layer GEML can be configured to directly contact the hole auxiliary layer G'HTL and the hole transport layer HTL.

[0310] Based on these configurations, when the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitter layer GEML can be directly moved to the hole auxiliary layer G'HTL and the hole transport layer HTL. Therefore, the movement speed of the holes emitted to the first electrode AE ​​can be quickly controlled.

[0311] Figure 14 Examples of cross-sectional views and band diagrams of light-emitting elements (EDs) based on various aspects of this disclosure are shown below. Figure 14 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 13 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0312] Reference Figure 14 In one or more example embodiments, the light-emitting element (ED) may include an electron blocking layer (EBL) disposed between the emitting layer GEML and the hole auxiliary layer G'HTL. The emitting layer GEML may have a structure that directly contacts the hole auxiliary layer G'HTL. For example, the emitting layer GEML may directly contact the hole auxiliary layer G'HTL without being disconnected by the electron blocking layer EBL. In this configuration, the hole transport layer HTL, the hole auxiliary layer G'HTL, the electron blocking layer EBL, and the emitting layer GEML may be stacked in this order in the light-emitting region of the ED, and the emitting layer GEML may be configured to directly contact the hole auxiliary layer G'HTL in the non-light-emitting region.

[0313] Reference Figure 14 As shown in the band structure diagram, the HOMO level H1 of the emitter layer GEML can be lower than the HOMO level H3 of the hole-assisted layer G'HTL and the HOMO level H4 of the hole transport layer HTL, and the HOMO level H3 of the hole-assisted layer G'HTL can be lower than the HOMO level H4 of the hole transport layer HTL. Furthermore, the energy difference ΔGH' between the HOMO level H1 of the emitter layer GEML and the HOMO level H3 of the hole-assisted layer G'HTL can be relatively small. Therefore, when the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitter layer GEML can quickly and directly move to the hole-assisted layer G'HTL, and the holes that have moved to the hole-assisted layer G'HTL can quickly move to the hole transport layer HTL.

[0314] Figure 15 This is based on the application of various aspects of this disclosure. Figure 14 An example cross-sectional view of a display device 100 showing a light-emitting element. In the following... Figure 15 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 14 Discussion of features and examples that are equal to, substantially equal to, or similar to those described.

[0315] Reference Figure 15 In one or more example embodiments, the display device 100 may include a planarization layer PLN, a first electrode AE, a dam BK, a hole transport layer HTL, a hole auxiliary layer G'HTL, an electron blocking layer EBL, an emitter layer GEML, a hole blocking layer HBL, an electron transport layer ETL, and a second electrode CE.

[0316] Reference Figure 15 For example, the width W1 of the emitter layer GEML can be the same as the width W2 of the hole-assisted layer G'HTL. Alternatively, the width W1 of the emitter layer GEML can be greater than the width W3 of the electron-blocking layer EBL.

[0317] Reference Figure 15 The emitter layer GEML can be configured to contact the hole auxiliary layer G'HTL. For example, the emitter layer GEML can be configured to cover the electron blocking layer EBL and contact the hole auxiliary layer G'HTL. The emitter layer GEML can be configured to cover the upper surface and at least one side surface of the electron blocking layer EBL and contact the hole auxiliary layer G'HTL. In this configuration, the emitter layer GEML can be configured to cover at least one side surface of the electron blocking layer EBL and contact the hole auxiliary layer G'HTL. The hole auxiliary layer G'HTL can be configured to directly contact the hole transport layer HTL.

[0318] The emitting layer GEML can contact the upper surface of the hole auxiliary layer G'HTL at the upper surface of the dam BK. The emitting layer GEML can also contact a portion of the upper surface of the hole auxiliary layer G'HTL at the upper surface of the dam BK. For example, the emitting layer GEML can contact a portion of the upper surface of the hole auxiliary layer G'HTL in a non-emitting region surrounding the opening area of ​​the dam BK.

[0319] Reference Figure 14 and Figure 15 The hole transport layer HTL, hole auxiliary layer G'HTL, electron blocking layer EBL, and emitter layer GEML can be stacked in this order in the opening region of the luminescent area of ​​the dam BK, and the emitter layer GEML can be configured to be disconnected from the hole transport layer HTL and the hole auxiliary layer G'HTL in the opening region. In the non-luminescent area surrounding the opening region of the dam BK, the emitter layer GEML can be configured to directly contact the hole auxiliary layer G'HTL, and the hole auxiliary layer G'HTL can be configured to directly contact the hole transport layer HTL.

[0320] Based on these structures, when the light-emitting element ED changes from the on state to the off state, the holes h accumulated in the emitter layer GEML can directly move to the hole auxiliary layer G'HTL, and the holes that have moved to the hole auxiliary layer G'HTL can move to the hole transport layer HTL. Therefore, the movement speed of the holes emitted to the first electrode AE ​​can be quickly controlled.

[0321] Figure 16 This is an example cross-sectional view used to compare a light-emitting element (ED) according to various aspects of this disclosure with a conventional light-emitting element. Below, regarding... Figure 16 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 15 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0322] and Figure 16 The characteristics related to the movement of holes h in the display device 100 according to various aspects of this disclosure may differ from those in the configuration. Figure 11 The features in the configuration, and therefore, by focusing on different features to provide support. Figure 16 The discussion of the configuration.

[0323] Reference Figure 16 In the display device 100 according to various aspects of this disclosure, when the device is off, holes h can move from the emitter layer GEML to the first electrode AE ​​via a third path and a fourth path. That is, when the display device 100 is off, due to the difference ΔGH'' between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the hole auxiliary layer, holes h can move relatively quickly from the emitter layer GEML to the first electrode AE. The difference ΔGH' between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the hole auxiliary layer can be smaller than the difference ΔGH between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the electron blocking layer. Therefore, a hole movement path that allows for rapid hole movement can be formed between the emitter layer GEML and the hole auxiliary layer G'HTL, allowing holes h to sequentially and rapidly move to the emitter layer GEML, the hole auxiliary layer G'HTL, the hole transport layer HTL, and the first electrode AE.

[0324] Reference Figure 16 The electron blocking layer (EBL) can be formed using the first mask (MASK1). The hole-assisting layer (G'HTL) and the emitter layer (GEML) can be formed using the second mask (MASK2). Other layers can be formed using the third mask (MASK3). The apertures in the first mask (MASK1) can have smaller dimensions than the apertures in the second mask (MASK2).

[0325] Figure 17 It was applied Figure 14The diagram shows an example cross-sectional view of a display device 100 with a light-emitting element (ED). The following section addresses... Figure 17 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 16 Discussion of features and examples that are equal to, substantially equal to, or similar to those described.

[0326] Reference Figure 17 In one or more example embodiments, the display device 100 may include a planarization layer PLN, a first electrode AE, a dam BK, a hole transport layer HTL, a hole auxiliary layer G'HTL, an electron blocking layer EBL, an emitter layer GEML, a hole blocking layer HBL, an electron transport layer ETL, and a second electrode CE.

[0327] Reference Figure 17 The width W2 of the hole auxiliary layer G'HTL can be greater than the width W1 of the emitter layer GEML and the width W3 of the electron blocking layer EBL. For example, the width W1 of the emitter layer GEML can be greater than the width W3 of the electron blocking layer EBL.

[0328] Reference Figure 17 The emitter layer GEML can be configured to contact the hole auxiliary layer G'HTL. For example, the emitter layer GEML can be configured to cover the electron blocking layer EBL and contact the hole auxiliary layer G'HTL. The emitter layer GEML can be configured to cover the upper surface and at least one side surface of the electron blocking layer EBL and contact the hole auxiliary layer G'HTL. The emitter layer GEML can be configured to cover at least one side surface of the electron blocking layer EBL and contact the hole auxiliary layer G'HTL. The hole auxiliary layer G'HTL can be configured to directly contact the hole transport layer HTL. In this configuration, the hole blocking layer HBL can be configured to contact a portion of the upper surface of the hole auxiliary layer G'HTL. For example, the hole blocking layer HBL can be configured to cover the upper surface and at least one side surface of the emitter layer GEML and contact a portion of the upper surface of the electron blocking layer EBL.

[0329] The emitting layer GEML can contact the upper surface of the hole-assisting layer G'HTL at the upper surface of the dam BK. The emitting layer GEML can also contact a portion of the upper surface of the hole-assisting layer G'HTL at the upper surface of the dam BK. For example, the emitting layer GEML can contact a portion of the upper surface of the hole-assisting layer G'HTL in a non-emitting region surrounding the opening area of ​​the dam BK. The hole-blocking layer HBL can be configured to contact a portion of the upper surface of the hole-assisting layer G'HTL in a non-emitting region surrounding the opening area of ​​the dam BK.

[0330] Reference Figure 14 and Figure 17The hole transport layer HTL, hole auxiliary layer G'HTL, electron blocking layer EBL, and emitter layer GEML can be stacked in this order in the opening region of the luminescent area of ​​the dam BK, and the emitter layer GEML can be configured to be disconnected from the hole transport layer HTL and the hole auxiliary layer G'HTL in the opening region. In the non-luminescent area surrounding the opening region of the dam BK, the emitter layer GEML can be configured to directly contact the hole auxiliary layer G'HTL, and the hole auxiliary layer G'HTL can be configured to directly contact the hole transport layer HTL.

[0331] Based on these configurations, when the light-emitting element ED changes from an on state to an off state, the holes h accumulated in the emitter layer GEML can directly move to the hole auxiliary layer G'HTL, and the holes that have moved to the hole auxiliary layer G'HTL can move to the hole transport layer HTL. Therefore, the movement speed of the holes emitted to the first electrode AE ​​can be quickly controlled.

[0332] Figure 18 and Figure 19 This is a graph illustrating example brightness and off characteristics in a display device 100 and a general display device according to various aspects of this disclosure. In the following... Figure 18 and Figure 19 In the discussion of the configuration, for ease of description, the references are omitted or briefly described. Figures 1 to 17 Discussion of features and examples that are equal to, substantially equal to, or similar to the described features and examples.

[0333] exist Figure 18 In the curve graph, the comparative example ComEx represents the curve from which the curve has been compared. Figure 8 The display device with the structure shown measures the brightness over time, and Example 1 Ex1 represents the brightness from... Figure 10 The brightness of the display device 100 as shown in the present disclosure is measured over time.

[0334] Reference Figure 18 When the display device is turned off from the on state, it can be seen that the corresponding brightness of Comparative Example ComEx and Example 1 Ex1 decreases over time. In the case of Comparative Example ComEx, it can be confirmed that even after the time TS1 when the brightness first reaches its minimum value, the brightness continues to decrease and eventually reaches its minimum value completely. Conversely, in the case of Example 1, it can be confirmed that the time TS2 when the brightness first reaches its minimum value is shorter than the time TS1 of Comparative Example ComEx, and thereafter, the time until the brightness reaches its minimum value completely is also shorter. This means that the holes accumulated in the emitter layer in Example 1 Ex1 move directly to the hole transport layer and are rapidly emitted to the first electrode.

[0335] exist Figure 19In the curve graph, the comparative example ComEx represents the curve from which the curve has been compared. Figure 8 The display device with the structure shown measures the brightness over time, and Example 2 Ex2 represents the brightness from... Figure 15 The brightness of the display device 100 as shown in the present disclosure is measured over time.

[0336] Reference Figure 19 When the display device is turned off from the on state, it can be confirmed that, in the case of Example 2 Ex2, the time TS3 for the brightness of Example 2 Ex2 to first reach its minimum value is shorter than the time TS1 for Comparative Example ComEx, and thereafter, the time until the brightness fully reaches its minimum value is also shorter. In particular, in the case of Example 2 Ex2, it can be confirmed that the difference ΔGH' between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the hole auxiliary layer has a smaller value than the difference ΔGH'' between the HOMO energy level of the emitter layer GEML and the HOMO energy level of the hole transport layer, and therefore, the width (or degree) of the brightness reduction in the initial period is increased. This means that in Example 2 Ex2, the holes accumulated in the emitter layer move directly to the hole auxiliary layer and are rapidly emitted to the hole transport layer and the first electrode.

[0337] The display device 100 based on the examples, aspects and embodiments of this disclosure can be described as follows.

[0338] A display device 100 according to an example embodiment of the present disclosure may include a plurality of light-emitting elements disposed on a substrate. In one or more aspects, at least one of the plurality of light-emitting elements may include a first electrode disposed on the substrate, a hole transport layer disposed on the first electrode, an electron blocking layer disposed on the hole transport layer, an emitting layer disposed on the electron blocking layer and having a width greater than that of the electron blocking layer, and a second electrode disposed on the emitting layer.

[0339] In one or more aspects, in a display device, the highest occupied molecular orbital (HOMO) energy level of the electron blocking layer may be lower than the HOMO energy level of the emitter layer.

[0340] In one or more aspects, in a display device, the following equation 1 is satisfied.

[0341] Equation 1: |H1-H2|>|H1-H4|

[0342] Where H1 is the HOMO level of the emitter layer, H2 is the HOMO level of the electron blocking layer, and H4 is the HOMO level of the hole transport layer.

[0343] In one or more aspects, in a display device, the emitting layer may be configured to cover the electron blocking layer and contact the hole transport layer.

[0344] In one or more aspects, in a display device, the light-emitting element may further include a hole-assist layer disposed between a hole transport layer and an electron blocking layer. In one or more aspects, the emitting layer may be configured to cover the electron blocking layer and the hole-assist layer, and to contact the hole transport layer.

[0345] In one or more aspects, in a display device, the width of the hole auxiliary layer may be the same as the width of the electron blocking layer.

[0346] In one or more aspects, in a display device, the emitting layer may be configured to cover the upper surface and at least one side surface of the electron blocking layer and at least one side surface of the hole assist layer, and to contact the hole transport layer.

[0347] In one or more aspects, in a display device, the width of the emitter layer may be greater than the width of the hole auxiliary layer, and the width of the hole auxiliary layer may be greater than the width of the electron blocking layer.

[0348] In one or more aspects, in a display device, the emitting layer may be configured to cover the upper surface and at least one side surface of the electron blocking layer and a portion of the upper surface and at least one side surface of the hole assist layer, and to contact the hole transport layer.

[0349] In one or more aspects, in a display device, the following equation 2 is satisfied.

[0350] Equation 2: |H1-H2|>|H1-H4|

[0351] Wherein, H1 is the HOMO level of the emitter layer, H2 is the HOMO level of the electron blocking layer, and H3 is the HOMO level of the hole-assisted layer.

[0352] In one or more aspects, in a display device, the light-emitting element may further include a hole auxiliary layer disposed between the hole transport layer and the electron blocking layer. In one or more aspects, the width of the hole auxiliary layer may be greater than the width of the electron blocking layer.

[0353] In one or more aspects, in a display device, the emitting layer may be configured to cover the electron blocking layer and contact the hole assist layer.

[0354] In one or more aspects, in a display device, the width of the hole auxiliary layer may be the same as the width of the emitter layer.

[0355] In one or more aspects, in a display device, the emitting layer may be configured to cover the upper surface and at least one side surface of the electron blocking layer and to contact at least a portion of the upper surface of the hole assist layer.

[0356] In one or more aspects, in a display device, the width of the hole auxiliary layer may be greater than the width of the emitter layer.

[0357] In one or more aspects, in a display device, the emitting layer may be configured to cover the upper surface and at least one side surface of the electron blocking layer and to contact the inner portion of at least one end of the upper surface of the hole assist layer.

[0358] In one or more aspects, the display device may further include a hole blocking layer disposed on the emission layer. In one or more aspects, the hole blocking layer may be configured to cover the emission layer and contact the hole transport layer.

[0359] In one or more aspects, in a display device, the substrate may include a general area having a first resolution and an optical area having a resolution lower than the first resolution. In one or more aspects, the display device may include an optoelectronic device that overlaps with the optical area and is disposed beneath the substrate.

[0360] In one or more aspects, in a display device, at least one light-emitting element may be disposed in a general area.

[0361] In one or more aspects, in a display device, at least one light-emitting element may be disposed in an optical region.

[0362] According to one or more aspects described herein, a display device may be provided, the display device including a light-transmitting structure that enables at least one optical electronic device disposed below or at the bottom of a display panel to normally receive light (e.g., visible light, infrared light, ultraviolet light, etc.) without being exposed in front of the display device.

[0363] According to one or more aspects described herein, a display device may be provided that is capable of full-screen display by using the entire display area of ​​a display panel as a display screen through a structure comprising at least one optical electronic device configured to overlap with and be located below the display area.

[0364] According to one or more aspects described herein, a display device may be provided that is capable of preventing or reducing the presence of residual light by including a structure that forms a hole movement path in the light-emitting element.

[0365] According to one or more aspects described herein, a display device may be provided that is capable of preventing or reducing failure of one or more optical sensors by including a structure that forms a hole movement path in a light-emitting element.

[0366] According to one or more aspects described herein, a display device may be provided that is capable of improving the sensing efficiency of one or more optical sensors for external light by including a structure that forms a hole movement path in a light-emitting element.

[0367] According to one or more aspects described herein, a display device may be provided that can improve the reliability of light-emitting elements by reducing brightness degradation and shortening the lifespan of light-emitting elements in the display area.

[0368] According to one or more aspects described herein, a display device may be provided that can achieve high efficiency, increased lifespan, and low power consumption by reducing brightness degradation in the display area and shortening the lifespan of the light-emitting elements.

[0369] The above description has been presented to enable any person skilled in the art to make, use, and practice the technical features of this disclosure, and has been provided as examples in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The above description and accompanying drawings are provided for illustrative purposes only, illustrating the technical ideas of this disclosure. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of this disclosure.

Claims

1. A display device, comprising: Multiple light-emitting elements are disposed on a substrate. At least one of the plurality of light-emitting elements includes: A first electrode is disposed on the substrate; A hole transport layer is disposed on the first electrode; An electron blocking layer is disposed on the hole transport layer; An emission layer disposed on the electron blocking layer and having a width greater than that of the electron blocking layer; and The second electrode is disposed on the emission layer.

2. The display device according to claim 1, wherein, The highest occupied molecular orbital (HOMO) energy level of the electron blocking layer is lower than the HOMO energy level of the emission layer.

3. The display device according to claim 2, wherein, In the display device, the following equation 1 is satisfied. Equation 1: |H1-H2|>|H1-H4| Wherein, H1 is the HOMO level of the emitter layer, H2 is the HOMO level of the electron blocking layer, and H4 is the HOMO level of the hole transport layer.

4. The display device according to claim 1, wherein, The emission layer is configured to cover the electron blocking layer and contact the hole transport layer.

5. The display device according to claim 4, wherein, The light-emitting element further includes a hole auxiliary layer disposed between the hole transport layer and the electron blocking layer, and The emission layer is configured to cover the electron blocking layer and the hole assist layer, and to contact the hole transport layer.

6. The display device according to claim 5, wherein, The width of the hole-assist layer is the same as the width of the electron-blocking layer.

7. The display device according to claim 6, wherein, The emission layer is configured to cover the upper surface and at least one side surface of the electron blocking layer, and at least one side surface of the hole auxiliary layer, and to contact the hole transport layer.

8. The display device according to claim 5, wherein, The width of the emitter layer is greater than the width of the hole-assisted layer, and the width of the hole-assisted layer is greater than the width of the electron-blocking layer.

9. The display device according to claim 8, wherein, The emission layer is configured to cover the upper surface and at least one side surface of the electron blocking layer, a portion of the upper surface and at least one side surface of the hole auxiliary layer, and to contact the hole transport layer.

10. The display device according to claim 5, wherein, In the display device, the following equation 2 is satisfied. Equation 2: |H1-H2|>|H1-H3| Wherein, H1 is the HOMO level of the emitter layer, H2 is the HOMO level of the electron blocking layer, and H3 is the HOMO level of the hole-assisted layer.

11. The display device according to claim 1, wherein, The light-emitting element further includes a hole auxiliary layer disposed between the hole transport layer and the electron blocking layer, and the width of the hole auxiliary layer is greater than the width of the electron blocking layer.

12. The display device according to claim 11, wherein, The emission layer is configured to cover the electron blocking layer and contact the hole assist layer.

13. The display device according to claim 11, wherein, The width of the hole auxiliary layer is the same as the width of the emission layer.

14. The display device according to claim 13, wherein, The emission layer is configured to cover the upper surface and at least one side surface of the electron blocking layer, and to contact at least a portion of the upper surface of the hole assist layer.

15. The display device according to claim 11, wherein, The width of the hole auxiliary layer is greater than the width of the emission layer.

16. The display device according to claim 15, wherein, The emission layer is configured to cover the upper surface and at least one side surface of the electron blocking layer, and to contact the inner portion of at least one end of the upper surface of the hole assist layer.

17. The display device according to claim 1, further comprising a hole blocking layer disposed on the emitting layer, in, The hole blocking layer is configured to cover the emission layer and contact the hole transport layer.

18. The display device according to claim 1, wherein, The substrate includes a general area having a first resolution and an optical area having a resolution lower than the first resolution, and an optoelectronic device overlaps with the optical area and is disposed below the substrate.

19. The display device according to claim 18, wherein, The at least one light-emitting element is disposed in the ordinary area.

20. The display device according to claim 18, wherein, The at least one light-emitting element is disposed in the optical region.

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