Oxidation-induced lattice softening etching method and patterning method of metal chalcogenide layer and method for constructing transistor device

Abstract

This invention relates to an oxidation-induced lattice softening etching method and patterning method for metal chalcogenide layers, and a method for fabricating transistor devices. The oxidation-induced lattice softening etching method of this invention includes: (A1) plasma treatment of the metal chalcogenide layer in an atmosphere containing O2 and / or O3, wherein the metal chalcogenide layer contains a metal chalcogenide compound that produces a non-volatile etching residue in any atomic layer etching method, and is composed of the formula XY. n The method is defined as follows: X is a metallic element, Y is sulfur, selenium, or tellurium, and n is 1 to 4; (A2) Plasma etching is performed on the oxidized metal chalcogenide layer in an inert rare gas atmosphere, wherein the etching power is lower than the threshold power required for plasma etching of the exposed, unoxidized substrate in the same atmosphere. The patterning method and transistor device fabrication method of the present invention are based on this etching method.

Description

TECHNICAL FIELD

[0001] The present application relates to an oxidation-induced lattice softening etching method of a metal chalcogenide layer, a patterning method and a transistor device construction method. BACKGROUND

[0002] With Moore's Law approaching the physical and power consumption limits, the development of low-dimensional new materials and new device architectures for the post-Moore era has become one of the important directions in the field of microelectronics. Transition metal dichalcogenides (TMDs) represented by platinum diselenide (PtSe2) are considered as key candidate materials for the next generation of high-performance optoelectronic and nanoelectronic devices due to their tunable energy bands, high mobility and high compatibility with silicon-based CMOS (Complementary Metal Oxide Semiconductor, CMOS) processes. However, to fully realize the device potential of PtSe2, nanometer patterning with atomic-level precision and construction of high-quality interfaces are prerequisites for its integration into high-performance devices. Among them, how to achieve high-precision patterning while considering the cleanliness of the substrate surface and the integrity of the lattice / interface, eliminating chemical residues and potential damage, is still a core challenge.

[0003] In particular, as the feature size of advanced micro-nano devices enters the sub-10 nm or even approaches the "atomic level" control requirement, the etching process not only needs to meet the geometric precision, but also needs to control the surface defects and damage.

[0004] The current mainstream dry etching usually uses reactive ion etching (RIE), which belongs to "continuous etching". However, in RIE, under the joint action of ions / neutral particles / reactive products and substrate atoms, a mixed layer is easily formed at the interface, which in turn leads to etching rate fluctuations, increased surface roughness or non-volatile residues, thereby reducing etching precision. For example, in the PtSe2 system, the non-volatility of Pt-based oxidation or halogenation reaction products makes this problem particularly prominent: the residual PtOx and other by-products cannot be removed by conventional gasification, seriously polluting the etching interface, resulting in the inability to obtain an atomic-level clean etching surface, which becomes a bottleneck for high-density integration of PtSe2 devices.

[0005] To improve precision and reduce damage, atomic layer etching (ALE) is proposed: (1) first modify the outermost layer of atoms with a self-limiting precursor to reduce their adhesion to the substrate; (2) then remove the modified layer by generating volatile products (thermal ALE) or low-energy ion / neutral beam bombardment (plasma ALE).

[0006] Plasma-based etching (ALE) primarily relies on chlorine gas or fluorocarbons (directly or via plasma activation) to modify the thin film, reducing the adsorption of the substrate by the material to be etched. Ar particles or neutral particles are then used to bombard the modified layer. Therefore, it lacks intrinsic selectivity for different materials. Intrinsic etching selectivity is defined as the ability of ALE to etch only specific materials under a certain mechanism, while having no etching effect on other materials. Therefore, the lack of intrinsic selectivity is a disadvantage for the fabrication of advanced micro / nano devices that require high etching precision.

[0007] By utilizing different reaction mechanisms, thermal ALE can more easily achieve intrinsic etching selectivity between different materials. However, as mentioned above, thermal ALE strongly depends on the generation of volatile products during the etching process.

[0008] However, taking the PtSe2 system as an example, on the one hand, as mentioned above, the products of Pt-based oxidation or halogenation reactions are non-volatile. On the other hand, the interfacial binding energy between Pt-based oxides (PtOx) and the PtSe2 substrate is extremely strong (DFT calculations show that the PtO2 / PtSe2 binding energy is on the order of -4 eV). Therefore, at conventional process temperatures, these products neither volatilize nor readily desorb from the substrate, making the aforementioned ALE scheme have an extremely narrow process window or even become completely ineffective in the PtSe2 system.

[0009] As can be understood from the above, traditional atomic layer etching (ALE) methods are also difficult to handle for high-precision, high-selectivity etching of two-dimensional metal chalcogenides, whose etching byproducts are non-volatile, strongly adsorbed, and thermally stable.

[0010] It is evident that for traditional etching of metal chalcogenides such as PtSe2, which produce non-volatile residues, the traditional approach relying on the "evaporation / desorption" path often fails to obtain high-resolution pattern transfer windows with no residue and low damage, thus facing the dilemma of "substrate lattice damage" and "interfacial physical adsorption".

[0011] In addition, pure Ar physical sputtering (unmodified) can avoid volatility dependence, but it requires high-energy / high-dose ion bombardment, which causes severe lattice damage to the substrate.

[0012] In addition, the method of relying on high-energy / high-dose ion bombardment is incompatible with the tolerance of photoresist masks with sub-20nm feature size, making it difficult to simultaneously ensure the complete transfer of ultra-fine linewidth patterns and the cleanliness of the interface. Summary of the Invention

[0013] <<The Problem the Invention Aims to Solve>>

[0014] Given the above, for high-precision and highly selective etching, it is necessary to solve problems such as the difficulty in removing non-volatile residues, unclean etching interfaces, excessive damage from high-energy sputtering, and difficulty in high-resolution nanopatterning.

[0015] Therefore, the purpose of this invention is to provide an oxidation-induced lattice softening etching method for metal chalcogenide layers. This method effectively overcomes the problem of difficulty in removing non-volatile etching residues in the above-mentioned traditional etching methods (such as RIE, ALE, pure physical sputtering, etc.), can obtain atomically clean etching interfaces and suppress substrate damage, and has good compatibility with photoresists. Moreover, this method is simple to operate and suitable for large-scale industrial production.

[0016] In addition, the present invention aims to provide a clean patterning method for metal chalcogenide layers. This method can obtain an atomically clean substrate etching interface and suppress substrate damage during the etching of metal chalcogenide layers. It is also suitable for high-resolution patterning and is simple to operate, making it suitable for large-scale industrial production.

[0017] Another objective of this invention is to provide a method for constructing a transistor device.

[0018] <<Solutions for Problem Solving>>

[0019] Through the inventor's dedicated research, the following technical solution was discovered that can achieve the above-mentioned technical objectives of this invention.

[0020] [1]. An oxidation-induced lattice softening etching method for metal chalcogenide layers, the method comprising:

[0021] (A1) Oxidation pretreatment step: The metal chalcogenide layer is subjected to plasma treatment in an atmosphere containing oxygen (O2) and / or ozone (O3).

[0022] The metal chalcogenide compound contained in the metal chalcogenide layer is a compound that produces non-volatile etching residues in any atomic layer etching method, and is composed of the formula XY. n It is indicated that X is a metallic element, Y is sulfur, selenium or tellurium, and n is 1 to 4;

[0023] (A2) Physical sputtering step: Plasma etching of the oxidized metal chalcogenide layer in an inert rare gas atmosphere, wherein the etching power is lower than the threshold power required for plasma etching of the exposed, unoxidized substrate in the same atmosphere.

[0024] [2]. According to the oxidation-induced lattice softening etching method described in [1], X is at least one of nickel (Ni), palladium (Pd), platinum (Pt), cobalt (Co), rhodium (Rh), iridium (Ir), iron (Fe), osmium (Os), rhenium (Re), chromium (Cr), tin (Sn), or indium (In).

[0025] [3]. The oxidation-induced lattice softening etching method according to [1] or [2], wherein the metal chalcogenide compound is at least one selected from PtS2, PtSe2, PtTe2, PdS2, PdSe2, PdTe2, NiSe2, NiTe2, CoSe2, CoTe2, FeTe2, IrS2, IrSe2, ReSe2, RhS2, RhSe2, CrS2, CrSe2, SnS2, or In2Se3.

[0026] [4]. The oxidation-induced lattice softening etching method according to any one of [1] to [3], wherein the thickness of the metal chalcogenide layer is a single-atom layer thickness to 15 atomic layers thickness.

[0027] [5]. The oxidation-induced lattice softening etching method according to any one of [1] to [4], wherein in the (A1) oxidation pretreatment step, the processing power is 5 to 500 W and the processing time is 1 to 200 seconds.

[0028] [6]. The oxidation-induced lattice softening etching method according to any one of [1] to [5], wherein, in the (A2) physical sputtering removal step, the lower limit of the etching power is 10W and the etching time is 5 seconds to 20 minutes.

[0029] [7]. The oxidation-induced lattice softening etching method according to any one of [1] to [6], wherein the root mean square roughness of the substrate obtained after etching in steps (A1) and (A2) is less than 0.3 nm.

[0030] [8]. A method for patterning a metal chalcogenide layer, comprising:

[0031] (B1) A photoresist layer is formed on the metal chalcogenide compound layer, and the photoresist layer is exposed and developed according to the desired pattern to form a photoresist mask.

[0032] (B2) According to the pattern of the photoresist mask, the exposed metal chalcogenide layer is etched by the oxidation-induced lattice softening etching method according to any one of [1] to 7.

[0033] [9]. According to the patterning method described in [8], the pattern is a nanoscale stripe array pattern, and the width of the stripes of the nanoscale stripe array pattern is at least 20 nm.

[0034]

[10] . A method for constructing a transistor device, comprising:

[0035] (C1) An oxide insulating layer is formed on the silicon wafer;

[0036] (C2) A metal chalcogenide layer as a channel material is formed on the oxide insulating layer;

[0037] (C3) The metal chalcogenide layer is patterned by the patterning method described in [8] or [9], and the source and drain patterns are defined;

[0038] (C4) The source and drain are formed by depositing metal, respectively.

[0039] <<The Effects of the Invention>>

[0040] This invention provides an innovative "Oxidation-Mediated Physical Sputtering" (OMPS) method, which enables high-quality etching of metal chalcogenide layers.

[0041] The OMPS method of this invention fundamentally bypasses the dependence on "volatile products" by decoupling the two processes of "lattice oxidation reconstruction" and "physical sputtering removal" in time from a physical mechanism perspective, thereby achieving highly selective etching and realizing atomically clean etching interfaces while simultaneously meeting the process requirements of low substrate damage and high resolution.

[0042] Specifically, the surface bonding characteristics are first induced to soften the lattice by oxidation treatment, so that the lattice structure of the originally chemically inert metal chalcogenide compound is reconstructed in situ into a structurally metastable "sacrificial oxide layer", which reduces the lattice stability of the layer surface and thus significantly reduces the etching energy required for the sacrificial oxide layer relative to the substrate; then, low-energy ion sputtering is used to selectively remove the sacrificial layer.

[0043] Here, the term "substrate" refers to the base material exposed after the etched sacrificial layer. It can be a substrate that differs in composition from the metal chalcogenide layer, or the metal chalcogenide itself if the metal chalcogenide layer has a thickness of more than two atomic layers.

[0044] Therefore, the present invention achieves the following three effects.

[0045] (1) Achieve atomically clean etching interface and completely eliminate non-volatile residues. Traditional RIE or ALE cannot achieve a clean interface due to non-volatile residues; however, OMPS can completely sputter away the sacrificial oxide layer by physical bombardment with low-energy Ar ions without relying on product volatilization, thus ensuring atomically clean etching interface from a mechanism perspective, providing a high-quality interface foundation for subsequent device processes.

[0046] (2) Significantly reduces physical damage and protects the intrinsic properties of two-dimensional materials. Since the oxidation step significantly weakens the surface bonding stability of the layer to be etched (at least partially converting the strong covalent bonds of XY into weak bonds of XO), the ion energy required for subsequent sputtering is far lower than the threshold required by traditional physical sputtering. This effectively avoids the penetration damage of high-energy ions to the next layer of the lattice (substrate lattice), protecting the intrinsic electrical properties and lattice integrity of the two-dimensional material. For example, the root mean square roughness of the etched interface obtained after etching can reach below 0.5 nm, and even in the embodiments described later in this invention, the root mean square roughness can reach 0.18 nm.

[0047] (3) Achieve high-resolution patterning while maintaining excellent photoresist compatibility. Due to the low energy required for sputtering, the photoresist mask can maintain good structural integrity throughout the etching process, demonstrating excellent compatibility with mainstream photolithography processes.

[0048] Furthermore, based on the OMPS scheme, this invention also provides a pattern transfer method for metal chalcogenide layers. Since the OMPS scheme is photoresist-friendly, this method is particularly suitable for forming nanoscale patterns at high resolution, for example, achieving sub-20nm ultra-high resolution patterning in the formation of nanoscale stripe array patterns.

[0049] Moreover, this method is simple to operate and suitable for large-scale industrial production, laying a solid technological foundation for the large-scale and high-density integration of two-dimensional material devices. Based on this, the present invention also provides a method for constructing transistor devices. Attached Figure Description

[0050] Figure 1 The process of the oxidation-induced lattice softening etching method of the present invention is illustrated using PtSe2 as an example.

[0051] Figure 2 The process of the patterning method of the present invention is illustrated by way of example.

[0052] Figure 3 An example of the structure of the transistor device of the present invention is shown in the figure.

[0053] Figure 4 The image shows an optical microscope (a) and an atomic force microscope (b) image of the transferred bilayer PtSe2 continuous film.

[0054] Figure 5 An atomic force microscope image of the SiO2 / Si substrate before transfer is shown.

[0055] Figure 6 The image shows atomic force microscopy (AFM) images and XPS spectra of the etched interfaces of the etched products in Examples 1-1 and 1-2 ((a): 60s, (b): 90s; (c) to (d) are Pt 4f high-resolution XPS spectra of the samples corresponding to (a) to (b); (e) to (f) are Se 3d high-resolution XPS spectra of the samples corresponding to (a) to (b).

[0056] Figure 7 The image shown is an atomic force microscope photograph of the etched interface of the etched product of Comparative Example 1-1.

[0057] Figure 8 The image shows atomic force micrographs of the etched interfaces of the etched products of Comparative Examples 1-2.

[0058] Figure 9 The images shown are atomic force microscopy and SEM images of the etching products obtained in Examples 2-1 to 2-3 (a to c), which are the AFM morphologies of PtSe2 nanoribbons with nominal linewidths of 20 nm, 50 nm and 100 nm, respectively.

[0059] Figure 10 The figure shows the transfer characteristic curve and output characteristic curve of the field-effect transistor obtained in Embodiment 3 of the present invention. Detailed Implementation

[0060] Various exemplary embodiments, features, and aspects of the present invention will be described in detail below. The term "exemplary" as used herein means "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0061] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art should understand that the present invention can be practiced without certain specific details. In other instances, methods, means, apparatus, and steps well known to those skilled in the art have not been described in detail in order to highlight the spirit of the present invention.

[0062] Unless otherwise stated, all units used in this specification are international standard units, and all numerical values ​​and ranges appearing in this invention should be understood to include systematic errors that are unavoidable in industrial production.

[0063] In this specification, the word "may" has two meanings: to perform a certain process and not to perform a certain process.

[0064] In this specification, references to "some specific / preferred embodiments," "other specific / preferred embodiments," "implementation," etc., refer to specific elements (e.g., features, structures, properties, and / or characteristics) related to that embodiment, which are included in at least one of the embodiments described herein and may or may not be present in other embodiments. Furthermore, it should be understood that these elements may be combined in any suitable manner in various embodiments.

[0065] In this specification, the numerical range referred to as "value A to value B" refers to the range including endpoint values ​​A and B. The numerical range referred to as "above" and "below" refers to the range including endpoint values. The numerical range referred to as "greater than" and "less than" refers to the range excluding endpoint values.

[0066] In this specification, "optional" or "optionally" means that the event or situation described below may or may not occur, and the description includes both the scenario in which the event occurs and the scenario in which the event does not occur.

[0067] <<Oxidation-Induced Lattice Softening Etching Method for Metal Chalcogenide Layers>>

[0068] The oxidation-induced lattice softening etching method of the present invention includes: (A1) an oxidation pretreatment step: plasma treatment of the metal chalcogenide layer in an atmosphere containing oxygen (O2) and / or ozone (O3); and (A2) a physical sputtering step: plasma etching of the oxidized metal chalcogenide layer in an inert rare gas atmosphere, wherein the etching power is lower than the threshold power required for plasma etching of the exposed, unoxidized substrate in the same atmosphere.

[0069] Figure 1 The process of the oxidation-induced lattice softening etching method of the present invention is illustrated using PtSe2 as an example. From... Figure 1 As can be seen, during the lattice oxidation and reconstruction stage, the surface Se is preferentially oxidized to volatile SeO2 and spontaneously desorbed and discharged from the cavity, while the surface Pt is oxidized to non-volatile PtOx (including PtO, PtO2 and other forms).

[0070] Furthermore, there are no particular limitations on the thickness of the metal chalcogenide layer; for example, the thickness of the metal chalcogenide layer can be from a single atomic layer to 15 atomic layers. When the thickness is greater than 2 atomic layers, the above steps (A1) and (A2) can be repeated sequentially multiple times as needed until the target etching depth is reached.

[0071] The steps will be described in more detail below.

[0072] <Step (A1)>

[0073] In step (A1), the metal chalcogenide layer is subjected to plasma treatment in an atmosphere containing oxygen (O2) and / or ozone (O3).

[0074] In this invention, the metal chalcogenide compound contained in the metal chalcogenide layer is a compound that produces non-volatile etching residues in any atomic layer etching method, and is composed of the formula XY. n The symbol indicates that X is a metallic element, Y is sulfur (S), selenium (Se) or tellurium (Te), and n is 1 to 4.

[0075] Here, the term "generating non-volatile etching residues in any atomic layer etching method" refers to the fact that in conventional atomic layer etching (ALE) methods, the products obtained when modifying a metal chalcogenide layer are non-volatile, including, but not limited to, oxides and / or halides of metal X. That is, the present invention can be widely used to generate the aforementioned non-volatile etching residues from formula XY. n In the etched object.

[0076] In some specific embodiments, X is preferably at least one of nickel (Ni), palladium (Pd), platinum (Pt), cobalt (Co), rhodium (Rh), iridium (Ir), iron (Fe), osmium (Os), rhenium (Re), chromium (Cr), tin (Sn), or indium (In).

[0077] In some specific implementation schemes, n is preferably 1 to 2.

[0078] As non-limiting examples, examples of metal chalcogenides may include PtS2, PtSe2, PtTe2, PdS2, PdSe2, PdTe2, NiSe2, NiTe2, CoSe2, CoTe2, FeTe2, IrS2, IrSe2, ReSe2, RhS2, RhSe2, CrS2, CrSe2, SnS2, In2Se3, etc.

[0079] The metal chalcogenide layer can be formed from one metal chalcogenide or from two or more metal chalcogenides. Examples of layers formed from two metal chalcogenides include IrS2 / IrSe2, RhS2 / RhSe2, and CrS2 / CrSe2.

[0080] Particularly preferred is that the metal chalcogenide compound is at least one selected from PtSe2 and PdSe2.

[0081] In the following embodiments, PtSe2 was used as the etching target to illustrate the effect of the present invention, but it can be understood from the above description that the present invention is not limited thereto.

[0082] In addition, the metal chalcogenide layer of the present invention can be formed on a substrate with a different composition as needed.

[0083] There are no particular restrictions on the materials used to form the substrate. For example, it can be ceramic materials other than metal chalcogenides, carbon materials, metal materials, glass, semiconductor substrate materials such as silicon wafers and / or their oxide materials, metal oxides such as alumina and hafnium oxide, and polymer materials such as polyethylene terephthalate, polyethylene naphthalate, polyethylene, and polycarbonate.

[0084] There are no particular limitations on the method for forming a metal chalcogenide layer on a substrate; for example, methods known in the art, such as deposition or transfer methods, can be used.

[0085] After step (A1), the metal chalcogenide layer is treated with an oxygen-containing source. By volatile oxidative removal of Y and oxidative reconstruction of X in the metal chalcogenide on the surface, the surface layer (typically about a single-atom layer thickness) of the chemically inert metal chalcogenide layer is transformed in situ into a structurally metastable X oxide sacrificial layer (e.g., for PtSe2, from strong Pt-Se bonds to weak Pt-O bonds), which significantly reduces the thermodynamic energy barrier for subsequent physical sputtering removal.

[0086] There are no particular limitations on the atmospheric composition of step (A1), as long as the aforementioned X oxide sacrificial layer can be formed and contains oxygen (O2) and / or ozone (O3). In some specific embodiments, the atmosphere of step (A1) may contain inert rare gases, such as argon (Ar), neon (Ne), krypton (Kr), etc.

[0087] In step (A1), in some preferred embodiments, the processing power is preferably 5–500 W, more preferably 10–500 W, and even more preferably 50–150 W. Here, processing power refers to the plasma power of a gas containing oxygen (O2) and / or ozone (O3). By keeping the processing power within the preferred range, the oxidation rate and the thickness of the oxide sacrificial layer can be better controlled.

[0088] In step (A1), in some preferred embodiments, the processing time is preferably 1 to 200 seconds, more preferably 10 to 200 seconds, and even more preferably 20 to 50 seconds. By keeping the processing time within the preferred range, the depth of modification in a single step can be better controlled.

[0089] In some specific implementations, step (A1) can be performed by placing the object to be treated with a metal chalcogenide layer in a plasma reaction chamber, introducing an atmosphere containing oxygen (O2) and / or ozone (O3), and oxidizing the exposed surface of the metal chalcogenide layer.

[0090] In the use of a plasma reaction chamber, in some preferred embodiments, the total flow rate of the atmospheric gas can be, for example, 5 to 50 sccm. In other preferred embodiments, the chamber pressure of the plasma reaction chamber can be, for example, 0.5 to 30 mTorr.

[0091] Furthermore, in the case of using a plasma reaction chamber, in some preferred embodiments, the fixed ICP source power can be, for example, 0–300 W. In other preferred embodiments, the RF bias power can be, for example, 5–200 W.

[0092] <Step (A2)>

[0093] In step (A2), the oxidized metal chalcogenide layer is plasma etched in an inert rare gas atmosphere, wherein the etching power is lower than the threshold power required to plasma etch the exposed, unoxidized substrate in the same atmosphere.

[0094] In this invention, the substrate forming material can be an unoxidized metal chalcogenide (which may have the same or different composition as the metal chalcogenide that is etched away), or it can be the aforementioned unoxidized substrate that has a different composition from the metal chalcogenide layer and is covered by the metal chalcogenide layer.

[0095] Details of the metal chalcogenide compound used as the substrate are as described in step (A1) above.

[0096] By using step (A2), a lower sputtering threshold power than that of the original unoxidized metal chalcogenide compound or substrate in the same atmosphere is used, thus enabling highly efficient selective sputtering removal of the oxide sacrificial layer while protecting the unoxidized substrate lattice from damage.

[0097] There are no particular restrictions on the composition of the atmosphere in step (A2), as long as it is an atmosphere consisting only of inert rare gases. In some preferred embodiments, the atmosphere gas in step (A2) is preferably at least one of argon (Ar), neon (Ne), and krypton (Kr), more preferably argon (Ar).

[0098] In step (A2), in some preferred embodiments, in order to more easily etch the sacrificial layer, the lower limit of the etching power is preferably 10W, more preferably 50W.

[0099] In some preferred embodiments, the etching power is preferably 80–150 W, more preferably 100–120 W. Here, etching power refers to the ion energy of the inert rare gas plasma. By keeping the processing power within the preferred range, etching selectivity can be better ensured.

[0100] In step (A2), the etching time is not particularly limited and can be varied according to the scale of the operation, as long as the sacrificial layer is removed. In some preferred embodiments, the etching time is preferably 5 seconds to 20 minutes, more preferably 30 seconds to 20 minutes, and even more preferably 60 seconds to 5 minutes.

[0101] In some specific implementations, step (A2) can be performed as follows: in the plasma reaction chamber, after oxidizing the surface of the metal chalcogenide layer, the atmosphere is switched, an inert rare gas is introduced, and an inert rare gas plasma is excited under low bias conditions to perform directional physical bombardment of the sacrificial layer with low-energy ions.

[0102] In the use of a plasma reaction chamber, in some preferred embodiments, the total flow rate of the atmospheric gas can be, for example, 5 to 50 sccm. In other preferred embodiments, the chamber pressure of the plasma reaction chamber can be, for example, 0.5 to 30 mTorr.

[0103] Furthermore, in the case of using a plasma reaction chamber, in some preferred embodiments, the fixed ICP source power can be, for example, 0–300 W. In other preferred embodiments, the RF bias power can be, for example, 5–200 W.

[0104] In step (A2), highly selective and efficient sputtering removal of the non-volatile sacrificial layer is achieved, while the physical damage to the underlying substrate lattice is effectively suppressed due to the low energy, thereby exposing an atomically clean etched interface. The root mean square roughness of the substrate obtained after etching in steps (A1) and (A2) varies depending on the substrate composition and lattice structure. However, in some preferred embodiments, the root mean square roughness of the substrate obtained after etching is preferably below 0.5 nm, more preferably below 0.4 nm, further preferably below 0.3 nm, and even more preferably below 0.2 nm.

[0105] <<Patterning Methods for Metal Chalcogenide Layers>>

[0106] The patterning method for the metal chalcogenide layer of the present invention includes: (B1) forming a photoresist layer on the metal chalcogenide layer, exposing and developing the photoresist layer according to a desired pattern to form a photoresist mask; (B2) etching the exposed metal chalcogenide layer according to the pattern of the photoresist mask by means of the oxidation-induced lattice softening etching method of the present invention.

[0107] The patterning method of the present invention is implemented based on the oxidation-induced lattice softening etching method of the present invention. It can be etched using low-energy sputtering, thus exhibiting excellent compatibility with photoresist masks, especially with high-resolution photoresist processes.

[0108] Figure 2 The process of the patterning method of the present invention is illustrated by way of example.

[0109] In this invention, there are no particular limitations on the shape of the pattern, which can be appropriately adjusted according to the application field. In some specific embodiments, the pattern can be a nanoscale stripe array pattern.

[0110] The patterning method of this invention can preferably achieve a minimum stripe width of 20 nm in the obtained nanoscale stripe array pattern, meaning that the patterning method of this invention can achieve a pattern with a minimum feature linewidth of 20 nm. However, it is clearly understood that the patterning method of this invention is not actually limited to this minimum feature linewidth, and smaller sizes can be achieved depending on the precision and capability of the EBL equipment used.

[0111] In some specific implementations, as described above, a metal chalcogenide layer may be formed on the substrate.

[0112] The steps will be described in more detail below.

[0113] <Step (B1)>

[0114] In step (B1), a photoresist layer is formed on the metal chalcogenide compound layer, and the photoresist layer is exposed and developed according to the desired pattern to form a photoresist mask.

[0115] There are no particular restrictions on the type of photoresist; it can be either positive or negative. Specifically, various commercially available photoresist products can be used. Positive photoresist, i.e., a photoresist that exhibits excellent insolubility before exposure and becomes soluble after exposure, is preferred.

[0116] The formation, exposure, and development of photoresist can each be performed using various methods known in the art.

[0117] One method for forming a photoresist layer on a metal chalcogenide layer is to coat the metal chalcogenide layer with photoresist and then cure it.

[0118] Photoresist can be coated onto a metal chalcogenide layer using coating methods known in the art. Examples of coating methods include, but are not limited to, dip coating, spin coating, bar coating, blade coating, curtain coating, screen printing, spray coating, slot coating, etc. These methods can be used alone or in combination of two or more. Spin coating is preferred.

[0119] Photoresist can be cured by methods such as heat curing, ultraviolet light curing, and / or visible light curing. The curing method varies depending on the type of photoresist.

[0120] There are no particular restrictions on the exposure method for photoresist cured materials. Exposure light can be injected through a mask, or exposure light can be injected directly according to the desired pattern without using a mask.

[0121] There are no particular restrictions on the exposure light; it can be varied according to actual needs. Examples of exposure light include, but are not limited to, visible light, ultraviolet light, X-rays, electron beams, ion beams, etc.

[0122] Exposure apparatuses can use a variety of devices known in the art, such as contact aligners, mirror projection, stepper exposure machines, and direct laser exposure apparatuses.

[0123] There are no particular restrictions on the developing method; any method known in the art may be used. Examples of developing methods include, but are not limited to, dip coating (optionally, this may be performed under ultrasonic irradiation), spin coating, spray coating, etc. These methods may be used alone or in combination of two or more.

[0124] There are no particular restrictions on the composition of the developer. It is usually adjusted according to the composition of the photoresist used. It can be an alkaline aqueous solution or a developer containing organic solvents.

[0125] Examples of alkaline substances contained in alkaline aqueous solutions include, but are not limited to: inorganic bases such as sodium hydroxide, sodium carbonate, sodium silicate, and ammonia; organic amines such as ethylamine, diethylamine, triethylamine, and triethanolamine; and quaternary ammonium salts such as tetramethylammonium hydroxide and tetrabutylammonium hydroxide.

[0126] Examples of developers containing organic solvents include, but are not limited to: ketones such as butanone; amide solvents such as N,N-dimethylformamide and N,N-dimethylacetamide; ether solvents such as propylene glycol methyl ether; mixed solvents of isopropanol and methyl isobutyl ketone; mixed solvents of isopropanol and water, etc.

[0127] In some specific implementations, step (B1) is performed as follows: a photoresist is coated onto a metal chalcogenide layer and cured by heating, followed by electron beam exposure and development using a developer containing an organic solvent.

[0128] In electron beam lithography, polymethyl methacrylate (PMMA) photoresist is preferred.

[0129] There are no particular limitations on the heat curing method; methods such as blowing heat, oven heating, and heating plate heating can be used. In some more specific embodiments, the curing temperature can be appropriately selected according to the composition of the photoresist, but is preferably 60–200°C, more preferably 75–150°C, and even more preferably 85–120°C. The curing time is typically 10 seconds to 60 minutes, preferably 30 seconds to 15 minutes, and more preferably 1 minute to 10 minutes.

[0130] Alternatively, the exposed product is preferably immersed in a developing solution containing an organic solvent for development.

[0131] <Step (B2)>

[0132] In step (B2), the exposed metal chalcogenide layer is etched according to the pattern of the photoresist mask using the oxidation-induced lattice softening etching method described above according to the present invention. Details of the oxidation-induced lattice softening etching method of the present invention have been described above and will not be repeated here.

[0133] <Step (B3)>

[0134] The patterning method of the present invention may also include step (B3) as needed.

[0135] In step (B3), the residual photoresist mask is removed. There are no particular limitations on the removal method; various methods known in the art can be used.

[0136] In some specific implementations, the etched target with a residual photoresist mask and a metal chalcogenide layer can be immersed in a cleaning solution.

[0137] There are no particular restrictions on the type of cleaning solution, such as organic solvents.

[0138] Examples of organic solvents used as cleaning agents include, but are not limited to: ketones such as acetone; amide solvents such as N,N-dimethylformamide and N,N-dimethylacetamide; ether solvents such as tetrahydrofuran, diethyl ether, propylene glycol methyl ether, and anisole; aromatic hydrocarbon solvents such as toluene; halogenated hydrocarbon solvents such as chlorobenzene and chloroform; and ester solvents such as ethyl acetate. These organic solvents can be used alone or in combination of two or more.

[0139] <<Methods for Constructing Transistor Devices>>

[0140] The method for constructing a transistor device according to the present invention includes: (C1) forming an oxide insulating layer on a silicon wafer; (C2) forming a metal chalcogenide layer as a channel material on the oxide insulating layer; (C3) patterning the metal chalcogenide layer by the patterning method described above in the present invention, and defining the patterns of the source and drain; (C4) forming the source and drain by depositing metal, respectively.

[0141] Figure 3 An example of the structure of the transistor device of the present invention is shown in the figure.

[0142] The steps will be described in more detail below.

[0143] <Step (C1)>

[0144] In step (C1), an oxide insulating layer is formed on the silicon wafer that serves as a substrate.

[0145] There are no particular restrictions on the type of silicon wafer; it can be selected appropriately according to actual needs. For example, highly doped silicon substrates are used in the embodiments of the present invention.

[0146] There are no particular restrictions on the composition of the oxide insulating layer; it can be silicon dioxide or other high dielectric constant materials such as hafnium oxide or aluminum oxide. Preferably, the oxide insulating layer is a silicon dioxide insulating layer.

[0147] In addition, the oxide insulating layer can be a single layer or two or more layers.

[0148] There are no particular restrictions on the method for forming the oxide insulating layer; it can be selected appropriately based on the type of oxide. For example, thermal oxidation or deposition methods can be used.

[0149] In the thermal oxidation method, silicon wafers are placed in a high-temperature oxidation furnace, and a high-quality, dense silicon dioxide layer is grown on the surface of the silicon wafer in an oxygen or water vapor atmosphere.

[0150] In deposition methods, oxide layers can be deposited using methods such as atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0151] <Step (C2)>

[0152] In step (C2), a metal chalcogenide layer as a channel material is formed on the oxide insulating layer.

[0153] There are no particular restrictions on the method for forming the metal chalcogenide layer. The pre-formed metal chalcogenide layer can be placed onto a pre-marked silicon wafer with an oxide insulating layer via dry or wet transfer. Alternatively, large-area two-dimensional thin films can be grown directly on the silicon wafer with the oxide insulating layer using chemical vapor deposition.

[0154] In some preferred embodiments, the pre-formed metal chalcogenide layer is placed onto a pre-marked silicon wafer with an oxide insulating layer by dry transfer.

[0155] <Step (C3)>

[0156] In step (C3), the metal chalcogenide layer is patterned using the patterning method described above in this invention, and the source and drain patterns are defined.

[0157] The details of the patterning method of the present invention have been described above and will not be repeated here.

[0158] <Step (C4)>

[0159] In step (C4), the source and drain are formed by depositing metal, respectively. There are no particular limitations on the constituent materials of the source and drain; those known in the art can be used, such as titanium (Ti), aluminum (Al), tungsten (W), gold (Au), platinum (Pt), copper (Cu), molybdenum (Mo), chromium (Cr), and their alloys.

[0160] In addition, the source and drain can each be composed of one or more metal thin films.

[0161] There are no particular restrictions on the deposition method; for example, electron beam evaporation or thermal evaporation can be used to deposit metal thin films.

[0162] <Step (C5)>

[0163] The construction method of the present invention may also include step (C5) as needed.

[0164] In step (C5), a bottom gate electrode is formed on the silicon wafer serving as a substrate. In some specific embodiments, the bottom gate electrode may have an adhesion layer and a conductive layer sequentially from the substrate.

[0165] The materials used to form the adhesion layer include, but are not limited to, titanium (Ti) or chromium (Cr). The thickness of the adhesion layer can be, for example, 5–20 nm.

[0166] The materials used to form the conductive layer include, but are not limited to, gold (Au), platinum (Pt), nickel (Ni), or palladium (Pd). The thickness of the conductive layer can be, for example, 50–100 nm.

[0167] There are no particular restrictions on the method for forming the bottom gate electrode; any method known in the art can be used.

[0168] Additionally, when using a bottom gate electrode, step (C5) can be performed before or after step (C1). That is, the bottom gate electrode can be formed between the silicon wafer and the oxide insulating layer, or it can be formed on the surface of the silicon wafer with the oxide insulating layer.

[0169] When the bottom gate electrode is formed on the surface of a silicon wafer with an oxide insulating layer, an oxide insulating layer as a gate insulating layer is further formed on the surface of the bottom gate electrode away from the substrate. That is, the bottom gate electrode is formed between the oxide insulating layers above the silicon wafer.

[0170] In some specific implementations, such as those of the present invention, a highly doped silicon substrate (e.g., n-doped silicon) is used. ＋ In the case of (e.g., Si), the bottom gate electrode may not be used.

[0171] <Step (C6)>

[0172] The construction method of the present invention may also include step (C6) as needed.

[0173] In step (C6), residual photoresist mask is removed from the device where the source and drain electrodes have been formed. This photoresist mask mainly comes from the photoresist mask remaining during the patterning process in step (C3).

[0174] The details of the removal method are as described in the steps (B3) of the patterning method above, and will not be repeated here.

[0175] <Other Steps>

[0176] As needed, the construction method of the present invention may also include other steps, such as the step of leading out each gate electrode, the step of forming the top gate electrode, the step of removing the photoresist remaining during the formation of the bottom gate electrode, and the step of annealing the prepared device.

[0177] Example

[0178] The embodiments of the present invention will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of the invention. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer are followed. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0179] <Materials Used>

[0180] (1) A bilayer PtSe2 continuous film transferred onto a 100 nm SiO2 / Si substrate (a highly doped silicon wafer with silicon dioxide) was used as the base sample (provided by Shenzhen Six Carbon Technology Co., Ltd.). The initial thickness of the film was measured to be 3.4–3.9 nm by atomic force microscopy (AFM).

[0181] Figure 4 The image shows optical micrographs (a) and atomic force micrographs (b) of the transferred bilayer PtSe2 continuous film. Figure 4 As can be seen from the image, the PtSe2 film exhibits uniform contrast under an optical microscope, demonstrating good macroscopic continuity and uniformity. AFM analysis reveals a uniform surface morphology with minimal undulations, confirming the continuous coverage characteristic of the PtSe2 film. Furthermore, the mean square roughness R0 of the biatomic layer PtSe2 continuous film is... q It is 0.23nm.

[0182] Figure 5 The image shown is an atomic force microscopy photograph of the SiO2 / Si substrate before transfer. Figure 5 As can be seen from the figure, the mean square roughness R q It is 0.19nm.

[0183] (2) The photoresist used is polymethyl methacrylate (PMMA) photoresist (Allresist, AR-P 672.02).

[0184] <Etching Equipment>

[0185] Inductively Coupled Plasma (ICP) etching system (Oxford Instruments ICP 180). Basic process parameters were kept constant: chamber pressure of 5 mTorr, substrate temperature of 20 °C, and gas flow rate of 20 sccm.

[0186] <Evaluation Equipment>

[0187] The macroscopic uniformity and defect distribution of the samples were evaluated using an optical microscope (OM, Leica DM-6M).

[0188] Atomic force microscopy (AFM) is used to precisely measure film thickness, surface roughness, and the shape and size of nanopatterns.

[0189] The structural integrity and linewidth consistency of high-resolution images were characterized using a scanning electron microscope (SEM, HITACHI SU8600).

[0190] The surface electronic state evolution of Pt and Se was analyzed using Raman spectroscopy (XploRA) and X-ray photoelectron spectroscopy (XPS, Thermo Scientific™ ESCALAB™ 250Xi).

[0191] The transfer characteristic curve and output characteristic curve were determined using a semiconductor analyzer (Agilent B1500).

[0192] <Example 1-1 (OMPS Etching)>

[0193] The above-mentioned basic sample was placed in the plasma reaction chamber of an inductively coupled plasma (ICP) etching system, and pure O2 (20 sccm) was introduced for 40 s of oxidation pretreatment; then pure Ar (20 sccm) was switched to physical sputtering for 60 s to expose the SiO2 / Si substrate.

[0194] Throughout the OMPS process, the ICP source was turned off (0 W), and only a 100W RF bias voltage was applied.

[0195] <Example 1-2 (OMPS Etching)>

[0196] Except for the etching time of 90s for physical sputtering using pure Ar (20 sccm), OMPS etching was performed in the same manner as in Example 1-1.

[0197] <Comparative Example 1-1>

[0198] The aforementioned basic sample was placed in the plasma reaction chamber of an inductively coupled plasma (ICP) etching system, and physical sputtering was performed directly using pure Ar (20 sccm) to expose the SiO2 / Si substrate. The RF and ICP power were each 100W, and the time was 120s.

[0199] <Comparative Examples 1-2>

[0200] The aforementioned basic sample was placed in the plasma reaction chamber of an inductively coupled plasma (ICP) etching system and directly subjected to physical sputtering using a 1:1 mixture of pure Ar and O2 (total 20 sccm). The ICP power was 0 W, the RF power was 100 W, and the time was 120 s.

[0201] <Performance Evaluation 1>

[0202] The substrate surface (etching interface) exposed by etching in the etched products obtained in Examples 1-1 to 1-2 was observed using atomic force microscopy, and each etched product was evaluated by XPS. Figure 6The image shows atomic force microscopy (AFM) images and XPS spectra of the etched interfaces of the etched products in each embodiment ((a): 60s, (b): 90s; (c) to (d) are Pt 4f high-resolution XPS spectra of the samples corresponding to (a) to (b); (e) to (f) are Se 3d high-resolution XPS spectra of the samples corresponding to (a) to (b).

[0203] from Figure 6 As can be seen from the above, the root mean square roughness R of the etched interface obtained in Examples 1-1 to 1-2 is... q The surface roughnesses are 0.19 nm and 0.18 nm, respectively, which are very close to the root mean square surface roughness of the initial SiO2 / Si substrate (0.19 nm). No damage features such as particulate contamination, protrusions, or pits were observed.

[0204] from Figure 6 As can be seen, the Pt 4f of the samples obtained in Examples 1-1 to 1-2 7 / 2 With Pt 4f 5 / 2 No significant shift in peak position was observed, and no high binding energy shoulder peaks associated with typical oxidation states were found, indicating that the electronic states of surface Pt remained within the intrinsic Pt-Se bonding characteristic range after Ar ion sputtering removal. The PtO introduced during the O2 pretreatment step... x The residue was effectively removed. Meanwhile, the Pt 4f bimodal peaks associated with Pt were almost entirely absent in both the main plot and the magnified areas of the inset, indicating that they were effectively removed.

[0205] In addition, from Figure 6 As can be seen, the Se 3d signals of the samples obtained in Examples 1-1 to 1-2 are close to the detection limit, and no identifiable peak shape appears at the intrinsic binding energy, indicating that the Se-related components have been completely removed during O2 pretreatment and subsequent Ar ion sputtering, and no detectable Se element remains in the system.

[0206] As can be seen, all of the above embodiments can achieve highly selective etching of PtSe2, obtain atomically clean etching interfaces, and suppress substrate damage.

[0207] In addition to Examples 1-1 to 1-2 described above, the inventors also conducted a 120-second OMPS etching test. However, the XPS results showed that the Pt 4f bimodal signal was similar to that of Examples 1-1 and 1-2. Therefore, it can be concluded that Examples 1-1 and 1-2 have successfully achieved highly selective etching of PtSe2.

[0208] The substrate surface (etching interface) exposed by etching in the etching products obtained in Comparative Examples 1-1 to 1-2 was observed using an atomic force microscope. Figure 7The image shown is an atomic force microscope photograph of the etched interface of the etched product of Comparative Example 1-1. Figure 8 The image shows atomic force micrographs of the etched interfaces of the etched products of Comparative Examples 1-2.

[0209] from Figure 7 and Figure 8 As can be seen, the root mean square roughness R of the etched interface is... q The roughness values ​​were 0.28 nm and 0.25 nm, respectively, both higher than the root mean square roughness of the initial SiO2 / Si substrate (0.19 nm). It is evident that the cleanliness and damage suppression performance of the etched interfaces in Comparative Examples 1-1 to 1-2 were inferior to those in Examples 1-1 to 1-2.

[0210] <Example 2-1 (Patterning Method)>

[0211] (1) Formation of photoresist mask

[0212] First, polymethyl methacrylate (PMMA) photoresist was spin-coated onto the surface of the base sample and cured by baking at 180°C for 2 minutes. Then, it was exposed to electron beam lithography (EBL, Raith Voyager), followed by immersion in a developer (MIBK:IPA mixture (methyl isobutyl ketone: isopropanol)) for 60 seconds, then in isopropanol for 60 seconds, and finally dried. After development, a photoresist pattern with a nominal linewidth of 20 nm was obtained to form a photoresist mask.

[0213] (2) OMPS-based etching

[0214] For the sample with the photoresist mask formed, OMPS etching was performed in the same manner as in Example 3.

[0215] (3) Remove residual photoresist mask

[0216] The OMPS-etched sample was immersed in acetone for 10 minutes to completely remove residual photoresist.

[0217] <Example 2-2 (Patterning Method)>

[0218] Except that the nominal linewidth of the photoresist pattern on the photoresist mask is 50 nm, the patterning is performed in the same manner as in Example 2-1.

[0219] <Examples 2-3 (Patterning Method)>

[0220] Except that the nominal linewidth of the photoresist pattern on the photoresist mask is 100 nm, the patterning is performed in the same manner as in Example 2-1.

[0221] <Performance Evaluation 2>

[0222] The substrate surface (etching interface) exposed by etching in the etching products obtained in Examples 2-1 to 2-3 was observed using atomic force microscopy and SEM, respectively. Figure 9 The image shows atomic force microscopy (AFM) and SEM images of the etching products obtained in Examples 2-1 to 2-3 ((a-c) are the AFM morphologies of PtSe2 nanoribbons with nominal linewidths of 20 nm, 50 nm and 100 nm, respectively; (d-f) are the SEM images of the nanoribbons corresponding to (a-c).

[0223] from Figure 9 As can be seen, even under this minimum feature size condition, the etched nanopattern still maintains extremely high structural integrity, with continuous and straight lines, and no fracture, peeling, or adhesion phenomena commonly observed in physical etching were observed. This result indicates that the OMPS method can effectively remove chemically inert products while effectively suppressing lateral etching and edge damage, thus possessing high-resolution processing capabilities on the 20nm scale. Furthermore, as the feature size increases to 50nm (… Figure 9 (b) and (e) in the middle are related to 100nm ( Figure 9 In (c) and (f), the edge contours of the nanoribbons are sharper and clearer, and the linear fidelity and contrast are further enhanced, further confirming that the method has excellent pattern fidelity and photoresist compatibility at different scales.

[0224] <Example 3 (Device Construction)>

[0225] Using the basic sample of the present invention, OMPS etching was performed using a mask in a similar manner to that in Example 2-1. Then, the source and drain electrodes were deposited by electron beam evaporation. After removing the residual photoresist by immersion in acetone for 10 minutes, a field-effect transistor was constructed.

[0226] The transfer characteristic curve and output characteristic curve of the field-effect transistor are as follows: Figure 10 As shown in the image.

[0227] from Figure 10 As can be seen from this, the field-effect transistor is a high-performance, low-power, and highly reliable transistor, which is very suitable for use in low-power and high-performance digital logic circuits.

[0228] It should be noted that although the technical solution of the present invention has been described with specific examples, those skilled in the art will understand that the present invention should not be limited thereto.

[0229] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for oxidation-induced lattice softening etching of a metal chalcogenide layer, characterized in that, The method includes: (A1) Oxidation pretreatment step: The metal chalcogenide layer is subjected to plasma treatment in an atmosphere containing oxygen (O2) and / or ozone (O3). The metal chalcogenide compound contained in the metal chalcogenide layer is a compound that produces non-volatile etching residues in any atomic layer etching method, and is composed of the formula XY. n It is indicated that X is a metallic element, Y is sulfur, selenium or tellurium, and n is 1 to 4; (A2) Physical sputtering step: Plasma etching of the oxidized metal chalcogenide layer in an inert rare gas atmosphere, wherein the etching power is lower than the threshold power required for plasma etching of the exposed, unoxidized substrate in the same atmosphere.

2. The oxidation-induced lattice softening etching method according to claim 1, characterized in that, X is at least one of nickel (Ni), palladium (Pd), platinum (Pt), cobalt (Co), rhodium (Rh), iridium (Ir), iron (Fe), osmium (Os), rhenium (Re), chromium (Cr), tin (Sn), or indium (In).

3. The oxidation-induced lattice softening etching method according to claim 1 or 2, characterized in that, The metal chalcogenide compound is at least one selected from PtS2, PtSe2, PtTe2, PdS2, PdSe2, PdTe2, NiSe2, NiTe2, CoSe2, CoTe2, FeTe2, IrS2, IrSe2, ReSe2, RhS2, RhSe2, CrS2, CrSe2, SnS2, or In2Se3.

4. The oxidation-induced lattice softening etching method according to any one of claims 1 to 3, characterized in that, The thickness of the metal chalcogenide compound layer is from a single atomic layer to 15 atomic layers.

5. The oxidation-induced lattice softening etching method according to any one of claims 1 to 4, characterized in that, (A1) In the oxidation pretreatment step, the treatment power is 5 to 500W and the treatment time is 1 to 200 seconds.

6. The oxidation-induced lattice softening etching method according to any one of claims 1 to 5, characterized in that, (A2) In the physical sputtering removal step, the lower limit of etching power is 10W, and the etching time is 5 seconds to 20 minutes.

7. The oxidation-induced lattice softening etching method according to any one of claims 1 to 6, characterized in that, The root mean square roughness of the substrate obtained after etching steps (A1) and (A2) is less than 0.3 nm.

8. A method for patterning a metal chalcogenide layer, characterized in that, It includes: (B1) A photoresist layer is formed on the metal chalcogenide compound layer, and the photoresist layer is exposed and developed according to the desired pattern to form a photoresist mask. (B2) According to the pattern of the photoresist mask, the exposed metal chalcogenide layer is etched by the oxidation-induced lattice softening etching method according to any one of claims 1 to 7.

9. The patterning method according to claim 8, characterized in that, The pattern is a nanoscale stripe array pattern, and the width of the stripes in the nanoscale stripe array pattern is at least 20 nm.

10. A method for constructing a transistor device, characterized in that, It includes: (C1) An oxide insulating layer is formed on the silicon wafer; (C2) A metal chalcogenide layer as a channel material is formed on the oxide insulating layer; (C3) The metal chalcogenide layer is patterned by the patterning method according to claim 8 or 9, and the source and drain patterns are defined. (C4) The source and drain are formed by depositing metal, respectively.

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