Transimpedance amplifier circuit

Abstract

It includes: a control unit (11) that separates the input control signal (st) generated by the reset signal (s1) and the frequency band switching signal (s2) into the reset signal (s1) and the frequency band switching signal (s2); and a transimpedance amplifier (12) that has a first input (P1) for the input reset signal (s1) and a second input (P2) for the input frequency band switching signal (s2), and converts the current signal into a voltage signal using the reset signal (s1) and the frequency band switching signal (s2).

Description

Technical Field

[0001] This disclosure relates to transimpedance amplifier circuits. Background Technology

[0002] In optical transmission devices such as optical transmission systems and passive optical networks (PON) that are capable of high-speed data transmission, transimpedance amplifiers (hereinafter referred to as "TIAs") are used to convert optical signals into electrical signals.

[0003] The TIA (Transmission Interchange Instrumentation) takes the photocurrent obtained from photodetectors such as photodiodes as input and outputs a voltage corresponding to the impedance conversion gain proportional to the value of the feedback resistor. In a PON (Push-On Network) system, uplink packet data from each participant-side device (ONU; Optical Network Unit) to the base station-side device (OLT; Optical Line Terminal) is transmitted in pulses using time-division multiplexing. At this time, due to differences in distance between the ONU and the OLT, as well as path variations, the optical power reaching the OLT is different. Therefore, the signal amplitude of the electrical signal of the photocurrent obtained by the photodetector in the optical receiving circuit through photo-to-electric conversion varies for each packet.

[0004] Patent documents 1 and 2 disclose the following: by inputting a reset signal to the TIA, when packets with significantly different receiving levels arrive, the AGC (Automatic Gain Control) and AOC (Automatic Offset Control) actions within the TIA are completed instantaneously.

[0005] Furthermore, the increasing functionality of PON systems requires high-speed response to burst signals with mixed accommodation of multiple speeds (1Gbps and 10Gbps, 10Gbps and 25Gbps, etc.) and improved bandwidth utilization efficiency.

[0006] Patent document 1 discloses a method to improve receiving sensitivity by inputting a frequency band switching signal (rate signal) to the TIA, switching the TIA's frequency band to a frequency band suitable for the bit rate of the signal to be received.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2010-178257

[0010] Patent Document 2: Japanese Patent Application Publication No. 2015-84474 Summary of the Invention

[0011] The problem that the invention aims to solve

[0012] However, in PON systems, the requirements for miniaturization and cost reduction of optical transceivers necessitate miniaturization and cost reduction of the packaging used in the ROSA (Receiver Optical Sub-Assembly) optical module, which functions as the optical receiver. To provide the two control signals (reset signal and band switching signal) to the TIA, the reset signal and band switching signal need to be assigned to two terminals of the package, increasing the number of terminals. Therefore, miniaturization and cost reduction become difficult.

[0013] This disclosure was made in view of the above circumstances, and its object is to provide a transimpedance amplifier circuit capable of reducing the number of terminals used to supply control signals to the TIA.

[0014] Methods for solving problems

[0015] One aspect of the present disclosure of a transimpedance amplifier circuit includes: a control unit that separates an input control signal generated by a first control signal and a second control signal into the first control signal and the second control signal; and a transimpedance amplifier having a first input unit for inputting the first control signal and a second input unit for inputting the second control signal, and using the first control signal and the second control signal to convert a current signal into a voltage signal.

[0016] Invention Effects

[0017] According to this disclosure, the number of terminals used to supply control signals to the TIA can be reduced. Attached Figure Description

[0018] Figure 1 This is a block diagram showing the structure of the TIA circuit in the first embodiment.

[0019] Figure 2 This is a block diagram showing the detailed structure of the control unit mounted in the TIA circuit of the first embodiment and the circuit connected to the front stage of the TIA circuit.

[0020] Figure 3 This is a diagram showing the relationship between the level of the input control signal in the first embodiment and the operating state of the TIA.

[0021] Figure 4 This is a timing diagram showing the changes in the input control signal st, reset signal s1, and frequency band switching signal s2 in the first embodiment.

[0022] Figure 5This is a block diagram showing the detailed structure of the control unit mounted on the TIA circuit in the second embodiment and the circuit connected to the front stage of the TIA circuit.

[0023] Figure 6 This is a circuit diagram showing a specific structural example of a comparator used for a window comparator.

[0024] Figure 7A This is a circuit diagram showing an example of a Schmitt trigger circuit constructed from CMOS.

[0025] Figure 7B This is a circuit diagram showing an example of a Schmitt trigger circuit composed of comparators.

[0026] Figure 8A This is a graph showing the relationship between the lower limit voltage v3 and the upper limit voltage v4, the third threshold voltage Vth3, and the fourth threshold voltage Vth4 of the Schmitt trigger circuit, with an example shown when v3 = Vth3 and v4 = Vth4.

[0027] Figure 8B This is a graph showing the relationship between the lower limit voltage v3 and the upper limit voltage v4, the third threshold voltage Vth3, and the fourth threshold voltage Vth4 of the Schmitt trigger circuit, and it shows an example when v3 > Vth3 and v4 > Vth4.

[0028] Figure 9 It is a characteristic graph showing the relationship between the voltage level input to the Schmitt trigger circuit and the output signal.

[0029] Figure 10 This is a diagram showing the relationship between the level of the input control signal and the operating state of the TIA in the second embodiment.

[0030] Figure 11 This is a timing diagram showing the changes in the input control signal st, reset signal s1, and frequency band switching signal s2 in the second embodiment.

[0031] Figure 12 This is a block diagram showing the detailed structure of the control unit mounted on the TIA circuit in the third embodiment and the circuit connected to the front stage of the TIA circuit.

[0032] Figure 13 This is a block diagram illustrating the hardware structure of this embodiment. Detailed Implementation

[0033] The embodiments will now be described with reference to the accompanying drawings.

[0034] [Description of the First Embodiment]

[0035] Reference Figures 1-4 The first embodiment will be described. Figure 1This is a block diagram showing the structure of the transimpedance amplifier circuit 100 (hereinafter simply referred to as "TIA circuit 100") according to the first embodiment. Figure 2 This is a circuit diagram showing the detailed structure of the control unit 11 mounted in the TIA circuit 100 and the circuit connected to the front stage of the TIA circuit 100. Figure 3 This is a diagram showing the relationship between the level of the control signal input to TIA100 (hereinafter referred to as "input control signal st", details to follow) and the operating state of TIA12. Figure 4 It is a timing diagram showing the changes in the input control signal st, the reset signal s1, and the frequency band switching signal s2.

[0036] like Figure 1 As shown, the TIA circuit 100 includes a control unit 11 and a transimpedance amplifier 12 (hereinafter referred to as "TIA12"). The control unit 11 has an input terminal Q1. The TIA circuit 100 is mounted on a socket in a TO-CAN (Transistor Outline-CAN) package, such as ROSA.

[0037] like Figure 2 As shown, a media access controller 31 (hereinafter referred to as "MAC31"), a tri-state buffer 32 and a bias circuit 33 are provided in the front stage of the TIA circuit 100.

[0038] MAC21 performs media access control for each device. MAC21 outputs a reset signal s1 and a band switching signal s2. The band switching signal s2 is a control signal used to switch the band of TIA12 to a band suitable for the bit rate of the signal to be received. The reset signal s1 is a control signal used to instantly complete the AGC and AOC actions within TIA12 when packets with significantly different received levels arrive.

[0039] The tri-state buffer 32 receives the band switching signal s2 and the reset signal s1 output from the MAC 31. The tri-state buffer 32 generates an input control signal st representing three states: L level, intermediate level "(L+H) / 2", and H level. The voltage value of the input control signal st is also represented by the same symbol "st".

[0040] The bias circuit 33 superimposes the voltage VDD / 2 onto the output of the tri-state buffer 32. Furthermore, the bias circuit 33 can be incorporated into the TIA circuit 100.

[0041] The control unit 11 separates the input control signal st into a band switching signal s2 and a reset signal s1. The control unit 11 outputs the separated band switching signal s2 and reset signal s1 to the TIA 12. The control unit 11 is connected to the input terminal Q1 provided in the TIA circuit 100. The input terminal Q1 is connected to the output of the tri-state buffer 32. The input control signal st is input to the input terminal Q1.

[0042] The control unit 11 includes a first comparison unit 21, a second comparison unit 22, a first power supply 23, a second power supply 24, and an encoding circuit 13.

[0043] The first power supply 23 outputs a first threshold voltage Vth1. The second power supply 24 outputs a second threshold voltage Vth2 (Vth2 > Vth1). The first threshold voltage Vth1 can be set to a voltage slightly smaller than the midpoint between the H level and the L level, "(H+L) / 2" (midpoint level). The second threshold voltage Vth2 can be set to a value slightly smaller than the H level.

[0044] An input control signal *st* is input to the non-inverting input terminal (+ terminal) of the first comparator 21, and a first threshold voltage *Vth1* is input to the inverting input terminal (- terminal). An input control signal *st* is input to the non-inverting input terminal of the second comparator 22, and a second threshold voltage *Vth2* is input to the inverting input terminal. That is, when the input control signal *st* is "Vth1 ≤ *st*", the output signal A1 of the first comparator 21 is at level *H*. When the input control signal *st* is "Vth2 ≤ *st*", the output signal A0 of the second comparator 22 is at level *H*.

[0045] Encoding circuit 13 includes a NOT circuit 25 and AND circuits 26 and 27. The output (output signal A0) of the second comparator 22 branches into two systems: one branch line is connected to the input of the NOT circuit 25, and the other branch line is connected to one input of the AND circuit 26. The output of the NOT circuit 25 is connected to one input of the AND circuit 27.

[0046] The output section (output signal A1) of the first comparator 21 is branched into two systems. One branch line is connected to another input section of the circuit 26, and the other branch line is connected to another input section of the circuit 27.

[0047] The output section (output signal Y0) of circuit 26 and the output section (output signal Y1) of circuit 27 are respectively connected to the second input section P2 and the first input section P1 of TIA12. Output signal Y0 corresponds to the band switching signal s2, and output signal Y1 corresponds to the reset signal s1.

[0048] When the input control signal st output from the tri-state buffer 32 is at level L, the output signals A1 and A0 are both at level L, and the output signals Y1 and Y0 are also at level L. That is, a band switching signal s2 at level L is input to the second input P2 of TIA12, and a reset signal s1 is not input to the first input P1.

[0049] When the input control signal st is at the intermediate level, the output signal A1 is at the high level, the output signal A0 is at the low level, the output signal Y1 is at the high level, and the output signal Y0 is at the low level. Therefore, a reset signal s1 is input to the first input section P1 of TIA12, and a frequency band switching signal s2 at the low level is input to the second input section P2.

[0050] When the input control signal st is at level H, the output signals A1 and A0 are both at level H, the output signal Y1 is at level L, and the output signal Y0 is at level H. Therefore, the band switching signal s2 is input to the second input P2 of TIA12, and the reset signal s1 is not input to the first input P1.

[0051] That is, the control unit 11 includes: a first comparison unit 21 that compares the input control signal st with a predetermined first threshold voltage Vth1; a second comparison unit 22 that compares the input control signal st with a second threshold voltage Vth2 that is higher than the first threshold voltage Vth1; and an encoding circuit 13 that outputs a first control signal to the first input unit P1 when the input control signal st is higher than or equal to the first threshold voltage Vth1 and lower than the second threshold voltage Vth2, and outputs a second control signal to the second input unit P2 when the input control signal st is higher than or equal to the second threshold voltage Vth2.

[0052] The control unit 11 separates the tri-state buffer output (input control signal st) generated by the input of the first control signal (e.g., reset signal s1) and the second control signal (e.g., band switching signal s2) into the first control signal and the second control signal.

[0053] The TIA12 (transimpedance amplifier) ​​converts a current signal detected by a photoelectric conversion device into a voltage signal. When a high-level band switching signal s2 is input, the TIA12 sets the receiving state to the high-frequency band. When a reset signal s1 is input, the TIA12 sets the receiving state to the low-frequency band. When a low-level band switching signal s2 is input but a reset signal s1 is not input (when the input control signal st is low level), the TIA12 sets the receiving state to the low-frequency band.

[0054] That is, such as Figure 3As shown in the corresponding table, the frequency band of TIA12 is switched to either "high frequency band" or "low frequency band" based on the three levels of the input control signal st: "H level", "intermediate level", and "L level". Additionally, the reset state of TIA12 is switched based on these three levels.

[0055] That is, TIA12 has a first input section P1 for inputting a first control signal (reset signal s1) and a second input section P2 for inputting a second control signal (band switching signal s2), and uses the first control signal and the second control signal to convert the current signal into a voltage signal.

[0056] Next, refer to Figure 4 The timing diagram shown illustrates the operation of the TIA circuit 100 of the first embodiment configured as described above. Figure 2 The tri-state buffer 32 shown outputs a band switching signal s2 (H level or L level) and an input control signal st generated by the reset signal s1. For example, as... Figure 4 As shown in (a), the input control signal st is a signal whose voltage level changes in three stages: L level, intermediate level "(L+H) / 2", and H level.

[0057] exist Figure 4 In the example shown in (a), the intermediate level is output at times t11, t13, t15, t17, and t19, the H level is output at times t12, t16, and t18, and the L level is output at time t14.

[0058] At time t11, the input control signal st is at the intermediate level, therefore Figure 2 The output signal Y0 of circuit 26 is at low level, and the output signal Y1 of circuit 27 is at high level. Therefore, Figure 4 The band switching signal s2 shown in (b) is at level L at time t11. Figure 4 The reset signal s1 shown in (c) is at level H at time t31 (corresponding to t11). Similarly, the reset signal s1 is also at level H at times t32 (corresponding to t13), t33 (corresponding to t15), t34 (corresponding to t17), and t35 (corresponding to t19).

[0059] exist Figure 4 As shown in (a), at time t12, the input control signal st is at level H, therefore Figure 2 The output signal Y0 of circuit 26 is H level, and the output signal Y1 of circuit 27 is L level. Therefore, Figure 4 The reset signal s1 shown in (c) is at level L at time t12. Figure 4The band switching signal s2 shown in (b) is at level H at time t21 (corresponding to t12). Similarly, at times t23 (corresponding to t16) and t25 (corresponding to t18), the band switching signal s2 is also at level H. In addition, at times t22 and t24, the band switching signal s2 is at level L.

[0060] The output signal Y0 of circuit 26 is output as a band switching signal s2 to the second input section P2 of TIA12. The output signal Y1 of circuit 27 is output as a reset signal s1 to the first input section P1 of TIA12. That is, the input control signal st generated by the band switching signal s2 and the reset signal s1 is separated into the band switching signal s2 and the reset signal s1 by the control section 11, and output to the second input section P2 and the first input section P1 of TIA12, respectively.

[0061] Thus, the TIA circuit 100 of the first embodiment includes: a control unit 11 that separates the input control signal st generated by the first control signal (e.g., reset signal s1) and the second control signal (e.g., band switching signal s2) into a first control signal and a second control signal; and a TIA 12 (transimpedance amplifier) ​​that has a first input P1 for inputting the first control signal (reset signal s1) and a second input P2 for inputting the second control signal (band switching signal s2), and uses the first control signal and the second control signal to convert the current signal into a voltage signal.

[0062] In the TIA circuit 100 of the first embodiment, when an input control signal st generated by a band switching signal s2 and a reset signal s1 is input from the tri-state buffer 32, the input control signal st is separated into a band switching signal s2 and a reset signal s1, and output to the TIA 12. Therefore, two control signals can be obtained by having a structure with one input terminal Q1, and the band switching and reset processes can be performed in the TIA 12.

[0063] That is, the band switching signal s2 used in the band switching function and the reset signal s1 used in the reset function can be combined into a single input terminal Q1. As a result, the number of terminals used to supply control signals to the TIA can be reduced, enabling miniaturization and cost reduction of the TIA circuit 100, and also contributing to the miniaturization and cost reduction of the optical transceiver. In addition, it is possible to achieve multiple speed correspondences and high-speed response of the burst-responsive transimpedance amplifier used in PON (Passive Optical Network) systems, etc.

[0064] Furthermore, in the first embodiment described above, when it is required to shorten the setup time (waiting time) when generating the input control signal st, it can also be configured to replace... Figure 2The tri-state buffer 32 shown uses an analog switching circuit to actively provide a low-impedance intermediate potential to the input terminal of the input control signal st.

[0065] Furthermore, the three voltages of the input control signal st—"H level," "intermediate level," and "L level"—are not limited to the combinations described above and can be set to various combinations. In this case, only the circuitry of the encoding circuit 13 needs to be changed.

[0066] In the first embodiment described above, an example of generating an input control signal st from the MAC circuit 31 to the TIA circuit 100 from the reset signal s1 (first control signal) and the band switching signal s2 (second control signal) is illustrated. However, the first control signal and the second control signal may also be assigned to other control signals.

[0067] In the first embodiment described above, an example of a TIA mounted in a TO-CAN package commonly used in optical component assemblies (TOSA, ROSA) is shown, but it can also be applied to other packages.

[0068] [Description of the Second Embodiment]

[0069] Next, the second embodiment will be described. Figure 5 This is a block diagram showing the structure of the TIA circuit 101 of the second embodiment and the circuitry provided in front of it. The TIA circuit 101 of the second embodiment differs from the TIA circuit 100 shown in the first embodiment in the structure of the control unit. Hereinafter, [further details will be provided]. Figure 5 The structure of the control unit 11A shown will be explained.

[0070] The control unit 11A includes a window comparator 14 and a Schmitt trigger circuit 15.

[0071] The window comparator 14 includes a third comparator 41, a fourth comparator 42, a third power supply 43, a fourth power supply 44, and an AND circuit 45. For example, Figure 6 As shown, the comparator used in window comparator 14 can be composed of a total of 12 CMOS sensors, P21~P24 and N21~N28.

[0072] Figure 5 The third power supply 43 outputs a third threshold voltage Vth3. The fourth power supply 44 outputs a fourth threshold voltage Vth4 (Vth4 > Vth3). The third threshold voltage Vth3 can be set to a voltage slightly smaller than the intermediate level "(L+H) / 2". The fourth threshold voltage Vth4 can be set to a voltage slightly smaller than the H level.

[0073] An input control signal *st* is input to the non-inverting input terminal of the third comparator 41, and a third threshold voltage *Vth3* is input to the inverting input terminal. An input control signal *st* is input to the inverting input terminal of the fourth comparator 42, and a fourth threshold voltage *Vth4* is input to the non-inverting input terminal. That is, when the input control signal *st* is "Vth3 ≤ *st* < Vth4", the output signals of both the third comparator 41 and the fourth comparator 42 are at level H, and the output signal of circuit 45 (corresponding to the reset signal *s1*) is also at level H. Therefore, the reset signal *s1* is at level H when the input control signal *st* is at an intermediate level, and at level L when the input control signal *st* is at both levels L and H.

[0074] That is, the window comparator 14 determines whether the input control signal st is within the range of a predetermined third threshold voltage Vth3 and a fourth threshold voltage Vth4 that is higher than the third threshold voltage Vth3. If the input control signal st is within this range, the first control signal is output to the first input unit P1.

[0075] The Schmitt trigger circuit 15 outputs a band switching signal s2 to maintain the band setting of the group preceding the input reset signal s1 during reset. A lower limit voltage (set to "v3") and an upper limit voltage (set to "v4") are set in the Schmitt trigger circuit 15. The Schmitt trigger circuit 15 outputs an H level when the input voltage is above the upper limit voltage v4, and outputs an L level when the input voltage is below the lower limit voltage v3.

[0076] That is, the Schmitt trigger circuit 15 is set with a lower limit voltage v3 and an upper limit voltage v4. When the input control signal st reaches the upper limit voltage v4, it outputs a second control signal to the second input section P2 and maintains the output of the second control signal until the input control signal st drops below the lower limit voltage v3.

[0077] Schmitt trigger circuit 15, for example, can be powered by... Figure 7A , Figure 7B The circuit configuration is shown. Figure 7A An example is shown of a Schmitt trigger circuit 15 consisting of a total of 6 CMOS sensors, namely P11, P12, P13, N11, N12, and N13. Figure 7B This example illustrates a Schmitt trigger circuit consisting of comparator 61 and resistors R1 and R2.

[0078] The lower limit voltage v3 is preferably the same as the third threshold voltage Vth3, and the upper limit voltage v4 is preferably the same as the fourth threshold voltage Vth4. This expands the range of voltages that can be identified as intermediate levels.

[0079] Figure 8AThis diagram illustrates the voltage ranges identified as L level, intermediate level, and H level when v3 = Vth3 and v4 = Vth4. In this case, the voltage range d3 identified as L level, the voltage range d2 identified as intermediate level, and the voltage range d1 identified as H level can be clearly defined.

[0080] Figure 8B This diagram illustrates the voltage ranges identified as L level, intermediate level, and H level when v3 > Vth3 and v4 > Vth4. In this case, there is an undetermined voltage range d14 between the voltage range d15 identified as L level and the voltage range d13 identified as intermediate level, and there is an undetermined voltage range d12 between the voltage range d13 identified as intermediate level and the voltage range d11 identified as H level.

[0081] That is, such as Figure 8A As shown, by setting v3 = Vth3 and v4 = Vth4, the existence of the voltage ranges d12 and d14 mentioned above can be avoided.

[0082] Figure 9 This is a characteristic graph showing the relationship between the voltage level input to the Schmitt trigger circuit 15 and the output signal. For example... Figure 9 As shown in (a), when the input voltage is less than the upper limit voltage v4, as Figure 9 As shown in (b), the output signal is at level L. When the input voltage reaches the upper limit voltage v4, the output signal switches to level H. Subsequently, when the input voltage drops to the lower limit voltage v3, the output signal switches to level L. That is, the output signal of the Schmitt trigger circuit 15 changes from level H to level L with hysteresis h1.

[0083] Therefore, even when the input control signal st switches from level H to an intermediate level, the output of the Schmitt trigger circuit 15 remains at level H, thus continuing to output the band switching signal s2. That is, even with the input reset signal s1, the band switching signal s2 is not affected. Furthermore, even with a reset signal s1 superimposed on the input voltage... Figure 9 Even with noise N1 as shown in (a), this effect can be avoided.

[0084] That is, such as Figure 10 As shown in the corresponding table, when the input control signal st is at level H, TIA12 enters the high-frequency band mode receiving state. At the intermediate level, TIA12 enters the band mode before the reset operation, becoming the reset state. At level L, TIA12 enters the low-frequency band mode receiving state.

[0085] Figure 11This is a timing diagram showing the changes in the input control signal st, the band switching signal s2, and the reset signal s1 in the second embodiment. As described above, the Schmitt trigger circuit 15 outputs the band switching signal s2 to maintain the band setting of the group preceding the input reset signal s1 during reset. That is, when in Figure 11 When the input control signal st switches to H level at time T1 as shown in (a), as Figure 11 As shown in (b), the output signal (band switching signal s2) of the Schmitt trigger circuit 15 becomes H level. Even when the input control signal st switches from H level to an intermediate level at time T2, the band switching signal s2 remains at H level.

[0086] When the input control signal st switches to L level at time T3, the band switching signal s2 switches to L level. Therefore, in Figure 11 During time t51 of the intervals T1 to T3 shown in (b), the band switching signal s2 remains at level H. Furthermore, when the input control signal st switches from level H to an intermediate level at time T5 and then switches back to level H at time T6, the band switching signal s2 remains at level H. That is, during time t53 of the intervals T4 to T8, the band switching signal s2 remains at level H.

[0087] That is, during the time period when a reset signal s1 is provided to TIA12, a high-level band switching signal s2 can also be output to TIA12. Specifically, during Figure 11 The times t43, t47, and t49 shown in (a) are as follows: Figure 11 As shown in (b), the band switching signal s2 can be kept at the H level.

[0088] In addition, such as Figure 11 As shown in (c), the reset signal s1 becomes H level when the input control signal st is at the intermediate level. Specifically, in relation to... Figure 11 The times t41, t43, t45, t47, and t49 shown in (a) correspond to the times t61, t62, t63, t64, and t65, and the reset signal s1 becomes H level.

[0089] Therefore, when high-frequency band grouped signals are adjacent, during the reset operation within the protection time, unnecessary frequency band switching to the low-frequency band can be prevented, thus maintaining the high-frequency band. That is, in the TIA circuit 100 of the first embodiment described above, the input control signal st is separated into three states (L level, intermediate level, and H level), so the TIA 12 is fixed to the low-frequency band during the input reset signal s1 time period. However, in the TIA circuit 101 of the second embodiment, the high-frequency band can be maintained during the input reset signal s1 time period.

[0090] Thus, in the TIA circuit 101 of the second embodiment, unnecessary band switching operations can be avoided, and the band switching signal s2 and the reset signal s1 can be input to a single input terminal Q1. Therefore, miniaturization and cost reduction of the semiconductor package can be achieved, and by avoiding unnecessary band switching operations between packets, the reception responsiveness of the packet signals is also improved.

[0091] [Description of the Third Embodiment]

[0092] Next, the third embodiment will be described. Figure 12 This is a circuit diagram showing the structure of the TIA circuit 102 and the MAC circuit 31 disposed in front of it in the third embodiment.

[0093] like Figure 12 As shown, the TIA circuit 102 of the third embodiment and the TIA circuit 101 of the second embodiment (see reference) Figure 5 In comparison, it differs in that it has a first input terminal Q11 and a second input terminal Q12, and in that the control unit 11B has an OR circuit 51 and a pull-down resistor 52.

[0094] The first input terminal Q11 is grounded via pull-down resistor 52.

[0095] The second input terminal Q12 is connected to the input p2 of the window comparator 14 and the input p3 of the Schmitt trigger circuit 15.

[0096] Alternatively, the input q1 of circuit 51 is connected to the output p1 of window comparator 14, and the input q2 is connected to the first input terminal Q11. Alternatively, the output q3 of circuit 51 is connected to the first input P1 of TIA12.

[0097] That is, the control unit 11B has a first input terminal Q11 and a second input terminal Q12. The first input terminal Q11 is grounded via a pull-down resistor 52 and connected to one input q2 of the OR circuit 51. The other input q1 of the OR circuit is connected to the output p1 of the window comparator 14, and the output q3 of the OR circuit is connected to the first input p1.

[0098] Other structures and Figure 5 The TIA circuit 101 shown is the same, so the same symbols are assigned to the same components and detailed descriptions are omitted.

[0099] As described in the second embodiment above (refer to...) Figure 5As shown in the diagram, in the third embodiment, when the TIA circuit 102 is provided with the output of the tri-state buffer 32 (a three-stage level output), the output is connected to the second input terminal Q12, leaving the first input terminal Q11 open. The input q2 of the OR circuit 51 is fixed to a low level by the pull-down resistor 52, thus directly becoming the output of the OR circuit 51. Therefore, it operates in the same way as the TIA circuit 101 shown in the second embodiment.

[0100] Furthermore, in the third embodiment, if the circuits that output the band switching signal s2 and the reset signal s1 respectively are arranged in the front stage as in the conventional case, such as Figure 12 As shown, the output of the frequency band switching signal s2 is connected to the input terminal Q12, and the output of the reset signal s1 is connected to the input terminal Q11.

[0101] In this case, when the band switching signal s2 is at level H, the output of the Schmitt trigger circuit 15 becomes level H and is output to the second input P2 of the TIA12. When the reset signal s1 is at level H, level H is input to the input q2 of the OR circuit 51, so the output of the OR circuit 51 (reset signal s1) becomes level H and is output to the first input P1 of the TIA12.

[0102] Thus, in the third embodiment, when an input control signal st representing three states is supplied, only the second input terminal Q12 is used. By opening the first input terminal Q11, as described in the second embodiment above, the input control signal st can be separated into a reset signal s1 and a band switching signal s2, and output to the first input section P1 and the second input section P2 of the TIA12, respectively. That is, since the first input terminal Q11 is not used, the number of terminals can be reduced.

[0103] Furthermore, when it is desired to input the band switching signal s2 and the reset signal s1 from the MAC circuit 31 located in the front stage of the TIA circuit 102 to the TIA separately, by using the first input terminal Q11, each signal s1 and s2 can be output to the first input section P1 and the second input section P2 of the TIA 12 respectively, thereby improving versatility.

[0104] Therefore, IC manufacturers can address both scenarios using and not using the input control signal st by manufacturing a common TIA circuit 102. This improves versatility and reduces manufacturing costs.

[0105] For example, such as Figure 13As shown, the TIA circuits 100, 101, and 102 of the various embodiments described above can use a general-purpose computer system. This computer system includes a CPU (Central Processing Unit) 901, a memory 902, a storage device 903 (HDD: Hard Disk Drive, SSD: Solid State Drive), a communication device 904, an input device 905, and an output device 906. The memory 902 and the storage device 903 are storage devices. In this computer system, the CPU 901 executes a predetermined program loaded on the memory 902, thereby realizing the functions of the TIA circuits 100, 101, and 102.

[0106] Furthermore, TIA circuits 100, 101, and 102 can be implemented by one computer or by multiple computers. Additionally, TIA circuits 100, 101, and 102 can also be virtual machines installed on a computer.

[0107] Furthermore, the programs used by TIA circuits 100, 101, and 102 can be stored on computer-readable recording media such as HDDs, SSDs, USB (Universal Serial Bus) storage devices, CDs (Compact Discs), and DVDs (Digital Versatile Discs), or can be distributed via a network. Computer-readable recording media include, for example, nontransitory recording media.

[0108] Furthermore, this disclosure is not limited to the above-described embodiments, and various modifications can be made within the scope of its spirit.

[0109] Symbol Explanation

[0110] 11, 11A, 11B Control Units;

[0111] 12 Transimpedance Amplifier (TIA);

[0112] 13. Encoding circuit;

[0113] 14. Window comparator;

[0114] 15. Schmitt trigger circuit;

[0115] 21. First Comparative Section;

[0116] 22. Second Comparative Section;

[0117] 23 First power source;

[0118] 24 Second power supply;

[0119] 25. Non-circuit;

[0120] 26, 27 and the circuit;

[0121] 31. Media Access Controller Circuit (MAC Circuit);

[0122] 32-state buffer;

[0123] 33 bias circuit;

[0124] 41. Third Comparative Section;

[0125] 42. Fourth Comparative Section;

[0126] 43. Third power source;

[0127] 44. Fourth power source;

[0128] 45 and circuit;

[0129] 51 or circuit;

[0130] 52 pull-down resistor;

[0131] 100, 101, 102 transimpedance amplifier circuits (TIA circuits);

[0132] P1 First Input Section;

[0133] P2 Second Input Section;

[0134] Q1 input terminal;

[0135] Q11 First Input Terminal;

[0136] Q12 Second Input Terminal;

[0137] S1 reset signal (first control signal);

[0138] S2 frequency band switching signal (second control signal);

[0139] st input control signal;

[0140] V3 lower limit voltage;

[0141] v4 upper limit voltage.

Claims

1. A transimpedance amplifier circuit, characterized in that, have: The control unit separates the input control signal generated by the first control signal and the second control signal into the first control signal and the second control signal; and A transimpedance amplifier having a first input section for receiving the first control signal and a second input section for receiving the second control signal, converting a current signal into a voltage signal using the first control signal and the second control signal.

2. The transimpedance amplifier circuit according to claim 1, characterized in that, The control unit includes: A first comparison unit compares the input control signal with a predetermined first threshold voltage; The second comparison unit compares the input control signal with a second threshold voltage that is higher than the first threshold voltage. as well as The encoding circuit outputs the first control signal to the first input unit when the input control signal is above the first threshold voltage and below the second threshold voltage, and outputs the second control signal to the second input unit when the input control signal is above the second threshold voltage.

3. The transimpedance amplifier circuit according to claim 1, characterized in that, The control unit includes: A window comparator determines whether the input control signal is within a range of a predetermined third threshold voltage and a fourth threshold voltage that is higher than the third threshold voltage. If the input control signal is within the range, the comparator outputs a first control signal to the first input unit. as well as The Schmitt trigger circuit has a lower limit voltage and an upper limit voltage. When the input control signal reaches the upper limit voltage, it outputs a second control signal to the second input section and maintains the output of the second control signal until the input control signal drops below the lower limit voltage.

4. The transimpedance amplifier circuit according to claim 3, characterized in that, The control unit has a first input terminal and a second input terminal. The first input terminal is grounded via a pull-down resistor and connected to one input of an OR circuit. The other input of the OR circuit is connected to the output of the window comparator, and the output of the OR circuit is connected to the first input. The second input terminal is connected to the input section of the window comparator and the input section of the Schmitt trigger circuit.

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