Determining downsample points in a symbol sample

Abstract

One approach may include obtaining samples associated with one or more symbols of a group; determining at least one downsampling point in a sequence of samples associated with a header portion of the group; and using the samples associated with the determined downsampling point to recover one or more symbols and subsequent symbols.

Description

Priority Statement

[0001] This application claims the benefit of Indian Patent Application Serial No. 202341076672, filed on November 9, 2023, entitled “DETERMINING DOWN-SAMPLING POINTIN SYMBOL SAMPLES”. Background Technology

[0002] Electronic communication, including digital electronic communication, is used in a variety of operating environments. Sometimes, electronic communication involves symbol recovery. Attached Figure Description

[0003] To facilitate the identification of any particular element or action in the discussion, the most important number in the figure labels refers to the figure number of the element when it was first introduced.

[0004] Figure 1 It is a block diagram depicting a device for determining downsampling points based on one or more examples.

[0005] Figure 2 It is a block diagram depicting a device for symbol recovery based on one or more examples, provided that the downsampling points are determined.

[0006] Figure 3 It is a block diagram depicting the determination of control downsampling points based on one or more examples.

[0007] Figure 4 It is a block diagram depicting a signal processing chain that uses downsampling point determination to recover symbols in a data stream based on one or more examples.

[0008] Figure 5 This is a signal diagram depicting an example of the transmitted symbols.

[0009] Figure 6 It is a signal graph depicting a portion of the downsampling window.

[0010] Figure 7 It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes or methods disclosed herein.

[0011] Figure 8 This describes an example process 800 for determining downsampling points in a symbol sample based on one or more examples. Detailed Implementation

[0012] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of embodiments in which this disclosure may be practiced are shown by way of example. These embodiments have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0013] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe embodiments of this disclosure. The figures presented herein are not necessarily drawn to scale. For the reader's convenience, similar structures or components in the figures may retain the same or similar designations; however, similar designations do not imply that the structure or component must be identical in size, composition, configuration, or any other attribute.

[0014] The following description may include examples to assist those skilled in the art in practicing the embodiments disclosed herein. The use of the terms “exemplary,” “by example,” and “for example” indicates that the related descriptions are illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified parts, steps, features, or functions, etc.

[0015] It should be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but rather to represent various embodiments only. While various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0016] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, as such details are not necessary for obtaining a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0017] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0018] The various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or executed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to implement the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor executes computational instructions (e.g., software code) related to the embodiments of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0019] The implementation scheme can be described based on a process depicted as a flowchart, schematic diagram, structural diagram, or block diagram. While a flowchart can describe operable actions as a continuous process, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. A process can correspond to a method, thread, function, procedure, subroutine, or subroutine, but is not limited thereto. Furthermore, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions can be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another.

[0020] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0021] As used herein, the term "substantially" refers to and includes the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. For example, depending on whether a particular parameter, attribute, or condition is substantially satisfied, it may be satisfied with at least 90%, at least 95%, or even at least 99%.

[0022] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc., but not limited thereto) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0023] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be an intermediary element or layer. In contrast, when an element is described as "directly coupled" to another element, then there is no intermediary element or layer. The term "connection" is used interchangeably with the term "coupled" in this specification and has the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0024] In digital electronic communication via physical channels (e.g., wired, wireless, or combinations thereof, but not limited to), data can be converted into packets, further converted into bits, and even further converted into symbols representing bits or groups of bits. A symbol represents a specific physical state of the signal used to represent a bit or group of bits. A symbol may correspond to a corresponding voltage level, a corresponding phase of a carrier wave, a corresponding frequency, or a combination thereof. The process of mapping bits or groups of bits to physical states, and the characteristics of these states, depend on the modulation scheme used (e.g., QAM (Quadrature Amplitude Modulation), PSK (Phase Shift Keying), FSK (Frequency Shift Keying), but not limited to these). After modulation, the symbols are transmitted over the physical channel.

[0025] As a non-limiting example, symbols can be filtered before transmission to reduce bandwidth requirements (the bandwidth needed for transmission), shape the available spectrum, reduce inter-symbol interference (ISI), or achieve a combination of these.

[0026] As a complement to or alternative to filtering, and as a non-limiting example, symbols can be upsampled before transmission to increase the density of the data stream (e.g., to create a denser and more detailed representation of the symbol waveform, but not limited to this). When symbols are filtered and upsampled, upsampling can be performed before, after, or during filtering.

[0027] As a non-limiting example, upsampling may involve increasing (e.g., via sampling rate, interpolation, or both, but not limited to) the number of samples per symbol (the number of samples per symbol is referred to as the "sampling rate"), increasing (e.g., via symbol duplication, zero-interpolation, or both, optionally followed by low-pass filtering to smoothly reconstruct a higher-rate signal, but not limited to) the number of instances of one or more symbols (the number of instances of symbols is also referred to as the "symbol rate"), or both. The increase in data density based on upsampling is referred to as the "upsampling rate".

[0028] At the receiver, the high-density data stream is downsampled (e.g., before or after the symbols of the data stream undergo signal conditioning and phase / frequency compensation), and the downsampling is used for symbol recovery. The inventors of this disclosure recognize that downsampling suitable for symbol recovery typically occurs at a point of consensus within the corresponding set of upsampled symbols. The process of determining and indicating the downsampling point (e.g., enabling, but not limited to, selecting downsampling for symbol recovery) may be referred to herein as “timing and synchronization.” The indication of the downsampling point may be referred to herein as “indexing.”

[0029] The invention disclosed herein discloses known methods for determining downsampling points that can be implemented using zero-crossing algorithms or Gardner algorithms, along with loop filters. Such algorithms typically use multiple samples (current, previous, and next samples) to identify downsampling points, which is complex, and stabilizing the loop filter can be challenging and costly. Furthermore, such algorithms require continuous computation, leading to high power consumption and potential drift or wobbling problems.

[0030] One or more examples together involve determining downsampling points for symbol recovery. In one or more examples, the determined downsampling points may be within an upsampled set of grouped symbols. In one or more examples, the indices of the determined downsampling points may be used to select downsamples (e.g., but not limited to selecting upsamples as downsamples) for reconstructing symbols, and optionally for reconstructing data.

[0031] In one or more examples, the process of determining the downsampling point may include:

[0032] A downsampling window is obtained, which is a set of samples (e.g., but not limited to upsampling) (e.g., but not limited to sequences). The obtained downsampling window can be a downsampling window within a set of downsampling windows (e.g., but not limited to sequences), referred to herein as the "maximum window". A subset or all of the downsampling windows of the maximum window (e.g., but not limited to those within the maximum window) can be obtained for analysis.

[0033] The sample sequence of the downsampling window is subjected to sequential maximum selection using index tracking to determine the current maximum sample and the current maximum index. Here, "maximum" refers to the maximum value window that the downsampling window is a member of.

[0034] For the sample sequence s1, s2…s n It begins with the current largest sample, whose value is set to the first sample s1, and the current largest index, which is set to 1. For each subsequent sample s at position i in the sequence... i Compare it with the current largest sample. If s i If the value is greater than the current maximum sample, then update the current maximum sample to s. i The value of is determined, and the current maximum index is updated to i. If s i If the sample size is less than or equal to the current maximum sample, do not update the current maximum index. Loop continuously until all samples in the sequence have been processed. When processing all samples in the sequence, the current maximum sample is the largest sample, and the current maximum index is its position in the sequence. The position of the current maximum sample within the sequence can be used as a downsampling point. Obtain the next downsampling window (if available) and repeat, but for subsequent downsampling windows, start with the determined current maximum sample and current maximum index from the previous downsampling window.

[0035] The maximum value is the highest sample determined by all downsampling windows across the maximum value window, and the maximum index is the index of the maximum value.

[0036] In one or more examples, a sample (e.g., but not limited to upsampling, downsampling) is a value representing a sign (e.g., but not limited to discrete values).

[0037] In one or more examples, the number of downsampling windows in the corresponding maximum value window is settable (can be set, e.g., programmable or configurable, but not limited to). The number of downsampling windows can be set at least in part based on specific operating conditions, such as a predetermined number of binary transitions (1 to 0 and 0 to 1), and a confidence level for the presence of a predetermined number of binary transitions present in the maximum value window, but not limited to. In one or more examples, the number of samples in the corresponding downsampling window is settable.

[0038] In one or more examples, the maximum value window may typically correspond to the header portion of the group. While processing the header, the determination of the downsampling point can be stopped, and the determined maximum index can be used for symbol recovery of the remainder of the group. In one or more examples, a control signal can be generated to indicate whether the determination of the downsampling point should occur. When the next group is obtained, a maximum value and corresponding index search can be performed on the header portions of the next and subsequent groups.

[0039] Figure 1 It is a block diagram depicting an apparatus 100 for determining downsampling points according to one or more examples.

[0040] Device 100 includes a next sample register 102, a current maximum sample register 104, a comparator 106, a counter 108, an index register 110, and an optional initialization register 112.

[0041] The next sample register 102 receives and stores the next upsample 114 (e.g., receives and stores the value as the next upsample 114, but is not limited thereto). The stored next upsample 114 will be used for comparisons discussed below.

[0042] The current maximum sample register 104 receives and stores a value that is either the current maximum sample or an initialization value used as the current maximum sample. The current maximum sample is the largest sample found during the sequential maximum search discussed herein. Generally, the current maximum sample corresponds to the highest sample value found so far. If the initialization value is used as the current maximum sample, it can come from an optional initialization register 112, as discussed below. The current maximum sample register 104 is initially set to the initialization value and its value is updated when the value of the input sample from the next sample register 102 is greater than the stored value.

[0043] Optional initialization register 112 provides an initialization value to the current maximum sample register 104. In one or more examples, the initialization value can be set to zero or another suitable starting value to ensure that the registers begin in a defined state for comparison.

[0044] Comparator 106 compares the value of the sample stored in the next sample register 102 with the value stored in the current maximum sample register 104, and sets its output to indicate whether the value stored in the current maximum sample register 104 is greater than the value stored in the next sample register 102.

[0045] In one or more examples, if a new group is being processed after a previous group has already been processed, the system starts with known valid values ​​obtained from the previous group: for example, using the final values ​​of the previous group from the previous group—the current maximum sample and the current maximum index—as the starting point for processing the next group.

[0046] If no groups have been processed yet, or if for some reason using values ​​from previous groups is undesirable: obtain random (random or pseudo-random) values, set the current maximum sample to a random value, and set the current maximum index to equal 1. These initial values ​​can (and may be) incorrect, but starting with potentially incorrect values ​​is acceptable because the group start delimiter in the packer header is repeated, thus affecting timing and synchronization blocks (e.g., Figure 2 Timing and synchronization 202) and symbol recovery blocks (e.g., Figure 2 Symbol recovery (204) can run multiple iterations to refine timing and synchronization, thereby ensuring that symbol recovery can detect and align with the packet header despite initial inaccuracies.

[0047] If the output of comparator 106 is set to indicate that the value of the current maximum sample register 104 is not greater than the value stored in the next sample register 102, then the value stored in the next sample register 102 is received in the current maximum sample register 104 (the current maximum sample register 104 is updated using the value of the next sample register 102). If the output of comparator 106 is set to indicate that the value of the current maximum sample register 104 is greater than the value stored in the next sample register 102, then the current maximum sample register 104 is not updated by the value stored in the next sample register 102 (the current maximum sample register 104 continues to store the same value).

[0048] Counter 108 increments in each cycle, tracking the position (index) of each incoming upsampled item in the sequence. The count value indicates the sample stored in the next sample register 102, compared to the sample stored in the current maximum sample register 104. Counter 108 resets whenever the symbol count exceeds a predetermined threshold. In one or more examples, such a predetermined threshold may be set based on a predetermined number of symbols in the downsampling window. In one or more examples, the reset signal may be an internal reset signal of counter 108 (e.g., counter 108 includes, but is not limited to, logic for storing the predetermined threshold, observing when the count exceeds the predetermined threshold, and asserting the reset signal) or an external reset signal provided to counter 108 by logic circuitry (not depicted) indicating the boundaries of the downsampling window.

[0049] Index register 110 stores the current maximum index, which can be read (e.g., by a symbol recovery block). Index register 110 receives an index value from counter 108 when the comparator determines that the next sample should update the current maximum sample. In one or more examples, at least in part in response to the output of comparator 106 being set to indicate that the value of the current maximum sample register 104 is greater than the value stored in the next sample register 102, the value of the current maximum index can be updated based on the count value at counter 108.

[0050] In one or more examples, the operation of device 100 can be enabled / disabled at least in part in response to a control signal. As a non-limiting example, a clock gate (not depicted) can provide a gated clock signal to the next sample register 102, the current maximum sample register 104, the comparator 106, the counter 108, and the index register 110. In response to a control signal configured to indicate that downsampling point determination should be performed, the clock gate can provide a gated clock signal corresponding to the clock signal (e.g., propagating the clock signal or a clock-based signal, but not limited thereto). In response to a control signal configured to indicate that downsampling point determination should not be performed, the clock gate can maintain the state of the gated clock signal (e.g., blocking the clock signal, but not limited thereto). This effectively freezes the state of downstream circuitry (e.g., device 100, but not limited thereto).

[0051] Figure 2 This is a block diagram depicting an apparatus 200 for symbol recovery, determined according to one or more examples, based on a provided downsampling point. As a non-limiting example, timing and synchronization 202 may be or include... Figure 1 Device 100 in the middle.

[0052] Timing and synchronization 202 determines the correct downsampling point (the determined index) within the upsampling sequence of the packet. Timing and synchronization 202 receives upsampled data from the packet and processes it to identify the index pointing to the optimal sample for symbol recovery. The identified index is used to control which samples are selected as downsampling points for further processing. The index determined by timing and synchronization 202 (the determined index represents the downsampling point) is provided to symbol recovery 204 for symbol recovery.

[0053] Symbol recovery 204 receives an index from timing and synchronization 202 and uses that index to select a specific upsample from the packet to convert it back to a symbol. More specifically, symbol recovery 204 receives upsampled packets and receives an index from timing and synchronization 202, and processes the selected sample (based on the received index) to reconstruct and output the recovered symbol of the packet.

[0054] The output of symbol recovery 204 (e.g., but not limited to, the recovered symbol) is provided to timing and synchronization 202. The recovered symbol provided to timing and synchronization 202 can be used to observe the packet header and enable / disable downsampling point determination, as discussed above. Without departing from the scope of this disclosure, the maximum value window may correspond to the header, a portion of the header, a part of the header and another part of the packet, or another part of the packet.

[0055] Figure 3 It is a block diagram depicting 300 for controlling the determination of downsampling points based on one or more examples.

[0056] Device 300 includes a freeze signal controller 302 and device 100. Device 300 is a non-limiting example of device 200.

[0057] The freeze signal controller 302 provides control signals that manage the process of freezing or halting updates to the current maximum sample and index. The freeze signal controller 302 is based, at least in part, on symbols recovered from the block (e.g., but not limited to, symbol recovery blocks). Figure 2 The symbol recovery (204) provides the recovered symbol to set a control signal. In one or more examples, 302 may set the control signal to instruct device 100 to perform or not perform the downsampling point determination as discussed above. In one or more examples, the control signal is triggered at least in part based on the state of the symbol recovery process. In one or more examples, the freeze signal controller 302 monitors the state of the symbol recovery process at least in part based on the recovered symbol output by device 100.

[0058] Figure 4 This is a block diagram depicting a signal processing chain 400 for recovering symbols in a data stream using downsampling point determination, based on one or more examples. The signal processing chain 400 includes an antenna, a signal conditioning unit, phase / frequency offset correction, a matched filter, timing and synchronization, a decoder, and depacketization. In one or more examples, as described above... Figure 1 , Figure 2 or Figure 3Timing and synchronization are implemented as discussed in one or more diagrams. More specifically, the correct downsampling point is determined to align the timing of the signal for symbol recovery as discussed above, and a freeze signal is transmitted when the correct timing has been established, indicating that the process of identifying new downsampling points is temporarily halted. The decoder converts the sampled data (symbols) into a format suitable for further processing, for example, by demodulating or decoding it based on the modulation scheme used. The decoder takes indexed and aligned samples from the timing and synchronization, and decodes the aligned samples into baseband data for interpretation based on the index. Depacketization breaks the decoded data down into usable packets or data structures for further processing. Depacketization ensures that the data is correctly constructed for the final application, whether for transmission to a higher protocol layer or for direct use.

[0059] In one or more examples, the timing and synchronization for symbol recovery are implemented only during the header period (e.g., when processing the header portion of the packet, but not limited to this). At least one downsampling point is in the sample sequence associated with the header portion of the packet. The index for symbol recovery is frozen when processing the portion of the packet outside the maximum value window (e.g., the downsampling point is determined only during the header period of the packet, and thereafter remains fixed for the rest of the packet, but not limited to this).

[0060] Figure 5 These are signal diagrams depicting examples of transmitted symbols. The upper graph (QPSK output data) shows a typical digital output waveform representing QPSK modulated data. This waveform depicts the original output data after modulation, where different amplitude levels correspond to coded symbols. The lower graph (raised cosine filter output of QPSK output data) illustrates the output of the QPSK signal after passing through a raised cosine filter. This filter smooths the digital waveform to reduce high-frequency components and minimize inter-symbol interference (ISI). The upper and lower graphs visually represent the difference between the original QPSK output data and the output after applying the raised cosine filter. Figure 5 The impact of filtering on signal integrity and ISI reduction is highlighted. In the context of timing and synchronization, Figure 5 The diagram illustrates what the signal looks like before and after filtering. Timing and synchronization blocks work together with these filtered signals to identify the correct downsampling point, thereby ensuring accurate symbol recovery.

[0061] The filtered output shows the rounding transitions between symbol levels, consistent with the raised cosine filter characteristics used to prepare the signal for transmission.

[0062] Figure 6 It is a signal graph depicting a portion of the downsampling window. Figure 6A detailed waveform diagram is shown, with marked indices indicating specific sampling points within the waveform. This diagram illustrates a high-density data stream, likely representing an upsampled signal used for symbol recovery. The waveform oscillates between positive and negative values, typical for digital communication signals. Figure 6 This includes marker points along the waveform at specific intervals, labeled as index=7, index=6, etc. These labels indicate the selected downsampling points identified by timing and synchronization blocks during processing. Figure 6 The index of each marker in the sequence corresponds to the sample selected as the best point for symbol extraction within the upsampled sequence.

[0063] Figure 6 The timing and synchronization process is visualized to identify the optimal points for downsampling across the upsampling sequence. These points (e.g., index=6, index=7) are selected as the most suitable locations for symbol recovery, ensuring alignment with the signal's peaks or most representative portions.

[0064] Search for the maximum value within the user-configurable window size. The maximum value is used to set an index for symbolic recovery as discussed in this article.

[0065] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 7 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware capable of performing the functional elements.

[0066] Figure 7 This is a block diagram of circuitry 700 that, in some examples, can be used to implement the various functions, operations, actions, processes, or methods disclosed herein. Circuitry 700 includes one or more processors 702 (sometimes referred to herein as "processor 702") operatively coupled to one or more data storage devices 704 (sometimes referred to herein as "storage device 704"). Storage device 704 includes machine-executable code 706 stored thereon, and processor 702 includes logic circuitry 708. Machine-executable code 706 includes information describing functional elements that can be implemented (e.g., executed) by logic circuitry 708. Logic circuitry 708 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 706. When executing the functional elements described by machine-executable code 706, circuitry 700 should be considered as dedicated hardware for executing the functional elements disclosed herein. In one or more examples, processor 702 may execute the functional elements described by machine-executable code 706 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0067] When implemented by the logic circuitry 708 of the processor 702, the machine-executable code 706 adapts the processor 702 to perform the operations of the examples disclosed herein. With the aid of non-limiting examples, the machine-executable code 706 can adapt the processor 702 to perform some or all of the process operations discussed herein.

[0068] Processor 702 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer is considered a special-purpose computer at least when it includes one or more processors 702 (including the general-purpose processor) executing functional elements corresponding to machine-executable code 706 (e.g., software code, firmware code, configuration data, hardware description, but not limited thereto) associated with the examples of this disclosure. It should be noted that the general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in alternatives, the general-purpose processor of processor 702 may include any conventional processor, controller, microcontroller, or state machine. The FPGA or other PLD of processor 702 may be configured (e.g., programmed, but not limited thereto) with configuration data to perform the functions disclosed herein, or additionally or alternatively, may be configured or reconfigured (e.g., programmable or reprogrammable, but not limited thereto) with configuration data to perform the functions disclosed herein. Processor 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0069] In one or more examples, storage device 704 includes volatile data storage devices (e.g., random access memory (RAM), static RAM (SRAM), but not limited thereto) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 702 and storage device 704 may be implemented as a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 702 and storage device 704 may be implemented as separate devices.

[0070] In one or more examples, machine-executable code 706 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 704, directly accessed by processor 702, and executed by processor 702 using at least logic circuitry 708. Also as a non-limiting example, the computer-readable instructions may be stored on storage device 704, passed to a memory device (not shown) for execution, and executed by processor 702 using at least logic circuitry 708. Processor 702 or its logic circuitry 708 may be coupled to or include such a memory device (e.g., configuring memory cells, but not limited thereto). Therefore, in some examples, logic circuitry 708 includes electrically configurable logic circuitry 708.

[0071] In one or more examples, machine-executable code 706 may describe the hardware (e.g., circuitry) to be implemented in logic circuitry 708 to perform functional elements. This hardware can be described from any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstractions, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), can be used. With the aid of non-limiting examples, Verilog, SystemVerilog, or VLSI hardware description language (VHDL) can be used.

[0072] HDL descriptions can be transformed into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be transformed into a logic-level description such as Register Pass Language (RTL), Gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, micro-operations performed by the hardware logic circuitry of logic circuitry 708 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL and then transformed into a GL description by a synthesis tool, and the GL description can be transformed into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic, discrete hardware components, or combinations thereof of a programmable logic device. Therefore, in some examples, machine-executable code 706 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0073] In an example where machine-executable code 706 includes a hardware description (at any level of abstraction), the system (not shown, but including storage device 704) implements the hardware description described by machine-executable code 706. As a non-limiting example, processor 702 may include a programmable logic device (e.g., an FPGA or PLC, but not limited thereto), and logic circuitry 708 may be electrically controlled (e.g., via configuration data, but not limited thereto) to implement circuitry corresponding to the hardware description into logic circuitry 708. Again, by a non-limiting example, logic circuitry 708 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage device 704) according to the hardware description of machine-executable code 706.

[0074] Regardless of whether the machine-executable code 706 includes computer-readable instructions or a hardware description, the logic circuit 708 is adapted to execute the functional elements described by the machine-executable code 706 when implementing the functional elements of the machine-executable code 706. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0075] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, but not limited thereto) of a computing system. In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0076] Figure 8 This describes an example process 800 for determining downsampling points in a symbol sample, based on one or more examples. Although the example process 800 depicts a specific sequence of operations, this sequence may be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of process 800. In other examples, different components of the example device or system implementing process 800 may perform their functions substantially simultaneously or in a specific order.

[0077] According to one or more examples, process 800 may include obtaining samples associated with one or more symbols of the group at operation 802. In one or more examples, the obtained samples are upsampled. Upsampling is sampling of the signal at a rate higher than the original symbol rate of the data (sampling rate > original symbol rate).

[0078] According to one or more examples, process 800 may include determining at block 804 at at least one downsampling point in the sample sequence associated with the header portion of the packet. In one or more examples, process 800 determines the downsampling point only during the header portion of the packet and does not determine the downsampling point during the portion of the packet other than the header portion. In one or more examples, the header portion may be defined as a fixed time window corresponding to a predetermined duration starting at the beginning of the packet or at a delimiter indicating the start of the header. This predetermined duration may be based on the bit rate or symbol rate and the number of bits or symbols in the header portion (header length). In one or more examples, the header portion may be defined based on a specific number of symbols or bits. In one or more examples, the header portion may be defined based on a known symbol pattern or synchronization sequence. In one or more examples, the header portion may be determined dynamically, for example, the header portion may be defined based on, but is not limited to, the time at which the system is actively processing and synchronizing with the header of the packet.

[0079] In one or more examples, process 800 may freeze the downsampling points for the remaining portion of the grouping determined.

[0080] According to one or more examples, process 800 may include recovering one or more symbols and subsequent symbols at block 806 using samples associated with the determined downsampling point. As used in this disclosure, the term "combination" relating to multiple elements may include any combination of all elements or any of a variety of different sub-combinations of some elements. For example, the phrase "A, B, C, D or combinations thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0081] The terms used in this disclosure, and especially in the appended concepts (e.g., the subject of the appended concepts, but not limited thereto), are generally intended to be “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, and the term “having” should be interpreted as “having at least, but not limited to”). As used herein, the term “each” means “some or all”. As used herein, the terms “each and every” mean “all”.

[0082] Furthermore, if a particular number of conceptual expressions are anticipated, such intent will be explicitly stated in the concept, and without such expressions, such intent does not exist. For example, as an aid to understanding, the concepts appended below may contain the use of introductory phrases “at least one” and “one or more” to introduce conceptual expressions. However, the use of such phrases should not be construed as implying that a conceptual expression introduced by the indefinite article “a” or “an” limits any particular concept containing such an introductory conceptual expression to an example containing only one such expression, even when the same concept includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”, but is not limited thereto); the same applies to the use of definite articles to introduce conceptual expressions.

[0083] Furthermore, even when a specific number of introduced conceptual expressions are explicitly stated, those skilled in the art will recognize that such expressions should be interpreted as referring to at least the stated number (e.g., the unmodified expression "two expressions" means, in the absence of other modifiers, at least two expressions, or two or more expressions, but not limited thereto). Additionally, in instances where conventions such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include, but are not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0084] Furthermore, any separate word or phrase presenting two or more alternative terms, whether in the specification, concept, or drawings, should be understood to imply the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0085] Additional non-limiting embodiments include:

[0086] Example 1: A method comprising: obtaining samples associated with one or more symbols of a group; determining at least one downsampling point in a sequence of samples associated with a header portion of the group; and recovering the one or more symbols and subsequent symbols using samples associated with the determined downsampling point.

[0087] Example 2: The method described in Example 1, wherein the subsequent symbols are recovered without redetermining the downsampling point or without determining a new downsampling point.

[0088] Example 3: The method according to any one of Examples 1 and 2, wherein the obtained sample is an upsampling of the group.

[0089] Example 4: The method according to any one of Examples 1 to 3, the method includes freezing the determined downsampling points after processing the header portion of the group, and maintaining the frozen downsampling points for the duration of the group.

[0090] Example 5: The method according to any one of Examples 1 to 4, the method includes initializing the current maximum sample register with a predetermined value or a random value before determining the downsampling point.

[0091] Example 6: The method according to any one of Examples 1 to 5, wherein determining the downsampling point includes sequentially comparing each sample in the header portion to identify the sample with the highest value.

[0092] Example 7: The method according to any one of Examples 1 to 6 further includes resetting or re-initializing the downsampling point determination process at the beginning of the new group.

[0093] Example 8: The method according to any one of Examples 1 to 7, the method further includes generating a control signal to freeze the downsampling point after processing the header portion.

[0094] Example 9: The method according to any one of Examples 1 to 8, wherein determining at least one downsampling point in the sample sequence associated with the header portion of the group comprises determining the at least one downsampling point based at least in part on a sequential search of the highest sample within the header portion.

[0095] Example 10: An apparatus comprising: a symbol recovery circuit; and a timing and synchronization circuit, the timing and synchronization circuit being configured to determine at least one downsampling point based at least in part on a sample sequence associated with a header portion of a packet, and to indicate the determined downsampling point to the symbol recovery circuit.

[0096] Example 11: The apparatus according to Example 10, wherein the symbol recovery circuit is used to recover subsequent symbols without re-determining or being uncertain about a new downsampling point after determining the initial downsampling point.

[0097] Example 12: The apparatus according to any one of Examples 10 and 11, wherein the timing and synchronization circuitry is used to obtain an upsampled sample of the group as the sampling sequence associated with the one or more symbols.

[0098] Example 13: The apparatus according to any one of Examples 10 to 12, wherein the timing and synchronization circuitry is used to freeze the determined downsampling point after the header portion of the packet is processed, and to maintain the frozen downsampling point for the duration of the packet.

[0099] Example 14: The apparatus according to any one of Examples 1 to 13, the apparatus further includes a current maximum sample register, which is initialized with a predetermined value or a random value before the timing and synchronization circuit determines the downsampling point.

[0100] Example 15: The apparatus according to any one of Examples 1 to 14, wherein the timing and synchronization circuit determines the downsampling point by sequentially comparing each sample in the header portion to identify the sample with the highest value.

[0101] Example 16: The apparatus according to any one of Examples 1 to 15, wherein the timing and synchronization circuitry is used to reset or reinitialize the downsampling point determination process at the beginning of a new group.

[0102] Example 17: The apparatus according to any one of Examples 1 to 16, the apparatus further comprising a control signal generator for generating a control signal to freeze the downsampling points after processing the header portion of the group.

[0103] Example 18: An apparatus according to any one of Examples 1 to 17, wherein the timing and synchronization circuitry is used to determine, at least one downsampling point in the sample sequence associated with the header portion of the group, based at least in part on a sequential search of the highest sample within the header portion.

[0104] Example 19: A system for a signal processing chain, the system comprising: an antenna for receiving an incoming communication signal; a signal conditioning unit for processing the incoming communication signal to reduce noise and adjust gain; a frequency and phase offset correction unit for aligning the signal in the time and frequency domains; a matched filter for optimizing the signal-to-noise ratio of the processed signal; a timing and synchronization circuit for: determining downsampling points in a sample sequence associated with a header portion of a packet; freezing the determined downsampling points after processing the header portion; and maintaining the frozen downsampling points for use throughout the remainder of the packet; a decoder block for decoding symbols associated with the frozen downsampling points provided by the timing and synchronization circuit; and a degrouping unit for constructing usable packets from the decoded data.

[0105] Example 20: The system according to Example 19, wherein the timing and synchronization circuit restricts the determination of the downsampling point to the header portion of the group.

[0106] Example 21: The system according to any one of Examples 19 and 20, the system further includes a control signal generator for transmitting a freeze signal to the timing and synchronization circuit to indicate when to maintain the determined downsampling point for the remainder of the group.

[0107] Example 22: The system according to any one of Examples 19 to 21, wherein the timing and synchronization circuitry is used to perform a sequential search on the highest sample within the header portion of the group to determine the downsampling point.

[0108] Example 23: The system according to any one of Examples 19 to 22, wherein the signal conditioning unit, the frequency and phase offset correction unit, and the matched filter are used to provide upsampling of the group to the timing and synchronization circuit for determining the downsampling point.

[0109] While this disclosure has been described with respect to certain exemplary embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the exemplary and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. A method, the method comprising: Obtain samples associated with one or more symbols in a group; Identify at least one downsampling point in the sample sequence associated with the header portion of the group; as well as The one or more symbols, as well as subsequent symbols, are recovered using samples associated with the determined downsampling points.

2. The method of claim 1, wherein the subsequent symbols are recovered without redetermining the downsampling point or without determining a new downsampling point.

3. The method of claim 1, wherein the obtained sample is an upsampling of the group.

4. The method of claim 1, wherein the method includes freezing the determined downsampling points after processing the header portion of the group, and maintaining the frozen downsampling points for the duration of the group.

5. The method of claim 1, wherein the method includes initializing the current maximum sample register with a predetermined value or a random value before determining the downsampling point.

6. The method of claim 1, wherein determining the downsampling point comprises sequentially comparing each sample in the header portion to identify the sample with the highest value.

7. The method of claim 1, further comprising resetting or reinitializing the downsampling point determination process at the beginning of the new group.

8. The method of claim 4, further comprising generating a control signal to freeze the downsampling points after processing the header portion.

9. The method of claim 1, wherein determining at least one downsampling point in the sample sequence associated with the header portion of the group comprises determining the at least one downsampling point based at least in part on a sequential search of the highest sample within the header portion.

10. An apparatus comprising: Symbol recovery circuit; and A timing and synchronization circuit is provided for determining at least one downsampling point based at least in part on a sample sequence associated with the header portion of a packet, and for indicating the determined downsampling point to the symbol recovery circuit.

11. The apparatus of claim 10, wherein the symbol recovery circuit is configured to recover subsequent symbols after determining the initial downsampling point without re-determining or determining a new downsampling point.

12. The apparatus of claim 10, wherein the timing and synchronization circuitry is used to obtain an upsampled version of the packet as the sampling sequence associated with the one or more symbols.

13. The apparatus of claim 10, wherein the timing and synchronization circuitry is configured to freeze the determined downsampling points after processing the header portion of the packet, and to maintain the frozen downsampling points for the duration of the packet.

14. The apparatus of claim 10, further comprising a current maximum sample register, the current maximum sample register being initialized with a predetermined value or a random value before the timing and synchronization circuit determines the downsampling point.

15. The apparatus of claim 10, wherein the timing and synchronization circuit determines the downsampling point by sequentially comparing each sample in the header portion to identify the sample with the highest value.

16. The apparatus of claim 10, wherein the timing and synchronization circuitry is used to reset or reinitialize the downsampling point determination process at the beginning of a new group.

17. The apparatus of claim 13, further comprising a control signal generator for generating a control signal to freeze the downsampling points after processing the header portion of the group.

18. The apparatus of claim 10, wherein the timing and synchronization circuitry is configured to determine, at least one downsampling point in the sample sequence associated with the header portion of the group, based at least in part on a sequential search of the highest sample within the header portion.

19. A system for a signal processing chain, the system comprising: An antenna for receiving incoming communication signals; A signal conditioning unit is used to process the incoming communication signal to reduce noise and adjust the gain; A frequency and phase offset correction unit, the frequency and phase offset correction unit being used to align the signal in the time domain and the frequency domain; A matched filter, wherein the matched filter is used to optimize the signal-to-noise ratio of the processed signal; Timing and synchronization circuit, the timing and synchronization circuit being used for: Determine the downsampling point in the sample sequence associated with the header portion of the group; After processing the header portion, the determined downsampling points are frozen; as well as Retain the frozen downsampling points for use throughout the remainder of the group; A decoder block for decoding symbols associated with frozen downsampling points provided by the timing and synchronization circuitry; and A degrouping unit is used to construct usable packets from the decoded data.

20. The system of claim 19, wherein the timing and synchronization circuitry limits the determination of the downsampling point to the header portion of the group.

21. The system of claim 19, further comprising a control signal generator for transmitting a freeze signal to the timing and synchronization circuitry to indicate when to maintain the determined downsampling point for the remainder of the group.

22. The system of claim 19, wherein the timing and synchronization circuitry is used to perform a sequential search on the highest sample within the header portion of the group to determine the downsampling point.

23. The system of claim 19, wherein the signal conditioning unit, the frequency and phase offset correction unit, and the matched filter are used to provide upsampling of the packets to the timing and synchronization circuit for determining the downsampling point.

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