Use of n-heterocyclic carbenes as self-assembled monolayer selective barriers for metal surfaces

Abstract

A method for selectively depositing material on a dielectric surface relative to a metal surface is disclosed. The metal surface is protected with a self-assembled monolayer comprising N-heterocyclic carbides before depositing a liner or barrier layer on an adjacent dielectric surface.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to methods for forming semiconductor structures. More specifically, some embodiments of this disclosure relate to a method for selectively depositing a self-assembled monolayer on a non-metallic surface using a precursor, wherein the precursor comprises an N-heterocyclic carbide. Background Technology

[0002] Generally speaking, an integrated circuit (IC) refers to a group of electronic components, such as transistors formed on a small chip of semiconductor material (usually silicon). Typically, an IC includes one or more metallization layers with metal lines to connect the IC's electronic components to each other and to external connections. Interlayer dielectric material layers are typically placed between the IC's metallization layers for insulation.

[0003] As IC dimensions decrease, the spacing between metal lines also decreases. Typically, a planar process is used to fabricate interconnect structures, which involves aligning one metallization layer with another.

[0004] Reducing the impedance of vias is crucial for improving the performance of electronic components. This reduction is typically achieved by minimizing the encapsulation and lowering the resistivity of the via material.

[0005] Selective barrier and liner applications typically utilize alkyne-based self-assembled monolayers (SAMs) to selectively block material (e.g., tantalum nitride) deposition onto metal surfaces, allowing for selective deposition on dielectric surfaces. This reduces RC delay and enables faster chipsets with lower power consumption. For newer technology nodes, selective deposition processes are challenging to integrate and may expose multiple metal surfaces during liner deposition. Conventional bifunctional self-assembled monolayers with alkyne and alcohol groups block both metals and dielectrics (such as alumina).

[0006] Therefore, a method is needed to selectively deposit a liner or barrier layer on a dielectric surface while preventing deposition on different metal surfaces. Summary of the Invention

[0007] One or more embodiments of this disclosure relate to a method of forming a semiconductor structure, the method comprising: selectively depositing a self-assembled monolayer (SAM) on a first surface of a substrate by exposing a substrate to a first precursor, wherein the substrate has at least one feature including a first surface and a second surface, and wherein the first precursor comprises N-heterocyclic carbides; selectively depositing a liner on a second surface by exposing the substrate to a second precursor; and removing the self-assembled monolayer (SAM), wherein the first surface comprises a metal and the second surface comprises a dielectric material.

[0008] Additional embodiments relate to a method of forming a semiconductor structure, the method comprising: exposing a substrate to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature including a first surface and a second surface; exposing the substrate to a second precursor to selectively deposit a liner on the second surface; and removing the self-assembled monolayer (SAM), wherein the first surface comprises a metal selected from one or more of the following: copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo), wherein the second surface comprises a dielectric material, wherein the first precursor has a molecular weight in the range of 50 to 500 ketons, and the first precursor comprises one or more of the following:

[0009] , , or , , , or .

[0010] Further embodiments of this disclosure relate to a method of forming a semiconductor structure, the method comprising: exposing a substrate to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature including a first surface and a second surface; exposing the substrate to a second precursor to selectively deposit a liner on the second surface; and removing the self-assembled monolayer (SAM), wherein the first surface comprises a metal selected from one or more of the following: tungsten (W) and molybdenum (Mo), wherein the second surface comprises a dielectric material, wherein the first precursor has a vapor pressure in the range of 100 millitorr to 100 tor at 120 °C, and wherein the first precursor comprises one or more of the following:

[0011] , , , , or . Attached Figure Description

[0012] Therefore, the above-described features of this disclosure can be understood in detail by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of this disclosure and should not be considered as limiting the scope, as other equivalent embodiments are permissible.

[0013] Figure 1Draw a process flow diagram of one or more embodiments of the method according to this disclosure;

[0014] Figures 2A to 2F A cross-sectional view of an exemplary substrate drawn during processing according to one or more embodiments of this disclosure; and

[0015] Figure 3 A tool for drawing exemplary clusters according to one or more embodiments of this disclosure. Detailed Implementation

[0016] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the setup or processing procedures set forth in the following description. This disclosure can have other embodiments and can be implemented or performed in various ways.

[0017] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which the process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may refer only to a portion of a substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0018] As used herein, "substrate" refers to any substrate or material surface formed on a substrate, on which a film treatment is performed during a manufacturing process. For example, depending on the application, substrate surfaces on which treatment can be performed may include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials (such as metals, metal nitrides, metal alloys, and other conductive materials). Substrates may include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any film treatment procedures disclosed herein (disclosed in more detail below) may also be performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such an underlayer as referred to herein. Therefore, for example, when a film / layer or part of a film / layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0019] As used herein, “atomic layer deposition” or “cyclical deposition” refers to the sequential exposure of two or more reactive compounds to deposit a material layer on a substrate surface. As used in this specification and the appended claims, the terms “reactive compound,” “reactive gas,” “reactive species,” “precursor,” “process gas,” etc., are used interchangeably to refer to a substance having a species capable of reacting with the substrate surface or with materials on the substrate surface in a surface reaction (e.g., chemisorption, oxidation, reduction). The substrate surface, or a portion of the substrate, is sequentially or substantially sequentially exposed to the precursor (or reactive gas). As used throughout this specification, “substantially sequentially” means that the majority of the duration of the precursor exposure does not overlap with the exposure to the auxiliary reagent, although some overlap may exist.

[0020] For many applications, metals can be grown via atomic layer deposition. One or more embodiments of this disclosure advantageously provide a process for atomic layer deposition to form metal-containing films. As used in this specification and the appended claims, the term "metal-containing film" refers to a film containing metal atoms and having a metal content greater than or equal to about 1 atomic percent, 2 atomic percent, 3 atomic percent, 4 atomic percent, 5 atomic percent, 10 atomic percent, 15 atomic percent, 20 atomic percent, 25 atomic percent, 30 atomic percent, 35 atomic percent, 40 atomic percent, 45 atomic percent, 50 atomic percent, 55 atomic percent, 60 atomic percent, or 65 atomic percent. In some embodiments, the metal-containing film comprises one or more of the following: metal, metal nitride, metal carbide, or metal oxide. Those skilled in the art to which this application pertains will understand that the use of a molecular formula such as MO (where M is a metal) does not imply a specific stoichiometric relationship between elements, but merely indicates the identity of the predominant component of the membrane. For example, MO refers to a membrane whose predominant composition comprises metal and oxygen atoms. In some embodiments, the predominant component of the membrane (i.e., the sum of the atomic percentages of the specified atoms) is greater than or equal to approximately 95%, 98%, 99%, or 99.5% of the membrane.

[0021] As used herein, the phrases “metallic material surface” and “non-metallic material surface” refer to the surface of a metallic or non-metallic material, respectively. For the purposes of this disclosure, a non-metallic material is any material that exhibits properties of a poor conductor or a good insulator. Non-metallic materials may include metallic atoms (e.g., tantalum nitride, titanium nitride) and still fall within the scope of non-metallic materials. In some embodiments, the term “conductive material” is used instead of “metallic material.” In some embodiments, the term “dielectric material” is used instead of “non-metallic material.”

[0022] As used herein, the phrase "selectively depositing on a first surface over a second surface" means: depositing a first amount or thickness on a first surface and depositing a second amount or thickness on a second surface, wherein the second amount or thickness is less than the first amount or thickness, or, in some embodiments, no amount of deposition on the second surface.

[0023] The term "over" as used in this article does not imply a physical orientation of one surface on top of another, but rather a thermodynamic or kinetic relationship of the chemical reactions of one surface relative to another. For example, selectively depositing a film onto a metallic surface more than a non-metallic surface means that the film is deposited on the metallic surface, with less or no film deposited on the non-metallic surface; or it means that there is a thermodynamic or kinetic tendency to form a film on a metallic surface compared to forming a film on a non-metallic surface.

[0024] Reducing contact resistance (Rc) is crucial for semiconductor structures at the 3 nm node (N3) and below. One or more embodiments of this disclosure relate to a method of selectively forming a self-assembled monolayer (SAM) on a first surface rather than a second surface of a substrate. The substrate comprises a metallic material (conductive material) having a first surface and a non-metallic material (dielectric material) having a second surface. In some embodiments, the first surface may be described as a metallic material surface or a conductive material surface. In some embodiments, the first surface comprises one or more of the following: copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo). In some embodiments, the second surface may be described as a non-metallic material surface or a dielectric material surface. In some embodiments, the methods described herein have both middle end-of-line (MEOL) and back end-of-line (BEOL) applications.

[0025] Please see Figure 1This is a process flow diagram. One or more embodiments of this disclosure relate to a method 100 for forming electronic components. Figure 1 The method described represents the integrated process.

[0026] Figures 2A to 2F A cross-sectional view of an exemplary element 200 during a processing method 100 according to one or more embodiments of this disclosure is provided. See also... Figure 2A The provided substrate 210 has a barrier layer 215, a metal liner 220, a conductive layer 225, an etch stop layer 230, and a dielectric layer 235. In one or more embodiments, the dielectric layer 235 has at least one feature 240. In some embodiments, the substrate 210 is a wafer, such as a semiconductor substrate. In some embodiments, the substrate 210 is an etch stop layer on a wafer.

[0027] For illustrative purposes, Figure 2A A substrate 210 with a single feature 240 is illustrated. However, those skilled in the art to which this invention pertains will understand that more than one feature may exist. For example... Figure 2A As shown, feature 240 includes a first surface 245 and a second surface 250. In some embodiments, the first surface 245 is the bottom surface of feature 240. In some embodiments, the second surface 250 is a sidewall of feature 240. The shape of feature 240 can be any suitable shape, including but not limited to trenches, vias (which, when filled with metal, can be used to conduct current between layers), and traces that conduct current within the same element layer. It should be understood that in one or more embodiments, conductive layer 225 forms a metal trace that conducts current within the same element layer. In some embodiments, feature 240 defines a gap in dielectric layer 235. As used herein, the term "feature" refers to any intentionally formed surface irregularity. Suitable examples of features include, but are not limited to, trenches and spikes, with trenches having a top, two sidewalls, and a bottom, and spikes having a top and two sidewalls. Features can have any suitable aspect ratio (the ratio of the depth of a feature to the width of a feature). In some implementations, the aspect ratio is greater than or equal to about 1:1, 2:1, 3:1, 4:1, 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1 or 40:1.

[0028] In one or more embodiments, the barrier layer 215 is a conformal layer. The barrier layer 215 may comprise any suitable material known to those skilled in the art to which this application pertains and can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the barrier layer is selected from titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). In a specific embodiment, the barrier layer 215 comprises tantalum nitride (TaN). In some embodiments, the barrier layer 215 is formed by ALD. In some embodiments, the barrier layer 215 prevents material from diffusing through itself to the underlying layer.

[0029] In one or more embodiments, the metal liner 220 may comprise any suitable metallic material known to those skilled in the art to which this application pertains, and may be deposited by any technique known to those skilled in the art. In one or more embodiments, the metal liner 220 comprises one or more of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In one or more embodiments, the metal liner 220 comprises one or more of a monolayer of tungsten (W) or a monolayer of molybdenum (Mo). In some embodiments, the metal liner 220 comprises tungsten or molybdenum, or is substantially composed of tungsten or molybdenum. As used in this specification and the appended claims, the term "consists essentially of" means that, atomically, the material is greater than or equal to about 95%, 98%, or 99% of the referred material.

[0030] In one or more embodiments, the conductive layer 225 comprises a metal or metallic material. In some embodiments, the metal or metallic material may be any suitable metallic material. In some embodiments, the metallic material disclosed herein is a conductive material. Suitable metallic materials include, but are not limited to: metals, conductive metal nitrides, conductive metal oxides, metal alloys, silicon, combinations of the foregoing, and other conductive materials.

[0031] As used in this specification and the appended claims, the term "oxide" and similar terms mean that a material contains a specified number of elements. This term should not be construed as implying a specific proportion of the elements. Therefore, "oxide" or the like may encompass either a stoichiometric ratio of elements or a non-stoichiometric ratio of elements.

[0032] In one or more embodiments, the metal or metallic material may comprise any suitable metal known to those skilled in the art to which this application pertains. In some embodiments, the metal or metallic material is selected from one or more of the following: copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), and platinum (Pt). In some embodiments, the metal or metallic material is substantially composed of copper (Cu), cobalt (Co), ruthenium (Ru), iridium (Ir), rhodium (Rh), molybdenum (Mo), tungsten (W), aluminum (Al), nickel (Ni), or platinum (Pt). In some embodiments, the metal or metallic material is substantially composed of copper, cobalt, ruthenium, tungsten, or molybdenum. In some embodiments, the metallic material comprises tungsten or molybdenum or is substantially composed of tungsten or molybdenum.

[0033] In one or more embodiments, the etch stop layer 230 comprises any suitable material known to those skilled in the art to which this application pertains. In one or more embodiments, the etch stop layer 230 comprises one or more of the following: silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlO). x ) and aluminum nitride (AlN). In some embodiments, techniques selected from CVD, PVD and ALD can be used to deposit the etch stop layer 230.

[0034] In one or more embodiments, a portion of the metal liner 220 and the etch stop layer 230 may be removed, exposing a bottom first surface 245 of at least one feature 240. In some embodiments, the bottom first surface 245 is a portion of the top surface of the conductive material 225, such that a portion of the conductive material 225 is exposed.

[0035] In one or more embodiments, dielectric layer 235 may be any suitable material. In some embodiments, dielectric layer 235 insulates adjacent components and prevents leakage. Suitable dielectric materials include, but are not limited to: silicon oxide (e.g., SiO2), silicon nitride (e.g., SiN), silicon carbide (e.g., SiC), and combinations thereof (e.g., SiCON). Suitable dielectric materials further include aluminum oxide, aluminum nitride, and low dielectric constant (k) dielectric materials. In some embodiments, the dielectric material is substantially composed of silicon dioxide (SiO2). In some embodiments, dielectric layer 235 comprises silicon nitride. In some embodiments, dielectric layer 235 is substantially composed of silicon nitride.

[0036] In one or more embodiments, any suitable deposition technique is used to deposit the dielectric layer 235, such as, but not limited to: chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), molecular beam epitaxy (“MBE”), metal-organic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALD”), spin coating, or other deposition techniques known to those skilled in the art of microelectronic component fabrication.

[0037] In one or more embodiments, during one or more operations of method 100, the substrate 210 can be independently maintained under an operating pressure. In some embodiments, the operating pressure is less than or equal to 100 tors, less than or equal to 80 tors, less than or equal to 70 tors, less than or equal to 60 tors, less than or equal to 50 tors, less than or equal to 40 tors, less than or equal to 30 tors, less than or equal to 20 tors, less than or equal to 15 tors, less than or equal to 10 tors, less than or equal to 5 tors, less than or equal to 1 tor, less than or equal to 500 millitons, less than or equal to 200 millitons, less than or equal to 100 millitons, or less than or equal to 50 millitons. In some embodiments, the operating pressure is 10 tors, 20 tors, 30 tors, 40 tors, 50 tors, or 100 tors. In some embodiments, during the deposition of a self-assembled monolayer (SAM)... During period 255, substrate 210 is maintained at pressures within the following ranges: from 1 millitor to 100 torts, from 1 millitor to 80 torts, from 1 millitor to 60 torts, from 1 millitor to 40 torts, from 1 millitor to 20 torts, from 1 millitor to 10 torts, from 1 millitor to 5 torts, from 1 millitor to 1 tort, from 1 millitor to 500 millitors, from 1 millitor to 200 millitors, from 1 millitor to 100 millitors, from 1 millitor to 50 torts, from 500 millitors to 100 torts, from 500 millitors to 80 torts, from 500 millitors to 60 torts, from 500 millitors to 40 torts, from 500 to 6 ... From millitor to 20 tors, from 500 millitor to 10 tors, from 500 millitor to 5 tors, from 500 millitor to 1 tor, from 1 tor to 100 tors, from 1 tor to 80 tors, from 1 tor to 60 tors, from 1 tor to 40 tors, from 1 tor to 20 tors, from 1 tor to 10 tors, from 1 tor to 5 tors, from 10 tor to 100 tors, from 10 tor to 80 tors, from 10 tor to 60 tors, from 10 tor to 40 tors, from 10 tor to 20 tors, from 20 tor to 100 tors, from 20 tor to 80 tors, from 20 tor to 60 tors, or from 20 tor to 40 tors.

[0038] In some embodiments, the temperature of the substrate is controlled during method 100. The temperature of the substrate may also be referred to as the operating temperature. In some embodiments, the operating temperature is less than or equal to 450°C, less than or equal to 400°C, less than or equal to 350°C, less than or equal to 300°C, less than or equal to 275°C, less than or equal to 250°C, less than or equal to 225°C, less than or equal to 200°C, less than or equal to 150°C, less than or equal to 100°C, or less than or equal to 80°C. In some embodiments, during the deposition of the self-assembled monolayer (SAM) 255, the operating temperature is in the following ranges: from 60°C to 450°C, from 60°C to 350°C, from 60°C to 250°C, from 60°C to 150°C, from 60°C to 100°C, from 100°C to 450°C, from 100°C to 350°C, from 100°C to 250°C, from 100°C to 200°C, from 200°C to 450°C, from 200°C to 350°C, from 200°C to 300°C, from 300°C to 450°C, from 300°C to 350°C, or from 400°C to 450°C.

[0039] Please see Figure 1 Example method 100 begins with a pre-cleaning operation 102, depending on the circumstances. The pre-cleaning operation can be any suitable pre-cleaning process known to those skilled in the art to which this application pertains. Suitable pre-cleaning operations include, but are not limited to, immersion, primary oxide removal, etc. In some embodiments, pre-cleaning operation 102 cleans the first surface 245 and the second surface 250. In some embodiments, pre-cleaning operation 102 results in the formation of substantially oxide-free surfaces of the substrate 210 (e.g., the first surface 245 and / or the second surface 250). As used herein, the term "substantially oxide-free" means that, on an atomic basis, the surface has less than 10%, less than 5%, less than 4%, less than 3%, less than 2%, or less than 1% oxygen.

[0040] In operation 104, substrate 210 is exposed to a first precursor to deposit a self-assembled monolayer (SAM) 255. As used herein, the phrase “exposing substrate to” means that the entire substrate (including the individual materials and layers thereon) is exposed to the referred process or conditions. Figure 2BA self-assembled monolayer (SAM) 255 is depicted deposited on the first surface 245 of feature 240. In some embodiments, the SAM 255 is selectively deposited on the first surface 245 of feature 240 more than on the second surface 250. In some embodiments, the SAM is not deposited on the second surface 250 of feature 240. In one or more embodiments, the SAM 255 is deposited on the exposed first surface 245 of the conductive layer 225 in the bottom of feature 240. Note that, as described above, a portion of the conductive layer 225 in the bottom of feature 240 (such as the first surface 245) can be exposed, for example, by etching away a portion of the metal liner 220 and a portion of the etch stop layer 230. In some embodiments, operation 104 is a dry deposition process.

[0041] In some implementations, "selectively" means forming the host material on the selected surface at a formation rate greater than or equal to approximately 1.5, 2, 3, 4, 5, 7, 10, 15, 20, 25, 30, 35, 40, 45, or 50 times the formation rate on the non-selected surface. In other words, the process has a selectivity for the selected surface greater than or equal to approximately 3:2, 2:1, 3:1, 4:1, 5:1, 7:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, or 50:1 relative to the non-selected surface.

[0042] In one or more embodiments, the first precursor is reversibly bonded to the metal. In some embodiments, the self-assembled monolayer (SAM) 255 formed from the first precursor remains substantially intact during subsequent operations of method 100. As used herein, the term "substantially" means that up to 99%, 98%, 95%, 90%, or 80% of the self-assembled monolayer (SAM) 255 remains intact during subsequent operations of method 100.

[0043] Some embodiments of this disclosure provide a selective deposition method that uses a derivative of benzimidazolium hydrogen carbonate to hinder deposition on a metal surface for selective barrier and / or liner applications.

[0044] In some embodiments, the first precursor has the general formula of structure (I) or structure (II):

[0045] (I)

[0046] (II)

[0047] Wherein R and R' are independently selected from: hydrogen, C1-C8 alkyl groups, aryl groups, C2-C8 alkenyl groups, and / or C2-C8 alkyne groups. Counter anions include, but are not limited to: bicarbonate ions (HCO3-). - ), chloride ions (Cl) - ), bromide ions (Br) - ), iodide ions (I) - ), cyanide ions (CN) - ), thiocyanate ion (SCN) - ), isothiocyanate ion (NCS) - ), cyanate ion (OCN) - ), isocyanate ions (NCO) - ), Azide group (N3) - ) and carboxylate ions (R''COO) - ), wherein R'' is selected from hydrogen, C1-C8 alkyl groups, C2-C8 alkenyl groups, C2-C8 alkynyl groups and / or aromatic groups.

[0048] In some embodiments, the first precursor (i.e., the SAM precursor) is a hydrocarbon molecule incorporating one or more amine or nitrogen-containing carbide groups attached to a carbon atom. In some embodiments, the precursor does not contain any metals and / or halogens. In some embodiments, the first precursor has a molecular weight in the range of 100 to 500 doltons. In some embodiments, the first precursor has a vapor pressure greater than or equal to 100 millitorrels at 120ºC.

[0049] Non-limiting examples of suitable chemicals for use as first precursors include:

[0050] , , or , , , or .

[0051] In some embodiments, the first precursor has a general formula according to any one of structures (III) to (IX):

[0052] (III)

[0053] (IV)

[0054] (V)

[0055] (VI)

[0056] (VII)

[0057] (VIII)

[0058] (IX)

[0059] R1 to R6 are each independently selected from hydrogen, straight-chain C1-C20 alkyl groups, branched C3-C20 alkyl groups, cyclic C3-C20 alkyl groups, or aryl groups.

[0060] Suitable examples of first precursor chemicals include, but are not limited to:

[0061] , , , , or .

[0062] In some implementations, the first precursor comprises a phosphorus-containing species. For example, any of the previously described species and general structures can be replaced with phosphorus atoms instead of nitrogen atoms.

[0063] In some embodiments, the first precursor has the general formula of structure (X) or structure (XI):

[0064] (X)

[0065] (XI)

[0066] Wherein R and R' are independently selected from: hydrogen, C1-C8 alkyl groups, aryl groups, C2-C8 alkenyl groups, and / or C2-C8 alkyne groups. Counter anions include, but are not limited to: bicarbonate ions (HCO3-). - ), chloride ions (Cl) - ), bromide ions (Br) - ), iodide ions (I) - ), cyanide ions (CN) - ), thiocyanate ion (SCN) - ), isothiocyanate ion (NCS) - ), cyanide ions (OCN) - ), isocyanate ions (NCO) - ), Azide group (N3) - ), Phosphate ions (P 3- ) and carboxylate ions (R''COO) - ), wherein R'' is selected from hydrogen, C1-C8 alkyl groups, C2-C8 alkenyl groups, C2-C8 alkynyl groups and / or aromatic groups.

[0067] In some embodiments, the first precursor (i.e., the SAM precursor) is a hydrocarbon molecule incorporating one or more amine or nitrogen-containing carbide groups attached to a carbon atom. In some embodiments, the precursor does not contain any metals and / or halogens. In some embodiments, the first precursor has a molecular weight in the range of 100 to 500 doltons. In some embodiments, the first precursor has a vapor pressure greater than or equal to 100 millitorrels at 120 °C.

[0068] Non-limiting examples of suitable chemicals for use as first precursors include:

[0069] , , , , , , or .

[0070] In some embodiments, the first precursor has the general formula according to any one of structures (XII) to (XVIII):

[0071] (XII)

[0072] (XIII)

[0073] (XIV)

[0074] (XV)

[0075] (XVI)

[0076] (XVII)

[0077] (XVIII)

[0078] R1 to R6 are each independently selected from hydrogen, straight-chain C1-C20 alkyl groups, branched C3-C20 alkyl groups, cyclic C3-C20 alkyl groups, or aryl groups.

[0079] Suitable examples of first precursor chemicals include, but are not limited to:

[0080] , , , , or .

[0081] In some embodiments, the first precursor is substantially free of one or more of a metal, halogen, or nitrogen. As used herein, the term “substantially free” means, on an atomic basis, less than 5%, 4%, 3%, 2%, or 1% of the referred material.

[0082] Not wanting to be limited by theory, it is believed that polymerization can make the self-assembled monolayer (SAM) 255 more difficult to remove from the surface during subsequent operations of method 100. Furthermore, the possibility of polymerization advantageously increases with the increase in the number of multiple unsaturated bonds. One or more embodiments of the precursor contain multiple unsaturated bonds. Furthermore, not wanting to be limited by theory, it is believed that the unsaturated bonds of the self-assembled monolayer (SAM) 255 inhibit one or more of the nucleation or growth rates of subsequent films on the first surface 245. Therefore, in some embodiments, the first precursor contains at least one unsaturated bond, wherein the first surface 245 contains copper, cobalt, ruthenium, tungsten, molybdenum, or a combination of the foregoing.

[0083] In some embodiments, a precursor having a single hydroxyl group can effectively achieve reverse selective ALD deposition. In some embodiments, a self-assembled monolayer (SAM) 255 formed from a precursor containing a single hydroxyl group affects the etch-stop layer 230 and / or modifies the non-metallic surface 250. Therefore, in one or more embodiments, bifunctional groups having lone pairs and conjugated systems are designed for metallic surfaces 245 containing copper, cobalt, ruthenium, tungsten, molybdenum, or combinations thereof. In other words, in some embodiments, the self-assembled monolayer (SAM) 255 selectively blocks the metallic surface 245 but keeps the non-metallic surface 250 intact during subsequent operations of method 100, wherein the metallic surface 245 contains copper, cobalt, ruthenium, tungsten, molybdenum, or combinations thereof.

[0084] In one or more embodiments, the first precursor has a molecular weight in the range of: 50 to 500 olfels, 100 to 500 olfels, 200 to 500 olfels, 300 to 500 olfels, 400 to 500 olfels, 50 to 400 olfels, 100 to 400 olfels, 200 to 400 olfels, 300 to 400 olfels, 50 to 300 olfels, 100 to 300 olfels, 200 to 300 olfels, 50 to 200 olfels, 100 to 200 olfels, or 50 to 100 olfels. In some embodiments, the first precursor has the following molecular weights: less than 500 ohms, less than 400 ohms, less than 300 ohms, or less than 100 ohms.

[0085] In one or more embodiments, at 120°C, the first precursor has a vapor pressure in the following ranges: from 100 millitors to 100 tors, from 300 millitors to 100 tors, from 500 millitors to 100 tors, from 800 millitors to 100 tors, from 100 millitors to 50 tors, from 300 millitors to 50 tors, from 500 millitors to 50 tors, from 800 millitors to 50 tors, from 100 millitors to 10 tors, from 300 millitors to 10 tors. Torr, from 500 mTor to 10 Torr, from 800 mTor to 10 Torr, from 100 mTor to 1 Torr, from 300 mTor to 1 Torr, from 500 mTor to 1 Torr, from 800 mTor to 1 Torr, from 100 mTor to 8 MTor, from 300 mTor to 800 mTor, from 500 mTor to 800 mTor, from 100 mTor to 500 mTor, from 300 mTor to 500 mTor, or from 100 mTor to 300 mTor. In some embodiments, the first precursor has the following vapor pressures: more than 100 mTor, more than 300 mTor, more than 500 mTor, more than 800 mTor, more than 1 Torr, more than 10 Torr, more than 50 Torr, or more than 90 Torr.

[0086] In one or more embodiments, the first precursor is a liquid at the operating temperature and / or operating pressure. In one or more embodiments, the first precursor is a solid at the operating temperature and / or operating pressure. In some embodiments, the first precursor is stored in an ampoule or cylinder, and the first precursor is conveyed from the ampoule or cylinder to the substrate 210. In some embodiments, the first precursor has a vapor pressure in the following ranges at the operating temperature and / or operating pressure: from 0.1 to 150 tones, from 0.1 to 100 tones, from 0.1 to 50 tones, from 0.1 to 10 tones, from 0.1 to 1 tones, from 0.1 to 0.5 tones, from 0.5 to 150 tones, from 0.5 to 10 ... The range is from 0.5 to 10 to 1 to 150 to 100 to 100 to 100 to 100 to 15 ...00 to 150 to 100 to 150 to 100 to 100 to 150 to 100 to 100 to 150 to 100 to 100 to 150 to 100 to 100 to 150 to 100 to 100 to 150 to 100 to 100 to 150 to 100 to 100 to 100 to 150 to 100 to 100 to 100 to 150 to 100 to 100 to 100 to 100 to 100 to 150 to 100 to 100 to

[0087] In one or more embodiments, substrate 210 may be exposed to a first precursor at any suitable flow rate to form a self-assembled monolayer (SAM) 255. In some embodiments, substrate 210 is exposed to a first precursor at flow rates in the following ranges: from 50 sccm to 2000 sccm, from 100 sccm to 2000 sccm, from 500 sccm to 2000 sccm, from 1000 sccm to 2000 sccm, from 1500 sccm to 2000 sccm, from 50 sccm to 100 sccm, and from 75 sccm to 100 sccm. In some embodiments, the flow rate of the first precursor is less than or equal to 2000 sccm, less than or equal to 1500 sccm, less than or equal to 1000 sccm, less than or equal to 600 sccm, less than or equal to 500 sccm, less than or equal to 400 sccm, less than or equal to 300 sccm, less than or equal to 250 sccm, less than or equal to 200 sccm, less than or equal to 150 sccm, less than or equal to 100 sccm, less than or equal to 75 sccm, or less than or equal to 50 sccm.

[0088] In some embodiments, the substrate 210 is immersed in the vapor of the first precursor. In some embodiments, the immersion time period can be any suitable time period for forming the self-assembled monolayer (SAM) 255. In some embodiments, the immersion time period is greater than or equal to 10 seconds, greater than or equal to 20 seconds, greater than or equal to 30 seconds, greater than or equal to 45 seconds, greater than or equal to 60 seconds, greater than or equal to 80 seconds, greater than or equal to 120 seconds, greater than or equal to 150 seconds, or greater than or equal to 200 seconds.

[0089] In one or more embodiments, the first precursor further comprises a carrier gas. In some embodiments, the carrier gas is a non-reactive gas. In some embodiments, the carrier gas comprises an inert gas. In some embodiments, the inert gas includes one or more of the following: helium (He), neon (Ne), or argon (Ar). In some embodiments, the carrier gas comprises argon (Ar).

[0090] In some embodiments, a carrier gas is flowed through a configuration to carry the first precursor from the container to the substrate 210. In some embodiments, the flow rate of the argon (Ar) gas configured to carry the first precursor to the substrate 210 is controlled.

[0091] Please see Figure 1 In operation 106, substrate 210 is exposed to the second precursor to selectively deposit a liner on the second surface 250. Figure 2CA liner 260 is selectively deposited on a second surface 250. In some embodiments, the liner 260 is formed on the second surface 250, rather than on the first surface 245. In some embodiments, the liner 260 is a conformal layer. The liner 260 may contain any suitable material known to those skilled in the art to which this application pertains and may be deposited by any suitable technique known to those skilled in the art to which this application pertains. In some embodiments, the liner 260 contains a metal nitride. In some embodiments, the liner 260 contains tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. In some embodiments, the liner 260 has the same properties as the barrier layer 215. In some embodiments, the liner 260 is selectively deposited by atomic layer deposition (ALD). In some embodiments, a self-assembled monolayer (SAM) 255 selectively blocks the metal interface 245 and maintains the integrity of the non-metallic surface 250 for selective ALD deposition. In some embodiments, the liner 260 is deposited by sequentially exposing the substrate 210 to a metal precursor and a reactant. In some embodiments, the liner 260 is formed without the use of plasma. In some embodiments, the liner 260 has a thickness ranging from about 2 Å to about 20 Å. In some embodiments, the liner 260 is formed in a single ALD cycle. In some embodiments, the liner 260 is formed in 1 to 40 ALD cycles. In one or more embodiments, each of the 1 to 40 ALD cycles is configured to deposit a liner 260 with a thickness of about 0.5 Å.

[0092] Please see Figure 1 In operation 108, remove self-assembled monolayer (SAM) 255. Figure 2D The self-assembled monolayer (SAM) 255 is depicted being removed from the first surface 245. The SAM 255 is removed by an etching process. In some embodiments, the etching process may include any suitable means, including but not limited to plasma cleaning processes. In one or more embodiments, the SAM 255 is removed by plasma treatment. In some embodiments, the plasma comprises one or more of the following: hydrogen (H2), nitrogen (N2), or argon (Ar) plasma. As used herein, plasma comprising hydrogen, nitrogen, or argon means plasma formed from the molecular form of the specified species. In some embodiments, the plasma is substantially composed of hydrogen, nitrogen, argon, or a combination thereof. In some embodiments, the SAM 255 is removed without causing substantial damage to the liner 260.

[0093] The plasma power can be varied depending on the composition, packing, and / or thickness of the self-assembled monolayer (SAM) and the composition and / or thickness of the surrounding material. In some embodiments, the plasma power is in the range of about 20 W to about 500 W, about 20 W to about 400 W, about 20 W to about 250 W, about 50 W to about 500 W, about 100 W to about 500 W, about 100 W to about 450 W, about 100 W to about 500 W, or about 200 W to about 400 W. In some embodiments, the plasma power is about 50 W, about 200 W, or about 400 W.

[0094] The duration of plasma exposure can be varied depending on the composition, packing, and / or thickness of the self-assembled monolayer (SAM) 255 and the composition and / or thickness of the surrounding material. In some embodiments, the substrate is exposed to plasma for a period ranging from about 2 seconds to about 60 seconds, from about 3 seconds to about 30 seconds, or from about 5 seconds to about 10 seconds. In some embodiments, the substrate is exposed to plasma for a period of about 3 seconds, about 5 seconds, about 10 seconds, or about 30 seconds.

[0095] Please see Figure 1 See also Figure 2E In operation 110, an adhesive layer 265 is deposited on the barrier layer 260 and the first surface 245. Figure 2F An adhesive layer 265 is depicted deposited on the barrier layer 260 and the first surface 245. In some embodiments, the adhesive layer 265 is conformally deposited on the barrier layer 260 and the first surface 245. In some embodiments, the thickness of the adhesive layer 265 on the barrier layer 260 is the same as the thickness of the adhesive layer 265 on the first surface 245. In some embodiments, the thickness of the adhesive layer 265 on the barrier layer 260 is different from the thickness of the adhesive layer 265 on the first surface 245. In some embodiments, the thickness of the adhesive layer 265 on the barrier layer 260 is greater than the thickness of the adhesive layer 265 on the first surface 245. In some embodiments, the adhesive layer 265 comprises any suitable material known to those skilled in the art to which this application pertains and can be deposited by any suitable technique known to those skilled in the art to which this application pertains.

[0096] Please see Figure 1 and Figure 2FIn operation 112, method 100 includes depositing conductive material 270 in at least one feature 240 by exposing a substrate to a third precursor. In some embodiments, the third precursor comprises a metal. In some embodiments, the third precursor comprises copper, cobalt, ruthenium, tungsten, molybdenum, or a combination thereof. In some embodiments, the conductive material 270 is deposited on an adhesive layer 265 by a gap-filling process. In some embodiments, the gap-filling process comprises bottom-up filling or conformal filling. Figure 2G illustrates the conductive material 270 forming interconnects within feature 245.

[0097] The conductive material 270 may be any suitable material known to those skilled in the art to which this application pertains. In some embodiments, the conductive filler material 270 comprises one or more of the following: copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo).

[0098] In some embodiments, feature 240 includes a bottom portion and a top portion. In some embodiments, the bottom portion includes a through-hole. In some embodiments, the top portion includes a trench. In some embodiments, a first conductive filler material is grown from bottom to top to fill the through-hole portion, which constitutes the lower portion of feature 240. In some embodiments, a second conductive material is deposited in the upper portion. In some embodiments, the first conductive material and the second conductive material are the same. In some embodiments, the first conductive material and the second conductive material are different. In some embodiments, the entire feature 240 is filled with a single conductive material at a time to fill both the lower and upper portions of feature 240 in one process.

[0099] The conductive material 270 can be deposited using any suitable technique known to a person skilled in the art to which this application pertains. In some embodiments, the conductive material 270 is deposited using one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes. In some embodiments, the conductive material 270 is deposited to overfill the feature 240 and form an overburden on the surface of the substrate 210. The overburden is then removed using any suitable technique, such as etching or chemical mechanical planarization (CMP).

[0100] Not wanting to be limited by theory, it is believed that the self-assembled monolayer (SAM) 255 only slightly increases the impedance of the conductive filler 270 compared to the impedance increase typically seen in most barrier layers (e.g., film 260). Therefore, the removal of the self-assembled monolayer (SAM) 255 is a process that can further reduce the impedance of the conductive filler 270. In some embodiments, the removal of the self-assembled monolayer (SAM) 255 reduces the impedance of the metal interconnect 270 by 30%, 20%, 10%, or 5%.

[0101] Additional implementations of this disclosure relate to, for example... Figure 3 The processing tool 900 shown is used to form components and for use with the methods described herein. A variety of multi-processing platforms can be used, including Centura®, Dual ACP, and Producer, all available from Applied Materials®. ® GT and Endura ® The platform also includes other processing systems. In one or more embodiments, the clustering tool 900 includes at least one central transfer station 921, 931 with multiple sides. Robots 925, 935 are housed within the central transfer stations 921, 931 and configured to move robot blades and wafers to each of the multiple sides.

[0102] The cluster tool 900 includes multiple process chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as processing stations, connected to a central transport station. Each process chamber provides an independent processing area isolated from adjacent processing stations. Process chambers can be any suitable chamber, including, but not limited to: selective metal deposition chambers; barrier metal deposition chambers; metal deposition chambers; PVD metal deposition chambers; CVD metal deposition chambers; self-assembled monolayer (SAM) deposition chambers; lined metal deposition chambers; plasma chambers; pre-cleaning chambers; etching chambers; multiple transport spaces; wafer orientation / degassing chambers; cryogenic cooling chambers, etc. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure.

[0103] In one or more embodiments, the clustering tool 900 includes a self-assembly monolayer (SAM) deposition chamber to expose a substrate to planar hydrocarbons and form a self-assembly monolayer (SAM). In one or more embodiments, the clustering tool 900 includes a pre-cleaning chamber connected to a central transport station.

[0104] exist Figure 3In the illustrated embodiment, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and a unloading chamber 956 located on the front side 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art to which this application pertains will understand that this represents only one possible configuration.

[0105] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending on, for example, the substrate to be processed in the clustering tool 900. In the illustrated embodiment, the dimensions of the loading chamber 954 and the unloading chamber 956 are configured to hold a wafer cassette in which multiple wafers are housed.

[0106] Robot 952 is located within factory interface 950 and can move between loading chamber 954 and unloading chamber 956. Robot 952 is capable of transferring wafers from a cassette in loading chamber 954 to a load-locking chamber 960 via factory interface 950. Robot 952 is also capable of transferring wafers from load-locking chamber 962 to a cassette in unloading chamber 956 via factory interface 950. As will be understood by those skilled in the art to which this application pertains, factory interface 950 may have more than one robot 952. For example, factory interface 950 may have a first robot transferring wafers between loading chamber 954 and load-locking chamber 960, and a second robot transferring wafers between load-locking chamber 962 and unloading chamber 956.

[0107] The illustrated clustering tool 900 has a first block 920 and a second block 930. The first block 920 is connected to a factory interface 950 via load-locking chambers 960, 962. The first block 920 includes a first transfer chamber 921 in which at least one robot 925 is located. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centered relative to the load-locking chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-armed robot capable of moving more than one wafer at a time independently. In one or more embodiments, the first transfer chamber 921 includes more than one robotic wafer transport mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Each wafer is mounted on a wafer transport blade located at the distal end of the first robotic mechanism.

[0108] After the wafer is processed in the first block 920, it can be transferred to the second block 930 via a pass-through chamber. For example, chambers 922 and 924 can be unidirectional or bidirectional pass-through chambers. Pass-through chambers 922 and 924 can be used, for example, to cryogenically cool the wafer before processing in the second block 930, or to allow the wafer to be cooled or post-processed before being moved back to the first block 920.

[0109] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of process chambers 902, 904, 916, 918, and the second plurality of process chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component that controls the process chambers and robots. For example, the system controller 990 can be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0110] Typically, the process can be stored as a software routine in the memory of the system controller 990. When executed by the processor, the software routine causes the process chamber to perform the process described in this disclosure. The software routine can also be stored and / or executed by a remote second processor (not shown) located in processor-controlled hardware. Some or all of the methods of this disclosure can also be executed in hardware. Thus, the process can be implemented as software and executed using a computer system, implemented as hardware (e.g., an application-specific integrated circuit or other type of hardware implementation), or implemented as a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the operation of the process chamber to perform the processing.

[0111] In one or more embodiments, the processing tool 900 includes central transport stations 921, 931, which include at least one robot 925, 935 configured to move a wafer; one or more of a selective via-fill station, a reverse selective deposition station, a self-assembled monolayer (SAM) formation station, a CVD station, and a PVD station connected to the central transport station; an optional pre-cleaning station connected to the central transport station; and at least one controller connected to one or more of the central transport station, the selective via-fill station, the reverse selective deposition station, the self-assembled monolayer (SAM) formation station, the CVD station, the PVD station, or the optional pre-cleaning station. In one or more embodiments, the at least one controller has at least one configuration selected from: a configuration for moving a wafer between stations using a robot; a configuration for selectively filling vias; a configuration for exposing a substrate to planar hydrocarbons and forming a self-assembled monolayer (SAM); a configuration for reverse selective deposition of a barrier layer; a configuration for depositing metal; and a configuration for pre-cleaning the wafer.

[0112] In one or more embodiments, the processing tool includes: a pre-cleaning chamber having a substrate support; a selective metal deposition chamber; a barrier metal deposition chamber; a metal deposition chamber; a PVD metal deposition chamber; a CVD metal deposition chamber; optionally, a self-assembled monolayer (SAM) deposition chamber with optional pre-cleaning; optionally, a lined metal deposition chamber; optionally, a plasma chamber; optionally, an etching chamber; a robot configured to receive the pre-cleaning chamber, the selective deposition chamber, the optional self-assembled monolayer (SAM) deposition chamber, the barrier metal deposition chamber, the PVD metal deposition chamber, the optional plasma chamber; and optionally, the etching chamber and the optional lined metal deposition chamber. The system includes a CVD metal deposition chamber and a PVD metal deposition chamber; and a controller connected to a pre-cleaning chamber, a selective deposition chamber, an optional self-assembled monolayer (SAM) deposition chamber, a barrier metal deposition chamber, a PVD metal deposition chamber, an optional plasma chamber; and an optional etching chamber, an optional liner metal deposition chamber, the CVD metal deposition chamber and the PVD metal deposition chamber, and a robot. The controller has one or more configurations selected from: cleaning the substrate, selectively forming a self-assembled monolayer (SAM), selectively depositing a liner, forming a metal liner as needed, forming a metallization layer, etching the substrate as needed, and removing the self-assembled monolayer (SAM) as needed.

[0113] Throughout this specification, references to "one embodiment," "some embodiments," "multiple embodiments," "one or more embodiments," or "an embodiment" mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, phrases appearing in various places throughout this specification, such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment," do not necessarily refer to the same embodiment of this disclosure. Furthermore, in one or more embodiments, specific features, structures, materials, or characteristics can be combined in any manner.

[0114] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of the disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a semiconductor structure, the method comprising: selectively depositing a self-assembled monolayer (SAM) on a first surface of a substrate by exposing the substrate to a first precursor, wherein the substrate has at least one feature comprising the first surface and a second surface, and wherein the first precursor comprises an N-heterocyclic carbene; selectively depositing a liner on the second surface by exposing the substrate to a second precursor; and removing the self-assembled monolayer (SAM), wherein the first surface comprises a metal and the second surface comprises a dielectric material.

2. The method of claim 1, wherein selectively depositing the self-assembled monolayer (SAM) comprises forming the SAM on the first surface and not forming the SAM on the second surface.

3. The method of claim 1, wherein selectively depositing the liner comprises forming the liner on the second surface and not forming the liner on the first surface.

4. The method of claim 1, further comprising cleaning the substrate to form a substantially oxide-free substrate surface prior to depositing the self-assembled monolayer (SAM).

5. The method of claim 1, wherein the first surface comprises one or more of: copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo).

6. The method of claim 1, further comprising depositing an adhesion layer on the first surface and on the liner after removing the self-assembled monolayer (SAM).

7. The method of claim 1, wherein the at least one feature comprises one or more of: a trench and a via.

8. The method of claim 1, further comprising depositing a conductive material in the at least one feature by exposing the substrate to a third precursor, the third precursor comprising a metal.

9. The method of claim 8, wherein depositing the conductive material comprises one or more of: bottom-up gap fill and conformal gap fill.

10. The method of claim 1, wherein the first precursor has a structure of Structure (I) or Structure (II): (I) (I) wherein R and R' are independently selected from: hydrogen, a C1-C8 alkyl group, an aryl group, a C2-C8 alkenyl group, and / or a C2-C8 alkynyl group, and a counter anion comprising one or more of: bicarbonate ion (HCO3 - ), chloride ion (Cl - ), bromide ion (Br - ), iodide ion (I - ), cyanide ion (CN - ), thiocyanate ion (SCN - ), isothiocyanate ion (NCS - ), cyanate ion (OCN - ), isocyanate ion (NCO - ), azide ion (N3 - ), and carboxylate ion (R''COO - ), wherein R'' is selected from hydrogen, a C1-C8 alkyl group, a C2-C8 alkenyl group, a C2-C8 alkynyl group, and / or an aryl group.

11. The method of claim 1, wherein the first precursor is substantially free of one or more of: a metal, a halogen, or nitrogen, substantially free meaning less than 5% by atoms.

12. The method of claim 1, wherein the first precursor is selected from the group consisting of: , , or , , , or consisting of.

13. The method of claim 1, wherein the first precursor comprises a compound having a general formula according to any one of Structures (III) through (IX): (III) (IV) (V) (VI) (VII) (VIII) (IX) wherein R1through R6are each independently selected from hydrogen, a linear C1-C20 alkyl group, a branched C3-C20 alkyl group, a cyclic C3-C20 alkyl group, or an aryl group.

14. The method of claim 1, wherein the first precursor is selected from one or more of: , , , , or .

15. The method of claim 1, wherein the first precursor has a molecular weight in a range from 50 daltons to 500 daltons.

16. The method of claim 1, wherein the first precursor has a vapor pressure in the range of 100 millitors to 100 tors at 120°C.

17. A method for forming a semiconductor structure, the method comprising: A substrate is exposed to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature comprising the first surface and a second surface; The substrate is exposed to a second precursor to selectively deposit a liner on the second surface; as well as Remove the self-assembled monolayer (SAM). The first surface comprises a metal selected from one or more of the following: copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo). The second surface contains a dielectric material. The first precursor has a molecular weight in the range of 50 to 500 olfels, and The first precursor includes one or more of the following: , , or .

18. A method for forming a semiconductor structure, the method comprising: A substrate is exposed to at least one first precursor to selectively deposit a self-assembled monolayer (SAM) on a first surface of the substrate, the substrate having at least one feature comprising the first surface and a second surface; The substrate is exposed to a second precursor to selectively deposit a liner on the second surface; as well as Remove the self-assembled monolayer (SAM). The first surface comprises a metal selected from one or more of the following: tungsten (W) and molybdenum (Mo), The second surface contains a dielectric material. The first precursor has a vapor pressure at 120°C in the range of 100 millitorr to 100 tors, and The aforementioned precursor comprises one or more of the following: , , , , or .

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