Chip testing system, method and tester
By introducing a second tester to work in conjunction with the first tester in the chip testing system, the problem of low chip testing efficiency in the existing technology is solved, and efficient testing of more chips is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ACTIONS ZHUHAI TECH CO
- Filing Date
- 2024-12-31
- Publication Date
- 2026-06-30
AI Technical Summary
In existing chip testing systems, the one-to-one connection between the sorting machine and the testing machine results in low chip testing efficiency and an inability to test a large number of chips.
By introducing at least one second tester without changing the one-to-one connection between the sorter and the first tester, the second tester can jointly perform chip testing with the first tester and feed the test results back to the sorter, thus realizing the joint operation of multiple testers.
It increases the testing capabilities of the chip testing system, improves testing efficiency, and enables the simultaneous testing of a larger number of chips.
Smart Images
Figure CN122298682A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit testing, and more specifically, to a chip testing system, method, and testing machine. Background Technology
[0002] Before leaving the factory, chips need to be tested to determine if they have defects, malfunctions, or failures. During chip testing, the sorting machine first places the chip to be tested at the testing station, and then the testing machine sends test signals to the chip to perform the test.
[0003] In related technologies, sorting machines and testing machines are connected one-to-one. Due to the limited processing capacity of a single testing machine, it is impossible to test a large number of chips under test, resulting in low testing efficiency of the chip testing system. Summary of the Invention
[0004] To overcome the problems existing in related technologies, this disclosure provides a chip testing system, method and testing machine.
[0005] To achieve the above objectives, this disclosure provides a chip testing system, including a sorting machine, a first testing machine connected to the sorting machine, and a second testing machine connected to the first testing machine; The sorting machine is used to send a chip test signal to the first tester, and the chip test signal indicates the test position of the chip under test. The first tester is used to receive the chip test signal and, together with the second tester, complete the test of the chip under test at the test position, and feed back the test results of the first tester and at least one of the second testers to the sorting machine.
[0006] Optionally, there may be multiple second test machines; The first test machine and a plurality of second test machines are connected in series; or, the plurality of second test machines are all directly connected to the first test machine.
[0007] Optionally, the first tester and a plurality of second testers are connected in series. Accordingly, the tester that receives the chip test signal is used to forward the chip test signal to the downstream second tester. The first tester and the multiple second testers each record the identifier of their respective test positions, so as to determine whether there is a chip under test at their respective test positions by comparing the identifier of the test position with the chip test signal.
[0008] Optionally, multiple second test machines are directly connected to the first test machine, and correspondingly, the first test machine records the identifier of the test position corresponding to each second test machine; The first tester is used to determine whether there is a chip under test at the test position corresponding to each of the second testers based on the chip test signal and the identifier of the test position corresponding to each of the second testers, and to send a corresponding test signal to each of the second testers where there is a chip under test at the corresponding test position, so as to instruct the second tester to test the chip under test at its corresponding test position.
[0009] Optionally, the second tester is connected to the first tester via RS232 or Ethernet.
[0010] This disclosure also provides a chip testing method, applied to the chip testing system described in any of the above claims, comprising: The sorting machine sends a chip test signal to the first testing machine, and the chip test signal indicates the test position of the chip under test. The first tester receives the chip test signal and, together with the second tester, completes the test of the chip under test at the test position, and feeds back the test results of the first tester and at least one of the second testers to the sorting machine.
[0011] This disclosure also provides a chip testing method applied to a first testing machine, the first testing machine being connected to a sorting machine and a second testing machine in a chip testing system, the chip testing method comprising: Receive chip test signals sent by the sorting machine, wherein the chip test signals indicate the test position of the chip under test; The second testing machine is used in conjunction to complete the testing of the chip under test at the test location; The test results of the first tester and at least one of the second testers for the chip under test are fed back to the sorting machine.
[0012] Optionally, the first tester and a plurality of second testers are connected in series. Each of the first tester and the plurality of second testers records an identifier for its corresponding test position. The step of using the second testers in conjunction to test the chip under test at the test position includes: By comparing the identifier of the test position corresponding to the first test machine with the chip test signal, it is determined whether there is a chip under test at the test position corresponding to the first test machine, and the chip under test at the test position corresponding to the first test machine is tested. The chip test signal is forwarded to the downstream second test machine.
[0013] Optionally, multiple second test machines are directly connected to the first test machine, and the first test machine records the identifier of the test position corresponding to each second test machine; The process of combining the second testing machine to perform testing on the chip under test at the test location includes: The first tester determines whether there is a chip under test at the test position corresponding to each of the second testers based on the chip test signal and the identifier of the test position corresponding to each of the second testers, and sends a corresponding test signal to each of the second testers where there is a chip under test at the corresponding test position, instructing the second tester to test the chip under test at its corresponding test position.
[0014] This disclosure also provides a testing machine, including: A memory on which computer programs are stored; A processor for executing the computer program in the memory to implement the steps of any of the chip testing methods described above.
[0015] Through the above technical solution, without changing the one-to-one correspondence between the sorter and the first tester, the first tester, in conjunction with at least one second tester, performs chip testing on the chip under test based on the chip test signal used to indicate the test position of the chip under test, and feeds back the test results of the chip under test to the sorter. The combination of the first tester and the second tester can perform chip testing on a larger number of chips under test simultaneously, increasing the testing capability of the chip testing system and improving the testing efficiency of the chip testing system.
[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description
[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a block diagram of a chip testing system.
[0018] Figure 2 This is a block diagram illustrating a chip testing system according to an exemplary embodiment.
[0019] Figure 3 This is a block diagram illustrating another chip testing system according to an exemplary embodiment.
[0020] Figure 4 This is a timing diagram of a chip testing system according to an exemplary embodiment.
[0021] Figure 5 This is a block diagram illustrating another chip testing system according to an exemplary embodiment.
[0022] Figure 6 This is a flowchart illustrating a chip testing method according to an exemplary embodiment.
[0023] Figure 7 This is a flowchart illustrating another chip testing method according to an exemplary embodiment.
[0024] Figure 8 This is a flowchart illustrating a sub-step of step S22 according to an exemplary embodiment.
[0025] Figure 9 This is a flowchart illustrating another step S22 according to an exemplary embodiment.
[0026] Figure 10 This is a block diagram illustrating a test machine according to an exemplary embodiment. Detailed Implementation
[0027] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.
[0028] In the following description, the words "first" and "second" are used only to distinguish the purpose of the description and should not be interpreted as indicating or implying relative importance or order.
[0029] Before leaving the factory, chips need to be tested to determine if they have defects, malfunctions, or failures. During chip testing, the sorting machine first places the chip to be tested at the testing station, and then the testing machine sends test signals to the chip to perform the test.
[0030] Please refer to the relevant technologies. Figure 1 The sorter and tester are connected one-to-one. The sorter sends a start test signal and a chip test signal indicating the test position of the chip under test to the tester. The tester tests the chip under test according to the chip test signal, feeds back the test results to the sorter, and sends a test end signal after the test is completed. Due to the limited processing capacity of a single tester, it is impossible to test a large number of chips under test, resulting in low testing efficiency of the chip testing system.
[0031] To increase the number of chips under test, i.e., to expand the number of test sites, such as from 4Site to 8Site, the test resources required for an 8Site test system are twice that of a 4Site test system. If the test equipment (ATE) resources cannot meet the requirements of an 8Site test system, two ATEs (or more ATEs) need to work together to meet the requirements of an 8Site test system.
[0032] By maintaining the one-to-one connection between the sorter and the first tester (i.e., compatibility with existing chip testing systems), the first tester, in conjunction with at least one second tester, performs chip testing on the chip under test based on chip test signals indicating the test location of the chip under test. The test results of the chip under test are then fed back to the sorter. The combination of the first and second testers allows for simultaneous chip testing on a larger number of chips under test, increasing the testing capability and efficiency of the chip testing system.
[0033] This disclosure provides a chip testing system. Please refer to [link / reference]. Figure 2 , Figure 2 This is a block diagram illustrating a chip testing system according to an exemplary embodiment. The chip testing system includes a sorter 10, a first tester 20, and at least one second tester 30. The first tester 20 is connected to the sorter 10, and the second tester 30 is connected to the first tester 20. The first tester 20 and the sorter 10 can be connected via communication interfaces such as GPIB or RS232. The second tester 30 can communicate with the first tester 20 via RS232 or Ethernet.
[0034] The sorter 10 is used to send chip test signals to the first tester 20. The chip test signals indicate the test position of the chip under test.
[0035] The sorter 10 transmits multiple chips to the corresponding test positions and sends a start test signal and a chip test signal to the first tester 20. The chip test signal may also include the items to be tested, test parameters, etc.
[0036] The first tester 20 is used to receive chip test signals and, together with the second tester 30, complete the test of the chip under test at the test position, and feed back the test results of the first tester 20 and at least one second tester 30 to the sorter 10.
[0037] By adding a second tester 30 to the testing process, the testing load on the first tester 20 can be reduced, providing additional testing resources. The first and second testers 20 work together to test the chip under test; that is, the first and second testers 20 run in parallel. The first tester 20 then summarizes and feeds back the test results of the chip under test to the sorter 10, enabling simultaneous testing of a larger number of chips under test. This increases the testing capacity and efficiency of the chip testing system. Furthermore, this can be achieved only by modifying the tester side; no modification is required on the sorter side.
[0038] Through communication and interaction between the test machines (first test machine 20 and at least one second test machine 30), two or more test machines can be combined to allow available test resources to be superimposed. When it is necessary to expand the number of test sites or require more test resources, multiple test machines can work together to improve the test efficiency of the chip test system. Moreover, the first test machine 20 can also work independently when no expansion is required.
[0039] Furthermore, the sorter 10 can also be used to classify chips at the test location based on the chip test results.
[0040] In one possible implementation, there are multiple second testers 30; the first tester 20 and the multiple second testers 30 are connected in series; or, the multiple second testers 30 are all directly connected to the first tester 20.
[0041] Please see Figure 3 ,exist Figure 3 In the chip testing system shown, the first tester 20 and multiple second testers 30 are connected in series, that is, the first tester 20 is connected to the first second tester 30, the first second tester 30 is connected to the second second tester 30, the second second tester 30 is connected to the third second tester 30, and so on.
[0042] In one possible implementation, please continue reading Figure 3 The first tester 20 and multiple second testers 30 are connected in series. Accordingly, the tester that receives the chip test signal is used to forward the chip test signal to the downstream second tester.
[0043] If the tester receiving the chip test signal is the first tester, the first tester forwards the chip test signal to its downstream first second tester; if the tester receiving the chip test signal is the first second tester, the first second tester forwards the chip test signal to its downstream second second tester; if the tester receiving the chip test signal is the second second tester, the second second tester forwards the chip test signal to its downstream third second tester, and so on.
[0044] The first tester and multiple second testers each record the corresponding test position identifiers, so as to determine whether the chip under test exists at their respective test positions by comparing the test position identifiers with the chip test signals.
[0045] Each tester records its own corresponding test position identifier. The identifier of the corresponding test position recorded in the tester can indicate that the tester has the ability to perform chip testing on the chip under test at the test position of the identifier.
[0046] For example, if the test positions recorded by the first tester are labeled DUT1, DUT2, DUT3, and DUT4, it means that the first tester can test the chips under test at the test positions of DUT1, DUT2, DUT3, and DUT4. If the test positions recorded by the second tester are labeled DUT5, DUT6, DUT7, and DUT8, it means that the second tester can test the chips under test at the test positions labeled DUT5, DUT6, DUT7, and DUT8.
[0047] By comparing the test position marker with the chip test signal, it can be understood that the presence of the chip under test at the corresponding test position of the first tester is determined by comparing the test position marker of the first tester with the chip test signal; and the presence of the chip under test at the test position of the second tester is determined by comparing the test position marker of the second tester with the chip test signal.
[0048] For example, if the chip test signal indicates that the chip under test is located at DUT1, DUT2, DUT5, or DUT6, then the chip under test exists at the test positions DUT1 and DUT2 corresponding to the first tester, and the chip under test exists at the test positions DUT5 and DUT6 corresponding to the second tester.
[0049] It should be understood that when a second tester is not connected in series with other second testers, that is, when there is no downstream second tester for a second tester, then the second tester does not need to forward the chip test signal.
[0050] In one embodiment, see Figure 4The chip testing system includes a sorting machine, a first testing machine, and a second testing machine. The sorting machine sends chip test signals to the first testing machine. The first testing machine sends chip test signals to the second testing machine. The first testing machine also compares the chip test signals with its own recorded identifiers for corresponding test locations to determine if a chip under test (DUT) exists at its corresponding test location, and tests the chip at that location to obtain its test result. The second testing machine compares the chip test signals with its own recorded identifiers for corresponding test locations to determine if a DUT exists at its corresponding test location, and tests the chip at that location to obtain its test result, which is then sent to the first testing machine. The first testing machine also sends both its test results and the second testing machine's test results to the sorting machine.
[0051] In another embodiment, the chip testing system includes a sorter, a first tester, and a second tester. The sorter sends chip test signals to the first tester; the first tester generates a first test signal instructing itself to perform a test and a second test signal instructing itself to perform a test based on the chip test signals, and sends the second test signal to the second tester. The first tester also performs tests on the chip under test at its test location based on the first test signal to obtain a test result. The second tester performs tests on the chip under test at its test location based on the second test signal to obtain a test result, and sends the test result to the first tester. The first tester also sends its test result and the test result of the second tester to the sorter.
[0052] In another embodiment, the chip testing system further includes a sorting machine, a first testing machine, and two second testing machines (referred to as the second testing machine and the third testing machine, respectively). The sorting machine sends chip test signals to the first testing machine. The first testing machine generates a first test signal instructing itself to perform testing, and an intermediate test signal instructing the second and third testing machines to perform testing, based on the chip test signals. It then sends the intermediate test signal to the second testing machines. The first testing machine also performs testing on the chip under test at its test location based on the first test signal, obtaining the test result of the first testing machine. The second testing machines generate a second test signal instructing themselves to perform testing, and a third test signal instructing the third testing machines to perform testing, based on the intermediate test signal. The three test signals are sent to the third tester. The second tester is also used to test the chip under test at its test position according to the second test signal and obtain the test result of the second tester. The third tester is used to test the chip under test at its test position according to the third test signal and obtain the test result of the third tester, and send the test result of the third tester to the second tester. The second tester is also used to send the test result of the second tester and the test result of the third tester to the first tester. The first tester is also used to send the test result of the first tester, the test result of the second tester, and the test result of the third tester to the sorting machine.
[0053] Please see Figure 5 ,exist Figure 5 In the chip testing system shown, multiple second testers 30 are directly connected to the first tester 20. That is, the first tester 20 is directly connected to the first second tester 30, the first tester 20 is directly connected to the second second tester 30, the first tester 20 is directly connected to the third second tester 30, and so on.
[0054] In one possible implementation, please continue reading Figure 5 Multiple second test machines 30 are directly connected to the first test machine 20. Correspondingly, the first test machine 20 records the identifier of the test position corresponding to each second test machine 30.
[0055] The first test machine 20 records the identifier of its own corresponding test position, as well as the identifier of the test position corresponding to each second test machine 30.
[0056] The first test machine records the identifier of its corresponding test position, indicating that it has the capability to perform chip testing on the chip under test at that identified test position. Similarly, the first test machine records the identifier of the test position corresponding to the second test machine, indicating that the recorded second test machine has the capability to perform chip testing on the chip under test at the corresponding test position.
[0057] For example, if the first tester records the identifiers of its corresponding test positions as DUT1, DUT2, DUT3, and DUT4, it indicates that the first tester can test the chips under test at test positions DUT1, DUT2, DUT3, and DUT4. If the first tester records the identifiers of the test positions recorded by the first second tester as DUT5, DUT6, DUT7, and DUT8, it indicates that the first second tester can test the chips under test at test positions DUT5, DUT6, DUT7, and DUT8. If the first tester records the identifiers of the test positions recorded by the second second tester as DUT9, DUT10, DUT11, and DUT12, it indicates that the second second tester can test the chips under test at test positions DUT9, DUT10, DUT11, and DUT12.
[0058] The first tester is used to determine whether there is a chip under test at the test position corresponding to each second tester based on the chip test signal and the identifier of the test position corresponding to each second tester, and to send a corresponding test signal to each second tester where there is a chip under test at the corresponding test position, so as to instruct the second tester to test the chip under test at its corresponding test position.
[0059] The first tester determines whether a chip under test (DUT) exists at the test position corresponding to each second tester based on the information in the chip test signal and the recorded test position identifier of each second tester. Once it is determined that a DUT exists at the test position corresponding to a certain second tester, the first tester sends a test signal to that second tester. This test signal instructs the second tester to perform the test on the DUT at its corresponding test position.
[0060] In other embodiments, multiple second testers are directly connected to the first tester. Both the first tester and the multiple second testers record the identifiers of their respective test positions. The first tester sends test signals to each second tester so that each second tester can determine whether there is a chip under test at its corresponding test position by using the identifier of its own corresponding test position and the chip test signal, and then test the chip under test at its own corresponding test position.
[0061] Based on the same inventive concept, this disclosure also provides a chip testing method, which can be applied to the chip testing system described above. Please refer to [link to relevant documentation]. Figure 6 The chip testing method may include steps S1 and S2.
[0062] Step S1: The sorting machine sends a chip test signal to the first tester. The chip test signal indicates the test position of the chip under test.
[0063] In step S2, the first tester receives the chip test signal and, together with the second tester, completes the test of the chip under test at the test position, and feeds back the test results of the first tester and at least one second tester to the sorting machine.
[0064] Optionally, there may be multiple second test machines; The first test machine and multiple second test machines are connected in series; or, multiple second test machines are all directly connected to the first test machine.
[0065] Optionally, the first tester and multiple second testers are connected in series. Accordingly, the tester that receives the chip test signal forwards the chip test signal to the downstream second tester. The first tester and multiple second testers each record the corresponding test position identifiers, so as to determine whether the chip under test exists at their respective test positions by comparing the test position identifiers with the chip test signals.
[0066] Optionally, multiple second test machines are directly connected to the first test machine, and correspondingly, the first test machine records the identifier of the test position corresponding to each second test machine; The first tester determines whether there is a chip under test at the test position corresponding to each second tester based on the chip test signal and the identifier of the test position corresponding to each second tester, and sends the corresponding test signal to each second tester where there is a chip under test at the corresponding test position, instructing the second tester to test the chip under test at its corresponding test position.
[0067] Optionally, the second tester can communicate with the first tester via RS232 or Ethernet.
[0068] Based on the same inventive concept, this disclosure also provides a chip testing method applied to a first testing machine, which is connected to a sorting machine and a second testing machine in a chip testing system. Please refer to [link to relevant documentation]. Figure 7 The chip testing method may include steps S21 to S23.
[0069] Step S21: Receive the chip test signal sent by the sorter. The chip test signal indicates the test position of the chip under test.
[0070] Step S22: The second tester is used in conjunction with the tester to complete the test of the chip under test at the test location.
[0071] Step S23: The test results of the first tester and at least one second tester on the chip under test are fed back to the sorting machine.
[0072] Optionally, a first testing machine and multiple second testing machines are connected in series. Each of the first testing machine and the multiple second testing machines records the corresponding test position identifiers. Please refer to [link to relevant documentation]. Figure 8 Step S22 may include steps S221 and S222.
[0073] Step S221: By comparing the identifier of the test position corresponding to the first test machine with the chip test signal, it is determined whether there is a chip under test at the test position corresponding to the first test machine, and the chip at the test position corresponding to the first test machine is tested.
[0074] Step S222: Forward the chip test signal to the downstream second test machine.
[0075] It should be understood that the second tester, upon receiving the chip test signal, compares the corresponding test position identifier recorded by itself with the chip test signal to determine whether the chip under test exists at the test position corresponding to the second tester. If it is determined that the chip exists, the test chip stored at the test position corresponding to the second tester is tested.
[0076] Correspondingly, after each tester finishes testing the chip under test at its corresponding test position, it obtains the test results and forwards them to the second tester upstream, and so on, until it reaches the first tester. The first tester then summarizes the test results from all the second testers and its own test results and sends them to the sorting machine.
[0077] Optionally, multiple second test machines are directly connected to the first test machine, and the first test machine records the identifier of the test position corresponding to each second test machine. Please refer to [link / reference]. Figure 9 Step S22 may include steps S223 and S224.
[0078] Step S223: The first tester determines whether there is a chip under test at the test position corresponding to each second tester based on the chip test signal and the identifier of the test position corresponding to each second tester.
[0079] Step S224: Send a corresponding test signal to each second tester where a chip under test is located at a corresponding test position, instructing the second tester to test the chip under test at its corresponding test position.
[0080] The first tester compares the chip test signal with the identifier of the test position corresponding to each second tester to determine whether there is a chip under test at the test position corresponding to each second tester. If it is determined that there is a chip under test, the first tester sends a corresponding test signal to each second tester with a chip under test, so as to instruct the second tester to test the chip under test at its corresponding test position.
[0081] Correspondingly, after each second tester finishes testing the chip under test at its corresponding test position, it obtains the test results of each second tester and forwards them to the first tester. The first tester then summarizes the test results of all the second testers and its own test results and sends them to the sorting machine.
[0082] Regarding the chip testing method in the above embodiments, the specific way in which each module performs its operation has been described in detail in the embodiments of the chip testing system, and will not be elaborated here.
[0083] Figure 10 This is a block diagram illustrating a test machine 700 according to an exemplary embodiment. For example... Figure 10 As shown, the test machine 700 may include: a processor 701 and a memory 702. The test machine 700 may also include one or more of the following: a multimedia component 703, an input / output (I / O) interface 704, and a communication component 705.
[0084] The processor 701 controls the overall operation of the test machine 700 to complete all or part of the steps in the chip testing method described above. The memory 702 stores various types of data to support the operation of the test machine 700. This data may include, for example, instructions for any application or method operating on the test machine 700, and application-related data such as contact data, sent and received messages, images, audio, video, etc. The memory 702 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The multimedia component 703 may include a screen and audio components. The screen may be, for example, a touchscreen, and the audio component is used for outputting and / or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 702 or transmitted via communication component 705. The audio component also includes at least one speaker for outputting audio signals. I / O interface 704 provides an interface between processor 701 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual or physical buttons. Communication component 705 is used for wired or wireless communication between the test machine 700 and other devices. Wireless communication may include Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination of these. Therefore, the corresponding communication component 705 may include a Wi-Fi module, a Bluetooth module, or an NFC module.
[0085] In an exemplary embodiment, the test machine 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the chip testing method described above.
[0086] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the chip testing method described above. For example, the computer-readable storage medium may be the memory 702 including program instructions described above, which may be executed by the processor 701 of the test machine 700 to complete the chip testing method described above.
[0087] In another exemplary embodiment, a computer program product is also provided, which includes a computer program executable by a processor, which, when executed by the processor, implements the steps of the chip testing method described above.
[0088] The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0089] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.
[0090] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.
Claims
1. A chip testing system, characterized by, It includes a sorting machine, a first testing machine connected to the sorting machine, and a second testing machine connected to the first testing machine; The sorting machine is used to send a chip test signal to the first tester, and the chip test signal indicates the test position of the chip under test. The first tester is used to receive the chip test signal and, together with the second tester, complete the test of the chip under test at the test position, and feed back the test results of the first tester and at least one of the second testers to the sorting machine.
2. The chip testing system of claim 1, wherein, The second test machine consists of multiple units; The first test machine and a plurality of second test machines are connected in series; or, the plurality of second test machines are all directly connected to the first test machine.
3. The chip testing system of claim 2, wherein, The first tester and a plurality of second testers are connected in series. Accordingly, the tester that receives the chip test signal is used to forward the chip test signal to the downstream second tester. The first tester and the multiple second testers each record the identifier of their respective test positions, so as to determine whether there is a chip under test at their respective test positions by comparing the identifier of the test position with the chip test signal.
4. The chip testing system of claim 2, wherein Multiple second test machines are directly connected to the first test machine, and correspondingly, the first test machine records the identifier of the test position corresponding to each second test machine; The first tester is used to determine whether there is a chip under test at the test position corresponding to each of the second testers based on the chip test signal and the identifier of the test position corresponding to each of the second testers, and to send a corresponding test signal to each of the second testers where there is a chip under test at the corresponding test position, so as to instruct the second tester to test the chip under test at its corresponding test position.
5. The system of any of claims 1-4, wherein, The second tester is connected to the first tester via RS232 or Ethernet.
6. A method of testing a chip, characterized by, The chip testing system applied to any one of claims 1-5 includes: The sorting machine sends a chip test signal to the first testing machine, and the chip test signal indicates the test position of the chip under test. The first tester receives the chip test signal and, together with the second tester, completes the test of the chip under test at the test position, and feeds back the test results of the first tester and at least one of the second testers to the sorting machine.
7. A method of testing a chip, characterized by, The chip testing method is applied to a first testing machine, which is connected to a sorting machine and a second testing machine in a chip testing system. Receive the chip test signal sent by the sorter, the chip test signal indicating the test position of the chip under test; The second testing machine is used in conjunction to complete the testing of the chip under test at the test location; The test results of the first tester and at least one of the second testers for the chip under test are fed back to the sorting machine.
8. The chip testing method according to claim 7, wherein The first tester and multiple second testers are connected in series. Each of the first tester and multiple second testers records an identifier for its corresponding test position. The step of using the second testers in conjunction to test the chip under test at the test position includes: By comparing the identifier of the test position corresponding to the first test machine with the chip test signal, it is determined whether there is a chip under test at the test position corresponding to the first test machine, and the chip under test at the test position corresponding to the first test machine is tested. The chip test signal is forwarded to the downstream second test machine.
9. The method of claim 7, wherein, Multiple second test machines are directly connected to the first test machine, and the first test machine records the identifier of the test position corresponding to each second test machine; The process of combining the second testing machine to perform testing on the chip under test at the test location includes: The first tester determines whether there is a chip under test at the test position corresponding to each of the second testers based on the chip test signal and the identifier of the test position corresponding to each of the second testers, and sends a corresponding test signal to each of the second testers where there is a chip under test at the corresponding test position, instructing the second tester to test the chip under test at its corresponding test position.
10. A testing machine characterized by, include: A memory on which computer programs are stored; A processor for executing the computer program in the memory to implement the steps of the chip testing method according to any one of claims 7-9.