An autonomous navigation system

Abstract

This invention provides an autonomous navigation system, relating to the field of intelligent navigation technology. It includes a navigation array, a read / write module, and a navigation control logic circuit. The navigation array is connected to the read / write module, and the navigation control logic circuit is connected to both the read / write module and the navigation array. The navigation control logic circuit receives target navigation information through a parallel read / write interface and generates a navigation enable signal. The read / write module writes the target navigation information into the navigation array based on the navigation enable signal. In response to the navigation enable signal being pulled high, the navigation array sequentially performs calculations on pixel circuits, annealing circuits, and propagation circuits based on the target navigation information to obtain real-time navigation results, which are then read out by the read / write module. The real-time navigation results include environmental perception results, map construction results, and path planning. This system is a fully integrated real-time autonomous navigation system that achieves low-latency autonomous navigation with high energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of intelligent navigation technology, and more specifically to an autonomous navigation system. Background Technology

[0002] Autonomous navigation systems are a key technology for applications such as autonomous driving, drone delivery, and robotic embodied intelligence. This technology aims to enable mobile platforms to plan and execute motion trajectories from start to finish in real time through perception and understanding of the environment, without human intervention.

[0003] Current autonomous navigation systems typically employ a discrete modular design, with simultaneous localization and mapping (SLAM) technology as their core framework. They acquire raw environmental information through various sensors such as LiDAR, visual cameras, and inertial measurement units (IMUs), then input this information into a computing platform to build a map and plan a path. Finally, they integrate all the information to achieve real-time navigation. However, the discrete architecture limits the energy efficiency and real-time performance of existing autonomous navigation systems, resulting in additional power consumption and latency. Therefore, a novel autonomous navigation system is urgently needed to address these technical challenges. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of the present invention propose an autonomous navigation system.

[0005] This invention provides an autonomous navigation system, including a navigation array, a read / write module, and a navigation control logic circuit. The navigation array is connected to the read / write module, and the navigation control logic circuit is connected to both the read / write module and the navigation array. The navigation control logic circuit receives target navigation information through a parallel read / write interface and generates a navigation enable signal. The read / write module writes the target navigation information into the navigation array based on the navigation enable signal. In response to the navigation enable signal being pulled high, the navigation array sequentially performs calculations on pixel circuits, annealing circuits, and propagation circuits based on the target navigation information to obtain real-time navigation results, which are then read out by the read / write module. The real-time navigation results include environmental perception results, map construction results, and path planning.

[0006] In the above scheme, the read / write module includes a WL selection circuit, an array read / write control logic circuit, and a read / write circuit. The array read / write control logic circuit is used to generate a WL signal and a column circuit signal according to the navigation enable signal, and send the WL signal to the WL selection circuit and the column circuit signal to the read / write circuit, respectively. The WL selection circuit is used to transmit the WL signal to the navigation array. The read / write circuit is used to perform the write operation of transmitting the converted column circuit signal to the navigation array, and to perform the read operation of the real-time navigation results output by the navigation array.

[0007] In the above scheme, the read / write circuit includes multiple column circuits. Each column circuit includes a BL precharge circuit, a write drive circuit, and an SA readout circuit. The process of the read / write circuit performing the write operation includes: after the WL selection circuit is turned on, the column circuit signal is converted and written into the navigation array through the write drive circuit.

[0008] In the above scheme, the process of the read operation performed by the read-write circuit includes: the BL precharge circuit resets the BL, and after the WL selection circuit is turned on, the SA readout circuit reads the real-time navigation results output by the navigation array.

[0009] In the above scheme, the navigation array includes multiple navigation units. Each navigation unit includes an SRAM circuit, a pixel circuit, an annealing circuit, and a propagation circuit. The SRAM circuit includes a raw pixel data SRAM circuit, a map grid data SRAM circuit, and a path direction data SRAM circuit. The pixel circuit generates an avalanche current in response to receiving a navigation enable signal and converts the avalanche current into a pulse voltage signal to be stored in the raw pixel data SRAM circuit. The annealing circuit calculates the target voltage signal based on the raw pixel data in the raw pixel data SRAM circuit in response to the navigation enable signal being pulled high and stores it in the map grid data SRAM circuit. The propagation circuit calculates the target transmission path based on the map grid data in the map grid data SRAM circuit in response to the navigation enable signal being pulled high and stores it in the path direction data SRAM circuit.

[0010] In the above scheme, the pixel circuit includes a SPAD pixel structure, an active hardening circuit, and a pulse readout circuit. The SPAD pixel structure is used to generate an avalanche current by absorbing photons after entering the exposure window in response to receiving a navigation enable signal. The pulse readout circuit is used to convert the avalanche current into a pulse voltage signal and write the pulse voltage signal into the original pixel data SRAM circuit. The active hardening circuit is used to reset the SPAD pixel structure after exposure.

[0011] In the above scheme, the annealing circuit includes a weight control switch, a status register, a random generator, a charge accumulation pulse circuit, and an analog-to-digital converter. The status register is used to obtain the original pixel data from the original pixel data SRAM circuit. The weight control switch is used to connect the neighboring navigation units to determine the intermediate state of the current iteration in response to the navigation enable signal being pulled high. The random generator is used to output the random state of the current navigation unit. The charge accumulation pulse circuit and the analog-to-digital converter are used to perform logical operations based on the intermediate state and the random state, and to determine the accumulation of the analog voltage signal. The analog-to-digital converter is used to convert the analog voltage signal into the target digital signal and store it in the map grid data SRAM circuit.

[0012] In the above scheme, the propagation circuit includes a wavefront signal locking circuit and a propagation delay control circuit; the wavefront locking signal is used to block the input of the wavefront signal in response to the navigation enable signal being pulled high; the propagation delay control circuit is used to control the propagation of the wavefront signal in multiple directions.

[0013] In the above scheme, the calculation process of the pixel circuit in each navigation unit includes: the SPAD pixel structure resets the output to 0 through its internal active quenching circuit and enters the exposure mode to wait for external photon incidence, thus obtaining the SPAD pixel structure in the global exposure mode; during the global exposure window, after the SPAD pixel structure that has captured photons generates an avalanche current, the pulse readout circuit converts the current into a pulse signal output; and the pulse signal is written into the original pixel data SRAM circuit inside the navigation unit.

[0014] In the above scheme, the calculation process of the annealing circuit in each navigation unit includes: acquiring the original pixel data in the original pixel data SRAM circuit, and identifying and removing noise grid points in the original pixel data according to the neighborhood information of the target grid point; if there are more similar grid points in the neighborhood of the target grid point, the type of the target grid point is retained; and writing the type information of the target grid point into the map grid data SRAM circuit inside the navigation unit.

[0015] The technical solution of this invention provides an autonomous navigation system, which has at least the following beneficial effects:

[0016] (1) The autonomous navigation system adopts a dedicated integrated circuit based on the sensor-memory-computing fusion architecture, which can break through the bottleneck of discrete architecture, minimize the additional power consumption and latency caused by data transfer, and concentrate the system's resource scheduling on effective computing operations, thereby achieving extremely high energy efficiency and extremely low processing latency. It is suitable for optimizing edge-side autonomous navigation applications with stringent requirements for energy efficiency and real-time performance.

[0017] (2) The system integrates environmental perception, map building and path planning modules into the same chip. Compared with the real-time autonomous navigation system based on discrete module combination configuration under the traditional architecture, the system achieves extremely high energy efficiency and extremely low navigation latency at the system level, providing high-performance hardware platform support for real-time autonomous navigation applications on the edge side. Attached Figure Description

[0018] Figure 1 This diagram schematically illustrates the architecture of an autonomous navigation system according to an embodiment of the present invention.

[0019] Figure 2 This schematic diagram illustrates the structural block diagram of a read / write module according to an embodiment of the present invention;

[0020] Figure 3 A schematic diagram illustrating the structure of a navigation unit according to an embodiment of the present invention is shown.

[0021] Figure 4 The diagram illustrates the principle of a navigation unit performing navigation calculations according to an embodiment of the present invention.

[0022] Figure 5 The diagram illustrates the calculation process of a navigation unit during the environmental perception phase according to an embodiment of the present invention.

[0023] Figure 6 The diagram illustrates the calculation process of a navigation unit during the map building phase according to an embodiment of the present invention.

[0024] Figure 7 The diagram illustrates the calculation process of a navigation unit during the path planning phase according to an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0026] Figure 1 The diagram illustrates the architecture of an autonomous navigation system according to an embodiment of the present invention.

[0027] In embodiments of the present invention, such as Figure 1 As shown, the autonomous navigation system includes a navigation array, a read / write module, and a navigation control logic circuit. The navigation array is connected to the read / write module, and the navigation control logic circuit is connected to both the read / write module and the navigation array. The navigation control logic circuit receives target navigation information through a parallel read / write interface and generates a navigation enable signal. The read / write module writes the target navigation information into the navigation array based on the navigation enable signal. The navigation array, in response to the navigation enable signal being pulled high, sequentially performs calculations on pixel circuits, annealing circuits, and propagation circuits based on the target navigation information to obtain real-time navigation results, which are then read out by the read / write module. The real-time navigation results include environmental perception results, map construction results, and path planning.

[0028] It is understandable that this autonomous navigation system is an on-chip integrated real-time autonomous navigation system that mainly includes a navigation array and a peripheral digital control module.

[0029] For example, the navigation array here is a sensor-memory-computing fusion navigation array used to realize environmental perception, map building, and path planning. The navigation array can be composed of multiple adjacent connected navigation units, each of which contains a 16-bit custom SRAM (Static Random Access Memory) circuit, a SPAD (Single Photon Avalanche Diode) based pixel circuit, an annealing circuit based on the Ising spin model, and a propagation circuit based on the wavefront propagation algorithm.

[0030] For example, the peripheral digital control module here includes a read / write module and a navigation control logic circuit. The read / write module is directly connected to the navigation array and is used to read and write the SRAM inside the navigation unit. The navigation control logic circuit is used to handle data exchange between the high-speed parallel read / write interface and the outside of the chip, and to receive target navigation information through the parallel read / write interface to generate a navigation enable signal, and send the enable signal to the read / write module and the navigation array respectively.

[0031] Please refer to Figure 1 As shown, the real-time navigation process of this autonomous navigation system is as follows: After the target navigation information is input to the navigation control logic circuit through a high-speed parallel read / write interface, the navigation control logic circuit generates an enable signal, which is transmitted to the read / write module and the navigation array. Further, the read / write module writes the target navigation information into the navigation array based on the enable signal. The navigation array then performs calculations on the pixel circuit, annealing circuit, and propagation circuit based on the enable signal and the target navigation information to obtain the real-time navigation result. At this point, the read / write module reads and outputs the real-time navigation result. It should be noted that the real-time navigation result in this embodiment includes environmental perception results, map construction results, and path planning.

[0032] Furthermore, the autonomous navigation system updates the target navigation information based on the real-time navigation results read by the read / write module, and controls the physical navigation platform to move to update the target navigation environment based on the updated target navigation information.

[0033] Understandably, this system integrates modules such as environmental perception, map building, and path planning into a single chip. Compared to traditional real-time autonomous navigation systems based on discrete module combinations, this system achieves extremely high energy efficiency and extremely low navigation latency at the system level, providing high-performance hardware platform support for real-time autonomous navigation applications at the edge.

[0034] Figure 2 The schematic diagram illustrates the structure of a read / write module according to an embodiment of the present invention. Figure 3 A schematic block diagram of a navigation unit according to an embodiment of the present invention is shown.

[0035] Below, in conjunction with Figures 1-7 The autonomous navigation system of this embodiment will be described in detail.

[0036] In embodiments of the present invention, the read / write module includes a WL (Word Line) selection circuit, an array read / write control logic circuit, and a read / write circuit. The array read / write control logic circuit generates a WL signal and a column circuit signal based on a navigation enable signal, and sends the WL signal to the WL selection circuit and the column circuit signal to the read / write circuit, respectively. The WL selection circuit transmits the WL signal to the navigation array. The read / write circuit performs a write operation to transmit the converted column circuit signal to the navigation array, and a read operation to read the real-time navigation results output by the navigation array.

[0037] For example, please refer to Figure 1 and Figure 2 As shown, the read / write module includes an SRAM array read / write control logic circuit, a WL buffer chain circuit, and an SRAM read / write circuit. The SRAM array read / write control logic circuit generates a WL signal and a column circuit signal upon receiving a navigation enable signal, and controls the SRAM array to exchange data by sending these signals. The WL buffer chain circuit transmits the received WL signal to each row of SRAM storage cells in the core navigation array. The SRAM read / write circuit converts the received column circuit signal and transmits it to each column of SRAM storage cells in the core navigation array, and also performs read operations on the real-time navigation results output by the navigation array.

[0038] In an embodiment of the present invention, the read / write circuit includes multiple column circuits, each column circuit including a BL (Bit Line) precharge circuit, a write drive circuit, and an SA (Sense Amplifier) ​​readout circuit.

[0039] For example, such as Figure 2 As shown, the SRAM read / write circuit includes multiple column circuits, each of which mainly includes a BL precharge circuit, a write drive circuit, and a sensitive amplifier circuit.

[0040] In an embodiment of the present invention, the process of the read / write circuit performing a write operation includes: after the WL selection circuit is turned on, the column circuit signal is converted and written into the navigation array through the write drive circuit. The process of the read / write circuit performing a read operation includes: the BL precharge circuit resetting the BL; after the WL selection circuit is turned on, the SA readout circuit reading the real-time navigation results output by the navigation array.

[0041] For example, when performing a read operation, BL is first reset by the BL precharge circuit, then waits for WL to turn on, and finally reads the result by the sensitive amplification circuit; when performing a write operation, WL is first turned on, and then the write drive circuit changes the level state of the SRAM memory cell to convert the column circuit signal and write it into the navigation array.

[0042] In embodiments of the present invention, the navigation array includes multiple navigation units, each navigation unit including an SRAM circuit, a pixel circuit, an annealing circuit, and a propagation circuit. The SRAM circuit includes a raw pixel data SRAM circuit, a map grid data SRAM circuit, and a path direction data SRAM circuit. The pixel circuit is used to generate an avalanche current in response to receiving a navigation enable signal, and convert the avalanche current into a pulse voltage signal to be stored in the raw pixel data SRAM circuit. The annealing circuit is used to calculate, based on the raw pixel data in the raw pixel data SRAM circuit, to obtain a target voltage signal in response to the navigation enable signal being pulled high, and store it in the map grid data SRAM circuit. The propagation circuit is used to calculate, based on the map grid data in the map grid data SRAM circuit, to obtain a target transmission path in response to the navigation enable signal being pulled high, and store it in the path direction data SRAM circuit.

[0043] For example, such as Figure 3 As shown, after receiving the navigation enable signal, the navigation unit performs navigation calculations and then sends a navigation identifier signal to the outside. It can also acquire the original pixel data, map grid data, and path direction data of the core navigation unit via the SRAM data read / write bus. The core navigation unit mainly includes a SPAD pixel circuit, an Ising spin model annealing circuit, and a dynamic logic wavefront propagation circuit. Specifically, during navigation operations, the SPAD pixel circuit calculates the target result based on the navigation enable signal and target navigation information, and writes the target result into the original pixel data SRAM. Then, the Ising spin model annealing circuit acquires this data and performs calculations, writing the result into the map grid data SRAM. Finally, the dynamic logic wavefront propagation circuit acquires this data and performs calculations, writing the result into the path direction data SRAM.

[0044] In embodiments of the present invention, the pixel circuit includes a SPAD pixel structure, an active hardening circuit, and a pulse readout circuit. The SPAD pixel structure, in response to receiving a navigation enable signal, generates an avalanche current by absorbing photons after entering the exposure window. The pulse readout circuit converts the avalanche current into a pulse voltage signal and writes the pulse voltage signal into the original pixel data SRAM circuit. The active hardening circuit resets the SPAD pixel structure after exposure.

[0045] For example, please continue reading Figure 3The SPAD pixel circuit mainly includes the SPAD pixel structure, the active hardening circuit, and the auto-reset pulse readout circuit. After receiving the navigation enable signal, the SPAD pixel structure enters the exposure window and absorbs photons to generate an avalanche current. The auto-reset pulse readout circuit converts the avalanche current into a pulse voltage signal and writes it into the original pixel data SRAM. After exposure, the active hardening circuit resets the SPAD pixel.

[0046] In an embodiment of the present invention, the annealing circuit includes a weight control switch, a state register, a random generator, a charge accumulation pulse circuit, and an analog-to-digital converter. The state register is used to obtain raw pixel data from the raw pixel data SRAM circuit; the weight control switch is used to connect neighboring navigation units to determine the intermediate state of the current iteration in response to a navigation enable signal being pulled high; the random generator is used to output the random state of the current navigation unit; the charge accumulation pulse circuit and the analog-to-digital converter are used to perform logical operations based on the intermediate state and the random state, and to determine the accumulation of the analog voltage signal; the analog-to-digital converter is used to convert the analog voltage signal into a target digital signal and store it in the map grid data SRAM circuit.

[0047] For example, please continue reading Figure 3 An annealing circuit, such as the Ising spin model annealing circuit, mainly includes a state register, a weight control switch, a random number generator, a charge accumulation pulse circuit, and a 2-bit Flash ADC (Analog-to-Digital Converter). An enable signal is input to the annealing circuit; when the enable signal goes high, the annealing circuit begins calculation. The state register obtains the initial state from the original pixel data SRAM. After calculation begins, the weight control switch connects the navigation units in the neighborhood to determine the intermediate state of the current iteration. Then, the charge accumulation pulse circuit obtains this intermediate state and the random state output by the random number generator, performs logical operations, and determines whether to accumulate pulses. After annealing, the 2-bit Flash ADC converts the analog voltage signal stored in the charge accumulation pulse circuit into a 2-bit digital signal and writes it into the map grid data SRAM.

[0048] In an embodiment of the present invention, the propagation circuit includes a wavefront signal locking circuit and a propagation delay control circuit. The wavefront locking signal is used to block the input of the wavefront signal in response to the navigation enable signal being pulled high; the propagation delay control circuit is used to control the propagation of the wavefront signal in multiple directions.

[0049] For example, please continue reading Figure 3The propagation circuit, for example, is a dynamic logic wavefront propagation circuit, mainly including a wavefront signal locking circuit and a propagation delay control circuit. The propagation delay control circuit includes eight sub-directions: NW, N, NE, E, SE, S, SW, and W. An enable signal enters the propagation circuit; when the enable signal goes high, the propagation circuit begins calculation. After calculation begins, when the navigation unit first receives a wavefront signal from a neighboring region from any direction, the wavefront signal locking circuit activates and prevents the input of subsequent wavefront signals. Simultaneously, the wavefront signal continues to propagate to neighboring navigation units through the propagation delay control circuit in the target direction.

[0050] Figure 4 The diagram illustrates the principle of a navigation unit performing navigation calculations according to an embodiment of the present invention.

[0051] Based on the above, it can be understood that each navigation unit performs navigation calculations after receiving the navigation enable signal. After completion, it sends a navigation identifier signal to the outside and obtains the original pixel data, map grid data and path direction data of the core navigation unit through the SRAM data read / write bus, thus obtaining the real-time navigation result.

[0052] Specifically, such as Figure 4 As shown, the pixel circuit first performs calculations (i.e., exposes the raw pixel data). The SPAD pixel array is affected by various noises during exposure, resulting in noise in the raw pixel image, manifested as: ① dark noise in bright areas; ② bright noise in dark areas. During exposure, the system does not perform any preprocessing on this noise, directly writing the read raw pulse value P into the corresponding SRAM inside the navigation unit.

[0053] Furthermore, map grid points are constructed based on the Ising spin model annealing circuit. Specifically, during the construction process, the original pixel data is first used as the initial type of each map grid point. Then, based on the types of nearby map grid points, the probability value of the current map grid point being a path or an obstacle is iteratively calculated. Finally, binary classification is performed according to a threshold, and the obtained map grid point type G is written into the corresponding SRAM inside the navigation unit.

[0054] Furthermore, the shortest path is calculated based on the dynamic logic wavefront propagation circuit, that is, based on the aforementioned PG data, signal transmission is achieved, and the shortest transmission path is determined. Specifically, during the calculation process, the wavefront signal propagates gradually from the starting point to the ending point. The direction of the wavefront signal first received by each navigation unit is the direction of the shortest path between the starting point and the ending point. By gradually tracing back from the ending point to the starting point, the shortest path can be obtained. Finally, each path direction R is written into the corresponding SRAM inside the navigation unit.

[0055] Furthermore, after the above navigation operation is completed, the real-time navigation result PGR under the current navigation environment settings can be obtained. The peripheral digital control circuit can read the result and update the settings to prepare for the next round of core navigation operation.

[0056] Figure 5 The diagram illustrates the calculation process of a navigation unit during the environmental perception phase according to an embodiment of the present invention. Figure 6 The diagram illustrates the calculation process of a navigation unit during the map building phase according to an embodiment of the present invention. Figure 7 The diagram illustrates the calculation process of a navigation unit during the path planning phase according to an embodiment of the present invention.

[0057] It is also understandable that the calculation process of the pixel circuit is the environmental perception stage, the calculation process of the annealing circuit is the map building stage, and the calculation process of the propagation circuit is the path planning stage.

[0058] In an embodiment of the present invention, in each navigation unit, the calculation process of the pixel circuit includes: the SPAD pixel structure resets its output to 0 through its internal active quenching circuit and enters the exposure mode to wait for external photons to be incident, thereby obtaining the SPAD pixel structure in the global exposure mode; during the global exposure window, after the SPAD pixel structure that has captured photons generates an avalanche current, the pulse readout circuit converts the current into a pulse signal output; and the pulse signal is written into the original pixel data SRAM circuit inside the navigation unit.

[0059] Specifically, such as Figure 5 As shown, the environmental perception stage can be broken down into the following steps: First, each SPAD pixel resets its output to 0 through its internal active quenching circuit and enters the exposure mode to wait for external photons to be incident. At this time, the pixel array works in the global exposure mode.

[0060] Furthermore, during the global exposure window, the SPAD pixels that capture photons generate avalanche currents, and the dynamic trigger pulse readout circuit inside the corresponding pixel starts working, converting the current into a pulse signal output.

[0061] Furthermore, the valid pulse signal is written into the raw pixel data SRAM inside the navigation unit.

[0062] In an embodiment of the present invention, in each navigation unit, the calculation process of the annealing circuit includes: acquiring the original pixel data in the original pixel data SRAM circuit, and identifying and removing noise grid points in the original pixel data according to the neighborhood information of the target grid point; if there are more similar grid points in the neighborhood of the target grid point, the type of the target grid point is retained; and writing the type information of the target grid point into the map grid data SRAM circuit inside the navigation unit.

[0063] Specifically, such as Figure 6 As shown, the map building phase can be broken down into the following steps: First, the original pixel data saved in the environmental perception phase is used as the initial condition, the Ising spin model annealing circuit is configured and input, and then global map building is prepared.

[0064] Furthermore, based on the neighborhood information of the target grid point, noise grid points in the original image are identified and removed. If there are more similar grid points in the neighborhood of the target grid point, the grid point has a higher probability of being a real grid point, and its type will be preserved; otherwise, the grid point has a higher probability of being a noise grid point, and its type will be reversed.

[0065] Furthermore, the type information of the grid points is written into the map grid data SRAM inside the navigation unit.

[0066] In embodiments of the present invention, such as Figure 7 As shown, in each navigation unit, the path planning stage can be broken down into the following steps: First, before executing global path planning, the navigation control logic circuit writes the coordinate information of the navigation start point and end point into the SRAM inside the corresponding navigation unit through the WL selection circuit and the BL drive circuit.

[0067] Furthermore, the map grid data saved during the map building phase is used as initial conditions to configure and input the dynamic logic wavefront propagation circuit, and then global path planning is prepared for execution.

[0068] Furthermore, after the formal solution process begins, the initial navigation signal propagates from the navigation starting point to the surrounding adjacent navigation grid points. The navigation signal has different propagation delays between navigation grid points at different distances, and navigation grid points closer to the navigation starting point will receive the navigation signal earlier. After each navigation grid point receives the navigation signal for the first time, it will trigger a latching circuit to prevent that navigation grid point from receiving subsequent navigation signals, and at the same time, read out the propagation direction of the first received navigation signal, i.e., the shortest path direction.

[0069] Furthermore, the latched direction information is written into the path direction data SRAM inside the navigation unit.

[0070] Based on the above, the system acquires the raw pixel data, map grid data, and path direction data of the core navigation unit via the SRAM data read / write bus, thereby obtaining real-time navigation results. These real-time navigation results are then read out by the read / write module. Furthermore, the autonomous navigation system updates the target navigation information based on the real-time navigation results read by the read / write module, and controls the physical navigation platform to move according to the updated target navigation information to update the target navigation environment.

[0071] Through the embodiments of the present invention, the autonomous navigation system adopts a dedicated integrated circuit based on a sensor-memory-computing fusion architecture, which can overcome the bottleneck of discrete architecture, minimize the additional power consumption and latency caused by data transfer, and concentrate the system's resource scheduling on effective computing operations, thereby achieving extremely high energy efficiency and extremely low processing latency. It is very suitable for optimizing edge-side autonomous navigation applications with stringent requirements for energy efficiency and real-time performance.

[0072] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

Claims

1. An autonomous navigation system, characterized in that, It includes a navigation array, a read / write module, and a navigation control logic circuit. The navigation array is connected to the read / write module, and the navigation control logic circuit is connected to both the read / write module and the navigation array. Navigation control logic circuitry is used to receive target navigation information and generate navigation enable signals through a parallel read / write interface; The read / write module is used to write the target navigation information into the navigation array according to the navigation enable signal; A navigation array is used to respond to the navigation enable signal being pulled high, and to perform calculations on the pixel circuit, annealing circuit and propagation circuit in sequence according to the target navigation information to obtain real-time navigation results, which are then read out by the read / write module. The real-time navigation results include environmental perception results, map construction results and path planning.

2. The autonomous navigation system according to claim 1, characterized in that, The read / write module includes a WL selection circuit, an array read / write control logic circuit, and a read / write circuit. An array read / write control logic circuit is used to generate a WL signal and a column circuit signal according to the navigation enable signal, and send the WL signal to the WL selection circuit and the column circuit signal to the read / write circuit respectively. The WL selection circuit is used to transmit the WL signal to the navigation array; The read / write circuit is used to perform a write operation that transmits the converted column circuit signal to the navigation array, and a read operation that performs the real-time navigation results output by the navigation array.

3. The autonomous navigation system according to claim 2, characterized in that, The read / write circuit includes multiple column circuits, each column circuit including a BL precharge circuit, a write drive circuit, and an SA readout circuit. The process of the read / write circuit performing a write operation includes: After the WL selection circuit is turned on, the column circuit signal is converted and written into the navigation array through the write drive circuit.

4. The autonomous navigation system according to claim 3, characterized in that, The process of the read / write circuit performing a read operation includes: The BL precharge circuit performs a BL reset, and after the WL selection circuit is turned on, the SA readout circuit reads the real-time navigation results output by the navigation array.

5. The autonomous navigation system according to claim 1, characterized in that, The navigation array includes multiple navigation units, each of which includes an SRAM circuit, a pixel circuit, an annealing circuit, and a propagation circuit. The SRAM circuit includes a raw pixel data SRAM circuit, a map grid data SRAM circuit, and a path direction data SRAM circuit. A pixel circuit is used to generate an avalanche current in response to receiving the navigation enable signal, and to convert the avalanche current into a pulse voltage signal to be stored in the original pixel data SRAM circuit. An annealing circuit is used to calculate the target voltage signal and store it in the map grid data SRAM circuit in response to the navigation enable signal being pulled high. A propagation circuit is used to calculate the target transmission path and store it in the path direction data SRAM circuit in response to the navigation enable signal being pulled high.

6. The autonomous navigation system according to claim 5, characterized in that, The pixel circuit includes a SPAD pixel structure, an active hardening circuit, and a pulse readout circuit. SPAD pixel structure, in response to receiving the navigation enable signal, generates avalanche current by absorbing photons after entering the exposure window; A pulse readout circuit is used to convert the avalanche current into a pulse voltage signal and write the pulse voltage signal into the original pixel data SRAM circuit; An active hardening circuit is used to reset the SPAD pixel structure after exposure.

7. The autonomous navigation system according to claim 5, characterized in that, The annealing circuit includes a weight control switch, a status register, a random generator, a charge accumulation pulse circuit, and an analog-to-digital converter; A status register is used to obtain raw pixel data from the raw pixel data SRAM circuit. A weight control switch is used to connect the neighboring navigation units in response to the navigation enable signal being pulled high to determine the intermediate state of the current iteration; A random generator is used to output the random state of the current navigation unit; A charge accumulation pulse circuit and an analog-to-digital converter are used to perform logical operations based on the intermediate and random states and to determine the accumulation of the analog voltage signal. An analog-to-digital converter is used to convert the analog voltage signal into a target digital signal and store it in the map grid data SRAM circuit.

8. The autonomous navigation system according to claim 5, characterized in that, The propagation circuit includes a wavefront signal locking circuit and a propagation delay control circuit; A wavefront lock signal is used to block the input of wavefront signals in response to the navigation enable signal being pulled high. The propagation delay control circuit is used to control the propagation of wavefront signals in multiple directions.

9. The autonomous navigation system according to claim 6, characterized in that, In each of the navigation units, the calculation process of the pixel circuit includes: The SPAD pixel structure resets its output to 0 through its internal active quenching circuit and enters the exposure mode to wait for external photons to be incident, thus obtaining the SPAD pixel structure in the global exposure mode. During the global exposure window, after the SPAD pixel structure that captures photons generates an avalanche current, the pulse readout circuit converts the current into a pulse signal output. The pulse signal is written into the raw pixel data SRAM circuit inside the navigation unit.

10. The autonomous navigation system according to claim 7, characterized in that, In each of the navigation units, the calculation process of the annealing circuit includes: The original pixel data in the SRAM circuit is obtained, and noise grid points in the original pixel data are identified and removed based on the neighborhood information of the target grid points. If there are more similar grid points in the neighborhood of the target grid point, the type of the target grid point is preserved. The type information of the target grid point is written into the map grid data SRAM circuit inside the navigation unit.

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