A high-frequency signal measurement method and circuit

Abstract

This invention discloses a high-frequency signal measurement method and circuit. The high-frequency signal to be measured is filtered and split into two paths: the first path is attenuated by 1 / N, protected by TVS, and conditioned, and then converted into code value MA by the first channel of the ADC; the second path is attenuated by 1 / M, protected by TVS, and conditioned, and then converted into code value MB by the second channel of the ADC, where M / N is an integer power of 2. The FPGA pads MA and MB and executes a periodic interrupt program: MA1 and MB1 are compared with a preset switching voltage threshold to determine the code value to be sent. This invention achieves real-time high-speed acquisition of high-frequency signals with a dynamic range of 70dB without complex algorithms through dual-channel parallel acquisition and simplified FPGA logic switching, reducing the sampling error from 15LSB to 8LSB, and is suitable for accurate measurement of wide-range high-frequency signals such as transformer partial discharge.

Description

Technical Field

[0001] This invention belongs to the field of detection technology, and in particular relates to a high-frequency signal measurement method and circuit. Background Technology

[0002] Partial discharge in transformers is a gradual process that begins weakly and progresses to severe discharge due to insulation breakdown. The discharge signal intensifies from weak to strong, and the discharge quantity can range from tens of picocorts initially to tens of thousands of picocorts, exhibiting a wide variation. Among various partial discharge signal detection methods, high-frequency current sensors (HFCTs) have become a commonly used method due to their intuitive and efficient characteristics. In early transformer inspections, HFCT sampling signals were mainly used for alarms, requiring only a determination of signal presence. With technological advancements, there is now a greater need to identify the development process of transformer faults. By analyzing and identifying partial discharge signals, it is necessary to determine whether protective tripping is required to disconnect the transformer, thereby improving equipment safety and preventing explosions. This places higher demands on the accurate sampling of the HFCT output signal throughout the entire process.

[0003] Traditional HFCT sampling typically employs a single-channel approach. However, due to the amplitude variation of partial discharge current signals exceeding 1000 times, the sampling difficulty is significant, ranging from an initial weak signal to a final strong signal: ensuring sampling accuracy for small signals easily leads to exceeding the measurement range for large signals; expanding the sampling range makes it difficult to guarantee accuracy for small signals. Furthermore, the frequency of partial discharge signals is extremely high, typically ranging from 1MHz to 30MHz, placing higher demands on the sampling rate, usually requiring speeds exceeding 100MHz. Therefore, achieving instantaneous measurement of wide-range, high-frequency pulse currents has become a key technical challenge.

[0004] In the prior art, CN115078798A proposes a current range switching method and a current acquisition device. The method includes: acquiring analog current data in large / small ranges and buffering the analog data; setting an initial value for the small range current upper limit; judging the buffered analog data based on the initial value for the small range current upper limit, and selecting large / small range AD channels for sampling according to the judgment result; calculating the current sampling accuracy based on the large range data or small range data output by the large / small range AD channels through an error tracing platform; and formulating a dual-range automatic switching strategy based on the calculated sampling accuracy using a Q-Learning algorithm improved by the Antlion optimization algorithm, dynamically adjusting the initial value of the small range current upper limit to determine the small range current upper limit value with the widest measurement range and optimal sampling accuracy, and determining the optimal dual-range automatic switching strategy. This scheme can ensure both the measurement accuracy of small range current acquisition and the wide range of large range acquisition.

[0005] However, this method requires switching logic processing using the improved Q-Learning algorithm based on the Antlion optimization algorithm through an error tracing platform. For signal processing with sampling rates above 100MHz, both real-time processing and computational resource consumption pose a significant challenge.

[0006] Furthermore, in the prior art, CN119165237A proposes a method and device for measuring wide-range impulse current. The method includes acquiring first-range, second-range, and third-range A / D sampling data generated by the surge arrester when subjected to impulse current; comparing the maximum A / D sampling value in each range with the maximum A / D sampling value corresponding to zero potential to determine the sign of the impulse current; selecting the optimal range of A / D sampling data based on the maximum A / D sampling value in each range and the sign of the corresponding impulse current; acquiring circuit data of each voltage divider circuit and performance data of the current transformer; and calculating the peak impulse current based on the optimal range of A / D sampling data, the circuit data of the corresponding voltage divider circuit, and the performance data of the current transformer. By performing range-based measurement, the range of each range is effectively reduced, achieving accurate measurement of wide-range impulse current. However, this method cannot perform real-time signal range switching and cannot meet the requirement of continuous real-time measurement of wide-range high-frequency signals. Summary of the Invention

[0007] Purpose of the invention: This invention provides a high-frequency signal measurement method and circuit, aiming to solve the problem of how to achieve real-time, high-precision, and continuous acquisition of wide-range signals in measurement scenarios of high-frequency signals above 100MHz (such as transformer partial discharge pulse current), so as to meet the needs of dynamic monitoring of equipment fault development process and rapid protection trip judgment.

[0008] Technical solution: This invention provides a high-frequency signal measurement method, comprising:

[0009] The high-frequency signal to be tested obtained within the sampling period is input into the filtering circuit for bandwidth limiting processing to obtain the filtered signal, which is then divided into two paths, including the first signal and the second signal.

[0010] The first signal is attenuated by the 1 / N attenuation circuit to obtain the attenuated first signal. Then, it is limited by the TVS1 protection circuit to obtain the limited first signal. Then, it is processed by the signal conditioning circuit 1 to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the first analog signal. The first channel of the ADC is then converted into the first digital code value MA.

[0011] The second signal is attenuated by the 1 / M attenuation circuit to obtain the attenuated second signal. It is then limited by the TVS1 protection circuit to obtain the limited second signal. After being processed by the signal conditioning circuit 2, it meets the signal input range requirements of the analog-to-digital converter (ADC) to obtain the second analog signal. It is then converted into the second digital code value MB by the second channel of the ADC. N and M are attenuation coefficients and M / N is an integer power of 2.

[0012] The programmable logic chip FPGA expands the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and expands the second digital code value MB to a 16-bit second code value MB1 by shifting the second digital code value MB to the left and padding its low bits. Through the periodic interrupt program, the first code value and the second code value are compared with the preset upper and lower limit thresholds in each sampling period to determine the code value to be sent.

[0013] Furthermore, the step of expanding the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and expanding the second digital code value MB to a 16-bit second code value MB1 by shifting it left and padding its low bits includes: calculating the difference x between the number of bits of the first digital code value MA and 16 bits, padding the high x bits of MA with 0 to obtain the 16-bit first code value MA1, shifting MB left by x bits, padding the xth bit from low to high with 0, and padding the 1st to x-1th bits with 1 to obtain the second code value MB1.

[0014] Furthermore, the step of comparing the first code value, the second code value, and preset upper and lower threshold values ​​to determine the code value to be sent includes:

[0015] Set the range switching voltage thresholds V_th+, V_tl+, V_th-, and V_tl-;

[0016] If it is the first comparison, proceed to judgment condition 1; otherwise, determine whether the code value sent in the previous sampling period is the first code value MA1. If it is, proceed to judgment condition 1; otherwise, proceed to judgment condition 2.

[0017] Judgment condition 1: Is MA1 greater than V_th+ or less than V_th-? If the condition is met, then MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0018] Judgment condition 2: Is MB1 greater than V_tl+ or less than V_tl-? If the condition is met, MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0019] Furthermore, the sampling period includes either 20ns or 4ns.

[0020] The present invention also provides a high-frequency signal measurement circuit, including: a filter circuit, an 1 / N attenuation circuit, an 1 / M attenuation circuit, a TVS1 protection circuit, a TVS2 protection circuit, a signal conditioning circuit 1, a signal conditioning circuit 2, an analog-to-digital converter (ADC), and a programmable logic chip (FPGA).

[0021] The filtering circuit is used to input the high-frequency signal to be tested obtained within the sampling period into the filtering circuit for bandwidth limiting processing, obtain the filtered signal, and split it into two paths;

[0022] The 1 / N attenuation circuit is used to attenuate the first signal by a 1 / N ratio to obtain the attenuated first signal; the TVS1 protection circuit is used to limit the amplitude of the attenuated first signal to obtain the limited first signal; the signal conditioning circuit 1 is used to condition the limited first signal to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the first analog signal.

[0023] The 1 / M attenuation circuit is used to attenuate the second signal by a 1 / M ratio to obtain the attenuated second signal; the TVS2 protection circuit is used to limit the amplitude of the attenuated second signal to obtain the limited second signal; the signal conditioning circuit 2 is used to condition the limited second signal to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the second analog signal; N and M are attenuation coefficients and M / N is an integer power of 2;

[0024] The analog-to-digital converter (ADC) includes a first channel and a second channel. The first channel is used to convert a first analog signal into a first digital code value MA, and the second channel is used to convert a second analog signal into a second digital code value MB.

[0025] The programmable logic chip FPGA is used to expand the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and to expand the second digital code value MB to a 16-bit second code value MB1 by shifting the second digital code value MB to the left and padding its low bits; through a periodic interrupt program, the first code value and the second code value are compared with preset upper and lower limit thresholds in each sampling period to determine the code value to be sent.

[0026] Furthermore, in a programmable logic chip (FPGA), the step of expanding the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and expanding the second digital code value MB to a 16-bit second code value MB1 by shifting it left and padding its low bits includes: calculating the difference x between the number of bits of the first digital code value MA and 16 bits, padding the high x bits of MA with 0 to obtain the 16-bit first code value MA1, shifting MB left by x bits, padding the xth bit from low to high with 0, and padding the first to x-1th bits with 1 to obtain the second code value MB1.

[0027] Furthermore, in a programmable logic chip (FPGA), comparing the first code value, the second code value, and preset upper and lower threshold values ​​to determine the code value to be sent includes:

[0028] Set the range switching voltage thresholds V_th+, V_tl+, V_th-, and V_tl-;

[0029] If it is the first comparison, proceed to judgment condition 1; otherwise, determine whether the code value sent in the previous sampling period is the first code value MA1. If it is, proceed to judgment condition 1; otherwise, proceed to judgment condition 2.

[0030] Judgment condition 1: Is MA1 greater than V_th+ or less than V_th-? If the condition is met, then MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0031] Judgment condition 2: Is MB1 greater than V_tl+ or less than V_tl-? If the condition is met, MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0032] Furthermore, the sampling period includes either 20ns or 4ns.

[0033] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0034] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0035] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0036] 1. The measurement circuit of this invention adopts a dual-channel design, which takes into account both small and large signal analog inputs, and with the switching logic, it realizes wide-range sampling.

[0037] 2. This invention does not employ complex algorithms, but only uses a shift-two's complement sampling method, which improves sampling accuracy compared to direct sampling. Attached Figure Description

[0038] Figure 1 This is a circuit architecture diagram for high-frequency signal measurement.

[0039] Figure 2 Select a discriminant graph for channel data transmission.

[0040] Figure 3 Flowchart of the power-on initialization procedure.

[0041] Figure 4 This is a flowchart of a periodic interrupt procedure. Detailed Implementation

[0042] like Figure 1 As shown, the high-frequency signal measurement method of the present invention is characterized by comprising:

[0043] The high-frequency signal to be tested obtained within the sampling period is input into the filtering circuit for bandwidth limiting processing to obtain the filtered signal, which is then divided into two paths, including the first signal and the second signal.

[0044] The first signal is attenuated by the 1 / N attenuation circuit to obtain the attenuated first signal. Then it is limited by the TVS1 protection circuit to obtain the limited first signal. Then it is processed by the signal conditioning circuit 1 to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the first analog signal.

[0045] The second signal is attenuated by the 1 / M attenuation circuit to obtain the attenuated second signal. It is then limited by the TVS1 protection circuit to obtain the limited second signal. It is then processed by the signal conditioning circuit 2 to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the second analog signal.

[0046] The analog-to-digital converter (ADC) acquires the smaller signal from the two input analog signals using the first channel and the larger signal from the two input analog signals using the second channel, based on the magnitudes of the first and second analog signals. The smaller and larger signals are then converted into digital signals, with the code value of the smaller signal denoted as the first digital code value MA and the code value of the larger signal denoted as the second digital code value MB.

[0047] N and M are attenuation coefficients, and M / N is an integer power of 2. With the selected configuration parameters, such as N=5 and M=80, a wide range of sampling of the input signal amplitude of 70dB can be achieved, realizing a wide sampling range.

[0048] The programmable logic chip FPGA expands the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and expands the second digital code value MB to a 16-bit second code value MB1 by shifting the second digital code value MB to the left and padding its low bits. Through the periodic interrupt program, the first code value and the second code value are compared with the preset upper and lower limit thresholds in each sampling period to determine the code value to be sent.

[0049] In this embodiment, the input signal bandwidth is limited to within 20MHz, and a bandpass filter circuit is selected. Num is 4. The ADC bit width of the first and second channels is 12, and the ADC sampling rate can be designed as 50MHz / 250MHz. The corresponding periodic interrupt program execution cycle is 20ns / 4ns, and high-speed parallel processing is achieved using FPGA.

[0050] The step of expanding the first digital code value MA to a 16-bit first code value MA1 by padding its high bits and expanding the second digital code value MB to a 16-bit second code value MB1 by shifting it left and padding its low bits includes: calculating the difference x between the number of bits of the first digital code value MA and 16 bits, which is 4; padding the high 4 bits of MA with 0 to obtain the 16-bit first code value MA1; shifting MB left by 4 bits and padding it with 0b0111 from high to low bits to obtain the second code value MB1.

[0051] like Figures 2 to 4 As shown, in the programmable logic chip FPGA, the first code value, the second code value, and preset upper and lower threshold values ​​are compared to determine the code value to be sent, including:

[0052] FPGA power-on initialization, setting range switching voltage thresholds V_th+, V_tl+, V_th- and V_tl-;

[0053] If it is the first power-on initialization of the FPGA, then proceed to judgment condition 1; otherwise, determine whether the code value sent in the previous sampling period is the first code value MA1. If it is, proceed to judgment condition 1; otherwise, proceed to judgment condition 2.

[0054] Judgment condition 1: Is MA1 greater than V_th+ or less than V_th-? If the condition is met, then MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0055] Judgment condition 2: Is MB1 greater than V_tl+ or less than V_tl-? If the condition is met, MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0056] To verify the effectiveness of the method, an error comparison analysis was performed between the method of the present invention and direct sampling. The MB before shifting is as follows:

[0057]

[0058] After shifting left by four bits, the form is:

[0059]

[0060] Let Vsample be the ADC sampling voltage before shifting, and CODE be the corresponding 12-bit sampling code value. For a 12-bit ADC, the maximum absolute value of the error introduced by code value rounding before shifting is determined by D0, and the maximum value does not exceed Vsample / CODE.

[0061] Shifting left by 4 bits is equivalent to amplifying Vsample by 16 times. The maximum absolute value of the error introduced by sensitivity is determined by D0×16, which does not exceed Vsample×16 / CODE, meaning the maximum absolute error is also amplified by 16 times. The error amplification mainly occurs because the ADC sensitivity decreases after the shift; the lowest 4 bits are left empty and considered 0, instead of the actual value (the sensitivity before the shift can characterize a range of values). The actual value can be any value between 0000 and 1111. The results show that compared to direct sampling, the error is reduced from a maximum of 15 LSB to 8 LSB, achieving high sampling accuracy.

[0062] Table 1 presents the data error analysis using this method. As can be seen from the table, compared to the unprocessed sampling data, the above processing effectively reduces the maximum error of the acquisition system.

[0063] Table 1 Instantaneous Error Analysis Data for Two's Complement Sampling Method

[0064]

[0065] Example 2

[0066] like Figure 1 As shown in Embodiment 1, the high-frequency signal measurement circuit of the present invention includes: a filter circuit, an 1 / N attenuation circuit, an 1 / M attenuation circuit, a TVS1 protection circuit, a TVS2 protection circuit, a signal conditioning circuit 1, a signal conditioning circuit 2, an analog-to-digital converter (ADC), and a programmable logic chip (FPGA).

[0067] The filtering circuit is used to input the high-frequency signal to be tested obtained within the sampling period into the filtering circuit for bandwidth limiting processing, obtain the filtered signal, and split it into two paths;

[0068] The 1 / N attenuation circuit is used to attenuate the first signal by a 1 / N ratio to obtain the attenuated first signal; the TVS1 protection circuit is used to limit the amplitude of the attenuated first signal to obtain the limited first signal; the signal conditioning circuit 1 is used to condition the limited first signal to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the first analog signal.

[0069] The 1 / M attenuation circuit is used to attenuate the second signal by a 1 / M ratio to obtain the attenuated second signal; the TVS2 protection circuit is used to limit the amplitude of the attenuated second signal to obtain the limited second signal; the signal conditioning circuit 2 is used to condition the limited second signal to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the second analog signal; N and M are attenuation coefficients and M / N is an integer power of 2;

[0070] The analog-to-digital converter (ADC) includes a first channel and a second channel. The first channel is used to convert a first analog signal into a first digital code value MA, and the second channel is used to convert a second analog signal into a second digital code value MB.

[0071] N and M are attenuation coefficients, and M / N is an integer power of 2. With the selected configuration parameters, such as N=5 and M=80, a wide range of sampling of the input signal amplitude of 70dB can be achieved, realizing a wide sampling range.

[0072] The programmable logic chip FPGA is used to expand the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and to expand the second digital code value MB to a 16-bit second code value MB1 by shifting the second digital code value MB to the left and padding its low bits; through a periodic interrupt program, the first code value and the second code value are compared with preset upper and lower limit thresholds in each sampling period to determine the code value to be sent.

[0073] In this embodiment, the input signal bandwidth is limited to within 20MHz, and a bandpass filter circuit is selected. Num is 4. The ADC bit width of the first and second channels is 12, and the ADC sampling rate can be designed as 50MHz / 250MHz. The corresponding periodic interrupt program execution cycle is 20ns / 4ns, and high-speed parallel processing is achieved using FPGA.

[0074] The step of expanding the first digital code value MA to a 16-bit first code value MA1 by padding its high bits and expanding the second digital code value MB to a 16-bit second code value MB1 by shifting it left and padding its low bits includes: calculating the difference x between the number of bits of the first digital code value MA and 16 bits, which is 4; padding the high 4 bits of MA with 0 to obtain the 16-bit first code value MA1; shifting MB left by 4 bits and padding it with 0b0111 from high to low bits to obtain the second code value MB1.

[0075] like Figures 2 to 4 As shown, the step of comparing the first code value, the second code value, and preset upper and lower threshold values ​​to determine the code value to be sent includes:

[0076] FPGA power-on initialization, setting range switching voltage thresholds V_th+, V_tl+, V_th- and V_tl-;

[0077] If it is the first power-on initialization of the FPGA, then proceed to judgment condition 1; otherwise, determine whether the code value sent in the previous sampling period is the first code value MA1. If it is, proceed to judgment condition 1; otherwise, proceed to judgment condition 2.

[0078] Judgment condition 1: Is MA1 greater than V_th+ or less than V_th-? If the condition is met, then MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0079] Judgment condition 2: Is MB1 greater than V_tl+ or less than V_tl-? If the condition is met, MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

[0080] To verify the effectiveness of the method, an error comparison analysis was performed between the method of the present invention and direct sampling. The MB before shifting is as follows:

[0081]

[0082] After shifting left by four bits, the form is:

[0083]

[0084] Let Vsample be the ADC sampling voltage before shifting, and CODE be the corresponding 12-bit sampling code value. For a 12-bit ADC, the maximum absolute value of the error introduced by code value rounding before shifting is determined by D0, and the maximum value does not exceed Vsample / CODE.

[0085] Shifting left by 4 bits is equivalent to amplifying Vsample by 16 times. The maximum absolute value of the error introduced by sensitivity is determined by D0×16, which does not exceed Vsample×16 / CODE, meaning the maximum absolute error is also amplified by 16 times. The error amplification mainly occurs because the ADC sensitivity decreases after the shift; the lowest 4 bits are left empty and considered 0, instead of the actual value (the sensitivity before the shift can characterize a range of values). The actual value can be any value between 0000 and 1111. The results show that compared to direct sampling, the error is reduced from a maximum of 15 LSB to 8 LSB, achieving high sampling accuracy.

[0086] Table 1 presents the data error analysis using this method. As can be seen from the table, compared to the unprocessed sampling data, the above processing effectively reduces the maximum error of the acquisition system.

Claims

1. A high-frequency signal measurement method, characterized in that, include: The high-frequency signal to be tested obtained within the sampling period is input into the filtering circuit for bandwidth limiting processing to obtain the filtered signal, which is then divided into two paths, including the first signal and the second signal. The first signal is attenuated by the 1 / N attenuation circuit to obtain the attenuated first signal. Then it is limited by the TVS1 protection circuit to obtain the limited first signal. Then it is processed by the signal conditioning circuit 1 to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the first analog signal. The first channel of the analog-to-digital converter (ADC) converts the first digital code value MA; The second signal is attenuated by the 1 / M attenuation circuit to obtain the attenuated second signal. It is then limited by the TVS1 protection circuit to obtain the limited second signal. It is then processed by the signal conditioning circuit 2 to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the second analog signal. The second channel of the analog-to-digital converter (ADC) converts the data into a second digital code value MB; N and M are attenuation coefficients and M / N is an integer power of 2. The programmable logic chip FPGA expands the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and expands the second digital code value MB to a 16-bit second code value MB1 by shifting the second digital code value MB to the left and padding its low bits. Through the periodic interrupt program, the first code value and the second code value are compared with the preset upper and lower limit thresholds in each sampling period to determine the code value to be sent.

2. The high-frequency signal measurement method according to claim 1, characterized in that, The step of expanding the first digital code value MA to a 16-bit first code value MA1 by padding its high bits and expanding the second digital code value MB to a 16-bit second code value MB1 by shifting it left and padding its low bits includes: calculating the difference x between the number of bits of the first digital code value MA and 16 bits, padding the high x bits of MA with 0 to obtain the 16-bit first code value MA1, shifting MB left by x bits, padding the xth bit from low to high with 0, and padding the 1st to x-1th bits with 1 to obtain the second code value MB1.

3. The high-frequency signal measurement method according to claim 2, characterized in that, The step of comparing the first code value, the second code value, and preset upper and lower threshold values ​​to determine the code value to be sent includes: Set the range switching voltage thresholds V_th+, V_tl+, V_th-, and V_tl-; If it is the first comparison, proceed to judgment condition 1; otherwise, determine whether the code value sent in the previous sampling period is the first code value MA1. If it is, proceed to judgment condition 1; otherwise, proceed to judgment condition 2. Judgment condition 1: Is MA1 greater than V_th+ or less than V_th-? If the condition is met, then MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value. Judgment condition 2: Is MB1 greater than V_tl+ or less than V_tl-? If the condition is met, MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

4. The high-frequency signal measurement method according to claim 1, characterized in that, The sampling period includes either 20ns or 4ns.

5. A high-frequency signal measurement circuit, characterized in that, include: Filtering circuit, 1 / N attenuation circuit, 1 / M attenuation circuit, TVS1 protection circuit, TVS2 protection circuit, signal conditioning circuit 1, signal conditioning circuit 2, analog-to-digital converter (ADC), programmable logic chip (FPGA). The filtering circuit is used to input the high-frequency signal to be tested obtained within the sampling period into the filtering circuit for bandwidth limiting processing, obtain the filtered signal, and split it into two paths; The 1 / N attenuation circuit is used to attenuate the first signal by a 1 / N ratio to obtain the attenuated first signal; the TVS1 protection circuit is used to limit the amplitude of the attenuated first signal to obtain the limited first signal; the signal conditioning circuit 1 is used to condition the limited first signal to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the first analog signal. The 1 / M attenuation circuit is used to attenuate the second signal by a 1 / M ratio to obtain the attenuated second signal; the TVS2 protection circuit is used to limit the amplitude of the attenuated second signal to obtain the limited second signal; the signal conditioning circuit 2 is used to condition the limited second signal to meet the signal input range requirements of the analog-to-digital converter (ADC) to obtain the second analog signal; N and M are attenuation coefficients and M / N is an integer power of 2; The analog-to-digital converter (ADC) includes a first channel and a second channel. The first channel is used to convert a first analog signal into a first digital code value MA, and the second channel is used to convert a second analog signal into a second digital code value MB. The programmable logic chip FPGA is used to expand the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and to expand the second digital code value MB to a 16-bit second code value MB1 by shifting the second digital code value MB to the left and padding its low bits; through a periodic interrupt program, the first code value and the second code value are compared with preset upper and lower limit thresholds in each sampling period to determine the code value to be sent.

6. The high-frequency signal measurement circuit according to claim 5, characterized in that, In a programmable logic chip (FPGA), the step of expanding the first digital code value MA to a 16-bit first code value MA1 by padding its high bits, and expanding the second digital code value MB to a 16-bit second code value MB1 by shifting it left and padding its low bits includes: calculating the difference x between the number of bits of the first digital code value MA and 16 bits, padding the high x bits of MA with 0 to obtain the 16-bit first code value MA1, shifting MB left by x bits, padding the xth bit from low to high with 0, and padding the first to x-1th bits with 1 to obtain the second code value MB1.

7. The high-frequency signal measurement circuit according to claim 6, characterized in that, In a programmable logic chip (FPGA), comparing the first code value, the second code value, and preset upper and lower threshold values ​​to determine the code value to be sent includes: Set the range switching voltage thresholds V_th+, V_tl+, V_th-, and V_tl-; If it is the first comparison, proceed to judgment condition 1; otherwise, determine whether the code value sent in the previous sampling period is the first code value MA1. If it is, proceed to judgment condition 1; otherwise, proceed to judgment condition 2. Judgment condition 1: Is MA1 greater than V_th+ or less than V_th-? If the condition is met, then MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value. Judgment condition 2: Is MB1 greater than V_tl+ or less than V_tl-? If the condition is met, MB1 is selected as the uploaded code value; otherwise, MA1 is selected as the uploaded code value.

8. The high-frequency signal measurement circuit according to claim 5, characterized in that, The sampling period includes either 20ns or 4ns.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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