A shielded, interference-resistant multichannel electrical stimulation circuit

Abstract

This invention discloses a shielded, interference-resistant multi-channel electrostimulation circuit. The circuit includes: a host computer touch control module, an FPGA waveform generator, a digital isolation module, a DAC digital-to-analog converter module, an analog signal conversion and amplification unit, and an output logic switching module. The output logic switching module is connected to electrodes. The host computer touch control module designs the waveform and timing sequence; the FPGA waveform generator generates digital signals; after processing by the digital isolation module and the DAC digital-to-analog converter module, the signals are converted into analog signals by the analog signal conversion and amplification unit and amplified. The output logic switching module selects the stimulation mode according to the settings and applies the stimulation to the target area through the electrodes. Implementing this invention results in a circuit with a reasonable structure, strong anti-interference performance, flexible output methods, support for difference frequency stimulation, and comprehensive safety monitoring, meeting the requirements for high precision, high safety, and ease of use.

Description

Technical Field

[0001] This invention relates to a multi-channel electrical stimulation circuit, and more specifically to a shielded, interference-resistant multi-channel electrical stimulation circuit. Background Technology

[0002] Electrical stimulation of the cerebral cortex, as an effective means of modulating brain function, has been widely used in neuroscience and clinical treatment. However, existing electrical stimulation devices still face many challenges in achieving precise localization and efficient stimulation. First, traditional multi-channel electrical stimulation circuits mostly rely on single-channel low-frequency output modes, making it difficult to effectively utilize high-frequency or differential frequency strategies to precisely modulate the activity of deep brain tissues. Due to the lack of support for complex waveforms, these devices are inadequate for providing fine stimulation to specific brain regions.

[0003] Furthermore, the weak anti-interference capability of existing systems is a significant problem. Because digital and analog signals share the same ground wire, noise easily crosstalks between them, severely affecting the quality and stability of the output waveform. Especially in complex electromagnetic environments like those used in medical settings, this interference can significantly reduce the stimulation effect and may even cause unnecessary side effects. Therefore, improving the system's anti-interference performance is crucial to ensuring the safety and effectiveness of electrical stimulation.

[0004] Finally, the user interfaces of traditional electrical stimulation devices are not user-friendly and lack flexibility. These devices typically only provide fixed voltage or current outputs and cannot flexibly adjust parameters or switch operating modes according to different application scenarios. At the same time, the host computer software interface is simple in design and does not support intuitive waveform editing and timing programming functions, which greatly limits its convenience and adaptability in practical applications.

[0005] Therefore, it is necessary to design a new circuit that has a reasonable circuit structure, strong anti-interference performance, flexible output mode, supports differential frequency stimulation, and is equipped with comprehensive safety monitoring to meet the requirements of high precision, high security, and ease of use. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a shielded, interference-resistant multichannel electrical stimulation circuit.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a shielded, interference-resistant multi-channel electrical stimulation circuit, comprising: a host computer touch module, an FPGA waveform generator, a digital isolation module, a DAC digital-to-analog converter module, an analog signal conversion and amplification unit, and an output logic switching module; the output logic switching module is connected to electrodes; the host computer touch module is connected to the FPGA waveform generator; the FPGA waveform generator is connected to the digital isolation module; the digital isolation module is connected to the DAC digital-to-analog converter module; the DAC digital-to-analog converter module is connected to the analog signal conversion and amplification unit; the analog signal conversion and amplification unit is connected to the output logic switching module;

[0008] The waveform and timing are designed by the host computer touch module, the FPGA waveform generator generates digital signals, which are processed by the digital isolation module and the DAC digital-to-analog converter module, and then converted into analog signals by the analog signal conversion and amplification unit and amplified. The output logic switching module selects the stimulation mode according to the settings and applies it to the target area through electrodes.

[0009] The further technical solution includes a first power module, a BUCK power supply, and a Boost power supply. The first power module is connected to the BUCK power supply and the Boost power supply respectively. The BUCK power supply and the Boost power supply provide power to the host computer touch module and the FPGA waveform generator.

[0010] The further technical solution includes a second power supply module, an isolated DC-DC power supply module, and an isolated high-voltage module. The second power supply module is connected to the isolated DC-DC power supply module and the isolated high-voltage module respectively. The power is processed by the isolated DC-DC power supply module and the isolated high-voltage module to supply power to the DAC digital-to-analog conversion module, the analog signal conversion and amplification unit, and the output logic switching module.

[0011] The further technical solution is as follows: the FPGA waveform generator includes two direct digital frequency synthesizers; each direct digital frequency synthesizer includes a 32-bit phase accumulator, a 16-bit sine / square / triangle wave lookup table and an amplitude register connected in sequence; the 32-bit phase accumulator is connected to the host computer touch module, and the amplitude register is connected to the digital isolation module.

[0012] The further technical solution is as follows: the digital isolation module includes a multi-channel π160E30 digital isolator, which is connected to the FPGA waveform generator and the DAC digital-to-analog conversion module respectively. The multi-channel π160E30 digital isolator performs path-by-path isolation processing on each digital signal output by the FPGA waveform generator, including differential clock signal, data signal and mode control signal.

[0013] The further technical solution is as follows: the DAC digital-to-analog conversion module includes a dual-channel DAC chip, an output terminal matching resistor, a decoupling capacitor, a filter network, and a clock buffer circuit; the dual-channel DAC chip includes an input terminal, an output terminal, and a clock input terminal, wherein the output terminal of the dual-channel DAC chip is connected in parallel with the output terminal matching resistor; the output terminal of the dual-channel DAC chip is connected to the analog signal conversion and amplification unit through the decoupling capacitor; the input terminal of the dual-channel DAC chip is connected to the digital isolation module.

[0014] The further technical solution is as follows: the DAC digital-to-analog conversion module includes a clock buffer circuit, and the dual-channel DAC chip includes a clock input terminal; the clock input terminal of the dual-channel DAC chip is connected to the clock buffer circuit.

[0015] The further technical solution is as follows: the analog signal conversion and amplification unit includes a low-voltage amplification module, a high-voltage amplification module, a low-voltage constant current module, and a high-voltage constant current module; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are connected in parallel; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are respectively connected to the DAC digital-to-analog conversion module; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are respectively connected to the output logic switching module; The low-voltage amplification module, high-voltage amplification module, low-voltage constant current module, and high-voltage constant current module are respectively connected to the output logic switching module via shielded cables.

[0016] The further technical solution is as follows: the output logic switching module includes a multi-channel relay array module and a relay status feedback loop; the multi-channel relay array module includes several relays; the relays are connected to the relay status feedback loop; the relay status feedback loop is connected to the host computer touch module; and the relays are connected to the electrodes.

[0017] The advantages of this invention compared to existing technologies are as follows: By integrating a host computer touch module, an FPGA waveform generator, a digital isolation module, a DAC digital-to-analog converter module, an analog signal conversion and amplification unit, and an output logic switching module, this invention forms a system with a reasonable structure, strong anti-interference performance, and flexible output modes. Specifically, users can conveniently design complex waveforms and timing sequences through the host computer touch module. The FPGA waveform generator is responsible for generating accurate digital signals, which are then converted into stable analog signals and amplified after efficient digital isolation and high-precision DAC conversion. The output logic switching module allows selection of appropriate stimulation modes according to experimental or clinical needs, ensuring the realization of advanced functions such as difference frequency stimulation. Throughout the process, digital isolation technology and shielding measures effectively prevent external electromagnetic interference, ensuring signal purity; while a complete safety monitoring mechanism further enhances the reliability and safety of the system, fully meeting the requirements for high precision, high safety, and ease of use.

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic block diagram of a shielded, interference-resistant multichannel electrical stimulation circuit provided for an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the direction of the conduction of electrical current within the brain through stimulation using two pairs of electrodes, as provided in an embodiment of the present invention. Figure 3 Embodiments of the present invention Figure 2 Waveform of the simulated 1Hz magnetic field strength after voltage stimulation; Figure 4 A partial bank circuit diagram of an FPGA waveform generator provided in an embodiment of the present invention; Figure 5 A specific circuit diagram of the digital isolation module provided in an embodiment of the present invention; Figure 6 This is a specific circuit diagram of the DAC digital-to-analog converter module provided in an embodiment of the present invention; Figure 7 The specific circuit of the analog signal conversion and amplification unit provided in the embodiments of the present invention. Figure 1 ; Figure 8The specific circuit of the analog signal conversion and amplification unit provided in the embodiments of the present invention. Figure 2 ; Figure 9 The specific circuit of the analog signal conversion and amplification unit provided in the embodiments of the present invention. Figure 3 ; Figure 10 The specific circuit of the analog signal conversion and amplification unit provided in the embodiments of the present invention. Figure 4 ; Figure 11 A specific circuit diagram of the output logic switching module provided in an embodiment of the present invention; Figure 12 The specific circuit diagrams of the first power module and the second power module provided in the embodiments of the present invention. Figure 1 ; Figure 13 The specific circuit diagrams of the first power module and the second power module provided in the embodiments of the present invention. Figure 2 ; Figure 14 The specific circuit diagrams of the first power module and the second power module provided in the embodiments of the present invention. Figure 3 ; Figure 15 The specific circuit diagrams of the first power module and the second power module provided in the embodiments of the present invention. Figure 4 .

[0021] Explanation of the markings in the image: 1. FPGA waveform generator; 2. Digital isolation module; 3. DAC digital-to-analog converter module; 4. Analog signal conversion and amplification unit; 5. Output logic switching module; 6. Electrodes; 7. Host computer touch module; 8. First power supply module; 9. Second power supply module. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0024] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0025] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] Electrical cortical stimulation (ECS) is a crucial tool for modulating brain function and is widely used in neuroscience and clinical treatment. However, existing devices face challenges in precise localization and efficient stimulation. These include limitations in supporting high-frequency or difference-frequency strategies and complex waveform outputs for fine-tuning, weak anti-interference capabilities due to shared grounding for digital and analog signals, and unfriendly user interfaces lacking flexibility and intuitive programming capabilities. These shortcomings collectively limit its effectiveness and adaptability in practical applications. These deficiencies render current ECS devices inadequate for complex application scenarios, impacting their safety and efficacy.

[0027] This embodiment provides a multi-channel electrical stimulation circuit with shielded interference, which achieves a reasonable circuit structure, strong anti-interference performance, flexible output mode, support for differential frequency stimulation, and is equipped with comprehensive safety monitoring, meeting the requirements for high precision, high safety, and ease of use.

[0028] Specifically, by integrating a host computer touch control module 7, an FPGA waveform generator 1, a digital isolation module 2, a DAC digital-to-analog converter module 3, an analog signal conversion and amplification unit 4, and an output logic switching module 5, a design with a reasonable structure and strong anti-interference performance is achieved. The FPGA generates programmable complex waveforms and timing sequences, digital isolation ensures signal purity, and the DAC module converts them into precise analog signals for amplification. Finally, the output logic switching module 5, with its flexible configuration, applies the signals to the target area, supporting multiple modes such as differential frequency stimulation. Furthermore, the equipped first and second power supply modules 9 and multiple power supply schemes ensure stable operation of all components, while the relay array and status feedback loop provide a comprehensive safety monitoring mechanism. The overall design meets the requirements for high precision, high safety, and ease of use.

[0029] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0030] Please see Figure 1A shielded, interference-resistant multichannel electrical stimulation circuit includes: a host computer touch module 7, an FPGA waveform generator 1, a digital isolation module 2, a DAC digital-to-analog converter module 3, an analog signal conversion and amplification unit 4, and an output logic switching module 5; the output logic switching module 5 is connected to electrodes 6; the host computer touch module 7 is connected to the FPGA waveform generator 1; the FPGA waveform generator 1 is connected to the digital isolation module 2; the digital isolation module 2 is connected to the DAC digital-to-analog converter module 3; the DAC digital-to-analog converter module 3 is connected to the analog signal conversion and amplification unit 4; and the analog signal conversion and amplification unit 4 is connected to the output logic switching module 5. The waveform and timing are designed by the host computer touch module 7, the FPGA waveform generator 1 generates digital signals, which are processed by the digital isolation module 2 and the DAC digital-to-analog converter module 3, and then converted into analog signals and amplified by the analog signal conversion and amplification unit 4. The output logic switching module 5 selects the stimulation mode according to the setting and applies it to the target part through the electrode 6.

[0031] In this embodiment, the host computer touch module 7 serves as the main interface for user interaction with the device, employing a 7.84-inch high-definition touchscreen to provide an intuitive and convenient operating experience. This module features three core pages: parameter setting, timing programming, and status display. Users can not only select the desired waveform type, such as a sine wave or square wave, but also set the frequency range from 0 to 100kHz and adjust the output mode to a voltage source or current source according to experimental requirements. Furthermore, this module has a real-time feedback function, dynamically displaying the graph and progress of the generated waveform during operation, allowing users to adjust settings instantly and optimize experimental results.

[0032] The FPGA waveform generator 1 is one of the core components of the entire system. It uses the Xilinx Artix-7 series XC7A200T chip, which supports the generation of dual independent programmable high-frequency waveforms. Each signal consists of a 32-bit phase accumulator and a 16-bit sine / square / triangular lookup table (LUT), allowing for precise control of the waveform frequency with a minimum step of 1Hz. More importantly, the two signals can achieve phase locking through a synchronization start signal, thereby ensuring the stability of the difference frequency output. This design is particularly suitable for applications requiring high-precision time synchronization.

[0033] To ensure signal transmission quality and system security, digital isolation module 2 employs a π160E30 isolator to handle communication between the FPGA and the DAC. This module not only implements differential clock isolation, data isolation, and mode setting isolation, but also ensures the purity of high-speed signal transmission. Specifically, the isolator has a withstand voltage of at least 3kVrms and a transmission rate of no less than 150Mbps. These performance indicators effectively avoid common-ground interference and improve the overall system reliability and anti-interference capability.

[0034] The digital-to-analog converter (DAC) is the key component that converts digital signals into analog signals. It features dual-channel 16-bit resolution and ±5V bipolar output capability, with a sampling rate up to 250MSps. This configuration ensures that signal flatness remains within ±0.1dB across the entire DC to 100kHz range. To further improve signal quality, the DAC module is also equipped with a 50Ω output termination resistor, effectively suppressing reflections and maintaining signal integrity.

[0035] The analog signal conversion and amplification unit 4 comprises four subunits: low-voltage amplification, high-voltage amplification, low-voltage constant current, and high-voltage constant current. The low-voltage amplification uses the OPA189IDBVR rail-to-rail operational amplifier, with a gain of 3, a bandwidth exceeding 1MHz, and an output of ±15V. The high-voltage amplification is based on the ADHV4702-1, paired with an isolated high-voltage source, achieving an output capability of ±100V. Both the low-voltage and high-voltage constant current circuits utilize Howland circuit design; the former achieves an accuracy of 0.1% with an amplitude limited to ±15V, while the latter is optimized for high-voltage environments, with its amplitude also clamped to ±100V.

[0036] The output logic switching module 5, through an array of TQ2-5V relays and in conjunction with the NX3008NBK driver chip, achieves rapid switching (≤7ms) while maintaining low on-resistance (≤0.1Ω). This module supports multiple combined closing modes, such as simultaneously activating low-voltage and high-voltage current modes, greatly increasing the system's flexibility and adaptability, and meeting the needs of various complex experiments.

[0037] The power supply section encompasses standard 12V power supplies, isolated switching power supplies, Boost / Buck converters, and specially designed ±110V isolated power supplies. All power supply designs take isolation requirements into account to reduce noise coupling and ensure signal quality and operational safety. For example, the ±110V isolated power supply used in the high-voltage amplification design exemplifies this, with noise coupling below -80dB, providing a solid foundation for the stable operation of the entire system.

[0038] Shielding structures such as single-point grounding and isolated power supplies, along with digital isolation technology, effectively reduce external interference. Users can precisely set waveform type, frequency, and amplitude via the host computer touch module 7 and monitor the electrical stimulation process in real time. It can generate multiple output modes (such as ±15V / ±100V voltage sources and ±2mA / ±10mA current sources) and achieve four-mode switching on a single port through a relay array. Utilizing dual-channel high-frequency signals to generate a low-frequency magnetic field on the cortical surface through differential frequency, combined with the low-pass filtering characteristics of brain tissue, precise stimulation of deep regions is achieved. Integrated status feedback loops and multiple protection measures ensure operational safety and reliability.

[0039] The user first sets the required parameters through the host computer touch module 7, and the FPGA waveform generator 1 generates corresponding digital signals accordingly. These signals are processed by the digital isolation module 2 and then enter the DAC digital-to-analog converter module 3, where they are converted into analog signals. The analog signals are then adjusted to an appropriate amplitude by the analog signal conversion and amplification unit 4, and finally, a specific output mode is selected through the output logic switching module 5, and applied to the surface of the cerebral cortex through electrodes 6.

[0040] This circuit design not only meets the requirements for high precision, high security, and ease of use, but also places special emphasis on its anti-interference performance, enabling it to operate stably in complex electromagnetic environments, thereby ensuring the accuracy and consistency of the neuromodulation effect.

[0041] In one embodiment, please refer to Figure 1 , Figures 12 to 15 The aforementioned shielded and interference-resistant multi-channel electrical stimulation circuit also includes a first power supply module 8, a BUCK power supply, and a Boost power supply. The first power supply module 8 is connected to the BUCK power supply and the Boost power supply respectively. The BUCK power supply and the Boost power supply provide power to the host computer touch module 7 and the FPGA waveform generator 1.

[0042] The first power module 8 provides the system with a basic input voltage (such as 12 V DC power) and is connected to the BUCK buck converter and Boost boost converter respectively, forming a dual-channel DC-DC conversion structure, which is used to provide stable and isolated multi-voltage level power supply for the host computer touch module 7 and FPGA waveform generator 1 and other digital core units.

[0043] exist Figures 12 to 15 In the circuit shown, the first power module 8 (which can be understood as an external 12V input source) is connected to the system through an input port, and its positive and negative terminals are respectively connected to the input terminals of multiple DC-DC conversion chips. Specifically: BUCK Power Supply: A synchronous buck converter, such as the LM2596 or similar model, is used to convert the 12V input voltage to lower output voltages, such as 5V and 3.3V. These voltages supply power to the Android main control processor (such as RK3308), display driver circuit, and FPGA digital I / O in the host computer touch module 7, respectively. This module is typically equipped with input / output filter capacitors (such as a 10μF electrolytic capacitor + a 0.1μF ceramic capacitor) to suppress ripple and transient noise.

[0044] Boost power supply: Using a boost DC-DC converter such as the LM2577 or TPS61088, the 12V input is boosted to a higher voltage, such as 18V, to drive the high-speed SerDes interface, DDR memory, or certain high-voltage logic devices inside the FPGA. Additionally, 18V can also serve as a pre-regulated voltage for analog power supply, used for subsequent voltage regulation.

[0045] It is worth noting that all DC-DC converters employ an isolated switching design, meaning there is an electrical isolation layer (such as transformer-coupled or magnetically isolated type) between the input and output, completely separating digital ground (DGND) from analog ground (AGND) to avoid common-mode noise crosstalk. Furthermore, both the BUCK and Boost modules feature overcurrent protection, short-circuit protection, and soft-start functionality, enhancing system safety and stability.

[0046] In addition, the entire digital power system is partitioned on the PCB layout, and the digital ground and analog ground are connected at the edge using a single-point grounding strategy to form a "star ground". This effectively reduces the ground loop current and makes the ground loop resistance less than 5mΩ, which significantly suppresses the impact of low-frequency power frequency interference (such as 50Hz) on sensitive signal paths.

[0047] In one embodiment, please refer to Figure 1 , Figures 12 to 15 The aforementioned shielded anti-interference multi-channel electrical stimulation circuit also includes a second power supply module 9, an isolated DC-DC power supply module, and an isolated high-voltage module. The second power supply module 9 is connected to the isolated DC-DC power supply module and the isolated high-voltage module respectively. After the power is processed by the isolated DC-DC power supply module and the isolated high-voltage module, it supplies power to the DAC digital-to-analog conversion module 3, the analog signal conversion and amplification unit 4, and the output logic switching module 5.

[0048] The second power module 9 also receives a 12V input, but its main function is to provide dedicated power support for the analog signal link and high-voltage output channel. It is connected to the isolated DC-DC power module (for generating ±24V) and the isolated high-voltage module (for generating ±110V), which together form a high-voltage power supply system to provide a high-quality, low-noise power supply environment for the DAC digital-to-analog conversion module 3, the analog signal conversion and amplification unit 4, and the output logic switching module 5.

[0049] exist Figures 12 to 15 In the circuit shown, the isolated DC-DC power supply module refers to an isolated DC-DC power supply module, such as the TSP series or PSU series. This module converts a 12V input to a ±24V bipolar output, used to drive operational amplifiers (such as OPA189, ADHV4702-1) in analog circuits and as the reference voltage source for the DAC. Due to its internal integrated transformer isolation structure, the isolation voltage between the output and input terminals is ≥3kV, and the noise coupling is less than -80dB, greatly reducing the interference of digital noise on analog signals.

[0050] High-voltage isolation module: This refers to a high-voltage isolated power supply module provided by the manufacturer, such as the HV-110 series. Its input is 12V or 24V, and its output is ±110V isolated high voltage. This module is specifically designed for high-voltage amplification units, providing bias power for high-voltage operational amplifiers such as the ADHV4702-1. Internally, it includes a high-voltage transformer, rectifier and filter circuits, and feedback control loop to ensure stable output voltage and minimal ripple. Simultaneously, it has a withstand voltage of up to 3kV between its output and input terminals to prevent high voltage backflow to the low-voltage side.

[0051] Both types of modules are individually packaged, with built-in heat sinks and EMI filter networks, enabling long-term stable operation under high power conditions. Their outputs are connected via dedicated power cables to the analog power supply pins of the DAC digital-to-analog converter module 3, the power supply pins of the high-voltage amplifier unit, and the drive power port of the relay array, respectively.

[0052] from Figure 9 It can be seen that the entire power system is divided into two major independent power supply domains: Digital power supply domain: After being processed by BUCK / Boost from the first power module 8, it provides multiple voltage levels such as 5V, 3.3V, and 18V to digital logic circuits such as FPGA, touch screen, and MCU; Analog and High Voltage Power Supply Domain: After being processed by the isolation high voltage module, the second power supply module 9 provides ±24V and ±110V isolated power supplies to analog front-end components such as DACs, operational amplifiers, and high voltage amplifiers.

[0053] The two power supply domains are electrically connected via a single-point grounding strategy, meaning that the digital ground (DGND) and analog ground (AGND) converge at only one point on the PCB edge to avoid forming ground loops. Simultaneously, all power modules are equipped with side protection circuits such as decoupling capacitors, TVS diodes, and RC snubber circuits to further enhance anti-interference capabilities and reliability.

[0054] also, Figure 9 Multiple power monitoring circuits (such as LTC3883 or similar chips) can also be seen to monitor the voltage level of each power rail in real time and trigger alarms or automatic power-off protection in case of abnormalities, ensuring the safe operation of the equipment.

[0055] In summary, this embodiment, by introducing a first power supply module 8, a BUCK power supply, a Boost power supply, a second power supply module 9, an isolated DC-DC power supply module, and an isolated high-voltage module, achieves discrete power supply, isolation design, and precise control for the digital and analog, low-voltage and high-voltage sections of the electrostimulation circuit. This architecture not only meets the stringent power quality requirements of key components such as FPGAs, DACs, and high-voltage amplifiers, but also comprehensively improves the system's anti-interference capability through multi-level isolation, single-point grounding, and low-noise filtering, ensuring the high fidelity and security of the neuromodulation signal, fully demonstrating the technical advantages of this embodiment in "shielding and anti-interference."

[0056] In this embodiment, the user operates the device via a 7.84-inch high-definition touchscreen. Developed on the Android platform, this touchscreen provides an intuitive and convenient operating environment, primarily comprising three functional pages: parameter settings, timing programming, and status display.

[0057] The parameter settings page allows users to customize various parameters of the electrical stimulation waveform according to experimental or application needs. Specifically, users can select from a variety of preset waveform types, such as sine waves and square waves, to suit different application scenarios. Furthermore, dual-channel frequencies can be set, meaning users can independently adjust the operating frequencies of the two output channels to meet complex experimental design requirements. For amplitude adjustment, users can precisely set the voltage magnitude of each waveform as needed, thereby controlling the intensity of the electrical stimulation. The output mode selection provides greater flexibility, allowing users to choose between continuous output or pulsed output.

[0058] The timing programming page offers a novel way to arrange electrical stimulation sequences. Users can add different stimulation segments via an intuitive drag-and-drop timeline, such as setting a 10-second sine wave stimulation followed by a 10-second square wave stimulation. This visual programming approach not only simplifies the design process for complex timing sequences but also improves efficiency. More importantly, these stimulation sequences support both single-execution and cyclical modes, making the planning of long-term experiments or treatment protocols much easier.

[0059] The status monitoring page ensures users can monitor the actual output of the electrical stimulation waveform in real time. On this page, the system dynamically displays the currently output electrical stimulation waveform and its progress bar, giving users a clear and timely understanding of the electrical stimulation process. This function is crucial for monitoring experimental progress and adjusting parameters promptly, especially in medical settings where accurate status feedback helps improve the success rate of experiments and treatment outcomes.

[0060] In summary, through these three main pages—parameter settings, timing programming, and status monitoring—users can efficiently and accurately control and monitor the operating status of electrical stimulation devices, meeting diverse application needs. This touch interface design, based on Android, aims to provide users with a user-friendly, flexible, and powerful operating platform, greatly improving user experience and work efficiency.

[0061] In one embodiment, please refer to Figure 4 The aforementioned FPGA waveform generator 1 includes two direct digital frequency synthesizers; each direct digital frequency synthesizer includes a 32-bit phase accumulator, a 16-bit sine / square / triangle wave lookup table amplitude register connected in sequence; the 32-bit phase accumulator is connected to the host computer touch module 7, and the amplitude register is connected to the digital isolation module 2.

[0062] Please see Figure 4 The aforementioned FPGA waveform generator 1 is implemented using a Xilinx Artix-7 XC7A200T device, which integrates two completely independent and parallel-operating direct digital frequency synthesizer (DDS) cores, used to generate dual high-precision, programmable high-frequency stimulation signals. This design fully leverages the powerful programmable logic resources and high-speed I / O capabilities of the FPGA, enabling precise control of key parameters in neural modulation through flexible configuration.

[0063] Each DDS core consists of three core functional units connected in sequence: a 32-bit phase accumulator, a 16-bit sine / square / triangle wave lookup table (LUT), and an amplitude register. The 32-bit phase accumulator, as the core calculation unit of the DDS, receives the frequency control word set by the host computer touch module 7 and accumulates it cycle by cycle under the drive of the system clock, generating a continuously increasing phase address. This phase address is then sent to the subsequent lookup table for waveform sampling. Because the phase accumulator is a 32-bit structure, its resolution is extremely high. Combined with the system clock frequency, the output frequency can be set in minimum steps of 1Hz within the range of 0 to 100kHz, meeting the fine frequency adjustment requirements of difference frequency stimulation.

[0064] Following this is a 16-bit sine / square / triangle lookup table (LUT) that stores discrete sampling point data of the corresponding waveform within one cycle. When the address index output by the phase accumulator enters the LUT, the corresponding amplitude value can be read in real time, thereby realizing the digital reconstruction of the waveform. This LUT supports multiple standard waveform types, and users can select to output sine, square, or triangle waves through the host computer interface, greatly improving the system's flexibility and applicability. In addition, the data output by the LUT is modulated by a 16-bit amplitude register, which receives amplitude parameters set by the host computer to dynamically adjust the peak value of the output signal, achieving precise control of voltage or current amplitude.

[0065] At the hardware circuit level, such as Figure 4 As shown, the multiple BANK areas of the FPGA are rationally allocated for I / O interfaces of different functions. For example, BANK0, BANK1, and BANK2 respectively carry the communication channels between the FPGA and external devices. The control input ports of the 32-bit phase accumulator (such as frequency control words and start signals) are connected to the host computer touch module 7 via dedicated GPIO pins, ensuring that parameters can be written quickly and stably into the FPGA's internal logic. The output of the amplitude register is connected to the digital isolation module 2 via a set of 16-bit parallel data lines. These data lines are processed by the π160E30 digital isolator before being transmitted to the DAC digital-to-analog converter module 3, achieving a seamless transition from digital to analog.

[0066] Specifically, the two DDS cores achieve phase locking through a shared synchronization start signal, which is uniformly generated by the FPGA's internal logic and synchronously triggered between the two channels, ensuring that the two output signals are aligned at the start time. This feature is crucial for achieving difference-frequency stimulation—for example, when one outputs a 1kHz sine wave and the other outputs a 1kHz±1Hz signal, their superposition will generate a stable 1Hz difference-frequency component on the cortical surface, utilizing the low-pass characteristics of brain tissue to achieve selective activation of deep neural tissue.

[0067] In summary, Figure 4 The FPGA's internal DDS architecture, as shown, not only achieves high-precision, high-resolution waveform generation capabilities but also ensures the stability and consistency of dual-channel signals through a reasonable BANK layout, multi-channel I / O allocation, and synchronous control mechanisms. This design efficiently connects the host computer's parameter settings with the underlying hardware logic, forming the core of the most critical signal source in the entire multi-channel electrical stimulation circuit, laying a solid foundation for subsequent digital isolation, digital-to-analog conversion, and multi-mode output.

[0068] In one embodiment, please refer to Figure 5 The aforementioned digital isolation module 2 includes a multi-channel π160E30 digital isolator, which is connected to the FPGA waveform generator 1 and the DAC digital-to-analog converter module 3 respectively. The multi-channel π160E30 digital isolator performs path-by-path isolation processing on each digital signal output by the FPGA waveform generator 1, including differential clock signal, data signal and mode control signal.

[0069] Please see Figure 5 The aforementioned digital isolation module 2 is located adjacent to the output of the FPGA waveform generator 1, and its core consists of a multi-channel π160E30 digital isolator. This isolator is a high-speed digital isolation device based on capacitive coupling technology, featuring high voltage withstand capability, low latency, and high transmission rate. It can effectively achieve electrical isolation between digital signals and analog circuits, preventing noise crosstalk. In the circuit structure shown in the figure, the π160E30 is used to isolate each key digital signal output by the FPGA, including differential clock signals, data signals, and mode control signals, thereby constructing a safety barrier from the digital logic domain to the analog signal domain.

[0070] Specifically, Figure 5 The diagram showcases multiple π160E30 chips (e.g., π160E30_1 to π160E30_4), connected between the FPGA's output pins and the DAC (digital-to-analog converter) module 3. Each π160E30 chip contains multiple independent isolation channels, such as "CH0" and "CH1" visible in the diagram, supporting single-ended or differential signal transmission. The differential clock signal output from the FPGA (e.g., FPGA_CLK_P / N) is connected to the π160E30's input via a dedicated channel and coupled through internal capacitors before being output, ensuring that the clock signal does not experience backflow interference due to a common ground path during transmission. This design effectively avoids ground loop currents formed by high-frequency clock signals in the PCB traces, improving the system's anti-interference capability.

[0071] Meanwhile, the data signals generated by the FPGA (such as FPGA_DATA[15:0]) are also isolated bit by bit through the π160E30. These signals come from the output of the DDS core and are the basic data source for subsequent DAC conversion. In the diagram, each data line is connected to an independent π160E30 channel, with its input connected to the FPGA output and its output connected to the input pin of the DAC chip. Since the π160E30 has a transmission rate of ≥150 Mbps, it fully meets the FPGA's requirement to output a 100 kHz waveform at a sampling rate of 250 MSps, ensuring the integrity and real-time performance of high-speed data transmission.

[0072] Furthermore, the mode control signals (such as MODE_SEL, OUT_MODE, etc.) set by the host computer touch module 7 are also transmitted in isolation through the π160E30. These signals are used to switch output modes (such as voltage / current, low voltage / high voltage) and must maintain electrical isolation between the digital and analog sections. As shown in the figure, these control signals are transmitted through a dedicated channel of the π160E30, ensuring that even with large transient voltages or noise on the analog side, the normal operation of the FPGA will not be affected.

[0073] In terms of power supply, each π160E30 chip is equipped with independent input-side (VDD1) and output-side (VDD2) power supplies, which are completely isolated from each other by an isolation layer. The input side is supplied by the FPGA power supply system (e.g., 3.3V), while the output side is driven by the DAC power supply system (e.g., 3.3V or 5V), forming a dual-power isolation architecture. This design not only achieves signal isolation but also blocks the common ground path between the FPGA and the back-end analog circuitry, fundamentally suppressing the conduction of digital noise to the analog front end.

[0074] It is worth noting that, Figure 5 The document also shows that each π160E30 chip is equipped with decoupling capacitors (such as 0.1μF ceramic capacitors) and filter networks at its input / output terminals to stabilize power supply voltage, reduce ripple, and suppress electromagnetic interference. Simultaneously, all isolators employ zoned wiring at their grounding terminals, achieving single-point grounding at the PCB edge to further reduce ground loop impedance, ensuring a ground loop resistance of less than 5mΩ and guaranteeing overall system immunity to interference better than -80dB.

[0075] In summary, Figure 5The digital isolation module 2 shown achieves comprehensive isolation of the differential clock, data, and mode control signals output from the FPGA through a multi-channel π160E30 isolator. Its voltage withstand capability is ≥3kVrms, and its transmission rate is ≥150Mbps, fully meeting the system's requirements for high-precision, high-stability electrical stimulation signals. This design not only ensures signal integrity but also significantly improves the system's safety and reliability, providing a clean digital input environment for subsequent DAC conversion and analog amplification.

[0076] In one embodiment, please refer to Figure 6 The aforementioned DAC digital-to-analog conversion module 3 includes a dual-channel DAC chip, an output terminal matching resistor, a decoupling capacitor, a filter network, and a clock buffer circuit. The dual-channel DAC chip includes an input terminal, an output terminal, and a clock input terminal. The output terminal of the dual-channel DAC chip is connected in parallel with the output terminal matching resistor. The output terminal of the dual-channel DAC chip is connected to the analog signal conversion and amplification unit 4 through the decoupling capacitor. The input terminal of the dual-channel DAC chip is connected to the digital isolation module 2.

[0077] In one embodiment, please refer to Figure 6 The aforementioned DAC digital-to-analog conversion module 3 includes a clock buffer circuit, and the dual-channel DAC chip includes a clock input terminal; the clock input terminal of the dual-channel DAC chip is connected to the clock buffer circuit.

[0078] Please see Figure 6 The aforementioned DAC (Digital-to-Analog Converter) module 3 is the crucial bridge connecting digital and analog signals in the entire multi-channel electrical stimulation circuit. Its core is the dual-channel high-performance DAC chip AD9747BCPZ. This chip features 16-bit resolution, ±5V bipolar output capability, and supports sampling rates up to 250MSps. It achieves a flat amplitude-frequency response of ±0.1dB within the DC to 100kHz frequency band, ensuring high fidelity and low distortion characteristics of the output waveform. In the circuit design, the input of the AD9747BCPZ is directly connected to the 16-bit parallel data bus from the digital isolation module 2, receiving the digital signal isolated by the π160E30, thus realizing the precise conversion from the digital waveform generated by the FPGA to the analog voltage.

[0079] like Figure 6As shown, the two output channels of the AD9747BCPZ are driven by independent output buffer stages to enhance their load-carrying capacity and anti-interference performance. Each output terminal is connected in parallel with a 50Ω terminating resistor (such as R101, R102). This resistor matches the transmission line impedance, effectively suppressing reflections of high-speed signals during long-distance transmission and preventing ringing and overshoot caused by impedance discontinuities, thus ensuring signal integrity and frequency response flatness. In addition, the DAC output is equipped with decoupling capacitors (such as C101, C102), typically 0.1μF ceramic capacitors, to filter out power supply noise and transient current fluctuations, further improving output stability.

[0080] In terms of signal path, the output of the AD9747BCPZ is buffered and then sent synchronously to four downstream analog conversion units (module 4) via a multi-parallel structure. These units include low-voltage amplification, high-voltage amplification, low-voltage constant current, and high-voltage constant current subunits. This parallel design allows the same basic analog signal to drive multiple output modes simultaneously, improving system flexibility and resource utilization. Simultaneously, each output is processed by a filtering network (such as an RC low-pass filter) to remove potential switching noise and spurious frequency components, ensuring that the signal input to subsequent amplification circuits is pure and distortion-free.

[0081] For clock processing, the AD9747BCPZ's clock input is connected to a dedicated clock buffer circuit (such as the AD9516 or a similar device). This circuit is responsible for shaping, multiplying, and distributing the differential clock signal from the FPGA, providing a stable, low-jitter reference clock. As shown in the diagram, the clock signal output from the buffer circuit enters the CLK+ and CLK- pins of the DAC chip through differential traces, ensuring precise synchronization of the sampling time. This buffer circuit also features programmable phase adjustment, which can be used to fine-tune timing delays and optimize the overall system timing performance.

[0082] In terms of power management, the AD9747BCPZ employs a multi-power supply architecture, including VDDA (analog power), VDDIO (digital I / O power), and AVSS / GND. All power pins are equipped with decoupling capacitors (such as a 10nF + 100nF combination) and are placed close to the chip on the PCB layout to minimize power loop area and reduce electromagnetic interference. Furthermore, analog ground and digital ground are connected at a single point on the PCB edge to avoid ground loops and ensure a low-noise environment for the signal links.

[0083] It is worth noting that, Figure 6The diagram also shows several side protection circuits: for example, pull-up / pull-down resistors are provided at the DAC input to prevent noise from being introduced by floating pins; TVS diodes (such as 1.5kV bidirectional transient suppression diodes) are added at the output to absorb overvoltage spikes and protect the subsequent op-amp from electrostatic discharge or surge impacts; and a precision voltage regulator (such as AD584) and filter capacitor are configured at the reference voltage input (REFIN) to ensure long-term stability and low drift characteristics of the reference voltage.

[0084] In summary, Figure 6 The DAC digital-to-analog converter module 3 shown not only integrates the high-performance AD9747BCPZ DAC chip, but also constructs a high-precision, high-stability, and highly interference-resistant signal conversion platform through carefully designed termination matching, decoupling filtering, clock buffering, and multiple protection circuits. This module successfully achieves high-quality conversion from digitally isolated signals to ±5V analog fundamental frequencies and provides a reliable basic signal source for subsequent multi-mode analog conversions, fully demonstrating the technical advantages of this embodiment in terms of "shielded interference resistance" and "high-fidelity output."

[0085] In one embodiment, please refer to Figures 7 to 10 The aforementioned analog signal conversion and amplification unit 4 includes a low-voltage amplification module, a high-voltage amplification module, a low-voltage constant current module, and a high-voltage constant current module; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are connected in parallel; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are respectively connected to the DAC digital-to-analog conversion module 3; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are respectively connected to the output logic switching module 5.

[0086] The aforementioned low-voltage amplification module, high-voltage amplification module, low-voltage constant current module, and high-voltage constant current module are connected to the output logic switching module 5 via shielded cables.

[0087] In this embodiment, please refer to Figures 7 to 10 The aforementioned analog signal conversion and amplification unit 4 consists of four parallel sub-circuits: a low-voltage amplification module, a high-voltage amplification module, a low-voltage constant current module, and a high-voltage constant current module. These four sub-units all receive the ±5V basic analog signal output from the DAC digital-to-analog converter module 3 and convert it into stimulation signals of different voltage or current levels according to a set mode. Finally, these signals are uniformly connected to the output logic switching module 5 via shielded cables, enabling flexible switching between multiple modes of electrical stimulation.

[0088] In terms of circuit structure, the four sub-units operate independently in parallel, sharing the same input source—the output of the AD9747BCPZDAC. This design ensures electrical isolation between channels, avoiding mutual interference, while supporting arbitrary output combinations (such as simultaneously enabling low voltage and high current). Each sub-unit employs an independent power supply and grounding strategy, with its power supplied by the module (±24V) and an isolated high-voltage module (±110V). Furthermore, the PCB layout implements zoned routing and single-point grounding, effectively suppressing ground loop noise.

[0089] The low-voltage amplifier module uses an OPA189IDBVR rail-to-rail operational amplifier to form a non-inverting amplifier circuit. Its feedback resistor R_f = 10kΩ and input resistor R_in = 5kΩ, resulting in a gain of 3, which can amplify a ±5V input signal to a ±15V output. The circuit includes an input RC filter network (such as C1 and R1) to suppress common-mode noise; the output is equipped with a buffer operational amplifier (such as OPA847) and a decoupling capacitor (such as C2) to enhance drive capability and stabilize output impedance. Furthermore, the module also includes overvoltage protection diodes (such as D1 and D2) and current-limiting resistors to prevent damage from abnormal voltage surges.

[0090] The high-voltage amplification module, based on the ADHV4702-1 high-voltage operational amplifier, features high voltage withstand capability and low offset characteristics, making it suitable for high-voltage stimulation scenarios. Its input is connected to the DAC output, and a 20x gain is achieved through a precision resistor network. Combined with ±110V isolated high-voltage sources (low-voltage isolated power supply module and high-voltage isolated power supply module 11), it achieves ±100V output with a maximum output current of 100mA. The circuit includes input protection diodes, output clamping circuitry, and an LC filter network to suppress transient spikes and electromagnetic interference. TVS diodes and current-limiting resistors are integrated into the power path to provide overvoltage and overcurrent protection, ensuring safe operation of the system even under extreme conditions.

[0091] The low-voltage constant current module is based on the OPA189 to build a Howland constant current source circuit. It achieves constant current output with an accuracy of 0.1% through a precision feedback network, an output impedance ≥1MΩ, and an amplitude clamped within ±15V. Its core is a quad op-amp structure, utilizing differential input and negative feedback mechanisms to maintain a constant output current, unaffected by load changes. The circuit includes a current sampling resistor (such as R_sense) and a matching filter capacitor for real-time monitoring of the current status. Simultaneously, the power supply section incorporates voltage regulation and filtering structures to ensure stable power supply and prevent current drift caused by voltage fluctuations.

[0092] The high-voltage constant current module uses the ADHV4702-1 to construct a high-voltage Howland constant current source, outputting a ±10mA constant current signal with an output impedance ≥10MΩ and amplitude clamped within ±100V, suitable for deep stimulation in high-impedance environments. The circuit combines a high-voltage operational amplifier and a precision resistor network to achieve high linearity and low-noise constant current output. Side circuitry includes an output current sampling and feedback loop, overcurrent protection switches (such as MOSFETs), high-voltage isolation capacitors, and TVS devices to ensure safe operation under extreme conditions. Multi-stage filtering and voltage regulation are implemented in the power supply path to prevent high-voltage fluctuations from affecting the constant current accuracy.

[0093] The outputs of all four sub-units are connected to the output logic switching module 5 (module 5) via double-shielded coaxial cables. These cables have an inner signal conductor, an outer metal shield, and an outermost insulating sheath, effectively suppressing external electromagnetic interference. The shield is grounded at a single point (usually near the output) to avoid ground loops and reduce common-mode noise. Furthermore, a terminating resistor (e.g., 50Ω) is provided at the end of the output bus to prevent signal reflection from causing waveform distortion.

[0094] In summary, Figures 7 to 10 The analog signal conversion and amplification unit 4 shown not only realizes multi-mode, high-precision signal conversion, but also significantly improves the stability, safety and anti-interference capability of the system through rich side circuits (including filtering, protection, feedback and voltage regulation, etc.), providing a high-quality and reliable excitation signal for the output of the subsequent electrode 6.

[0095] In one embodiment, please refer to Figure 11 The aforementioned output logic switching module 5 includes a multi-channel relay array module and a relay status feedback loop. The multi-channel relay array module includes several relays. The relays are connected to the relay status feedback loop. The relay status feedback loop is connected to the host computer touch module 7. The relays are connected to the electrode 6.

[0096] In this embodiment, please refer to Figure 11 The aforementioned output logic switching module 5 is a high-performance, high-reliability multi-channel relay array system. Its core consists of a TQ2-5V miniature electromagnetic relay, which, in conjunction with the NX3008NBK driver chip, enables precise switching and combination control of four analog signals. As a key interface connecting the analog signal conversion and amplification unit 4 and the output of electrode 6, this module features fast response, low on-resistance, and flexible configuration. It supports arbitrary mode combination outputs and can simultaneously activate low-voltage and high-voltage currents to meet complex neural modulation requirements.

[0097] In terms of circuit structure, this module contains four independent relay channels, corresponding to four output signals from the analog signal conversion and amplification unit 4: low-voltage amplification, high-voltage amplification, low-voltage constant current, and high-voltage constant current. Each channel uses a TQ2-5V relay, whose normally open contact (NO) is connected to the corresponding signal source, and the common terminal (COM) is uniformly connected to a single bus, ultimately transmitting the signal to electrode 6 via a double-shielded coaxial cable. This "multi-input, single-output" architecture enables flexible switching from multiple analog sources to a single stimulation output, while ensuring electrical isolation between channels to avoid mutual interference.

[0098] The relay drive control is handled by the NX3008NBK chip. The control signal generated by the FPGA waveform generator 1 is processed by a digital isolator (such as π160E30) and then sent to the input port of the NX3008NBK. This chip converts the logic level into current pulses sufficient to drive the relay coil. As shown in the diagram, a reverse diode (such as 1N4007) is connected in parallel across each relay coil to absorb the reverse electromotive force generated when the coil is de-energized, preventing voltage spikes from damaging the driver chip or FPGA. Furthermore, current-limiting resistors (such as R101 to R104) are connected in series in the coil power supply path to limit the starting current and extend the relay lifespan. Some designs also incorporate an RC buffer network (such as C101+R105) to further suppress transient noise.

[0099] To enhance system security and monitorability, this module integrates a relay status feedback loop. The contact status of each relay can be fed back to the FPGA or the host computer touch module 7 in real time via an optocoupler or voltage divider sampling circuit. For example, when a relay is closed, the detection resistor in the feedback loop generates a voltage change, which is read by a comparator or ADC and uploaded to the host computer, achieving closed-loop monitoring. This allows users to intuitively view whether the current output mode is being executed correctly on the interface, improving operational transparency and system reliability.

[0100] In terms of power supply, the relay coil is powered by a 3.3V or 5V DC power supply. A decoupling capacitor (such as a 0.1μF ceramic capacitor) is provided next to its power supply pin to stabilize the power supply voltage and prevent power fluctuations caused by switching operations from affecting other circuits. At the same time, all relays share a common ground (COM), and a partitioned routing and single-point grounding strategy is adopted in the PCB layout to ensure that the ground loop resistance is less than 5mΩ, thereby reducing common-mode interference.

[0101] The output signal transmission uses a double-shielded coaxial cable. The inner layer is the signal conductor, the outer layer is a metal shield, and the outermost layer is an insulating sheath, effectively suppressing external electromagnetic interference. The shield is grounded at a single point (usually near the output end) to avoid ground loops. In addition, a terminating matching resistor (e.g., 50Ω) is provided at the end of the output bus to prevent signal reflection from causing waveform distortion.

[0102] In summary, Figure 11 The output logic switching module 5 shown not only realizes multi-mode, high-precision signal switching, but also significantly improves the stability, safety and anti-interference capability of the system through rich side circuits (including reverse diodes, current limiting resistors, decoupling capacitors, status feedback and shielding processing, etc.), providing high-quality and reliable excitation signals for the subsequent electrode 6 output.

[0103] In this embodiment, the operator sets the dual-channel sine wave frequencies to 1000Hz and 1001Hz via the host computer touch module 7, and selects the output mode as a ±15V voltage source. These parameters are sent to FPGA1, which generates a 16-bit precision digital waveform and simultaneously generates a differential clock signal to be transmitted to digital isolation module 2. In digital isolation module 2, advanced electrical isolation technology is used to prevent external interference from affecting system stability, ensuring that the digital signal remains pure and uncontaminated during the conversion process. Next, the isolated digital signal enters DAC digital-to-analog converter module 3, where it is converted into a ±5V analog waveform. Subsequently, this analog signal is input in parallel to one of the four sub-units in module 4—the low-voltage amplifier unit, which is responsible for amplifying the signal to the required ±15V voltage level.

[0104] The output logic switching module 5 can switch different channels to select the appropriate output path according to control commands. In this case, the output logic switching module 5 is configured to only allow the low-voltage amplification channel to be turned on, which means that the ±15V voltage waveform generated by the analog signal conversion and amplification unit 4 will be directly transmitted to the electrode 6 through the shielded coaxial cable. This design not only ensures the quality of signal transmission, but also takes advantage of the shielded cable to minimize the influence of external electromagnetic interference. When the stimulation electrode 6 is placed on the surface of the cerebral cortex, it generates a high-frequency magnetic field, where the difference between two frequencies (i.e., 1Hz) can penetrate deep tissues and induce specific biological effects in the target area.

[0105] Further analysis Figure 2The numerical simulation results show that two pairs of electrodes 6 are arranged at opposite ends of a sphere, 2 cm apart. Each pair of electrodes 6 receives ±15V voltage from the system at frequencies of 1kHz and 1kHz+1Hz, respectively. The model material parameters include a conductivity of 0.4 S / m and a relative permittivity of 80 for brain tissue, while the air domain imparts lower conductivity and relative permittivity. Transient solutions were performed using COMSOL Multiphysics software, recording the changes in the conduction current density vector field over time. The simulation results show that the two high-frequency fields superimpose between electrodes 6 to form closed streamlines. Particularly near the intersection point, the difference frequency component is significantly enhanced due to the close frequency, indicating that the low-frequency magnetic field can concentrate in a specific region, thereby achieving efficient neuromodulation.

[0106] In addition, Figure 3 The diagram illustrates the change in magnetic flux density over time at various points on the same spherical surface under the excitation of two pairs of electrodes 6. Of particular note is the maximum 1Hz envelope amplitude at the center point, due to the most stable phase difference of the high-frequency electric field at this location, resulting in optimal superposition of the difference-frequency components. As the distance from the center point gradually increases, the 1Hz envelope gradually attenuates, while the original 1kHz and 1kHz+1Hz frequency components exhibit a cone-shaped enhancement trend. This is because brain tissue exhibits significant attenuation characteristics for frequencies above 10Hz, similar to a low-pass filter. Therefore, although high-frequency components are enhanced further away from electrodes 6, these high-frequency signals cannot effectively activate nerve cells due to the frequency response limitations of the tissue; only the low-frequency difference-frequency envelope located in the central region can effectively participate in the neural modulation process. This phenomenon confirms the core hypothesis of this invention: by using dual-channel high-frequency voltage to create a strong difference-frequency envelope on the cortical surface and leveraging the low-pass characteristics of brain tissue, spatially concentrated deep localization stimulation can be achieved in the target area, thereby effectively modulating neural activity. This provides a solid theoretical foundation and technical support for the "using difference-frequency to generate a low-frequency magnetic field and achieving deep localization stimulation through the low-pass characteristics of tissue" in this embodiment.

[0107] In one embodiment, a smart collaborative control method for a multi-channel electrical stimulation circuit with shielded anti-interference features is also provided, implemented based on the above-described hardware architecture, including: By deploying a multi-dimensional environmental sensing network at the electrode 6 interface, operational data and basic environmental parameters from multiple functional modules in the multi-channel electrostimulation circuit are acquired. These multiple functional modules include a low-voltage amplification module, a high-voltage amplification module, a low-voltage constant current module, a high-voltage constant current module, and a relay array in the output logic switching module 5. The operational data includes the output voltage / current feedback of each amplification module, the relay contact status, and the contact impedance of electrode 6. The basic environmental parameters include the electromyographic feedback signal of the target site, skin temperature, and the intensity of the ambient electromagnetic field. The operational data and basic environmental parameters are fused and analyzed in real time to identify any abnormal signals. These abnormal signals include safety anomaly signals, physiological response trigger signals, or fault alarm signals issued by any functional module. The real-time fusion processing employs a spatiotemporal alignment algorithm to perform timestamp alignment and interpolation resampling on heterogeneous frequency data from different sensor sources, generating a multi-source fusion dataset with a unified time reference. The state analysis includes multi-scale feature extraction from the fusion dataset to obtain first feature data corresponding to the electrical stimulation safety state, second feature data corresponding to the physiological response training, and third feature data corresponding to the equipment operating state. When any type of abnormal signal is detected, the host computer touch module 7 generates a corresponding linkage control instruction based on the type of the abnormal signal using a logic control algorithm, and converts the linkage control instruction into a timing control signal through the FPGA waveform generator 1. The linkage control instruction includes a multi-channel collaborative stimulation instruction set, a physiological response adaptive instruction set, or a fault isolation protection instruction set. The multi-channel collaborative stimulation instruction set, physiological response adaptive instruction set, or fault isolation protection instruction set are sent to the corresponding external rehabilitation system after being isolated by the digital isolation module 2 through the cross-system joint control mechanism. The external rehabilitation system includes a rehabilitation assessment system, a vital signs monitoring system, an exercise training system, and an emergency braking system. The system receives feedback signals from the corresponding external rehabilitation system and dynamically adjusts the waveform generation parameters in the FPGA waveform generator 1 and the channel selection strategy of the output logic switching module 5 according to the feedback signals to realize a closed-loop intelligent control system. The waveform generation parameters include the step frequency of the 32-bit phase accumulator, the amplitude coefficient of the 16-bit lookup table, and the output mode of the dual-channel DAC chip.

[0108] The real-time fusion and status analysis of operational data and basic environmental parameters includes: The operating data and basic environmental parameters are input into the multimodal fusion engine in the upper computer touch module 7 for spatiotemporal alignment processing: First, the data streams of each sensor are timestamped, including interpolation and resampling of electromyographic signals and voltage feedback signals sampled at different frequencies to achieve a unified time reference; then, spatial coordinate transformation is performed to map the local coordinate systems of different sensors to a unified electrode 6 array coordinate system. Based on the preset source fusion rules, the spatiotemporally aligned data is subjected to feature-level fusion processing to generate a multi-source fusion dataset. Each data unit in the multi-source fusion dataset contains a fusion representation of the electrical stimulation operation feature vector, the physiological interaction feature vector, and the environmental interference feature vector. The multi-source fusion dataset is analyzed using a pre-defined behavioral analysis network: the multi-scale convolutional structure of the feature extraction layer is used to extract electrical stimulation operation features, the environmental interaction feature extraction branch is used to analyze the correlation between electromyographic feedback and stimulation output, and the behavioral continuity feature extraction branch is used to extract temporal stimulation patterns through a recurrent neural network. When the first feature data exceeds the preset safe voltage / current range, a safety abnormality signal is determined to exist; when the second feature data meets the preset physiological response training conditions, a physiological response trigger signal is determined to exist; when the third feature data exceeds the preset equipment fault threshold, a fault alarm signal is determined to exist.

[0109] In one embodiment, the host computer touch module 7 generates a linkage control command based on the type of the abnormal signal, including: When a safety anomaly signal is detected, a multi-channel coordinated stimulation instruction set is generated. The multi-channel coordinated stimulation instruction set includes: sending an emergency frequency reduction instruction to the 32-bit phase accumulator through the FPGA waveform generator 1 to achieve output return to zero, sending an adjacent channel gradient attenuation instruction to the output logic switching module 5, and sending an amplitude register clearing instruction to the dual-channel DAC chip. When a physiological response trigger signal is detected, a physiological response adaptive instruction set is generated. The physiological response adaptive instruction set includes: a positive frequency modulation instruction based on electromyographic feedback signal, an intermittent stimulation mode switching instruction based on skin temperature changes, and a voltage / current mode switching instruction based on contact impedance adaptation. When a fault alarm signal is detected, a fault isolation protection instruction set is generated. The fault isolation protection instruction set includes: sending a fault channel locking instruction to the relay array in the output logic switching module 5, sending a communication isolation instruction for the corresponding channel to the multi-channel π160E30 digital isolator, and sending a backup channel activation instruction to the analog signal conversion and amplification unit 4.

[0110] Among these, the dynamic adjustment of the collaborative control strategy based on feedback signals from the external rehabilitation system includes: It receives training phase feedback signals from the rehabilitation assessment system, physiological threshold exceedance signals from the vital signs monitoring system, posture deviation signals from the exercise training system, and trigger signals from the emergency braking system. Analyze the state parameters in each feedback signal to obtain the current rehabilitation training completion rate, physiological safety margin, and motor coordination indicators; Based on the training completion rate, physiological safety margin, and motor coordination indicators, they are compared one by one with the preset rehabilitation target threshold, safety boundary threshold, and expected motor accuracy threshold. Based on the degree of difference in the comparison results, identify whether there is a deviation in the execution of stimulus parameters or an abnormal system response; When the identification result is a deviation in the execution of the stimulus parameters, the host computer touch module 7 analyzes the duration and magnitude of the deviation and generates corresponding strategy adjustment parameters, including adjusting the frequency step value of the 32-bit phase accumulator and adjusting the amplitude mapping curve of the 16-bit lookup table. When the identification result is that the system response is abnormal, the communication status and device status of the abnormal function module are detected by the deep learning fault diagnosis model embedded in the host computer touch module 7. The detection includes feature extraction of the communication message sequence between FPGA waveform generator 1 and digital isolation module 2 through the communication status analysis branch, and feature extraction of the operation log of low voltage / high voltage amplification module through the device status analysis branch. Based on the test results, alternative control paths are generated, including switching to a backup amplification module, enabling redundant relay channels, or activating a safety degradation mode.

[0111] In one embodiment, updating the cooperative control strategy based on strategy adjustment parameters or alternative control paths includes: The strategy adjustment parameters or alternative control paths are mapped to the state space vector of the reinforcement learning decision model. The state space vector is evaluated to obtain the corresponding system response time score, stimulus energy utilization efficiency score, and physiological response matching score. Based on the system response time score, stimulus energy utilization efficiency score, and physiological response matching score, the optimal control strategy is output through the decision network of the reinforcement learning decision model. The optimal control strategy is converted into FPGA configuration instructions to update the initial phase value of the 32-bit phase accumulator, update the output timing of the dual-channel DAC chip, and update the channel switching logic of the output logic switching module 5, thereby achieving closed-loop strategy optimization.

[0112] In one embodiment, the multi-dimensional environmental sensing network includes an impedance detection sensor, a temperature sensor, and an electromyography signal pickup electrode 6 deployed at the electrode 6 interface. The sensing network is connected to the multimodal data interface of the host computer touch module 7 via a shielded cable. The cross-system joint control mechanism is implemented through the communication interface of the host computer touch module 7. The communication interface includes an Ethernet interface, a USB interface, or a wireless communication module, which is used to establish data interaction with an external rehabilitation system. When the FPGA waveform generator 1 receives the linkage control command, it generates a normal stimulation waveform and a safety redundancy waveform through two internal direct digital frequency synthesizers, and realizes real-time adjustment of the waveform amplitude through dynamic updating of the amplitude register.

[0113] Therefore, without changing the original hardware architecture, by introducing multimodal data fusion, deep learning anomaly recognition, and reinforcement learning decision-making algorithms, the traditional open-loop multichannel electrical stimulation circuit is upgraded into a collaborative stimulation platform with closed-loop intelligent control capabilities of "perception-analysis-decision-execution-feedback". This achieves dynamic optimization of stimulation parameters and predictive diagnosis of faults, significantly improving the system's adaptability and intelligence level. Specifically, this solution utilizes the real-time reconfigurability of FPGA and the intelligent decision-making capabilities of the host computer. While maintaining the advantages of the original shielded and anti-interference hardware, it achieves accurate analysis of multi-source physiological signals through spatiotemporal alignment and feature-level fusion algorithms, enabling the electrical stimulation output to be dynamically adjusted in milliseconds based on physiological states such as electromyographic feedback and skin impedance.

[0114] This solution, through a cross-system joint control mechanism and a multi-dimensional physiological sensing network, achieves real-time collaboration between the electrical stimulation process and external systems such as rehabilitation assessment and vital sign monitoring. It not only significantly enhances the safety and accuracy of electrical stimulation (such as deep learning-based fault prediction, microsecond-level channel isolation, and backup path switching), but also empowers existing hardware through software algorithms. Without increasing hardware costs, it achieves the closed-loop adaptive adjustment and multi-system collaborative capabilities typically found only in high-end intelligent electrical stimulation devices. This ensures both the safety and reliability of clinical use and good engineering practicality and economy, providing a cost-effective technical path for the intelligent transformation of traditional electrical stimulation devices.

[0115] In the previous embodiment, the following was added: A multi-dimensional environmental sensing network, including an impedance detection sensor, a temperature sensor, and an electromyography signal pickup electrode 6 deployed at the electrode 6 interface, is connected to the host computer touch module 7 via a shielded cable to collect basic environmental parameters. A cross-system communication interface is integrated into the host computer touch module 7, which is used to establish communication connections with external rehabilitation assessment systems and vital sign monitoring systems to achieve cross-system joint control.

[0116] The aforementioned shielded, interference-resistant multichannel electrical stimulation circuit integrates a host computer touch module 7, an FPGA waveform generator 1, a digital isolation module 2, a DAC digital-to-analog converter 3, an analog signal conversion and amplification unit 4, and an output logic switching module 5, forming a system with a reasonable structure, strong anti-interference performance, and flexible output modes. Specifically, users can easily design complex waveforms and timing sequences through the host computer touch module 7. The FPGA waveform generator 1 is responsible for generating precise digital signals, which are then converted into stable analog signals and amplified after efficient digital isolation and high-precision DAC conversion. The output logic switching module 5 allows selection of appropriate stimulation modes according to experimental or clinical needs, ensuring the realization of advanced functions such as difference frequency stimulation. Throughout the process, digital isolation technology and shielding measures effectively prevent external electromagnetic interference, ensuring signal purity; while a comprehensive safety monitoring mechanism further enhances the system's reliability and safety, fully meeting the requirements for high precision, high safety, and ease of use.

[0117] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A shielded, interference-resistant multichannel electrical stimulation circuit, characterized in that, include: The system includes a host computer touch control module, an FPGA waveform generator, a digital isolation module, a DAC digital-to-analog converter module, an analog signal conversion and amplification unit, and an output logic switching module. The output logic switching module is connected to the electrodes; the host computer touch module is connected to the FPGA waveform generator; the FPGA waveform generator is connected to the digital isolation module; the digital isolation module is connected to the DAC digital-to-analog converter module; the DAC digital-to-analog converter module is connected to the analog signal conversion and amplification unit; the analog signal conversion and amplification unit is connected to the output logic switching module. The waveform and timing are designed by the host computer touch module, the FPGA waveform generator generates digital signals, which are processed by the digital isolation module and the DAC digital-to-analog converter module, and then converted into analog signals by the analog signal conversion and amplification unit and amplified. The output logic switching module selects the stimulation mode according to the settings and applies it to the target area through electrodes.

2. The shielded, interference-resistant multichannel electrical stimulation circuit according to claim 1, characterized in that, It also includes a first power module, a BUCK power supply, and a Boost power supply. The first power module is connected to the BUCK power supply and the Boost power supply respectively. The BUCK power supply and the Boost power supply provide power to the host computer touch module and the FPGA waveform generator.

3. The shielded, interference-resistant multichannel electrical stimulation circuit according to claim 1, characterized in that, It also includes a second power supply module, an isolated DC-DC power supply module, and an isolated high-voltage module. The second power supply module is connected to the isolated DC-DC power supply module and the isolated high-voltage module respectively. The power is processed by the isolated DC-DC power supply module and the isolated high-voltage module to supply power to the DAC digital-to-analog conversion module, the analog signal conversion and amplification unit, and the output logic switching module.

4. A shielded, interference-resistant multichannel electrical stimulation circuit according to claim 1, characterized in that, The FPGA waveform generator includes two direct digital frequency synthesizers; each direct digital frequency synthesizer includes a 32-bit phase accumulator, a 16-bit sine / square / triangle wave lookup table, and an amplitude register connected in sequence; the 32-bit phase accumulator is connected to the host computer touch module, and the amplitude register is connected to the digital isolation module.

5. A shielded, interference-resistant multichannel electrical stimulation circuit according to claim 1, characterized in that, The digital isolation module includes a multi-channel π160E30 digital isolator, which is connected to the FPGA waveform generator and the DAC digital-to-analog converter module respectively. The multi-channel π160E30 digital isolator performs path-by-path isolation processing on each digital signal output by the FPGA waveform generator, including differential clock signal, data signal and mode control signal.

6. A shielded, interference-resistant multichannel electrical stimulation circuit according to claim 1, characterized in that, The DAC digital-to-analog conversion module includes a dual-channel DAC chip, an output termination matching resistor, a decoupling capacitor, a filter network, and a clock buffer circuit. The dual-channel DAC chip includes an input terminal, an output terminal, and a clock input terminal. The output terminal of the dual-channel DAC chip is connected in parallel with the output termination matching resistor. The output terminal of the dual-channel DAC chip is connected to the analog signal conversion and amplification unit through the decoupling capacitor. The input terminal of the dual-channel DAC chip is connected to the digital isolation module.

7. A shielded, interference-resistant multichannel electrical stimulation circuit according to claim 6, characterized in that, The DAC digital-to-analog conversion module includes a clock buffer circuit, and the dual-channel DAC chip includes a clock input terminal; the clock input terminal of the dual-channel DAC chip is connected to the clock buffer circuit.

8. A shielded, interference-resistant multichannel electrical stimulation circuit according to claim 1, characterized in that, The analog signal conversion and amplification unit includes a low-voltage amplification module, a high-voltage amplification module, a low-voltage constant current module, and a high-voltage constant current module; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are connected in parallel; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are each connected to the DAC digital-to-analog conversion module; the low-voltage amplification module, the high-voltage amplification module, the low-voltage constant current module, and the high-voltage constant current module are each connected to the output logic switching module. The low-voltage amplification module, high-voltage amplification module, low-voltage constant current module, and high-voltage constant current module are respectively connected to the output logic switching module via shielded cables.

9. A shielded, interference-resistant multichannel electrical stimulation circuit according to claim 1, characterized in that, The output logic switching module includes a multi-channel relay array module and a relay status feedback loop. The multi-channel relay array module includes several relays. The relays are connected to the relay status feedback loop. The relay status feedback loop is connected to the host computer touch module. The relays are connected to the electrodes.

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