Reset device and system for control chassis

Abstract

This application provides a reset device and system for a control chassis. The control chassis includes multiple control boards. The control connection port of each reset device is connected to the reset pins of all control boards in the control chassis. The transceiver connection ports of each reset device are also connected, and the transceiver connection port of one of the reset devices is also connected to the control port of the main controller. The reset signal generated by the main controller is sent to each reset device through the control port of the main controller and the transceiver connection ports of each reset device. The reset signal is used to indicate the target control board to be reset. Each reset device parses the reset signal to determine whether to perform a reset operation. If so, the reset device generates a reset signal and sends it to the reset pin of the target control board through the control connection port to reset the target control board.

Description

Technical Field

[0001] This application relates to the field of automation control technology, and more specifically, to a reset device and system for a control chassis. Background Technology

[0002] With the rapid development of industrial automation technology, complex control systems are widely used in key fields such as power, rail transportation, and aerospace. These systems typically employ a distributed architecture, consisting of multiple control chassis, each containing multiple control boards with specific functions. PowerPC processors, due to their high performance and reliability, are often used as the core processing unit for these control boards.

[0003] During system operation, when a board experiences a software deadlock or hardware malfunction, a remote reset is required to restore functionality. Existing technologies include reset methods for single PowerPC processors, using specific hardware monitoring circuits and software control processes to perform the reset operation on an individual processor. However, in real-world applications with multiple control chassis, each containing multiple boards, these boards are interconnected via network switches or backplane buses, forming a complex hierarchical structure. Existing reset technologies cannot precisely locate a specific board within a specific chassis, and lack the technical means to selectively reset the target board while maintaining the normal operation of other boards. This limitation forces maintenance personnel to restart the entire subsystem or even the entire system, causing unnecessary service interruptions. Summary of the Invention

[0004] The purpose of this application is to provide a reset device and system for a control chassis, so as to solve the technical problem that the board cannot be accurately located for reset in the complex control system composed of the existing control chassis.

[0005] In a first aspect, the present invention provides a reset device for a control chassis, the control chassis including multiple control boards, and the control connection port of each reset device being connected to the reset pins of all control boards of a control chassis. Each reset device has a separate transmit / receive port, and one of the reset devices' transmit / receive ports is also connected to the main control unit's control port. The reset signal generated by the main controller is sent to each reset device through the control port of the main controller and the transceiver connection port of each reset device. The reset signal is used to indicate the target control board to be reset. Each reset device analyzes the reset signal to determine whether to perform a reset operation; If so, the reset device generates a reset signal and sends it to the reset pin of the target control board through the control connection port to reset the target control board.

[0006] In an optional embodiment, the reset device includes a reset board body, a receiving and transmitting module integrated on the reset board body, and a protocol processing module. The first transceiver connection port of the receiving and transmitting module is used to receive a reset signal and send it to the protocol processing module. The protocol processing module parses the reset signal to obtain the control chassis address and control board address from the reset signal; The protocol processing module determines whether the control chassis address is the control chassis address of the control chassis to which the current reset device is connected; If so, the protocol processing module generates a reset execution signal based on the control board address and sends it to the reset control module; The protocol processing module generates a reset signal and sends it through the control connection port to the reset pin corresponding to the control board address, so as to reset the target control board.

[0007] In an optional implementation, the receiving and transmitting module includes a first serial port connector, a second serial port connector, and a connection driving circuit. The first end of the first serial port connector is the first transceiver connection port, and the second end of the first serial port connector is connected to the first end of the connection driver circuit. The first end of the second serial port connector is the second transceiver connection port, and the second end of the second serial port connector is connected to the second end of the connection driver circuit. The third terminal of the drive circuit is connected to the protocol processing module.

[0008] In an optional implementation, the protocol processing module includes at least an FPGA, and the connection driving circuit includes a driver chip, resistors, and capacitors. Specifically, the A, B, Y, and Z pins of the driver chip are connected to pins 1, 2, 3, and 4 of the first serial port connector, and the A, B, Y, and Z pins of the driver chip are also connected to pins 1, 2, 3, and 4 of the second serial port connector. The first resistor is connected in parallel between pins A and B of the driver chip, and the second resistor is connected in parallel between pins Y and Z of the driver chip. The first end of the third resistor is connected to the TXD pin of the driver chip, and the second end of the third resistor is connected to the R18 pin of the FPGA. The first end of the fourth resistor is connected to the DE pin of the driver chip, and the second end of the fourth resistor is connected to the R17 pin of the FPGA. The first end of the fifth resistor is connected to the RXD pin of the driver chip, and the second end of the fifth resistor is connected to the U18 pin of the FPGA. The first end of the sixth resistor is connected to the RE pin of the driver chip, and the second end of the third resistor is connected to the T18 pin of the FPGA. The capacitor is connected in parallel between the VCC and GND1 pins of the driver chip.

[0009] In an optional embodiment, the reset device further includes a reset driver module integrated on the reset board body. The reset driver module includes at least a reset driver chip and a third serial port connector. Specifically, pin A of the reset driver chip is connected to a corresponding output pin of the FPGA to obtain the reset signal of the target control board. The B pin of the reset driver chip is connected to one end of multiple pins of the third serial port connector, and the other end of multiple pins of the third serial port connector is connected to the reset pin of the corresponding control board.

[0010] In an optional implementation, the main controller determines whether the target control board needs to be reset based on the operating status of each control board. If a reset is required, a corresponding reset signal is generated.

[0011] In an optional implementation, the first transceiver connection port of the receiving and transmitting module is used to receive a reset signal, which is parsed into parallel data and sent to the protocol processing module. The protocol processing module parses the parallel data based on a preset reset protocol to obtain the control chassis address and control board address in the reset signal.

[0012] Secondly, the present invention provides a control system, including a main controller, a corresponding control chassis, and a reset device as described in any of the foregoing embodiments.

[0013] In an optional implementation, the control chassis further includes a chassis body, and a reset bus connector is provided on the back panel of the chassis body. One end of the reset bus connector is connected to the reset pin of all control boards in the current control chassis via the reset bus, and the other end of the reset bus connector is plugged into the transceiver port of the reset device.

[0014] In an optional implementation, the protocol processing module of the reset device is also used to generate a reset status signal and feed it back to the main controller.

[0015] This application provides a reset device and system for a control chassis. The control chassis includes multiple control boards. The control connection port of each reset device is connected to the reset pins of all control boards in the control chassis. The transceiver connection ports of each reset device are also connected, with one of the reset devices' transceiver connection ports also connected to the control port of a main controller. A reset signal generated by the main controller is sent to each reset device via its control port and the transceiver connection ports of each reset device. The reset signal indicates the target control board to be reset. Each reset device analyzes the reset signal to determine whether to perform a reset operation. If so, the reset device generates a reset signal and sends it to the reset pin of the target control board via its control connection port to reset the target control board. This system allows for precise positioning and reset of any single board in a complex system consisting of multiple control chassis and multiple control boards. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the structure of a control system provided in an embodiment of this application; Figure 2 A circuit diagram of a receiving and transmitting module provided in an embodiment of this application; Figure 3 A circuit diagram of an FPGA chip for a protocol processing module provided in an embodiment of this application; Figure 4 A circuit diagram of a reset drive module provided in an embodiment of this application; Figure 5 This is a circuit diagram of a reset bus connector provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0019] Example 1 Figure 1 The control system provided in this application includes a main controller, a corresponding control chassis, and a reset device.

[0020] The control chassis includes multiple control boards. The control chassis also includes a chassis body. A reset bus connector is located on the back panel of the chassis body. One end of the reset bus connector is connected to the reset pins of all control boards in the current control chassis via a reset bus. The other end of the reset bus connector is pluggably connected to the transceiver port of the reset device.

[0021] Based on the operating status of each control board, the main controller determines whether the target control board needs to be reset. If a reset is required, a corresponding reset signal is generated.

[0022] The control connection port of each reset device is connected to the reset pin of all control boards in a control chassis. The transceiver connection port of each reset device is connected to the main control unit. The transceiver connection port of one of the reset devices is also connected to the control port of the main control unit.

[0023] The reset signal generated by the main controller is sent to each reset device through the control port of the main controller and the transceiver connection ports of each reset device. The reset signal is used to indicate the target control board to be reset. Each reset device parses the reset signal to determine whether to perform a reset operation. If so, the reset device generates a reset signal and sends it to the reset pin of the target control board through the control connection port to reset the target control board.

[0024] Specifically, the reset device includes a reset board body, a receiving and transmitting module integrated on the reset board body, and a protocol processing module. The first transceiver connection port of the receiving and transmitting module is used to receive a reset signal and send it to the protocol processing module. The protocol processing module parses the reset signal to obtain the control chassis address and control board address. The protocol processing module determines whether the control chassis address is the control chassis address of the control chassis to which the current reset device is connected. If so, the protocol processing module generates a reset execution signal based on the control board address and sends it to the reset control module. The protocol processing module generates a reset signal and sends it through the control connection port to the reset pin corresponding to the control board address to reset the target control board.

[0025] The receiving and transmitting module includes a first serial port connector, a second serial port connector, and a connection driving circuit. The first end of the first serial port connector is a first transceiver connection port, and the second end of the first serial port connector is connected to the first end of the connection driving circuit. The first end of the second serial port connector is a second transceiver connection port, and the second end of the second serial port connector is connected to the second end of the connection driving circuit. The third end of the connection driving circuit is connected to the protocol processing module.

[0026] The first transceiver connection port of the receiving and transmitting module is used to receive the reset signal, parse it into parallel data and send it to the protocol processing module; the protocol processing module parses the parallel data based on the preset reset protocol to obtain the control chassis address and control board address in the reset signal.

[0027] The protocol processing module includes at least an FPGA. The connection driving circuit includes a driver chip, resistors, and capacitors. The A, B, Y, and Z pins of the driver chip are connected to pins 1, 2, 3, and 4 of the first serial connector, and also to pins 1, 2, 3, and 4 of the second serial connector. A first resistor is connected in parallel between pins A and B of the driver chip, a second resistor is connected in parallel between pins Y and Z of the driver chip, the first end of the third resistor is connected to the TXD pin of the driver chip, and the second end of the third resistor is connected to the R18 pin of the FPGA, the first end of the fourth resistor is connected to the DE pin of the driver chip, and the second end of the fourth resistor is connected to the R17 pin of the FPGA, the first end of the fifth resistor is connected to the RXD pin of the driver chip, and the second end of the fifth resistor is connected to the U18 pin of the FPGA, the first end of the sixth resistor is connected to the RE pin of the driver chip, and the second end of the third resistor is connected to the T18 pin of the FPGA. A capacitor is connected in parallel between the VCC and GND1 pins of the driver chip.

[0028] The protocol processing module of the reset device is also used to generate a reset status signal and feed it back to the main controller.

[0029] In this embodiment, a reset bus is designed on the control chassis backplane. The reset signals of the reset boards are connected to the reset signals of each board slot within the control chassis via the reset board slots on the backplane. A board reset network is designed, allowing cascading of reset boards from multiple control chassis. By connecting the reset buses between control chassis, the reset target can be expanded to multiple control boards. A board reset protocol is also designed. Through protocol constraints, the main control computer can obtain accurate information in real time regarding whether each board needs to be reset and can send the reset signal to the entire reset network. Upon receiving the reset information, the reset board, through the reset protocol, can accurately identify the board to be reset and perform the board reset. This solution enables precise positioning and reset of any board in a complex system consisting of multiple control chassis and multiple control boards.

[0030] Example 2 The reset device also includes a reset driver module integrated on the main body of the reset board. The reset driver module includes at least a reset driver chip and a third serial port connector. The A pin of the reset driver chip is connected to an output pin of the FPGA to obtain the reset signal of the target control board. The B pin of the reset driver chip is connected to one end of multiple pins of the third serial port connector. The other end of multiple pins of the third serial port connector is connected to the reset pin of the corresponding control board.

[0031] In this way, stable signal transmission can be guaranteed even when the reset signal needs to be transmitted over a long trace.

[0032] Example 3 In one specific embodiment, a method for remotely resetting a complex electronic control system containing multiple control chassis, each chassis having multiple control boards, is provided.

[0033] A reset board can be designed to generate 24 reset signal outputs. An FPGA chip is used as the main control chip of the board. Two RS422 interfaces are designed as input and output serial interfaces for reset signals, which are connected to external reset cables. The board is plugged into the back panel of the chassis through a custom interface. The back panel of the chassis is designed with a reset bus, so that the reset signal of the reset board can be connected to the reset signal of the board in each slot through the reset bus.

[0034] A reset network is formed. The reset signal is output from the serial port of the main control server and connected to the X1 interface of the reset board RSTB1 in the first chassis using a reset cable. The signal is then led out from the X2 interface of RSTB1 and connected to the X1 interface of the reset board RSTB2 in the second chassis. The signal is then led out from the X2 interface of RSTB2 and connected to the reset board in the third chassis. This process is repeated to form a reset network.

[0035] A reset signal protocol can also be configured. This protocol allows setting the control chassis and its control boards by writing to the reset register. The board reset register specifies the control chassis slot number, and the chassis address register specifies the chassis number that needs to be reset. The protocol also allows reading the status of the control chassis and its control boards by reading the reset register. Reading the board reset register status reveals which board in the chassis needs resetting, and reading the chassis address register status reveals the chassis number that needs resetting. Employing the RS422 serial communication bus protocol with differential signals, simultaneous bidirectional data transmission and reception are possible, improving reset response speed.

[0036] By configuring the I / O ports of the FPGA chip in the reset board, two RS422 interface circuits are designed as input and output interfaces for reset signals, as interfaces for communication with the host computer and as reset bus interfaces for cascading with the lower-level chassis. The reset interfaces are silkscreened as X1 and X2 respectively, and the connector type is DB9 connector.

[0037] By configuring the I / O ports of the FPGA chip in the reset board, 24 reset signals are designed and connected to the reset bus on the backplane through a custom bus interface.

[0038] Specifically, such as Figure 2 As shown, the receiving and transmitting module consists of a signal input circuit 1, an interface driver circuit 2, an impedance matching circuit 3, and an interface circuit 4. The interface circuit 4 uses a DB9 connector and comprises a reset signal input interface X1 and a reset signal output interface X2. The impedance matching circuit 3 consists of resistors R57 and R79 for 120 Ω impedance matching. The interface driver circuit 2 consists of U9 resistors and uses an ADM2582 chip, with isolation between the input and output. The signal input circuit 1 consists of resistors R65, R73, R75, and R78 from the impedance matching and reflection suppression circuit 1, and also provides current limiting protection and EMI reduction.

[0039] Specifically, the ADM2582 chip can be used. Its features include a 2500Vrms isolation voltage, effectively blocking ground loop interference and improving system safety; a maximum data transmission rate of 16Mbps; suitability for RS422 communication; strong differential drive capability; up to 256 nodes can be connected to a single bus; and ±15KVHBM electrostatic discharge protection on the bus pins, maintaining a low bit error rate even in strong magnetic interference environments. It also integrates current limiting, short-circuit protection, and overheat shutdown functions to effectively prevent device damage.

[0040] like Figure 3 The diagram shows the FPGA chip circuit of the protocol processing module. The board signals requiring reset are distributed to the FPGA's I / O ports. Specifically: RESTB_FPGA_WarmResetn_UART_485_D and RESTB_FPGA_WarmResetn_UART_485_R are the FPGA-side reset output and input signals, respectively; RETB_X201_WarmResetn...RETB_X222_WarmResetn are the 22 allocated reset output signals. The reset signals can be expanded as needed, demonstrating good circuit expandability and strong compatibility.

[0041] like Figure 4The diagram shows the circuit schematic of the reset driver module. The main driver circuit uses an 8-bit dual-power bus transceiver, which provides tri-state output, high drive capability, and an output current of up to 24mA. It can drive long PCB traces and has good anti-interference capabilities, making it suitable for scenarios where the chassis has many boards, resulting in excessively long PCB traces for the backplane reset signal, ensuring stable signal transmission. In this circuit, by connecting the DIR pin to the power supply and the OE pin to GND, the data flow is locked from A to B.

[0042] The reset driver module here adopts a dual-power-rail design, with two completely independent power supplies, enabling bidirectional voltage level switching between input and output. The circuit uses a single direction pin (DIR) to switch the data flow direction. The output enable pin (OE) can simultaneously set ports A and B to a high-impedance state, facilitating multi-bus sharing. This circuit is characterized by its ability to output ±24mA current, directly drive bus loads, and provide good anti-interference capabilities. In this circuit, by connecting the DIR pin to the power supply and the OE pin to GND, the data flow is locked from A to B.

[0043] like Figure 5 The diagram shown is a circuit diagram of the reset bus connector. A 160-pin onboard bent-pin connector can be used to connect the reset signal to the backplane reset bus for resetting multiple boards in the control chassis.

[0044] In this embodiment, the reset boards in each chassis to be reset are connected by a reset line to form an RS422 serial reset network. This reset network is scalable, uses an RS422 bus, and performs remote reset operations on each chassis board through the chassis ID and reset bus protocol.

[0045] By acquiring data through the RS422 interface, the FPGA chip of the RETB reset board receives RS422 reset data from the host computer. This data is then parsed by the RS422 receive / transmit module, converted into parallel data, and transmitted to the protocol processing module. The protocol processing module parses the data to obtain commands such as reset control and status read. Finally, the reset control module executes the reset operation or reports the status, ensuring the accuracy of the reset.

[0046] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0047] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0048] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0049] It should be noted that if the function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several signals to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0050] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0051] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A reset device for a control chassis, the control chassis comprising multiple control boards, characterized in that, The control connection port of each reset device is connected to the reset pins of all control boards in a control chassis. Each reset device has a separate transmit / receive port, and one of the reset devices' transmit / receive ports is also connected to the main control unit's control port. The reset signal generated by the main controller is sent to each reset device through the control port of the main controller and the transceiver connection port of each reset device. The reset signal is used to indicate the target control board to be reset. Each reset device analyzes the reset signal to determine whether to perform a reset operation; If so, the reset device generates a reset signal and sends it to the reset pin of the target control board through the control connection port to reset the target control board.

2. The reset device according to claim 1, characterized in that, The reset device includes a reset board body, a receiving and transmitting module integrated on the reset board body, and a protocol processing module. The first transceiver connection port of the receiving and transmitting module is used to receive a reset signal and send it to the protocol processing module. The protocol processing module parses the reset signal to obtain the control chassis address and control board address from the reset signal; The protocol processing module determines whether the control chassis address is the control chassis address of the control chassis to which the current reset device is connected; If so, the protocol processing module generates a reset execution signal based on the control board address and sends it to the reset control module; The protocol processing module generates a reset signal and sends it through the control connection port to the reset pin corresponding to the control board address, so as to reset the target control board.

3. The reset device according to claim 2, characterized in that, The receiving and transmitting module includes a first serial port connector, a second serial port connector, and a connection driver circuit. The first end of the first serial port connector is the first transceiver connection port, and the second end of the first serial port connector is connected to the first end of the connection driver circuit. The first end of the second serial port connector is the second transceiver connection port, and the second end of the second serial port connector is connected to the second end of the connection driver circuit. The third terminal of the drive circuit is connected to the protocol processing module.

4. The reset device according to claim 3, characterized in that, The protocol processing module includes at least an FPGA, and the connection driving circuit includes a driver chip, resistors, and capacitors. Specifically, the A, B, Y, and Z pins of the driver chip are connected to pins 1, 2, 3, and 4 of the first serial port connector, and the A, B, Y, and Z pins of the driver chip are also connected to pins 1, 2, 3, and 4 of the second serial port connector. The first resistor is connected in parallel between pins A and B of the driver chip, and the second resistor is connected in parallel between pins Y and Z of the driver chip. The first end of the third resistor is connected to the TXD pin of the driver chip, and the second end of the third resistor is connected to the R18 pin of the FPGA. The first end of the fourth resistor is connected to the DE pin of the driver chip, and the second end of the fourth resistor is connected to the R17 pin of the FPGA. The first end of the fifth resistor is connected to the RXD pin of the driver chip, and the second end of the fifth resistor is connected to the U18 pin of the FPGA. The first end of the sixth resistor is connected to the RE pin of the driver chip, and the second end of the third resistor is connected to the T18 pin of the FPGA. The capacitor is connected in parallel between the VCC and GND1 pins of the driver chip.

5. The reset device according to claim 4, characterized in that, The reset device also includes a reset driver module integrated on the main body of the reset board. The reset driver module includes at least a reset driver chip and a third serial port connector. Specifically, pin A of the reset driver chip is connected to a corresponding output pin of the FPGA to obtain the reset signal of the target control board. The B pin of the reset driver chip is connected to one end of multiple pins of the third serial port connector, and the other end of multiple pins of the third serial port connector is connected to the reset pin of the corresponding control board.

6. The reset device according to claim 5, characterized in that, Based on the operating status of each control board, the main controller determines whether the target control board needs to be reset. If a reset is required, a corresponding reset signal is generated.

7. The reset device according to claim 2, characterized in that, The first transceiver connection port of the receiving and transmitting module is used to receive the reset signal, which is parsed into parallel data and sent to the protocol processing module. The protocol processing module parses the parallel data based on a preset reset protocol to obtain the control chassis address and control board address in the reset signal.

8. A control system, characterized in that, It includes a main control unit, a corresponding control chassis, and a reset device as described in any one of claims 1-7.

9. The control system according to claim 8, characterized in that, The control chassis also includes a chassis body, and a reset bus connector is located on the back panel of the chassis body. One end of the reset bus connector is connected to the reset pin of all control boards in the current control chassis via the reset bus, and the other end of the reset bus connector is plugged into the transceiver port of the reset device.

10. The control system according to claim 8, characterized in that, The protocol processing module of the reset device is also used to generate a reset status signal and feed it back to the main controller.

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