Drive systems and drive circuits used for calibration and synchronization in touch sensing

Abstract

This invention discloses a driving system and its driving circuit. The driving system includes multiple driving circuits connected in series, wherein each driving circuit is connected to one or two adjacent driving circuits through a master control terminal and a slave terminal. The multiple driving circuits include a first driving circuit and a second driving circuit. The first driving circuit is used to output a first synchronization signal through the master control terminal. The second driving circuit is used to output a second synchronization signal through the slave terminal when it receives the first synchronization signal through the master control terminal. A corresponding compensation time for the second driving circuit is calculated based on an output time point of the first synchronization signal and a reception time point of the second synchronization signal.

Description

Technical Field

[0001] This invention relates to a driving system and its driving circuit, and more particularly to a driving system having multiple driving circuits for jointly driving a display screen. Background Technology

[0002] Touchscreens, as data communication interfaces, are widely used in various electronic products today, such as mobile phones, satellite navigation systems, monitors, and laptops. Touchscreens are user-friendly input devices that, in addition to meeting the requirements of multi-level menu designs, also offer the functions of a keyboard, mouse, and handwriting input, providing convenient operation methods. Their ability to integrate input and output functions into a single interface (such as a screen) is a feature unmatched by other traditional input devices.

[0003] As touchscreen sizes and resolutions increase, touchscreens typically require multiple driving circuits (such as driver integrated circuits, or driver ICs) to operate. Each driver circuit controls touch sensing and display operations in a corresponding area of ​​the touchscreen. During touch sensing, the driver circuit outputs a touch drive signal to the corresponding area; this signal is usually a sine wave. If the touch drive signals from two driver circuits are not synchronized, the received sensing signal may not be properly demodulated. Summary of the Invention

[0004] Therefore, the main objective of this invention is to provide a driving system and driving circuit that can be used to control a display screen, wherein each driving circuit can be calibrated and synchronized to achieve synchronized touch sensing operation.

[0005] An embodiment of the present invention discloses a driving system comprising multiple driving circuits connected in series, wherein each driving circuit is connected to one or two adjacent driving circuits via a master control terminal and a slave terminal. The multiple driving circuits include a first driving circuit and a second driving circuit. The first driving circuit is used to output a first synchronization signal through the master control terminal. The second driving circuit is used to output a second synchronization signal through the slave terminal when receiving the first synchronization signal through the master control terminal. A corresponding compensation time for the second driving circuit is calculated based on an output time point of the first synchronization signal and a reception time point of the second synchronization signal.

[0006] Another embodiment of the present invention discloses a driving system comprising a plurality of driving circuits connected in series, wherein each driving circuit is connected to one or two adjacent driving circuits via a master control terminal and a slave terminal. The plurality of driving circuits includes a plurality of slave driving circuits and a master control driving circuit. Each of the plurality of slave driving circuits is used to output a notification. The master control driving circuit is used to receive the notification from the plurality of slave driving circuits; after receiving the notification from the plurality of slave driving circuits, output an acknowledgment signal via the master control terminal; and after outputting the acknowledgment signal, initiate a sensing operation with a delay having a compensation time for the master control driving circuit. The plurality of slave driving circuits also receive the acknowledgment signal via the master control terminal, and after receiving the acknowledgment signal, initiate the sensing operation with a delay having a compensation time for each of the individual slave driving circuits.

[0007] Another embodiment of the present invention discloses a first driving circuit connected in series with a plurality of driving circuits. The first driving circuit is connected to one or two adjacent driving circuits among the plurality of driving circuits via a master control terminal and a slave terminal. The first driving circuit is used to output a first synchronization signal via the master control terminal; receive a second synchronization signal via the slave terminal, wherein the second synchronization signal is output by a second driving circuit among the plurality of driving circuits upon receiving the first synchronization signal; and calculate a corresponding compensation time for the second driving circuit based on an output time point of the first synchronization signal and a reception time point of the second synchronization signal.

[0008] Another embodiment of the present invention discloses a master control driving circuit connected in series with a plurality of slave driving circuits. The master control driving circuit is connected to one or two adjacent slave driving circuits via a master control terminal and a slave terminal. The master control driving circuit is used to receive a notification from the plurality of slave driving circuits; after receiving the notification from the plurality of slave driving circuits, it outputs an acknowledgment signal through the master control terminal; and after outputting the acknowledgment signal, it initiates a sensing operation with a delay having a compensation time for the master control driving circuit.

[0009] Another embodiment of the present invention discloses a slave drive circuit located among a plurality of drive circuits connected in series, wherein the slave drive circuit is connected to one or two adjacent drive circuits among the plurality of drive circuits via a master control terminal and a slave terminal. The slave drive circuit is used to output a notification; receive an acknowledgment signal from a master drive circuit among the plurality of drive circuits via the master control terminal, wherein the acknowledgment signal is generated in response to the notification; and, upon receiving the acknowledgment signal, initiate a sensing operation with a delay having a compensation time for the slave drive circuit. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the driving system according to Embodiment 1 of the present invention.

[0011] Figure 2A and Figure 2B An exemplary operation of the drive system in calibration mode is shown.

[0012] Figure 3 The diagram shows the main control circuit simultaneously outputting the first left synchronization signal and the first right synchronization signal.

[0013] Figure 4 This illustrates a path delay correction operation used in a driving system according to an embodiment of the present invention.

[0014] Figure 5 In order to be in Figure 4 The waveform of the synchronization signal at each endpoint under the delay time.

[0015] Figure 6 This is a schematic diagram of another driving system according to an embodiment of the present invention.

[0016] Figure 7 for Figure 6 The waveform diagram of the synchronization signal at each endpoint of the drive system.

[0017] Figure 8 This is a schematic diagram of another driving system according to an embodiment of the present invention.

[0018] Figure 9 for Figure 8 The waveform diagram of the synchronization signal at each endpoint of the drive system.

[0019] Figure 10 An exemplary operation of the drive system in synchronous mode is shown.

[0020] Figure 11 for Figure 1 The waveforms of touch sensing operations and related notification and confirmation signals at each endpoint of the drive system.

[0021] Figure 12 for Figure 6 The waveforms of touch sensing operations and related notification and confirmation signals at each endpoint of the drive system.

[0022] Figure 13 Another exemplary operation of the drive system in synchronous mode is shown.

[0023] Figure 14 This illustrates yet another exemplary operation of the drive system in synchronous mode, where the display ready signal is omitted.

[0024] Figure 15The waveforms of touch sensing operations and related notification and confirmation signals at each endpoint of the drive system are omitted to omit the display of the ready signal.

[0025] The reference numerals in the attached figures are explained as follows: Detailed Implementation

[0026] In a display driving system where the display is controlled by multiple driver integrated circuits (driver ICs), these driver ICs are required to be synchronized. For example, the display may be a touchscreen, and the driver ICs may be Touch and Display Driver Integration (TDDI) ICs, which need to be synchronized during touch sensing operations. Generally, driver ICs can be synchronized in various ways, such as through a timing controller, or one of these driver ICs can act as a master driver IC, providing synchronization signals to the other driver ICs via a command line.

[0027] Traditional synchronization schemes lack correction functionality, and due to inconsistent wire loads between different driver ICs, their operation cannot be well synchronized. For example, a driver IC closer to the timing controller or the master driver IC used to transmit the synchronization signal often has a smaller load, while a driver IC farther away from the timing controller or master driver IC often has a larger load. In this situation, the closer driver IC receives the synchronization signal earlier, while the farther driver IC receives it later. Therefore, these driver ICs cannot simultaneously initiate touch sensing operations using the synchronization signal.

[0028] U.S. Patent Application No. 18 / 225,156 discloses a driving system for a touchscreen, in which the driving integrated circuits are connected via two transmission buses, and the driving integrated circuits can perform calibration operations through the transmission buses. The path delays of each driving integrated circuit, indicated by the calibration results, can be well synchronized, enabling these driving integrated circuits to initiate touch sensing operations simultaneously.

[0029] However, in the drive system described in U.S. Patent Application No. 18 / 225,156, all drive ICs are connected to two common transmission buses. This means that each transmission bus needs to be connected to a large number of drive ICs, resulting in a more complex wiring and layout on the circuit board. For example, the transmission buses require many crossovers in the circuit layout. Furthermore, the input / output states of each endpoint connected to the transmission bus will differ depending on the calibration target, and these endpoints need to switch to different states during calibration operations, inevitably generating leakage current during these state transitions.

[0030] Therefore, this invention proposes a novel structure for a display system in which the driving circuits can be connected in series with each other via two endpoints. More specifically, each driving circuit can be connected to one or two adjacent driving circuits via two endpoints (such as a master terminal and a slave terminal). If a driving circuit is located at the end of a series connection, it can be connected to an adjacent driving circuit via two endpoints (such as a master terminal and a slave terminal); if a driving circuit is connected between two adjacent driving circuits, it can be connected to one of the adjacent driving circuits via a first master terminal and a first slave terminal, and to the other adjacent driving circuit via a second master terminal and a second slave terminal. In this way, all driving circuits in the display system can be connected in series with each other.

[0031] Since each drive circuit is connected to only one or two adjacent drive circuits, cross-line requirements are simplified, thereby reducing the circuit cost of the layout. Furthermore, because the drive circuits of this invention are not connected via a shared bus, the input / output states of the connection endpoints do not need to be switched during calibration operations, reducing design complexity and avoiding leakage current issues that may occur during state switching.

[0032] Similarly, the cascaded drive circuits can operate together for calibration and synchronization to initiate touch sensing operations simultaneously. In one embodiment, the drive circuits are required to perform touch sensing in a synchronized timing sequence, therefore they need to operate in a synchronization mode to achieve synchronized touch sensing operations. Before executing the synchronization mode, the path delay between different drive circuits should be calibrated. It should be noted that due to differences in transmission distance, the transmission time of signals on the connection line may vary and is easily affected by various environmental factors, such as temperature, load, and / or noise interference. Therefore, before executing the synchronization mode, the drive circuits can operate in a calibration mode to determine the path delay between different drive circuits. The path delay information can be used to synchronize the timing of touch sensing in subsequent synchronization operations. The calibration mode can be executed at any time before the touch sensing operation. To adapt to environmental changes, the calibration mode can be executed periodically. In one embodiment, the calibration mode can be executed during the idle time of the drive system to avoid affecting other drive operations.

[0033] In some embodiments, a touch sensing operation represents an operation by a driving circuit to acquire touch data corresponding to a touch gesture applied to the touchscreen, which may be related to finger touch sensing or stylus sensing. As described above, multiple driving circuits in the driving system can jointly control the touch sensing operation. In an exemplary embodiment, a master driving circuit can output a touch driving signal, and the corresponding touch sensing signal can be received by a driving circuit used to control this corresponding area, which may be the master driving circuit or another slave driving circuit. Since the touch sensing signals of different areas are received by different driving circuits, the touch sensing signal processing between these driving circuits needs to be synchronized to achieve the desired sensing result.

[0034] Figure 1 This is a schematic diagram of a driving system 10 according to an embodiment of the present invention. The driving system 10 includes five driving circuits 102, 104, 106, 108, and 110 for jointly controlling a touchscreen (not shown). Among these driving circuits, driving circuit 102 is configured as a master driving circuit, and each of the other driving circuits 104, 106, 108, and 110 is configured as a slave driving circuit. Each driving circuit 102 to 110 is responsible for controlling a corresponding area on the touchscreen. Generally, in a driving system used to control a touchscreen, there may be one master driving circuit and the other driving circuits are slave driving circuits. In an exemplary embodiment, the driving circuit used to initiate the transmission of a confirmation signal for synchronization may be configured as the master driving circuit, and the other driving circuits are configured as slave driving circuits.

[0035] In embodiments of the present invention, each driving circuit may be an integrated circuit implemented on a chip. Hereinafter, the master driving circuit will be referred to simply as the master control circuit, and the slave driving circuit will be referred to simply as the slave circuit.

[0036] like Figure 1 As shown, drive circuits 102 to 110 are connected in series. The main control circuit 102 is located in the middle, with two slave circuits 104 and 106 connected to the left side of the main control circuit 102, and two slave circuits 108 and 110 connected to the right side of the main control circuit 102. It should be noted that the left and right sides defined here only represent different sides / directions of the series connection and are not used to restrict the position of the drive circuits.

[0037] Each drive circuit 102-110 is connected to the adjacent drive circuit through two terminals: a master control terminal and a slave terminal. Each terminal can be an input / output port of an integrated circuit. Specifically, slave circuit 104 is connected to slave circuit 106 through a master control terminal SL1_MR and a slave terminal SL1_SR. Slave circuit 106 is connected to slave circuit 104 through a master control terminal SL2_ML and a slave terminal SL2_SL, and to master circuit 102 through a master control terminal SL2_MR and a slave terminal SL2_SR. Master circuit 102 is connected to slave circuit 106 through a master control terminal M_ML and a slave terminal M_SL, and to slave circuit 108 through a master control terminal M_MR and a slave terminal M_SR. Slave circuit 108 is connected to master circuit 102 via a master control terminal SR2_ML and a slave terminal SR2_SL, and is connected to slave circuit 110 via a master control terminal SR2_MR and a slave terminal SR2_SR. Slave circuit 110 is connected to slave circuit 108 via a master control terminal SR1_ML and a slave terminal SR1_SL. By connecting the master control terminal and slave terminal between every two adjacent drive circuits, all drive circuits 102 to 110 included in drive system 10 can be connected in series with each other.

[0038] In this example, each drive circuit 102-110 may also be coupled to a command line for communication between these drive circuits 102-110. The command line can be implemented using any type of interface, such as a Serial Peripheral Interface (SPI). In another embodiment, the command line may be omitted. Each master control circuit 102 and slave circuits 104-110 may include a synchronization controller SCTL for performing calibration and synchronization operations on each drive circuit.

[0039] Through the connection method of the drive system 10, a closed loop can be formed between any two drive circuits via the connection lines between the master and slave terminals of these two drive circuits and any intermediate drive circuits (if any). For example, a closed loop can be formed between the master control circuit 102 and any slave circuit 104-110. Taking the master control circuit 102 and slave circuit 104 as an example, the closed loop can start from the master control terminal M_ML, pass through the master control terminals SL2_MR, SL2_ML, and SL1_MR and the slave terminals SL1_SR, SL2_SL, and SL2_SR, and reach the slave terminal M_SL. In this case, the path delay between any two drive circuits can be obtained.

[0040] Figure 2A and Figure 2B An exemplary operation of the drive system 10 in calibration mode is shown. Figure 2AThe diagram illustrates how the master control circuit 102 corrects the signal paths of the slave circuits 104 and 106 located on the left. In this example, the master control circuit 102 serves as the starting point for signal transmission, used to measure the corresponding path delays of the slave circuits 104 and 106 on the left. Specifically, the master control circuit 102 first outputs a first left synchronization signal SYNC1_L to the slave circuit 106 via the master control terminal M_ML, and simultaneously starts a timer. Next, the slave circuit 106 receives the first left synchronization signal SYNC1_L via the master control terminal SL2_MR, and transmits it to the slave circuit 104 via the master control terminal SL2_ML. Simultaneously, when the leftmost slave circuit 104 receives the first left synchronization signal SYNC1_L via the master control terminal SL1_MR, this slave circuit 104 outputs a second left synchronization signal SYNC2_L to the slave circuit 106 via the slave terminal SL1_SR. Next, slave circuit 106 receives the second left synchronization signal SYNC2_L through slave terminal SL2_SL, and transmits the second left synchronization signal SYNC2_L to master control circuit 102 through slave terminal SL2_SR. Master control circuit 102 can stop the timer when it receives the second left synchronization signal SYNC2_L.

[0041] In this way, the master control circuit 102 can obtain the path delay between the master control circuit 102 and the slave circuit 104 based on the timing result of the timer. It records the time difference between the output time of the first left synchronization signal SYNC1_L by the master control circuit 102 and the reception time of the second left synchronization signal SYNC2_L by the master control circuit 102. Then, based on the path delay, the master control circuit 102 can calculate and obtain the corresponding compensation time for the slave circuit 104.

[0042] In one embodiment, the path delay value can be divided by 2 to obtain the compensation time for the slave circuit 104, which is used to synchronize the sensing times of the master circuit 102 and the slave circuit 104 in synchronization mode. In one embodiment, the compensation time can also be further manually adjusted or fine-tuned to achieve optimal synchronization results.

[0043] The first left synchronization signal SYNC1_L and the second left synchronization signal SYNC2_L can also be used to correct the slave circuit 106. Specifically, when the slave circuit 106 receives the first left synchronization signal SYNC1_L from the master control circuit 102 via the master control terminal SL2_MR (or when the slave circuit 106 outputs the first left synchronization signal SYNC1_L via the master control terminal SL2_ML), it can start a timer. Subsequently, when the slave circuit 106 receives the second left synchronization signal SYNC2_L from the slave circuit 104 via the slave terminal SL2_SL (or when the slave circuit 106 outputs the second left synchronization signal SYNC2_L via the slave terminal SL2_SR), it can stop the timer. Therefore, the timer of the slave circuit 106 records the time difference between the time the slave circuit 106 receives the first left synchronization signal SYNC1_L and the time the slave circuit 106 receives the second left synchronization signal SYNC2_L, which is equivalent to the path delay between slave circuits 104 and 106.

[0044] Next, slave circuit 106 can send the recorded timer information to master circuit 102 (e.g., via a command line). Based on the information from slave circuit 106, master circuit 102 can obtain the path delay between slave circuits 104 and 106. Alternatively or additionally, slave circuit 106 can store the recorded timer information for its own use in subsequent synchronization modes.

[0045] In this way, by outputting a synchronization signal through the master control terminal M_ML on the left and receiving a synchronization signal through the slave terminal M_SL on the left, the master control circuit 102 can obtain the compensation time required by the slave circuits 104 and 106 connected to the left side of the master control circuit 102. The master control circuit 102 can calculate the compensation time for slave circuit 104 and / or the compensation time for slave circuit 106 based on the path delay information obtained in the correction mode.

[0046] Similarly, the drive system 10 can also execute another transmission scheme to correct the slave circuits 108 and 110 connected to the right side of the main control circuit 102, such as... Figure 2BAs shown. The master control circuit 102 can first output a first right synchronization signal SYNC1_R to the slave circuit 108 through the master control terminal M_MR, and simultaneously start a timer. Then, the slave circuit 108 receives the first right synchronization signal SYNC1_R through the master control terminal SR2_ML, and transmits the first right synchronization signal SYNC1_R to the slave circuit 110 through the master control terminal SR2_MR. When the rightmost slave circuit 110 receives the first right synchronization signal SYNC1_R through the master control terminal SR1_ML, this slave circuit 110 can output a second right synchronization signal SYNC2_R to the slave circuit 108 through the slave terminal SR1_SL. Then, the slave circuit 108 receives the second right synchronization signal SYNC2_R through the slave terminal SR2_SR, and transmits the second right synchronization signal SYNC2_R to the master control circuit 102 through the slave terminal SR2_SL. The master control circuit 102 can stop the timer when it receives the second right synchronization signal SYNC2_R.

[0047] In this way, the master control circuit 102 can obtain the path delay between the master control circuit 102 and the slave circuit 110 based on the timing result of the timer. It records the time difference between the output time of the first right synchronization signal SYNC1_R by the master control circuit 102 and the reception time of the second right synchronization signal SYNC2_R by the master control circuit 102. Then, based on the path delay, the master control circuit 102 can calculate and obtain the corresponding compensation time for the slave circuit 110.

[0048] In one embodiment, the path delay value can be divided by 2 to obtain the compensation time for slave circuit 110, which is used to synchronize the sensing times of master circuit 102 and slave circuit 110 in synchronization mode. In one embodiment, the compensation time can also be further manually adjusted or fine-tuned to achieve optimal synchronization results.

[0049] The first right synchronization signal SYNC1_R and the second right synchronization signal SYNC2_R can also be used to correct the slave circuit 108. Specifically, when the slave circuit 108 receives the first right synchronization signal SYNC1_R from the master control circuit 102 via the master control terminal SR2_ML (or when the slave circuit 108 outputs the first right synchronization signal SYNC1_R via the master control terminal SR2_MR), it can start a timer. Subsequently, when the slave circuit 108 receives the second right synchronization signal SYNC2_R from the slave circuit 110 via the slave terminal SR2_SR (or when the slave circuit 108 outputs the second right synchronization signal SYNC2_R via the slave terminal SR2_SL), it can stop the timer. Therefore, the timer of the slave circuit 108 records the time difference between the time the slave circuit 108 receives the first right synchronization signal SYNC1_R and the time the slave circuit 108 receives the second right synchronization signal SYNC2_R, which is equivalent to the path delay between the slave circuits 108 and 110.

[0050] Next, slave circuit 108 can send the recorded timer information to master circuit 102 (e.g., via a command line). Based on the information from slave circuit 108, master circuit 102 can obtain the path delay between slave circuit 108 and 110. Alternatively or additionally, slave circuit 108 can store the recorded timer information for its own use in subsequent synchronization modes.

[0051] In this way, by outputting a synchronization signal through the master control terminal M_MR on the right and receiving a synchronization signal through the slave terminal M_SR on the right, the master control circuit 102 can obtain the compensation time required by the slave circuits 108 and 110 connected to the right of the master control circuit 102. The master control circuit 102 can calculate the compensation time for slave circuit 108 and / or the compensation time for slave circuit 110 based on the path delay information obtained in the correction mode.

[0052] Therefore, the path delay of multiple driving circuits can be obtained in a single correction operation. In one embodiment, the main control circuit 102 can simultaneously output the first left synchronization signal SYNC1_L and the first right synchronization signal SYNC1_R in correction mode, such as... Figure 3 As shown. It should be noted that in the drive system of U.S. Patent Application No. 18 / 225,156, because the left and right sides use the same transmission bus to transmit synchronization signals, the calibration of the left and right drive circuits must be performed at different times. In contrast, in this invention, since the left and right drive circuits are coupled to the main control circuit through different wire paths, the calibration operations on both sides can be performed simultaneously.

[0053] like Figure 3As shown, the main control circuit 102 can simultaneously output the first left synchronization signal SYNC1_L and the first right synchronization signal SYNC1_R, thereby saving the time consumed by the calibration operation. The main control circuit 102 can also simultaneously monitor the left slave terminal M_SL and the right slave terminal M_SR to determine the reception time of the second left synchronization signal SYNC2_L and the second right synchronization signal SYNC2_R.

[0054] In some embodiments, even if the first left synchronization signal SYNC1_L and the first right synchronization signal SYNC1_R are output simultaneously, the main control circuit 102 may receive the second left synchronization signal SYNC2_L and the second right synchronization signal SYNC2_R at different times. This indicates that the path delay obtained from the left slave circuit 104 is different from the path delay obtained from the right slave circuit 110. This time difference can be used as an offset value to be added to the synchronization mode calculation. The offset value can be used to compensate for the time difference between the left driving circuit and the right driving circuit, so that the touch sensing operations on both sides are well synchronized.

[0055] Figure 4 This illustration shows a correction operation for obtaining path delay in a drive system 10 according to an embodiment of the present invention, wherein the value of the delay time is marked on the path of the connecting line. Figure 5 In order to be in Figure 4 The waveform of the synchronization signal at each endpoint under the delay time. Figure 5 In this context, the synchronization signals SYNC1_L, SYNC1_R, SYNC2_L, and SYNC2_R are all pulse signals, but those skilled in the art should understand that the implementation of the signals is not limited thereto.

[0056] like Figure 4 As shown, drive circuits 104 to 110 are sequentially connected in series with the same or different path delays. Each pair of adjacent drive circuits is interconnected by two wires corresponding to the master and slave terminals, respectively. Specifically, slave circuits 104 and 106 are interconnected by two wires with a delay time of 2. Slave circuit 106 is interconnected with master circuit 102 by two wires with a delay time of 2. Master circuit 102 is interconnected with slave circuit 108 by two wires with a delay time of 1. Slave circuits 108 and 110 are interconnected by two wires with a delay time of 1.

[0057] like Figure 5As shown, the master control circuit 102 first outputs a first left synchronization signal SYNC1_L through the master control terminal M_ML and a first right synchronization signal SYNC1_R through the master control terminal M_MR. Simultaneously, it starts a first timer and a second timer. The first timer is used for the calibration of the left slave circuits 104 and 106, and the second timer is used for the calibration of the right slave circuits 108 and 110. The first left synchronization signal SYNC1_L is transmitted to the left and reaches the master control terminal SL2_MR of slave circuit 106 after a delay time of 2. At this time, slave circuit 106 starts a timer in response to the reception of the first left synchronization signal SYNC1_L. Slave circuit 106 can further transmit the first left synchronization signal SYNC1_L to slave circuit 104 through the master control terminal SL2_ML. The first left synchronization signal SYNC1_L continues to be transmitted to the left and then reaches the master control terminal SL1_MR of slave circuit 104 after another delay time of 2. When slave circuit 104 receives the first left synchronization signal SYNC1_L, it can transmit the second left synchronization signal SYNC2_L back through the slave terminal SL1_SR. The second left synchronization signal SYNC2_L is transmitted to the right and arrives at the slave terminal SL2_SL of slave circuit 106 after a delay of 2. At this time, slave circuit 106 stops its timer in response to the receipt of the second left synchronization signal SYNC2_L. The timer of slave circuit 106 can record the path delay (denoted as PD) between slave circuits 104 and 106, which is equal to 4.

[0058] The second left synchronization signal SYNC2_L continues to be transmitted to the right, and then arrives at the slave terminal M_SL of the master control circuit 102 after another delay time of 2. At this time, the master control circuit 102 stops the first timer in response to the receipt of the second left synchronization signal SYNC2_L. The first timer of the master control circuit 102 can record the path delay between the master control circuit 102 and the leftmost slave circuit 104, which is equal to 8.

[0059] Similarly, the first right synchronization signal SYNC1_R output by the master control circuit 102 is transmitted to the right and arrives at the master control terminal SR2_ML of the slave circuit 108 after a delay time of 1. At this time, the slave circuit 108 starts a timer in response to the receipt of the first right synchronization signal SYNC1_R. The slave circuit 108 can further transmit the first right synchronization signal SYNC1_R to the slave circuit 110 through the master control terminal SR2_MR. The first right synchronization signal SYNC1_R continues to be transmitted to the right and then arrives at the master control terminal SR1_ML of the slave circuit 110 after another delay time of 1. When the slave circuit 110 receives the first right synchronization signal SYNC1_R, it can send back the second right synchronization signal SYNC2_R through the slave terminal SR1_SL. The second right synchronization signal SYNC2_R is transmitted to the left and arrives at the slave terminal SR2_SR of the slave circuit 108 after a delay time of 1. At this time, the slave circuit 108 stops the timer in response to the receipt of the second right synchronization signal SYNC2_R. The timer of slave circuit 108 can record the path delay between slave circuits 108 and 110, which is equal to 2.

[0060] The second right synchronization signal SYNC2_R continues to be transmitted to the left, and then arrives at the slave terminal M_SR of the master control circuit 102 after another delay time of 1. At this time, the master control circuit 102 stops the second timer in response to the receipt of the second right synchronization signal SYNC2_R. The second timer of the master control circuit 102 can record the path delay between the master control circuit 102 and the rightmost slave circuit 110, which is equal to 4.

[0061] As described above, the path delay value can be divided by 2 to obtain the compensation time for the corresponding slave circuit. Based on the timer value, the compensation time required between slave circuits 104 and 106 can be calculated as 4 / 2 = 2, the compensation time required between slave circuit 104 and master control circuit 102 can be calculated as 8 / 2 = 4, the compensation time required between slave circuits 108 and 110 can be calculated as 4 / 2 = 2, and the compensation time required between master control circuit 102 and slave circuit 108 can be calculated as 2 / 2 = 1. Therefore, the corresponding drive circuit can use this compensation time information in the subsequent synchronization mode.

[0062] In this example, since the path delays of the left slave circuits 104 and 106 are asymmetrical with those of the right slave circuits 108 and 110, an offset value can be used to modify or adjust the compensation time, thereby synchronizing the slave circuits 104 to 110 on both sides.

[0063] In detail, such as Figure 5As shown, the maximum path delay on the left (i.e., the path delay between master circuit 102 and the leftmost slave circuit 104) is 8, while the maximum path delay on the right (i.e., the path delay between master circuit 102 and the rightmost slave circuit 110) is 4. Since these two path delays are unequal, an additional offset value is needed to compensate for the difference. As mentioned above, the compensation time is obtained by dividing the path delay by 2. Similarly, the offset value can be calculated by dividing the difference in path delays by 2. In this example, the difference in path delays between the left and right sides is 4, and dividing it by 2 yields an offset value of 2. This offset value can be added to the slave circuit on the side with the smaller path delay. Therefore, an offset value of 2 can be added to the compensation time used for the right-side slave circuits 108 and 110, thereby achieving synchronization between the right-side slave circuits 108 and 110 and the left-side slave circuits 104 and 106.

[0064] It is worth noting that the drive circuitry in a drive system can also be configured in another way. For example, the main control circuit does not need to be located at the center of the drive system. Figure 6 This is a schematic diagram of another drive system 60 according to an embodiment of the present invention, which includes one master control circuit 602 and four slave circuits 604, 606, 608 and 610. These drive circuits 602 to 610 are connected in series, wherein the master control circuit 602 is the leftmost drive circuit, and all slave circuits 604 to 610 are connected to the right side of the master control circuit 602. Similarly, each drive circuit 602 to 610 may include a synchronization controller SCTL for performing correction and synchronization operations.

[0065] Similarly, in the drive system 60, each pair of adjacent drive circuits is interconnected by two wires via a master control terminal and a slave terminal. Specifically, the master control circuit 602 includes a master control terminal M_MR and a slave terminal M_SR, which are respectively connected to a master control terminal SR4_ML and a slave terminal SR4_SL of the slave circuit 604. The other master control terminal SR4_MR and the other slave terminal SR4_SR of the slave circuit 604 are respectively connected to a master control terminal SR3_ML and a slave terminal SR3_SL of the slave circuit 606. The other master control terminal SR3_MR and the other slave terminal SR3_SR of the slave circuit 606 are respectively connected to a master control terminal SR2_ML and a slave terminal SR2_SL of the slave circuit 608. The other master control terminal SR2_MR and the other slave terminal SR2_SR of the slave circuit 608 are respectively connected to a master control terminal SR1_ML and a slave terminal SR1_SL of the slave circuit 610.

[0066] Figure 6The delay time information is also shown. In this example, the delay time between the master circuit 602 and the slave circuit 604 is equal to 2, the delay time between slave circuits 604 and 606 is equal to 2, the delay time between slave circuits 606 and 608 is equal to 1, and the delay time between slave circuits 608 and 610 is equal to 1.

[0067] In the calibration mode, the transmission of the synchronization signal may begin in the master control circuit 602, but the present invention is not limited thereto. In another embodiment, the transmission of the synchronization signal may also begin in any of the slave circuits 604 to 610.

[0068] The master control circuit 602 can output a first synchronization signal SYNC1 through its master control terminal M_MR and start a timer. The first synchronization signal SYNC1 is transmitted to the right, sequentially reaching the master control terminals SR4_ML of slave circuit 604, SR3_ML of slave circuit 606, SR2_ML of slave circuit 608, and SR1_ML of slave circuit 610. When slave circuit 610 receives the first synchronization signal SYNC1, it can output a second synchronization signal SYNC2 through its slave terminal SR1_SL. The second synchronization signal SYNC2 is transmitted to the left, sequentially reaching the slave terminals SR2_SR of slave circuit 608, SR3_SR of slave circuit 606, SR4_SR of slave circuit 604, and M_SR of master control circuit 602. The master control circuit 602 can stop the timer when it receives the second synchronization signal SYNC2.

[0069] In this way, the master control circuit 602 can obtain the path delay between the master control circuit 602 and the slave circuit 610, which is equal to 12 (i.e., PD = 12), such as Figure 7 As shown. Based on this path delay, the master control circuit 602 can further calculate the compensation time for the slave circuit 610, which is 12 / 2 = 6. Similarly, slave circuits 604, 606, and 608 can each use a timer to record the difference between the reception time of the first synchronization signal SYNC1 and the reception time of the second synchronization signal SYNC2, thereby obtaining the corresponding path delay. Figure 7 As shown, slave circuit 604 can obtain the path delay between slave circuits 604 and 610, which is equal to 8. Slave circuit 606 can obtain the path delay between slave circuits 606 and 610, which is equal to 4. Slave circuit 608 can obtain the path delay between slave circuits 608 and 610, which is equal to 2. Based on the above path delay information, the compensation time between any two drive circuits can be easily calculated.

[0070] In one embodiment, the master control circuit 602 can collect path delay information (e.g., via command lines) from the slave circuits 604, 606 and 608, and calculate the compensation time for the master control circuit 602 and each slave circuit 604 to 610 accordingly. The detailed calculation method can be referred to the description in the above paragraph, and will not be repeated here.

[0071] In the above embodiment, the drive system includes five drive circuits, wherein the master control circuit and slave circuits are arranged symmetrically for calibration operations. In another embodiment, a drive system may contain any number of drive circuits, and the master control circuit may be located anywhere. For example, Figure 8 This is a schematic diagram of another driving system 80 according to an embodiment of the present invention, which includes one main control circuit 802 and three slave circuits 804, 806 and 808. These driving circuits 802 to 808 are connected in series, wherein two slave circuits 804 and 806 are connected to the left side of the main control circuit 802, and one slave circuit 808 is connected to the right side of the main control circuit 802.

[0072] Similarly, in the drive system 80, each pair of adjacent drive circuits is interconnected by two wires via a master control terminal and a slave terminal, respectively. Specifically, a master control terminal SL1_MR and a slave terminal SL1_SR of slave circuit 804 are connected to a master control terminal SL2_ML and a slave terminal SL2_SL of slave circuit 806, respectively. Another master control terminal SL2_MR and another slave terminal SL2_SR of slave circuit 806 are connected to a master control terminal M_ML and a slave terminal M_SL of master control circuit 802, respectively. Another master control terminal M_MR and another slave terminal M_SR of master control circuit 802 are connected to a master control terminal SR1_ML and a slave terminal SR1_SL of slave circuit 808, respectively.

[0073] Figure 8 The delay time information is also shown. In this example, the delay time between slave circuits 804 and 806 is 2, the delay time between slave circuit 806 and master circuit 802 is 2, and the delay time between master circuit 802 and slave circuit 808 is 1.

[0074] In this example, the synchronization signal transmission in correction mode can begin in the master control circuit 802, which uses different synchronization signals to correct the paths of the left slave circuits 804 and 806 and the right slave circuit 808. Specifically, the master control circuit 802 can output a first left synchronization signal SYNC1_L through the master control terminal M_ML and a first right synchronization signal SYNC1_R through the master control terminal M_MR. Simultaneously, it starts a first timer and a second timer. The first timer is used for the correction of the left slave circuits 804 and 806, and the second timer is used for the correction of the right slave circuit 808. The first left synchronization signal SYNC1_L is transmitted to the left, sequentially reaching the master control terminal SL2_MR of slave circuit 806 and the master control terminal SL1_MR of slave circuit 804. When slave circuit 804 receives the first left synchronization signal SYNC1_L, it can output a second left synchronization signal SYNC2_L through the slave terminal SL1_SR. The second left synchronization signal SYNC2_L is transmitted to the right, sequentially reaching the slave terminal SL2_SL of the slave circuit 806 and the slave terminal M_SL of the master control circuit 802. The master control circuit 802 can stop the first timer when it receives the second left synchronization signal SYNC2_L.

[0075] Similarly, slave circuit 806 can also use a timer to record the difference between the receiving time of the first left synchronization signal SYNC1_L and the receiving time of the second left synchronization signal SYNC2_L, thereby obtaining the corresponding path delay between slave circuits 804 and 806.

[0076] The first right synchronization signal SYNC1_R output by the master control circuit 802 is transmitted to the right and reaches the master control terminal SR1_ML of the slave circuit 808. Simultaneously with receiving the first right synchronization signal SYNC1_R, the slave circuit 808 can output a second right synchronization signal SYNC2_R through its slave terminal SR1_SL. The second right synchronization signal SYNC2_R is transmitted to the left and reaches the slave terminal M_SR of the master control circuit 802. The master control circuit 802 can stop the second timer upon receiving the second right synchronization signal SYNC2_R.

[0077] Based on the aforementioned operations of sending synchronization signals and controlling timers, the main control circuit 802 can obtain and / or calculate the path delay between every two drive circuits, and can calculate the corresponding compensation time accordingly. The waveforms of the synchronization signals SYNC1_L, SYNC1_R, SYNC2_L, and SYNC2_R at each endpoint are shown below. Figure 9 middle. Figure 9 It also shows Figure 8 The path delay (denoted as PD) is obtained under the given delay time. For details on the implementation methods for obtaining the path delay and calculating the compensation time, please refer to the foregoing paragraphs for a detailed explanation, which will not be repeated here.

[0078] The compensation time obtained in the calibration mode for each drive circuit can be further applied to the synchronization mode to synchronize the sensing time of touch sensing between different drive circuits, as described below.

[0079] In synchronous operation, each driving circuit can determine whether a touch sensing operation can be performed based on a display ready signal. The display ready signal is a signal output from the display circuit (i.e., the display portion) in the driving circuit to the touch circuit (i.e., the touch portion) in the driving circuit, indicating whether a display is currently in progress. Generally, in a touch display driver integrated circuit, display operations and touch sensing operations should be performed time-sharingly to avoid mutual interference. Therefore, the display circuit can transmit a display ready signal to the touch circuit to indicate the state of the display operation. Based on the display ready signal, the touch circuit can determine whether and when to start the touch sensing operation. In one embodiment, the touch circuit starts the touch sensing operation only when the display ready signal indicates that the display operation is interrupted or disabled. In one embodiment, the display ready signal can also be considered a sensing start signal.

[0080] In synchronous mode, each slave circuit generates and outputs a notification when it receives a display ready signal indicating that it is ready for touch sensing. After the master circuit receives its display ready signal and notifications from each slave circuit, it outputs an acknowledgment signal via its master terminal. Following the acknowledgment signal, the master circuit initiates touch sensing operation with a delay including a compensation time. The acknowledgment signal is sequentially transmitted to the slave circuits via the corresponding master terminals connected between the drive circuits. Upon receiving the acknowledgment signal via the master terminal, the slave circuit initiates touch sensing operation with a delay including a compensation time. The touch sensing operation of each drive circuit can utilize a specific delay time, which can be an offset value added to the compensation time obtained in the aforementioned correction mode. Through appropriate delay control, each drive circuit can initiate touch sensing operation at the same time to achieve synchronization of touch sensing operations.

[0081] For ease of explanation, the operation of synchronous mode will be illustrated here using the same drive system with the same master control circuit and slave circuit configuration. Figure 10 An exemplary operation of the drive system 10 (which has one master control circuit 102 and four slave circuits 104-110) in synchronous mode is shown.

[0082] First, when the touchscreen controlled by the driving system 10 wants to perform touch sensing, each driving circuit 102-110 can obtain a display ready signal DPR, which indicates that the operation of the display section has been interrupted and the touch sensing operation can begin. Regarding the left side of the main control circuit 102, when the leftmost slave circuit 104 obtains the display ready signal DPR, it can output a notification NTF_L through the slave terminal SL1_SR. The notification NTF_L is transmitted to the right and then received by the slave circuit 106 through the slave terminal SL2_SL. The slave circuit 106 can determine whether it has received the notification NTF_L and whether it has obtained the display ready signal DPR (i.e., whether it has received the display ready signal DPR from its display circuit). When the slave circuit 106 obtains the display ready signal DPR and receives the notification NTF_L from the slave circuit 104, it can further transmit the notification NTF_L to the next level through the slave terminal SL2_SR. In other words, for slave circuit 106, the notification NTF_L will only be output if both the display ready signal DPR and the notification NTF_L are received. Then, master circuit 102 can receive the notification NTF_L through slave terminal M_SL, which indicates that the driving circuits on the left (including 104 and 106) have completed the preparation for touch sensing.

[0083] Similarly, regarding the right side of the main control circuit 102, when the rightmost slave circuit 110 obtains the display ready signal DPR, it can output a notification NTF_R through the slave terminal SR1_SL. The notification NTF_R is transmitted to the left and then received by the slave circuit 108 through the slave terminal SR2_SR. The slave circuit 108 can determine whether it has received the notification NTF_R and whether it has obtained the display ready signal DPR (i.e., whether it has received the display ready signal DPR from its display circuit). When the slave circuit 108 obtains the display ready signal DPR and receives the notification NTF_R from the slave circuit 110, it can further transmit the notification NTF_R to the next level through the slave terminal SR2_SL. In other words, for the slave circuit 108, the notification NTF_R will only be output if both the conditions of obtaining the display ready signal DPR and receiving the notification NTF_R are met. Next, the main control circuit 102 can receive a notification NTF_R through the slave terminal M_SR, which indicates that the driving circuits on the right (including 108 and 110) have completed the preparation for touch sensing.

[0084] The main control circuit 102 can determine whether it has received notifications NTF_L and NTF_R through the slave terminals M_SL and M_SR, respectively, and simultaneously determine whether it has acquired the display ready signal DPR (i.e., whether it has received the display ready signal DPR from its display circuit). When the main control circuit 102 acquires the display ready signal DPR and receives notifications NTF_L and NTF_R, it can output confirmation signals CONF_L and CONF_R through the main control terminals M_ML and M_MR, respectively. It should be noted that the notification NTF_L is received from the slave circuits 104 and 106 on the left, while the notification NTF_R is received from the slave circuits 108 and 110 on the right. Therefore, the main control circuit 102 is required to successfully receive both notifications NTF_L and NTF_R to ensure that all slave circuits 104 to 110 in the drive system 10 have completed the preparation for touch sensing. After the main control circuit 102 outputs confirmation signals CONF_L and CONF_R, it can start the touch sensing operation with a delay for the compensation time of the main control circuit 102. The compensation time can be equal to the maximum path delay corresponding to the farthest slave circuit.

[0085] Next, the confirmation signal CONF_L is received sequentially by slave circuits 106 and 104 through the master control terminals SL2_MR and SL1_MR, respectively. After receiving the confirmation signal CONF_L, each slave circuit 106 and 104 initiates the touch sensing operation with a delay having a compensation time for each slave circuit. Similarly, the confirmation signal CONF_R is received sequentially by slave circuits 108 and 110 through the master control terminals SR2_ML and SR1_ML, respectively. After receiving the confirmation signal CONF_R, each slave circuit 108 and 110 initiates the touch sensing operation with a delay having a compensation time for each slave circuit. With appropriate compensation time, each drive circuit 102-110 can initiate the touch sensing operation at the same time, thereby performing touch sensing synchronously.

[0086] It is worth noting that, Figure 4 The implementation of the delay time shown can also be applied to synchronous mode to perform touch sensing. Please refer to... Figure 4 Matching Figure 11 As shown, where, Figure 11 This is a waveform diagram of touch sensing operations and related notification and confirmation signals at each endpoint of the drive system 10. (Example:) Figure 11 As shown, the touch sensing operation begins with a sensing setting SET (e.g., a preset operation) and ends with a sensing termination SEND (e.g., a postset operation).

[0087] In this example, the slave device is used to transmit notifications NTF_L and NTF_R, with the low-to-high transition representing the output of the corresponding notification. For example... Figure 11As shown, the display ready signal DPR can be a flag signal that indicates that the touch sensing operation is ready when it is pulled high, and the display ready signal DPR of each driving circuit can be obtained (i.e. pulled high) at different times.

[0088] For the right-hand slave circuit, when the rightmost slave circuit 110 receives the display ready signal DPR, it can output a notification NTF_R to slave circuit 108 via the slave terminal SR1_SL. The notification NTF_R is then transmitted to the slave terminal SR2_SR of slave circuit 108 after a delay of 1. At this time, slave circuit 108 can determine that it has received the display ready signal DPR and the notification NTF_R, and thus transmits the notification NTF_R via the slave terminal SR2_SL. The notification NTF_R is then transmitted to the slave terminal M_SR of master control circuit 102 after a delay of 1. For the left-hand slave circuit, when the leftmost slave circuit 104 receives the display ready signal DPR, it can output a notification NTF_L to slave circuit 106 via the slave terminal SL1_SR. The notification NTF_L is then transmitted to the slave terminal SL2_SL of slave circuit 106 after a delay of 2. At this time, the slave circuit 106 can determine that it has obtained the display ready signal DPR and received the notification NTF_L, and thus transmits the notification NTF_L through the slave terminal SL2_SR. The notification NTF_L is then transmitted to the slave terminal M_SL of the master control circuit 102 after a delay time of 2.

[0089] Next, the main control circuit 102 determines that both NTF_L and NTF_R notifications have been received, and the display ready signal DPR indicates that the touch sensing operation is ready. At this time, the main control circuit 102 can output an acknowledgment signal CONF_L to the left via the main control terminal M_ML, and simultaneously output an acknowledgment signal CONF_R to the right via the main control terminal M_MR. In this example, each acknowledgment signal CONF_L or CONF_R is represented by a pulse (or the rising edge of a pulse), but those skilled in the art should understand that acknowledgment signals can be implemented in any way. When the main control circuit 102 outputs acknowledgment signals CONF_L and CONF_R, the touch sensing operation can be started after a delay of a compensation time (e.g., start sensing setting SET), the compensation time of which can be calculated by the maximum path delay of the main control circuit 102 obtained in the calibration mode.

[0090] In this example, based on the correction operation on the left, the master control circuit 102 (and / or slave circuits 104 and 106) can achieve a path delay of 8 between 102 and 104, and a path delay of 4 between 104 and 106. Based on the correction operation on the right, the master control circuit 102 (and / or slave circuits 108 and 110) can achieve a path delay of 4 between 102 and 110, and a path delay of 2 between 110 and 108. Since the maximum path delay (denoted by PD) of the master control circuit 102 is 8, the compensation time (denoted by CT) for the master control circuit 102 can be calculated as 8 / 2 = 4. Figure 11 As shown.

[0091] In addition, since the path delays of the left slave circuits 104 and 106 are greater than those of the right slave circuits 108 and 110, the compensation time for the right slave circuits 108 and 110, which have smaller path delays, needs to be increased by an offset value (denoted as OFS) to compensate for the difference in path delays. In this example, the offset value is equal to the difference between the path delays between 102 and 104 and between 102 and 110, divided by 2, i.e., (8-4) / 2 = 2.

[0092] The confirmation signal CONF_L on the left can be received sequentially by slave circuits 106 and 104. When slave circuit 106 receives the confirmation signal CONF_L through the master control terminal SL2_MR, it can start the touch sensing operation after a compensation time delay. The compensation time for slave circuit 106 is equal to its path delay divided by 2, i.e., 4 / 2 = 2. Then, when slave circuit 104 receives the confirmation signal CONF_L through the master control terminal SL1_MR, since slave circuit 104 has the maximum path delay corresponding to master circuit 102 and is the slowest to receive the confirmation signal, it can immediately start the touch sensing operation without any delay.

[0093] The confirmation signal CONF_R on the right side can be received sequentially by slave circuits 108 and 110. When slave circuit 108 receives the confirmation signal CONF_R through the master control terminal SR2_ML, it can start the touch sensing operation after a delay of one compensation time plus an offset value. The actual compensation time for slave circuit 108 is 3, which is equal to the path delay divided by 2 plus the offset value. Next, when slave circuit 110 receives the confirmation signal CONF_R through the master control terminal SR1_ML, it can start the touch sensing operation after a compensation time equal to the offset value. This offset is equal to 2, which can be calculated from the delay difference between the left and right sides.

[0094] like Figure 11As shown, through appropriate delay control, the main control circuit 102 and the slave circuits 104-110 can start sensing the setting SET at the same time, thereby synchronously executing the touch sensing operation.

[0095] In another embodiment, Figure 6 The implementation of the master control circuit, slave circuit, and their delay times shown can also be applied to synchronous mode to perform touch sensing. Please refer to... Figure 12 Matching Figure 6 As shown, where, Figure 12 This is a waveform diagram of touch sensing operations and related notification and confirmation signals at each endpoint of the drive system 60. Similarly, as... Figure 12 As shown, the touch sensing operation begins with a sensing setting SET and ends with a sensing termination SEND.

[0096] Similarly, the slave terminal is used to transmit the notification NTF, while the master terminal is used to transmit the acknowledgment signal CONF. In this example, since the master control circuit 602 is the leftmost driving circuit, only one notification NTF and one acknowledgment signal CONF are needed to achieve synchronous operation of the slave circuits 604 to 610, which are all connected to the right side of the master control circuit 602.

[0097] In detail, the transmission of the notification NTF can begin in the rightmost slave circuit 610, which outputs the notification NTF via the slave terminal SR1_SL upon receiving the display ready signal DPR. The notification NTF is then transmitted to the left, arriving sequentially at the drive circuits 608, 606, 604, and 602 after respective delay times. For slave circuits 608, 606, or 604, the notification NTF can be transmitted to the next stage upon receiving the display ready signal DPR and receiving the notification NTF from the previous stage (i.e., both conditions are met).

[0098] When the master control circuit 602 receives the notification NTF through the slave terminal M_SR and obtains the display ready signal DPR indicating that the touch sensing operation is ready, the master control circuit 602 can output an acknowledgment signal CONF through the master control terminal M_MR, and start the touch sensing operation with a delay having a compensation time for the master control circuit 602. The acknowledgment signal CONF is then transmitted to the right, and arrives sequentially at the drive circuits 604, 606, 608 and 610 after their respective delay times. For the slave circuits 604 to 610, after receiving the acknowledgment signal CONF, they can start the touch sensing operation with a delay having a compensation time for each slave circuit, the compensation time of which can be calculated through the above-described correction operation.

[0099] In this example, after the correction operation is completed, the main control circuit 602 can obtain a path delay of 12 between 602 and 610, a path delay of 8 between 604 and 610, a path delay of 4 between 606 and 610, and a path delay of 2 between 608 and 610. Since the maximum path delay of the main control circuit 602 is 12, the compensation time for the main control circuit 602 can be calculated as 12 / 2 = 6. Figure 12 As shown. The confirmation signal CONF output by the main control circuit 602 can be received sequentially by slave circuits 604 to 610. When slave circuit 604 receives the confirmation signal CONF, it can start the touch sensing operation after a delay of one compensation time, and the compensation time for slave circuit 604 is equal to its path delay divided by 2, i.e., 8 / 2 = 4. When slave circuit 606 receives the confirmation signal CONF, it can start the touch sensing operation after a delay of one compensation time, and the compensation time for slave circuit 606 is equal to its path delay divided by 2, i.e., 4 / 2 = 2. When slave circuit 608 receives the confirmation signal CONF, it can start the touch sensing operation after a delay of one compensation time, and the compensation time for slave circuit 608 is equal to its path delay divided by 2, i.e., 2 / 2 = 1. When slave circuit 610 receives the acknowledgment signal CONF, since slave circuit 610 has the maximum path delay corresponding to master circuit 602 and is the slowest to receive the acknowledgment signal CONF, it can immediately initiate touch sensing operation without any delay. It should be noted that in this example, only one-sided correction is performed; therefore, no offset value is required for calculating the compensation time.

[0100] like Figure 12 As shown, through appropriate delay control, the main control circuit 602 and the slave circuits 604-610 can start sensing the setting SET at the same time, thereby synchronously executing the touch sensing operation.

[0101] In the above embodiments, the slave circuit can send notifications through a corresponding slave terminal, but the implementation of the notification is not limited to this. In another embodiment, the slave circuit can also send notifications through a command line coupled between the master circuit and the slave circuit.

[0102] Figure 13Another exemplary operation of the drive system 10 in synchronous mode is shown. In this example, slave circuits 104-110 send their respective notifications NTF1-NTF4 to the master control circuit 102 via command lines. For example, the master control circuit 102 can read the status of each slave circuit 104-110 via command lines to determine whether each slave circuit 104-110 is ready for touch sensing. Alternatively, slave circuits 104-110 can send signals carrying the corresponding notifications NTF1-NTF4 to the master control circuit 102 via command lines. After receiving notifications NTF1-NTF4, the master control circuit 102 can transmit confirmation signals CONF_L and CONF_R respectively via the master control terminals M_ML and M_MR. Detailed operation of the confirmation signals CONF_L and CONF_R can be found in the description above and will not be repeated here.

[0103] In the above embodiments, the display circuit in the driving circuit can transmit a display ready signal to the touch circuit in the driving circuit to indicate whether a touch sensing operation can be performed. In another embodiment, the touch circuit may not receive a display ready signal from the display circuit. For example, when the display circuit is in sleep mode, its display function is turned off, and therefore it cannot output a display ready signal. In this case, an acknowledgment signal provided by the main control circuit can replace the function of the display ready signal, allowing the driving circuit to know whether other driving circuits are ready for touch sensing.

[0104] Figure 14 This illustrates another exemplary operation of the drive system 10 in synchronous mode, omitting the display ready signal DPR; the relevant waveform is shown below. Figure 15 As shown, it illustrates the touch sensing operations and related notifications NTF_L, NTF_R and confirmation signals CONF_L, CONF_R at each endpoint of the drive system 10.

[0105] In this example, there is no display ready signal to indicate whether each driving circuit is ready for touch sensing. Therefore, the master control circuit 102 does not need to know whether the touch sensing of each slave circuit 104-110 is ready. In this case, each slave circuit 104-110 does not send a notification, and when the touchscreen jointly controlled by the driving circuits 102-110 wants to perform touch sensing, the master control circuit 102 can output confirmation signals CONF_L and CONF_R. It should be noted that the display circuit is turned off or disabled at this time, so the master control circuit 102 can start sending confirmation signals CONF_L and CONF_R without considering interference from display operation. Since the function of displaying the ready signal is replaced by the confirmation signals CONF_L and CONF_R, the main control circuit 102 can enter the sensing ready state after outputting the confirmation signals CONF_L and CONF_R with a corresponding delay time (i.e., compensation time). Similarly, each slave circuit 104-110 can enter the sensing ready state after receiving the corresponding confirmation signal CONF_L or CONF_R with a corresponding delay time (i.e., compensation time). Figure 15 As shown.

[0106] Therefore, with appropriate delay control, the main control circuit 102 and the slave circuits 104-110 can enter the sensing ready state at the same time, and thus can start the sensing setting SET at the same time, thereby synchronously executing the touch sensing operation.

[0107] In this invention, the drive circuits in the drive system are connected in series, and every two adjacent drive circuits can be connected via two endpoints. In this configuration, the drive circuit has a maximum of four endpoints for calibration and synchronization operations (in addition to the endpoints coupled to the command line). More specifically, the leftmost and rightmost drive circuits have two endpoints to connect to their adjacent drive circuits, while the other drive circuits have four endpoints to connect to their adjacent left and right drive circuits, respectively. This connection method reduces layout complexity and minimizes the use of cross-line connections.

[0108] In addition, unlike the structure in U.S. Patent Application No. 18 / 225,156, where the endpoints are interconnected via a transmission bus, in the drive system structure of this invention, each endpoint is connected to only one corresponding endpoint of the adjacent drive circuit. Therefore, correction and synchronization operations can be well designed to fix the input / output state of each endpoint, thereby avoiding leakage current caused by state switching. For example, in some embodiments, the master terminal is always used to transmit signals away from the master circuit, while the slave terminal is always used to transmit signals towards the master circuit. In this case, each endpoint must always be either an output or an input.

[0109] Furthermore, the series connection of the drive circuits can support any number and no upper limit of drive circuits, and the main control circuit can be located anywhere. In a preferred embodiment, the drive system may include more than three series-connected drive circuits.

[0110] In some embodiments, a synchronization mode can be executed when the touchscreen, jointly controlled by the driving circuit, intends to perform touch sensing. The calibration mode can be executed at any time before the touch sensing operation. To adapt to environmental changes, the calibration mode can be executed periodically to ensure accurate path delay values ​​are obtained under current environmental parameters.

[0111] It is worth noting that the purpose of this invention is to provide a method for synchronizing touch sensing operations in a driving system with multiple driving circuits. Those skilled in the art will be able to make modifications or variations accordingly, and are not limited thereto. For example, in the above embodiments, the values ​​of path delay and compensation time are merely illustrative examples. In another embodiment, if the driving circuits have different delay times, the calculated compensation time may also have different results. Furthermore, in the embodiments of this invention, the driving system may include any number of driving circuits, wherein the master control circuit and slave circuits can be configured symmetrically or asymmetrically, and correction and synchronization modes can be performed in various driving systems. For example, Figure 8 The drive system 80 shown includes only four drive circuits. Therefore, different numbers of slave circuits are connected to the left and right sides of the master control circuit. This structure can also be used in a similar way to perform synchronous mode operation by transmitting notification and confirmation signals. The timing differences caused by the asymmetrical architecture can also be compensated for by offset values. Those skilled in the art can deduce its related operation based on the above description, which will not be elaborated here.

[0112] In summary, this invention proposes a method for synchronizing touch sensing operations in a driving system. The driving system contains multiple driving circuits that operate together to control a touchscreen. These driving circuits are connected in series, with each pair of adjacent driving circuits connected by two wires. One driving circuit is designated as the master control circuit, and the others are designated as slave circuits. The method proposed in this invention includes a calibration mode and a synchronization mode. In the calibration mode, the path delay between the driving circuits is measured to calculate the compensation time for each driving circuit. The compensation time obtained in the calibration mode is then used in the synchronization mode to synchronize touch sensing. By using accurate compensation time for appropriate delay control, each driving circuit can initiate touch sensing operations at the same time, thereby synchronously executing touch sensing.

[0113] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A drive system, characterized in that, include: Multiple drive circuits connected in series, wherein each drive circuit is connected to one or two adjacent drive circuits via a master control terminal and a slave terminal, the multiple drive circuits including: A first driving circuit is used to output a first synchronization signal through the main control terminal; and A second driving circuit is used to output a second synchronization signal through the slave terminal when the first synchronization signal is received through the master terminal; The compensation time of the second driving circuit is calculated based on the output time of the first synchronization signal and the reception time of the second synchronization signal.

2. The drive system as described in claim 1, characterized in that, The multiple drive circuits include more than three drive circuits.

3. The drive system as described in claim 1, characterized in that, A third drive circuit among the plurality of drive circuits is coupled between the first drive circuit and the second drive circuit, and is used to receive the first synchronization signal from the first drive circuit through the master control terminal and to receive the second synchronization signal from the second drive circuit through the slave terminal.

4. The drive system as described in claim 3, characterized in that, The corresponding compensation time of the third driving circuit is calculated based on a receiving time point when the third driving circuit receives the first synchronization signal and a receiving time point when the third driving circuit receives the second synchronization signal.

5. The drive system as described in claim 1, characterized in that, The first drive circuit is a master control drive circuit that obtains multiple compensation times by outputting the first synchronization signal, wherein each compensation time corresponds to one of the multiple drive circuits.

6. The drive system as described in claim 1, characterized in that, The first driving circuit is a slave driving circuit that sends the corresponding compensation time of the second driving circuit to a master driving circuit among the plurality of driving circuits.

7. The drive system as described in claim 1, characterized in that, The first driving circuit is a master control driving circuit, and the plurality of driving circuits include at least one first slave driving circuit coupled to the master control driving circuit through a first master control terminal and a first slave terminal, and at least one second slave driving circuit coupled to the master control driving circuit through a second master control terminal and a second slave terminal. The master control driving circuit outputs the first synchronization signal to the at least one first slave driving circuit through the first master control terminal, and outputs a third synchronization signal to the at least one second slave driving circuit through the second master control terminal.

8. The drive system as described in claim 7, characterized in that, The first driving circuit simultaneously outputs the first synchronization signal and the third synchronization signal.

9. The drive system as described in claim 1, characterized in that, The multiple driving circuits utilize multiple compensation times to synchronize the touch sensing time.

10. A drive system, characterized in that, include: Multiple drive circuits connected in series, wherein each drive circuit is connected to one or two adjacent drive circuits via a master control terminal and a slave terminal, the multiple drive circuits including: Multiple slave driver circuits, each of which outputs a notification; and A main control drive circuit is used to: Receive the notification from the multiple slave drive circuits; After receiving the notification from the multiple slave drive circuits, the master control terminal outputs an acknowledgment signal; and After the confirmation signal is output, a sensing operation is initiated with a delay having a compensation time for the main control drive circuit. The plurality of slave drive circuits also receive the confirmation signal through the master control terminal, and after receiving the confirmation signal, they initiate the sensing operation with a delay having a compensation time for each of the slave drive circuits.

11. The drive system as described in claim 10, characterized in that, The first of the plurality of slave drive circuits outputs the notification when a display ready signal is received.

12. The drive system as described in claim 10, characterized in that, A first slave driver circuit among the plurality of slave driver circuits outputs the notification when it receives a display ready signal and receives the notification from a second slave driver circuit among the plurality of slave driver circuits.

13. The drive system as described in claim 10, characterized in that, The main control drive circuit outputs the confirmation signal after receiving a display ready signal.

14. The drive system as described in claim 10, characterized in that, The master control drive circuit receives the notification from the multiple slave drive circuits through the slave terminal.

15. The drive system as described in claim 10, characterized in that, The master control drive circuit receives the notification from the multiple slave drive circuits via a command line.

16. A first driving circuit, connected in series with multiple driving circuits, characterized in that, The first driving circuit is connected to one or two adjacent driving circuits among the plurality of driving circuits via a master control terminal and a slave terminal. The first driving circuit is used to: The main control terminal outputs a first synchronization signal; A second synchronization signal is received through the slave terminal, wherein the second synchronization signal is output by a second drive circuit among the plurality of drive circuits upon receiving the first synchronization signal; and Based on an output time point of the first synchronization signal and a reception time point of the second synchronization signal, a corresponding compensation time for the second drive circuit is calculated.

17. The first driving circuit as described in claim 16, characterized in that, The first synchronization signal is received by a third drive circuit among the plurality of drive circuits through the master control terminal, and the second synchronization signal is received by the third drive circuit through the slave terminal.

18. The first driving circuit as described in claim 17, characterized in that, The corresponding compensation time of the third driving circuit is calculated based on a receiving time point when the third driving circuit receives the first synchronization signal and a receiving time point when the third driving circuit receives the second synchronization signal.

19. The first driving circuit as described in claim 16, characterized in that, The first drive circuit is a master control drive circuit that obtains multiple compensation times by outputting the first synchronization signal, wherein each compensation time corresponds to one of the multiple drive circuits.

20. The first driving circuit as described in claim 16, characterized in that, The first driving circuit is a slave driving circuit that sends the corresponding compensation time of the second driving circuit to a master driving circuit among the plurality of driving circuits.

21. The first driving circuit as described in claim 16, characterized in that, The first driving circuit is a master control driving circuit, and the plurality of driving circuits include at least one first slave driving circuit coupled to the master control driving circuit through a first master control terminal and a first slave terminal, and at least one second slave driving circuit coupled to the master control driving circuit through a second master control terminal and a second slave terminal. The master control driving circuit outputs the first synchronization signal to the at least one first slave driving circuit through the first master control terminal, and outputs a third synchronization signal to the at least one second slave driving circuit through the second master control terminal.

22. The first driving circuit as described in claim 21, characterized in that, The first driving circuit simultaneously outputs the first synchronization signal and the third synchronization signal.

23. The first driving circuit as described in claim 16, characterized in that, The first driving circuit utilizes multiple compensation times and a sensing time that synchronizes the multiple driving circuits for touch sensing.

24. A master control drive circuit, connected in series with multiple slave drive circuits, characterized in that, The master control drive circuit is connected to one or two adjacent slave drive circuits among the plurality of slave drive circuits through a master control terminal and a slave terminal. The master control drive circuit is used to: Receive a notification from the multiple slave drive circuits; After receiving the notification from the multiple slave drive circuits, the master control terminal outputs an acknowledgment signal. as well as After the confirmation signal is output, a sensing operation is initiated with a delay having a compensation time for the main control drive circuit.

25. The main control drive circuit as described in claim 24, characterized in that, The main control drive circuit outputs the confirmation signal after receiving a display ready signal.

26. The main control drive circuit as described in claim 24, characterized in that, The master control drive circuit receives the notification from the multiple slave drive circuits through the slave terminal.

27. The main control drive circuit as described in claim 24, characterized in that, The master control drive circuit receives the notification from the multiple slave drive circuits via a command line.

28. A slave drive circuit, located in a plurality of drive circuits connected in series, characterized in that, The slave drive circuit is connected to one or two adjacent drive circuits among the plurality of drive circuits via a master control terminal and a slave terminal. The slave drive circuit is used to: Output a notification; The main control terminal receives an acknowledgment signal from one of the multiple drive circuits, namely the main control drive circuit. The confirmation signal is generated in response to the notification; and Upon receiving the confirmation signal, a sensing operation is initiated with a delay having a compensation time for the slave drive circuit.

29. The slave drive circuit as described in claim 28, characterized in that, The slave drive circuit outputs this notification when it receives a display ready signal.

30. The slave drive circuit as described in claim 28, characterized in that, The slave driver circuit outputs the notification when it receives a display ready signal and receives the notification from another slave driver circuit among the plurality of slave driver circuits.

31. The slave drive circuit as described in claim 28, characterized in that, The slave drive circuit outputs the notification through the slave terminal.

32. The slave drive circuit as described in claim 28, characterized in that, The slave driver circuit outputs the notification via a command line.

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