Floating-point arithmetic devices, methods, chips, electronic devices, media, and program products

Abstract

This application discloses a floating-point arithmetic device, method, chip, electronic device, medium, and program product, relating to the field of multiplication technology. The floating-point arithmetic device includes a multiplier and a parallel prediction module. The multiplier performs arithmetic operations on an input floating-point number to obtain a preliminary calculation result. The parallel prediction module performs operations in parallel with the multiplier to analyze the significant bits of the input floating-point number to obtain significant bit information. The significant bit information is used to normalize the preliminary calculation result, converting it into a normalized number. This application reduces the critical path timing overhead of the floating-point arithmetic device circuit, thereby shortening the critical path and improving the timing margin.

Description

Technical Field

[0001] This application relates to the field of multiplication technology, and more particularly to a floating-point arithmetic device, method, chip, electronic device, medium, and program product. Background Technology

[0002] In related technologies, floating-point arithmetic instructions can be implemented through a floating-point arithmetic unit. In the floating-point arithmetic unit, the mantissa multiplier can perform operations on a pair of input floating-point numbers, and the preamble detection module can perform preamble detection to achieve normalization operations. However, in the critical path of the floating-point arithmetic unit circuit, the mantissa multiplier and the preamble detection module are serial, which will result in a large timing overhead in the critical path of the floating-point arithmetic unit circuit, which may lead to problems such as difficulty in increasing chip frequency and increased power consumption. Summary of the Invention

[0003] The purpose of this application is to at least solve one of the technical problems existing in the prior art, and to provide a floating-point arithmetic device, method, chip, electronic device, medium and program product, which aims to reduce the critical path timing overhead of the floating-point arithmetic device circuit, thereby shortening the critical path of the floating-point arithmetic device and improving the timing margin.

[0004] In a first aspect, embodiments of this application provide a floating-point arithmetic device, including a first normalization processing module, a multiplier, and a parallel prediction module;

[0005] The multiplier is used to perform multiplication on the mantissas of the first and second floating-point operands to obtain the mantissa product;

[0006] The parallel prediction module is used to predict the leading bit offset of the mantissa product based on the effective bit information of the first and second floating-point operands while the multiplier is performing operations.

[0007] The first normalization processing module is used to shift the mantissa product according to the predicted offset to obtain the first normalized mantissa result.

[0008] According to the technical solution of the embodiments of this application, at least the following beneficial effects are achieved: the multiplier is used to perform basic mantissa operations on the input floating-point number, and while the multiplier performs mantissa operations on the input floating-point number, the parallel prediction module performs parallel valid bit analysis on the input floating-point number, so that the mantissa multiplication operation and the valid bit analysis are performed in parallel, thereby obtaining valid bit information that can be used to normalize the preliminary calculation result, so as to convert the preliminary calculation result into a normalized number, reduce the critical path timing overhead of the floating-point arithmetic device circuit, thereby shortening the critical path of the floating-point arithmetic device and improving the timing margin.

[0009] According to some embodiments of this application, the parallel prediction module includes:

[0010] Operand analysis unit is used to determine whether an operand is a denormalized number;

[0011] The offset calculation unit is used to calculate the leading bit offset based on the mantissa of the denormalized operand.

[0012] According to some embodiments of this application, the operand analysis unit determines whether an operand is a denormalized number by detecting whether the exponent field of the operand is zero and the mantissa field is non-zero.

[0013] According to some embodiments of this application, the normalization processing module includes a barrel shifter, the number of shifts of which is controlled by the leading offset.

[0014] According to some embodiments of this application, it also includes:

[0015] The exponent calculation module is used to calculate the exponent of the product result based on the exponents of the first floating-point operand and the second floating-point operand, the leading bit offset, and the offset value of the floating-point format.

[0016] The result synthesis module is used to combine the first normalized mantissa result, the product result exponent, and the product sign bit determined by the sign bits of the first floating-point operand and the second floating-point operand, and output the floating-point multiplication result.

[0017] Secondly, embodiments of this application provide a floating-point fused multiply-accumulate arithmetic device, comprising:

[0018] The floating-point arithmetic device described above is used to perform a multiplication operation on the first floating-point operand and the second floating-point operand, and output the first normalized mantissa result and the corresponding product result exponent.

[0019] The operand alignment module is used to align the exponent of the first normalized mantissa result with the mantissa of the third floating-point operand.

[0020] The mantissa addition module is used to add the aligned first normalized mantissa result to the mantissa of the third floating-point operand to obtain the intermediate mantissa sum;

[0021] The second normalization processing module is used to normalize and round the intermediate mantissa to obtain the second normalized mantissa result.

[0022] According to some embodiments of this application, it also includes:

[0023] The multiply-accumulate exponent processing module is used to calculate the fused multiply-accumulate exponent based on the product result exponent, the exponent of the third floating-point operand, and the secondary offset generated by normalizing the intermediate mantissa.

[0024] The multiply-accumulate result synthesis module is used to combine the second normalized mantissa result, the exponent of the fused multiply-accumulate result, and the fused multiply-accumulate sign bit determined according to the sign bits of the first, second, and third floating-point operands, and output the floating-point fused multiply-accumulate result.

[0025] Thirdly, embodiments of this application provide a floating-point arithmetic method, including:

[0026] Perform a multiplication operation on the mantissas of the first and second floating-point operands to obtain the mantissa product;

[0027] The multiplication operation is performed in parallel, and the leading bit offset of the mantissa product is predicted based on the valid bit information of the first and second floating-point operands.

[0028] The mantissa product is shifted according to the leading bit offset to obtain the first normalized mantissa result.

[0029] According to some embodiments of this application, it also includes:

[0030] The product result exponent is calculated based on the exponents of the first and second floating-point operands, the leading bit offset, and the floating-point format offset.

[0031] The first normalized mantissa result, the product result exponent, and the product sign bit determined by the sign bits of the first and second floating-point operands are combined to form the floating-point multiplication result.

[0032] Fourthly, embodiments of this application provide a floating-point fused multiply-accumulate operation method, including:

[0033] Perform a multiplication operation on the mantissas of the first and second floating-point operands to obtain the mantissa product;

[0034] The multiplication operation is performed in parallel, and the leading bit offset of the mantissa product is predicted based on the valid bit information of the first and second floating-point operands.

[0035] The mantissa product is shifted according to the leading bit offset to obtain the first normalized mantissa result;

[0036] The product result exponent is calculated based on the exponents of the first and second floating-point operands, the leading bit offset, and the floating-point format offset.

[0037] The first normalized mantissa result is exponentially aligned with the mantissa of the third floating-point operand and then added to obtain the intermediate mantissa sum;

[0038] The intermediate mantissas are normalized and rounded to obtain the second normalized mantissa result.

[0039] According to some embodiments of this application, it also includes:

[0040] The fused multiply-accumulate result exponent is calculated based on the product result exponent, the exponent of the third floating-point operand, and the secondary offset generated by normalizing the intermediate mantissa.

[0041] The second normalized mantissa result, the exponent of the fused multiply-accumulate result, and the fused multiply-accumulate sign bit determined according to the sign bits of the first, second, and third floating-point operands are combined to form the floating-point fused multiply-accumulate result.

[0042] Fifthly, embodiments of this application provide a chip that integrates any of the above-mentioned floating-point arithmetic devices or floating-point fused multiply-accumulate arithmetic devices.

[0043] Sixthly, embodiments of this application provide an electronic device including the chip described in the fifth aspect, wherein the electronic device is any one of an artificial intelligence processor, a graphics processor, a data center accelerator card, an autonomous driving computing unit, or an edge computing device.

[0044] In a seventh aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which are used to cause a computer to perform the computational methods described in the second or third aspect above.

[0045] Eighthly, embodiments of this application provide a computer program product, including a computer program or computer instructions, the computer program or computer instructions being stored in a computer-readable storage medium, a processor of a computer device reading the computer program or computer instructions from the computer-readable storage medium, and the processor executing the computer program or computer instructions to cause the computer device to perform the arithmetic methods as described in the second or third aspect.

[0046] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0047] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0048] The present application will be further described below with reference to the accompanying drawings and embodiments;

[0049] Figure 1This is a schematic diagram of the structure of a floating-point arithmetic device in the prior art;

[0050] Figure 2 This is a first structural schematic diagram of a floating-point arithmetic device provided in one embodiment of this application;

[0051] Figure 3 This is a second structural schematic diagram of a floating-point arithmetic device provided in one embodiment of this application;

[0052] Figure 4 This is a schematic diagram of the third structure of a floating-point arithmetic device provided in one embodiment of this application;

[0053] Figure 5 This is a schematic diagram of the fourth structure of a floating-point arithmetic device provided in one embodiment of this application;

[0054] Figure 6 This is a fifth structural schematic diagram of a floating-point arithmetic device provided in one embodiment of this application;

[0055] Figure 7 This is a schematic diagram of the structure of a floating-point fusion computing device provided in one embodiment of this application;

[0056] Figure 8 This is a flowchart of a floating-point arithmetic method provided in one embodiment of this application;

[0057] Figure 9 This is a flowchart of a floating-point fused multiplication and addition operation method provided in one embodiment of this application. Detailed Implementation

[0058] This section will describe in detail the specific embodiments of this application. Preferred embodiments of this application are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of this application, but they should not be construed as limiting the scope of protection of this application.

[0059] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0060] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0061] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0062] In some cases, refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a floating-point arithmetic device in the prior art. In the prior art floating-point arithmetic device, the mantissa multiplication module can perform multiplication operations on a pair of input floating-point numbers, and the preamble detection module can perform preamble detection to achieve normalization operations. However, in the critical path of the floating-point arithmetic device circuit, the mantissa multiplication module and the preamble detection module are serial, which will result in a large timing overhead in the critical path of the floating-point arithmetic device circuit, which may lead to problems such as difficulty in increasing chip frequency and increased power consumption.

[0063] Based on the above, this application proposes a floating-point arithmetic device, method, chip, electronic device, medium, and program product, aiming to reduce the critical path timing overhead of the floating-point arithmetic device circuit, thereby shortening the critical path of the floating-point arithmetic device and increasing the timing margin.

[0064] The various embodiments of the floating-point arithmetic device of this application will be further described below with reference to the accompanying drawings.

[0065] like Figure 2 As shown, Figure 2 This is a first structural schematic diagram of a floating-point arithmetic device provided in an embodiment of the present application. The floating-point arithmetic device includes a multiplier 110, a parallel prediction module 120, and a first normalization processing module 130.

[0066] Multiplier 110 is used to perform multiplication on the mantissas of the first floating-point operand and the second floating-point operand to obtain the mantissa product;

[0067] The parallel prediction module 120 is used to predict the leading bit offset of the mantissa product based on the effective bit information of the first floating-point operand and the second floating-point operand while the multiplier 110 is performing operations.

[0068] The first normalization processing module 130 is used to shift the mantissa product according to the predicted offset to obtain the first normalized mantissa result.

[0069] It is understandable that the effective bit analysis, which predicts the leading bit offset of the mantissa product based on the effective bit information of the first and second floating-point operands, refers to the parallel prediction of the adjustment amount required for result normalization before the actual completion of the mantissa multiplication operation, so as to achieve the normalization processing of the final result. For example, static or dynamic feature analysis and pattern matching are performed on the mantissa part (i.e., effective bits) of the two input operands in parallel to predict the possible position of the first non-zero bit or consecutive zero bits in the mantissa of the product after the multiplication operation, thereby generating effective bit information. Therefore, the essence of the effective bit analysis process is a computational shortcut. By analyzing the attributes of the input, certain features of the output are inferred, thereby breaking the inherent serial dependency relationship in the traditional calculation process. The leading bit detection work, which originally had to wait for the multiplication result to be produced, is significantly advanced to be performed simultaneously with the multiplication operation.

[0070] Specifically, significant bit analysis delves into the numerical distribution and potential correlation of the two mantissas at the binary level. For example, it needs to determine which interval the integer part of the product of the two mantissas will fall into—whether it remains in the range [1,2) (product form 01.xxx...) or carries over to the range [2,4) (product form 1x.xxx...), or whether the product will be small enough to produce a large number of leading zeros when the input operands include denormalized numbers. To achieve prediction, the parallel prediction module 120 needs to comprehensively consider various factors, including but not limited to the values ​​of the high-order significant words of the two mantissas, because the high-order bits play a decisive role in the integer part of the product; the run length of consecutive zeros or consecutive ones in the mantissas, which affects the distribution pattern of the partial product during multiplication; and whether the operands belong to the special category of denormalized numbers, because the mantissas of denormalized numbers do not have implicit leading 1s, and their numerical range is significantly different from that of normalized numbers, which will greatly affect the order of magnitude of the product. Significant bit analysis can be considered a complex prediction based on binary number theory. It estimates the approximate logarithm of the product or its higher-order bits by constructing a simplified shadow computation path parallel to the main multiplication data path. The computational depth and complexity of the shadow path are far lower than a full floating-point arithmetic unit, but the accuracy of the output directly affects the correctness of subsequent normalization shifts, thus determining the final precision and reliability of the entire multiplication operation. Incorrect prediction will lead to deviations in the normalization shift direction or the number of bits, resulting in a loss of precision. Therefore, despite being a prediction, its algorithm design must be extremely rigorous, covering all possible input combinations to ensure prediction accuracy in the vast majority of cases.

[0071] For example, the parallel prediction module 120 can be composed of a series of dedicated combinational logic circuits that directly perform logical operations on the bits of the two input mantissas, supplemented by a structure such as a priority encoder, to ultimately output a fixed-length binary number, i.e., the effective bit information, which directly corresponds to the predicted shift amount. For example, in a scenario processing normalized numbers, the effective bit information might be a single 1-bit signal indicating whether no shift is needed or a right shift of 1 bit is required; while in a general design that needs to process denormalized numbers and support arbitrary shift amounts, the effective bit information might be a multi-bit signal capable of encoding all possible shift amounts from 0 to the mantissa width.

[0072] For example, effective bit analysis can exhibit a wide variety of approaches depending on target precision, circuit complexity, power consumption constraints, and the ability to process different input types. These approaches can be mainly summarized into the core paths of fast interval judgment based on the high-order bits of the input mantissa, logarithmic field approximation based on leading zero prediction, accurate prediction based on partial product prefix analysis, and pattern matching based on lookup tables. Each method makes a unique trade-off between precision, speed, and area.

[0073] For example, the logarithmic field approximation method based on leading zero prediction is a more general and mathematically sound approach that is applicable not only to normalized numbers but also handles multiplication operations involving denormalized numbers well. Specifically, there is an approximately linear relationship between the number of leading zeros and the binary logarithm of a binary number, and multiplication can be transformed into addition in the logarithmic field. Therefore, the parallel prediction module 120 can calculate the approximate binary logarithms of the two input operands in parallel. For denormalized numbers, the number of leading zeros in the mantissa is directly calculated. Subsequently, the approximate logarithms of the two operands are added to obtain the approximate logarithm of the product. From this sum, the approximation of the product can be deduced, thus predicting the shift amount required for normalization. This method can cover the entire range from extremely small denormalized numbers to extremely large normalized numbers, with high prediction accuracy.

[0074] For example, the precise prediction method based on partial product prefix analysis is a highly accurate strategy that can predict the leader bit by analyzing the overall state of the partial products generated during multiplication before the final product is generated from the floating-point operation. Specifically, the floating-point device uses Wallace trees or Dadda trees to compress the partial products. While this compression process is underway, a prefix analysis network can run in parallel. This network does not calculate specific bit values, but rather analyzes the final impact of the carry propagation chains that may be generated in each column of the partial product matrix. It infers the possible states of the bits near the most significant bit of the final product through a prefix operation similar to that in a parallel prefix adder. This method can obtain extremely reliable leader bit predictions before the floating-point operation output stabilizes, achieving almost zero error. However, the cost is the introduction of very complex additional circuitry, so it can only be used in high-end processors with extreme performance requirements.

[0075] For example, lookup table-based pattern matching is a more effective method in certain scenarios. It combines the high-order bits of the two input mantissas as an address to look up a pre-compiled lookup table that stores values ​​corresponding to various input combinations. As long as the lookup table is large enough, it can remember and accurately handle various complex nonlinear boundary cases, providing very accurate predictions. However, for mantissas with larger bit widths, the required storage capacity becomes larger, occupying a larger chip area. Therefore, this method can be used in some application-specific integrated circuits with narrow mantissa bit widths for specific applications.

[0076] For example, a fast interval judgment method can be used as the main path to handle most common cases, while a simple backup path based on leading zero prediction can be used to cover the boundary cases where the input is unnormalized or the interval judgment method is uncertain. An arbitration logic is used to ultimately select which prediction result to use. Alternatively, in a design based on partial product prefix analysis, in order to reduce circuit complexity, only the highest few rows of the partial product matrix may be accurately analyzed, while ignoring the slight influence of carry generated by the lower bits on the highest bits, thereby controlling costs while ensuring extremely high accuracy.

[0077] Understandably, complete mantissa multiplication is a computationally extremely deep process. For example, multiplying two 24-bit significant numbers requires generating hundreds of partial products, compressing them through a multi-level adder tree, and finally passing through a carry-passing adder that may span 24 or even more bits to produce the final 48-bit product. This data path involves numerous logic gate levels, and the signal needs to pass through dozens of gate delays to stabilize, making it the most time-consuming part of the entire floating-point multiplication operation. Significant bit analysis, however, does not calculate the exact value of the product but predicts the position of the highest non-zero bit of that exact value. This is metadata with far less information than the complete product. Therefore, it is entirely possible to obtain this information in advance by constructing a dedicated shortcut path with a much shallower computational depth.

[0078] For example, parallelism between multiplication and significant bit analysis can be achieved based on a rapid estimation of the higher-order bits of the input operands. Only the most significant bits of the two input mantissas need to be considered, as these higher-order bits are crucial to the integer part and the highest few decimal places of the product. A specially designed combinational logic circuit can directly perform logical operations and a rough range determination on these two sets of higher-order bits. For instance, it checks if both operands are greater than or equal to 1.5. If so, their product must be greater than 2.25, thus determining that the final product format must be "1x.xxxx...", requiring a right shift of one bit. This determination requires only a few logic gate levels, making it much faster than a complete floating-point arithmetic device.

[0079] For example, parallelism between multiplication and significant bit analysis can be achieved based on advance partial product analysis. That is, a parallel, simplified prediction engine starts working at the same time as the main floating-point arithmetic unit begins partial product compression. The prediction engine may only focus on the highest few rows of the partial product matrix, or use a modified, more aggressive prefix network to quickly analyze the propagation trend of the carry chain, thereby predicting the state of the highest bit before the final summation is completed. Although this method is more circuitically complex than the method based on high-bit estimation, it has higher prediction accuracy, especially in handling tricky cases with boundary conditions.

[0080] For example, parallelism between multiplication and significant bit analysis can be achieved based on mathematical approximations, such as operations in the logarithmic domain. This is because the logarithm of the product of two numbers is approximately equal to the sum of their individual logarithms, and the integer part of the binary logarithm of a number is directly related to the number of its leading zeros (or leading ones). Therefore, two parallel, very fast approximate logarithm calculation units can be designed. For example, a simple estimate can be made by calculating the number of leading zeros of the input mantissa itself and combining it with its exponent. Then, these two approximations are added together, and the approximate exponent and normalized shift of the product are deduced from the sum. This path completely avoids complex multiplication arrays, and its latency mainly comes from two fast approximation calculations and a short-bit-width adder.

[0081] For example, in order to achieve parallelism, in terms of hardware architecture, multiplier 110 and parallel prediction module 120 are physically two independent circuit units that simultaneously obtain the same operand mantissa from the input register at the beginning of the same clock cycle, and then each start a segment of calculation. Moreover, regardless of the input data, the delay of valid bit analysis is shorter than that of mantissa multiplication.

[0082] The mantissa normalization step of the first normalization processing module 130 can be performed by a barrel shifter based on the significant bit information, adjusting the mantissa of the preliminary calculation result to the range [1.0, 2.0). However, when the mantissa is shifted right, some lower-order bits are shifted out. These shifted-out bits are not directly discarded; the hardware accurately captures these bits and classifies them as the least significant bit (LSB) itself, the immediately following guard bit, and the sticky bit formed after ORing all the lower-order bits. These three bits are the decision basis for subsequent rounding operations.

[0083] Rounding is a crucial step in ensuring the output is both accurate and meets the target precision. It involves checking these three bits using the nearest even rounding rule. If the guard bit is 0, the bit is discarded (round down). If the guard bit is 1 and the sticky bit is 1 or the LSB is 1, the bit is rounded up (round up). If the guard bit is 1, the sticky bit is 0, and the LSB is 0, the bit is rounded towards even numbers (i.e., the LSB is 0), potentially creating a carry in the least significant bit of the mantissa that propagates forward along the mantissa. The most critical case is when the mantissa itself is all 1s (i.e., 1.111...1), and the rounding operation requires a carry. This carry will cause the mantissa to become 10.000...0, thus violating the newly established normalized form. Therefore, the system has the capability to handle overflow caused by rounding, which triggers post-rounding normalization in the entire normalization process. The detection circuit will find that the mantissa has become in the form of 10.xxx... and immediately initiate an additional right shift operation of 1 bit. After this possible second normalization shift, the mantissa finally stabilizes in the form of 1.000...0. At the same time, at the end of the entire process, there is a final check to process the sign of the result (determined by XORing the input sign bit) and to comprehensively handle all possible abnormal situations.

[0084] refer to Figure 3 , Figure 3 This is a second structural schematic diagram of a floating-point arithmetic device provided in another embodiment of this application. In the floating-point arithmetic device provided in one embodiment of this application, the parallel prediction module 120 includes an operand analysis unit 310 and an offset calculation unit 320.

[0085] Operand analysis unit is used to determine whether an operand is a denormalized number;

[0086] The offset calculation unit is used to calculate the leading bit offset based on the mantissa of the denormalized operand.

[0087] For example, the leading bit offset can represent the final result produced by the parallel prediction module 120. Essentially, it is a multi-bit wide binary control signal whose value encodes the prediction result for the most significant non-zero bit position of the mantissa product that has not yet been formally calculated, and directly indicates the shift direction and amount required by the subsequent normalization shifter. Prediction defines the fundamental attribute of this value; it is a predicted value calculated in advance based on the characteristics of the input operand through a preset algorithm model. In the circuit, the prediction occurs while the mantissa calculation is still in progress. Secondly, the leading bit precisely points to the specific target object of the prediction action, namely the leading bit; in binary floating-point numbers, it specifically refers to the first bit with a value of 1 encountered when scanning from the most significant bit to the least significant bit in the binary representation of the mantissa product. Locating this leading 1 is the primary task in the floating-point normalization step, because the goal of normalization is to shift left and right so that this leading 1 is exactly located to the left of the binary decimal point, thus forming the standard format "1.xxxx...". Finally, the number represents the output carrier and output format. The leading bit offset can be a specific digital quantized value that can be directly understood and used by the hardware circuit. It can be a binary code with a fixed number of bits, or a single-bit signal. For example, 0 represents a predicted product format of 1.xxx..., which does not require shifting or shifts left by 0 bits, and 1 represents a predicted product format of 1x.xxx..., which requires shifting right by 1 bit. Or it can be a multi-bit field. For example, a 5-bit binary number can represent a shift amount from 0 to 31. Part of the encoding range represents no shift, another part represents a right shift of 1 bit, and most of the encoding represents a left shift of 1 to 30 bits to eliminate leading zeros.

[0088] Understandably, for input floating-point numbers, when a normalized number and a denormalized number are input, assuming src0 = 6.0 (normalized number, hexadecimal 0x40C00000, exponent 130, mantissa 1.5) and src1 = 0.25 (denormalized number, hexadecimal 0x3E800000, exponent 0, mantissa 0.01), multiplier 110 first preprocesses the denormalized number src1, checking that its mantissa has 2 leading zeros, shifting it left by 2 bits to obtain the significant number 1.0, and adjusting the exponent to -126; then, it calculates the exponent in parallel: 130 + (-126) - 127 = -123, and calculates the mantissa as 1. 0.5 × 1.0 = 1.5 (1.1 in binary); The parallel prediction module 120 needs to consider the large exponent characteristics of the normalized number and the small numerical influence of the denormalized number at the same time. By analyzing the difference in exponents and the mantissa distribution of the two operands, it accurately predicts that although the mantissa of the product is normal, the exponent -123 is lower than the minimum exponent of the normalized number -126, so denormalization is required; Therefore, the leading bit offset value is generated to shift right by 3 bits, because -126 - (-123) = -3. After the multiplication is completed, the barrel shifter shifts the mantissa 1.1 right by 3 bits to get 0.0011, sets the exponent to -126, and outputs an accurate denormalized result.

[0089] Based on this, the prediction logic of the parallel prediction module 120 can dynamically adapt to different numerical characteristics, accurately balancing the mutual influence of large exponents and small values ​​in mixed multiplication. Furthermore, these prediction decisions are completed within extremely short time windows, maintaining strict synchronization with the main multiplication operation, avoiding any erroneous predictions that could lead to normalization shift errors, resulting in loss of accuracy or even complete error in the result.

[0090] For example, the operand analysis unit 310, as the front-end perception unit of the parallel prediction module 120, is used to identify the type and extract features of the input operands, quickly and accurately determining the denormalized floating-point numbers in the input stream. This determination directly affects the selection of subsequent prediction strategies and the scheduling of computation paths, and is a prerequisite for the correct operation of the entire parallel prediction system. The hardware of the operand analysis unit 310 can be based on a deep analysis of the IEEE 754 floating-point standard, constructing a multi-level parallel detection network to capture the digital fingerprint of denormalized numbers in real time. Based on the unique characteristics of denormalized numbers in binary encoding—an all-zero exponent field and a non-zero mantissa field—the detection logic can be implemented using combinational circuits.

[0091] Specifically, refer to Figure 4 , Figure 4This is a schematic diagram of the third structure of a floating-point arithmetic device provided in one embodiment of this application. The operand analysis unit 310 can be composed of three cooperating sub-detection units, including an exponent field all-zero detector, a mantissa field non-zero detector, and a result synthesis logic. The exponent field all-zero detector is used to determine whether all bits of the exponent part of each input operand are zero. For single-precision floating-point numbers, it is necessary to detect whether each bit of the 8-bit exponent field is 0, which can be easily achieved by a multi-input NOR gate. When all exponent bits are 0, logic 1 is output. At the same time, the mantissa field non-zero detector detects whether there is a 1 in the mantissa part. It requires a multi-input OR gate to traverse all mantissa bits. As long as there is a mantissa 1, logic 1 is output. The result synthesis logic performs an AND operation on the outputs of the two detectors. The operand is confirmed to be a denormalized number only when the exponent field is all zero and the mantissa field is non-zero at the same time. In addition, several boundary cases and performance optimizations need to be considered. First, the operand analysis unit 310 needs to distinguish between denormalized numbers and true zero, because true zero also has the characteristic of all zero exponents, but its mantissa is also all zero. Therefore, this situation needs to be excluded in the synthesis logic. Second, in order to support multiple floating-point formats, the detection circuit needs to have configurable bit-width processing capability, which can be achieved through parameterized design.

[0092] In addition to basic detection, the operand analysis unit 310 also integrates a pattern prediction function. By analyzing the specific tail value of the denormalized number, it estimates the impact on the order of magnitude of the final product. For example, multiplying a denormalized number with a tail of 000...001 by a normalized number is very likely to result in the product still being in the denormalized range. This predictive information is crucial for the subsequent selection of normalization strategies. The operand analysis unit 310 also needs to interact with the anomaly handling unit. When multiple denormalized numbers are detected or when denormalized numbers are mixed with special values, the corresponding anomaly handling process can be triggered in advance. The operand analysis unit 310 introduces a scan chain and a boundary scan unit to facilitate fault detection and diagnosis during the manufacturing process. The output of the entire operand analysis unit 310 can be a multi-bit state vector, which not only indicates whether there are denormalized numbers, but also includes the specific type information of each operand, an approximate order of magnitude estimate of the mantissa, and a confidence index. This provides a decision basis for the subsequent offset calculation unit 320, ensuring that the entire multiplier analysis system can make a fast and accurate response when faced with various complex input patterns, and ultimately achieve optimal performance of the floating-point arithmetic device while maintaining standard compliance.

[0093] For example, the mechanism by which the operand analysis unit 310 determines the denormalized floating-point number in the input floating-point number is based on logical condition judgment. This goal is achieved through a hierarchical detection process. In the lowest bit-level detection, the operand analysis unit 310 simultaneously monitors the exponent field and mantissa field of the two input operands and independently verifies three basic conditions for each operand, including verifying whether all bits in the exponent field are logic 0, verifying whether the mantissa field is not all zero, and excluding the special case of zero value. The result of the logical AND operation of these three conditions is the final judgment of the normalized number of the operand.

[0094] However, the determination process involves more than simple logical operations; it also requires handling a series of complex boundary cases and architectural optimizations. In floating-point systems that support asymptotic underflow, the operand analysis unit 310 also needs to distinguish between denormalized numbers and denormalized results, requiring the detection logic to trace the historical state of the data. For designs that support multiple rounding modes, the detection timing needs to be coordinated with the rounding decision point to avoid misjudgments due to timing deviations. In superscalar processors, multiple multiplication instructions may enter the pipeline simultaneously, and the operand analysis unit 310 must have multiple sets of parallel detection capabilities and be able to correctly handle the data dependencies between operands. When a denormalized number is detected, the operand analysis unit 310 also needs to further analyze its numerical characteristics to support subsequent optimizations. For example, it can quickly estimate the order of magnitude of the denormalized number using a leading zero predictor, or determine whether it belongs to a common special value using a mantissa pattern recognizer. For architectures that support floating-point anomaly accumulation, specific status flags need to be set when a denormalized number is detected. In power-sensitive applications, the operand analysis unit 310 will adopt an on-demand activation strategy, activating the complete analysis circuit only when an exponent domain anomaly is initially detected.

[0095] For example, the offset calculation unit 320 predictively infers the position of the leading bit of the product before the mantissa multiplier completes its calculation by constructing a prediction network parallel to the main multiplication data path. (See reference) Figure 4The hardware implementation of the offset calculation unit 320 integrates computer arithmetic, digital circuit design, and pattern recognition technologies, and can include three cooperating sub-units: an input feature extraction unit, a prediction algorithm execution unit, and a result encoding output unit. The input feature extraction unit receives classified operand information from the operand analysis unit 310 and deeply mines its numerical features. For normalized numbers, it extracts the high-order significant word of the mantissa and calculates the run length of consecutive 1s or 0s in the mantissa, which helps predict carry propagation behavior during multiplication. For denormalized numbers, the input feature extraction unit obtains its leading zero count and the approximate value after normalization shift, thereby estimating its true order of magnitude. The prediction algorithm execution unit employs multiple parallel prediction strategies to cover different numerical scenarios. The most important strategies include an interval prediction method based on high-order product, which uses a simplified multiplier to calculate only the product of the highest 4-5 bits of the mantissa of the two operands. From the integer part of this abbreviated product, it can reliably predict whether the complete product falls within the interval [1,2) or [2,4). Another strategy is a prediction method based on logarithmic approximation. The approximate binary logarithm of the two mantissas is quickly calculated using a lookup table or combinational logic. The logarithms are then added together and back-calculated into the linear domain to estimate the range of the product. For cases involving denormalized numbers, the prediction algorithm execution unit initiates leading zero prediction logic based on the exponent difference, estimating the number of leading zeros that may appear in the product by analyzing the exponent difference between the two operands. The result encoding output unit converts the final prediction into a standardized leading bit offset value. This value is usually a fixed-width binary code. For example, in a design that supports single-precision floating-point numbers, a 5-bit leading bit offset field can encode 32 different shift cases: 0 indicates no shift, 1 indicates a right shift of 1 bit, and 2-31 indicate a left shift of 1-30 bits. To ensure reliability, the result encoding output unit also generates a confidence index for decision-making reference in subsequent stages when multiple prediction results occur.

[0096] For example, the offset calculation unit 320 also integrates a self-calibration mechanism, which dynamically adjusts internal parameters to adapt to different operational characteristics by comparing historical predictions with actual results. In terms of physical implementation, the prediction algorithm is mapped to a multi-level combinational logic network, which minimizes critical path latency through logic compression technology, while using transistor-level optimization to balance speed and power consumption, so that the offset calculation unit 320 can provide accurate normalized instructions before the main floating-point arithmetic device completes the calculation.

[0097] For example, the offset calculation unit 320 obtains the type identifier, exponent value, and mantissa pattern of each operand from the operand analysis unit 310, and then initiates multi-path parallel analysis. For normalized number input, a fast prediction path based on the high-order multiplication product is adopted. The most significant bit segments of the two mantissas are extracted, and the product of the high-order segments is calculated through a simplified but fast multiplier. Although this abbreviated product has limited precision, it is sufficient to reliably indicate whether the integer part of the complete product will be 01 or 1x. If the integer part of the abbreviated product is greater than or equal to 2, it can be assured that the complete product must be in the range [2,4), and a right shift of 1 bit is required. If the integer part is 1 and the high-order product is large enough to be close to 2, it may be in a boundary case that requires a right shift. If it is clearly less than 2, the prediction does not require a shift. The hardware implementation of this path can use a Booth-encoded and compressed adder tree, which can give the prediction result within a very short delay.

[0098] Meanwhile, for inputs of denormalized numbers, the offset calculation unit 320 initiates a prediction path based on orders of magnitude estimation: first, the denormalized number is transformed into a pseudo-normalized form through leading zero counting and left shift operations, and the required normalization shift amount is recorded. Then, the sum of the significant bits of the two operands is calculated, and the exponent range of the final product is predicted by analyzing the relationship between the sum and the lower limit of the normalization exponent. If the calculated exponent is much lower than the normalization minimum, it is predicted that a large number of right shift operations are needed; if the exponent is close to or higher than the normalization range, the prediction of the mantissa product is combined to determine whether to shift left, not shift, or shift right.

[0099] Additionally, paths predicted using heuristics based on statistical patterns are quickly matched by searching a pre-stored table of common numerical patterns to operand combinations known to produce specific leader bit patterns. The results of all these predicted paths are fed into an arbiter, which selects the final prediction based on input type, path confidence, and historical accuracy data. For example, when two paths give conflicting predictions, the arbiter may prioritize the result based on high-order multiplication because it is generally more reliable when dealing with normalized numbers, or it may assign higher weight to the path based on order-of-magnitude estimation when the input is detected to include denormalized numbers.

[0100] In a floating-point arithmetic apparatus provided in one embodiment of this application, the operand analysis unit determines whether an operand is a denormalized number by detecting whether the exponent field of the operand is zero and the mantissa field is non-zero.

[0101] For example, when the parallel prediction module 120 determines the denormalized floating-point number by the exponent part of the input floating-point number, the architecture of the operand analysis unit 310 will exhibit a specialized form that is completely different from full operand analysis. The parallel prediction module 120 will become a simplified but faster exponent feature detection system. The core structure revolves around bit pattern recognition of the exponent field, completely abandoning the complex logic of monitoring the mantissa field at the same time in the traditional design.

[0102] refer to Figure 5 , Figure 5 This is a schematic diagram of the fourth structure of a floating-point arithmetic device provided in one embodiment of this application. The parallel prediction module 120 is specifically implemented to construct a two-level multi-channel exponent analysis network. The first level is a parallel exponent feature extraction layer, which consists of two completely symmetrical processing units corresponding to two input operands src0 and src1, respectively. Each unit contains three core detectors, including an all-zero exponent detector, an all-one exponent detector, and a normal range detector. The all-zero exponent detector directly determines whether all bits of the 8-bit exponent field (taking single precision as an example) are 0 through a multi-input NOR gate. The all-one exponent detector determines whether the exponent is all 1 through a multi-input AND gate. The normal range detector determines whether the exponent is between 1 and 254 (corresponding to -126 to +127 after bias representation) through combinational logic. These detectors adopt a completely parallel circuit structure to ensure that the preliminary judgment result can be output within a single gate delay.

[0103] The second level is the cross-correlation logic layer. This layer receives the detection results from two channels and generates the final classification conclusion through a decision table. When the all-zero exponent flag of either channel is valid, it immediately marks the detection of a candidate for a non-normalized number. However, since the module can only access exponent information, it cannot distinguish between true non-normalized numbers and zero values. This leads the module to adopt a conservative strategy, uniformly classifying all cases with all zero exponents as potential non-normalized numbers, and passing this uncertainty to subsequent processing stages, resulting in a loss of accuracy. The parallel prediction module 120 will incorrectly identify all zero values ​​as non-normalized numbers. Although this misjudgment will not cause functional errors because the processing of zero values ​​in multiplication operations is somewhat similar to that of non-normalized numbers, it will cause the subsequent prediction module to choose a suboptimal processing path, potentially leading to performance penalties. Therefore, a statistical compensation mechanism can be introduced to dynamically adjust the aggressiveness of subsequent processing by monitoring the proportion of zero values ​​and non-normalized numbers in historical calculations.

[0104] Operand analysis unit 310 can be adjacent to operand register and complete the parsing of exponent features in the same cycle in which data is loaded into the register, thus providing time margin for the entire multiplication pipeline. In addition, parallel prediction module 120 will output detailed exponent feature vectors, including exponent type encoding for each operand, exponent difference estimation, and anomaly warning. This information can provide valuable reference for offset calculation unit 320 even if it is incomplete.

[0105] For example, when the offset calculation unit 320 generates the leading bit offset using the mantissa of the denormalized floating-point number, the offset calculation unit 320 evolves into a prediction engine specifically designed for extremely small numerical features. This engine extracts key information from the mantissa patterns unique to denormalized numbers, sufficient to predict the normalization behavior of the multiplication result. Unlike the general-purpose prediction module, the offset calculation unit 320 no longer focuses on conventional product interval judgments, but instead concentrates its computational resources on analyzing the leading zero distribution pattern, significant bit sparsity, and magnitude characteristics of the numerical mantissa in the denormalized number.

[0106] The specific architecture of the offset calculation unit 320 can be a multi-layered denormalized number mantissa analysis pipeline. The first layer is the mantissa feature extraction layer, which performs in-depth analysis of the mantissa of the input denormalized number. This includes a high-precision leading zero counter, which uses a parallel prefix tree structure to quickly determine the number of consecutive zero bits starting from the most significant bit in the mantissa. This count directly reflects how far the denormalized number is from its normalized form. At the same time, the effective bit density analyzer will statistically analyze the distribution of 1 bits in the mantissa, especially the consecutive bit patterns after the first 1, because this pattern will affect the carry propagation during multiplication. The first layer is the product effect prediction layer, which specifically analyzes the impact of the denormalized number's mantissa on the final product when multiplied by another operand. When the other operand is a normalized number, this layer uses a simplified numerical range model to convert the leading zero count of the denormalized number into an estimate of its contribution to the product exponent. The second layer is the shift decision generation layer, which integrates and encodes the analysis results of the first two layers into specific leading bit offset values. Since the participation of denormalized numbers often leads to a left shift operation in the product, the predicted leading value is mainly a left shift bit field, with an additional direction flag bit to distinguish the very few special cases that require a right shift.

[0107] For example, the core algorithm of the offset calculation unit 320 is based on the numerical characteristics of denormalized numbers. The value of a denormalized number can be represented as m×2^(-126) (single precision), where m is a mantissa less than 1. When this number is multiplied by another number n, the product is approximately m×n×2^(-126). The task of the offset calculation unit 320 is to predict the order of magnitude of m×n through the characteristics of m, and then determine how much left shift is needed to normalize it.

[0108] Since only the case of denormalized numbers needs to be handled, the circuit of the offset calculation unit 320 can omit the complex logic for judging the product range of normalized numbers, greatly simplifying the data path. The leading zero counter can adopt a more aggressive design, minimizing the counting latency through multi-level parallel prefix optimization. The decision logic can be specialized for the numerical range unique to denormalized numbers, achieving accurate prediction with fewer comparators and logic gates. In addition, the offset calculation unit 320 can also integrate the pattern memory function of denormalized numbers, recording the best prediction value corresponding to the common denormalized number mantissa patterns through a small lookup table. When the same pattern is encountered repeatedly, the calculation can be completely bypassed and the result can be output directly.

[0109] For example, regarding the contradiction between prediction accuracy and the limited information about the mantissa of the denormalized number, since the offset calculation unit 320 can only see the mantissa of the denormalized number and has no knowledge of the other operand, it may mispredict the normalization requirement of the product when the other operand is a normalized number with a maximum value. Therefore, a conservative prediction strategy can be introduced, which tends to predict that more left shift operations are needed when the uncertainty is high, ensuring that even if the prediction is not completely accurate, it will not lead to functional errors, but may only cause a slight performance loss.

[0110] For example, the parallel prediction module 120 can be implemented using a speculation strategy based on the high-order bits of the operands. By analyzing the most significant bits of the two input mantissas, it can quickly determine which range the product will ultimately fall into. This is because whether the product of two numbers in the range [1.0, 2.0) reaches or exceeds 2.0 largely depends on whether they are both close to the upper bound of the range. For example, if the high-order bits of both mantissas show a value greater than or equal to 1.5, then the product must be greater than 2.25, thus ensuring the final format is 1x.xxxx...; if the value of at least one operand is close to 1.0, then the product is likely to remain in the range [1.0, 2.0). The hardware implementation of the parallel prediction module 120 can be accomplished through a specially designed combinational logic circuit. This circuit receives the high-order bits of the two input mantissas and outputs the prediction result within a very short delay through a series of AND, OR, and NOT gate combinations, and possibly a small lookup table. The logic depth of the entire prediction path is controlled within the critical path delay of the main floating-point arithmetic device, ensuring that the predicted value is ready before the multiplication result stabilizes. The output of the prediction result is encoded as a predicted leading 1 number. In this scenario, the predicted leading 1 number either indicates that the leading 1 is in the standard position (corresponding to the product being in the interval [1.0, 2.0), and no normalization shift is required), or indicates that the leading 1 needs to be shifted one bit to the right (corresponding to the product being in the interval [2.0, 4.0), and needs to be shifted one bit to the right for normalization). In addition, the predicted leading 1 number may also contain confidence information. When the input operand is at the boundary value, the uncertainty of the prediction is marked for reference in subsequent processing stages.

[0111] For example, when the input floating-point number includes a denormalized floating-point number, the feasibility of the mechanism of the parallel prediction module 120 is based on the unique numerical representation characteristics of denormalized floating-point numbers. The exponent field of a denormalized number is all zeros, and the mantissa field does not have an implicit leading 1. Its numerical range is in the smallest representable interval below the normalized number. When multiplied with other numbers, whether normalized or denormalized, the product may still remain in the denormalized interval or be in a subnormal range that requires special processing, making the number of leading zeros in the predicted product a key factor in determining the subsequent processing strategy.

[0112] The parallel prediction module 120 can employ a prediction strategy based on numerical order-of-magnitude analysis to accurately estimate the order-of-magnitude range of the product and the number of consecutive leading zero bits that may appear in the prediction result. The prediction of the parallel prediction module 120 is based on the special representation of denormalized numbers. The actual value of a denormalized number can be represented as (0.M)×2^(-126) (single precision), where M is a 23-bit mantissa field. When multiplied by another value N, the product is approximately (0.M)×N×2^(-126). The prediction module predicts how many bits the final product needs to be shifted left to reach the normalized form, or whether the product will remain within the denormalized range, by analyzing the characteristics of the mantissa M of the denormalized number and the approximate range of the other operand. The parallel prediction module 120 can be implemented using a specially designed hybrid analysis circuit. This circuit needs to simultaneously process the different characteristics of normalized and denormalized numbers. For denormalized inputs, the circuit initiates high-precision leading zero detection logic to accurately calculate the number of consecutive zero bits starting from the most significant bit in the mantissa. For normalized inputs, the circuit analyzes the exponent value and the high-order bits of the mantissa to estimate their contribution to the order of magnitude of the final product. Then, through a dedicated numerical range fusion unit, the characteristic information of the two operands is integrated to predict the approximate exponent value of the final product. If the predicted exponent is lower than the minimum exponent of the normalized number -126, the number of bits to be right-shifted (i.e., the number of leading zeros) is further calculated. If the predicted exponent is close to or higher than the normalized range, the mantissa product prediction is combined to determine whether a left shift operation is needed. The logical complexity of the entire prediction path is higher than that of the pure normalized number case, but its critical path delay is still controlled within the computation time of the main multiplier, ensuring that the predicted value can guide subsequent processing in a timely manner.

[0113] For example, the output of the prediction result of the parallel prediction module 120 is encoded as the number of predicted leading zeros. In this scenario, the number of predicted leading zeros is no longer a simple binary decision, but an integer value that may be in a large range, precisely indicating the number of bits that need to be shifted left in order to normalize the product result. In addition, the number of predicted leading zeros may also contain metadata such as processing direction information, result type prediction, and confidence index.

[0114] For example, the floating-point arithmetic device provided in this application embodiment can be used to execute floating-point multiplication instructions, such as SIMT (Single Instruction Multi-Thread) floating-point multiplication instructions. In one embodiment, the floating-point arithmetic device provided in this application embodiment may further include an adder, so that the floating-point arithmetic device can execute floating-point fused multiply-add instructions, such as SIMT single-instruction multi-threaded floating-point fused multiply-add instructions.

[0115] In a floating-point arithmetic apparatus provided in one embodiment of this application, the normalization processing module includes a barrel shifter, and the number of shift bits of the barrel shifter is controlled by the leading bit offset.

[0116] Understandably, the preamble offset is used to normalize the initial result after the mantissa multiplication is complete. In other words, the trigger condition for normalization is the completion of the multiplication operation, and the preamble offset may not be the trigger, but rather a pre-prepared control parameter or operation instruction waiting to be used. In synchronous digital circuit design, especially in complex data paths like floating-point arithmetic units, the operation is precisely controlled by a clock signal, much like a metronome. The entire multiplication operation, from the input operands being latched into the register to the final result being written to the output register, can be organized into a multi-stage pipeline or at least divided into several distinct timing stages. Within this timing framework, the completion of the multiplication operation can be specifically represented by the bits representing the mantissa product. After a fixed delay, calculated from the rising edge of the clock and determined by the logic depth of the floating-point arithmetic unit, the electrical signal on these bits reaches a correct and stable logic level from an initial unstable state, and this stable state meets the setup time requirements of the next stage circuit (i.e., the barrel shifter). This completion event can be physically detected by the circuit in several ways. For example, it might be automatically confirmed by timing control logic after a specific clock cycle, or in more sophisticated dynamic circuits, the floating-point unit itself might generate a completion handshake signal after the critical path stabilizes. Therefore, regardless of the specific implementation, this event can serve as a start signal to initiate subsequent operations, including normalization shifting, rounding, and result write-back. The leading bit offset is calculated in advance by the parallel prediction module 120 during the multiplication operation, and its calculation path is shorter than the main multiplication path of the multiplier 110. Therefore, while the multiplication operation is still in progress, the leading bit offset value has already stably appeared on its dedicated output line. The preamble offset eliminates waiting time. When the multiplication operation is complete, the circuit needs to activate a time-consuming preamble detector to scan the product before shifting can begin. However, since the preamble offset is already in place, once the completion signal is valid, the barrel shifter can immediately perform the shift operation based on this predicted value with almost zero delay. This allows the normalization step to be appended after the multiplication step, greatly reducing the total delay. Therefore, the completion of the multiplication operation is a timing prerequisite, indicating the precise moment when the normalization operation begins; while normalization based on the preamble offset describes that when that moment arrives, the control information upon which the actual operation depends is the preamble offset.

[0117] Understandably, the leading bit offset itself is not the primary trigger for the normalization operation. However, the final execution of the normalization operation may not simply involve mechanically performing multiplication operations on the signal and the isolated leading bit offset. Instead, it may introduce a more complex decision-making and triggering process involving the leading bit offset, other key data, and mechanisms. Because there is a small probability of error in the prediction, and the floating-point unit, as the processor's infrastructure, must guarantee the absolute correctness of the result, a multi-layered triggering and execution mechanism with verification and correction capabilities can be constructed.

[0118] For example, other key data used to trigger the normalization operation may include some immediate verification information about the product itself from the main multiplication path. By embedding lightweight monitoring circuitry in the multiplier tree, highly confident judgments about the highest few bits of the product can be generated quickly. For instance, a very fast, small carry-out detection network can determine whether the integer part is 01 or 10 shortly before the complete product stabilizes. Its fast verification result is compared with the leading bit offset. If they match, the leading bit offset can be used directly to control the barrel shifter when the multiplication completion signal arrives, achieving enhanced triggering of the leading bit offset plus the fast verification consistency signal.

[0119] When an inconsistency occurs, i.e. when the fast verification circuit detects a possible error in the prediction, the combination of the preamble offset and the verification failure signal will trigger a completely different operating mode. In other words, in this case, the potentially incorrect prediction value will not be used. Instead, an alternative path may be initiated, which may be slightly slower but guarantees correctness. For example, a precise but slightly delayed preamble detector may be triggered to start working. This detector scans the already stable 48-bit product, overwrites the preamble offset with the result, and then performs normalization. Although some penalty cycles are introduced here, correctness is guaranteed.

[0120] The predict-verify-execute pipeline can also be used to trigger normalization operations. The normalization operation may still be initiated based on the predicted value in the same cycle as the multiplication operation, but the verification circuit is also working at the same time. If the subsequent verification fails, the pipeline flushing and re-execution mechanism is triggered, discarding the erroneous result and recalculating. In this case, the preamble offset plus the verification failure signal does not trigger the normalization operation itself, but an error recovery process.

[0121] The signal output by the processing logic for special input cases can also be used to trigger normalization operations. For example, when processing the multiplication of denormalized numbers, if the exponent of the input operand is very small, it may cause the product exponent to underflow severely, making the normalization operation no longer a simple left or right shift by one bit, but requiring complex exponent adjustment and mantissa processing. In this case, the module used to process special values ​​may generate an overlay signal. This signal, combined with the leading bit offset, will actually correct or replace the meaning of the leading bit offset, instructing the barrel shifter to perform a non-standard shift operation, or bypass the regular normalization path to enter a special processing flow. At this time, it can be said that the leading bit offset + the exponent underflow abnormal signal jointly trigger another set of normalization (or denormalization) processing logic.

[0122] Based on this, the top-level trigger for initiating the entire normalization operation is the multiplier operation completing this event. However, the final formation of the control word at this level can be a selection or arbitration result of multiple inputs. This final control word may originate from the default leader offset from the parallel prediction module 120; or from the correction value from the backup leader detector when prediction fails; or from a special code provided by the exception handling unit indicating that no shift or fixed shift is required when special cases such as a result of zero, infinity, or NaN are detected. The final control value is selected by a multiplexer according to priority (e.g., exception is the highest, correction is the second highest, and prediction is the lowest).

[0123] In one embodiment of the floating-point arithmetic apparatus provided in this application, the floating-point arithmetic apparatus further includes an exponent calculation module 140, which is used to calculate the exponent of the product result based on the exponents of the first floating-point operand and the second floating-point operand, the leading bit offset, and the offset value of the floating-point format.

[0124] The result synthesis module 150 is used to combine the first normalized mantissa result, the product result exponent, and the product sign bit determined by the sign bits of the first floating-point operand and the second floating-point operand, and output the floating-point multiplication result.

[0125] In one embodiment, the parallelism optimization of the entire operation process of multiplier 110 is reflected in multiple dimensions. Among them, the parallel processing of the exponent path and the mantissa path shortens the critical path; the partial product generation and compression inside the mantissa multiplier achieve bit-level parallelism, enabling multiplier 110 to maintain strict timing constraints.

[0126] Understandably, multiplier 110 performs multiplication on the mantissas of the first and second floating-point operands. The initial characteristics of the preliminary result stem from the multi-stage nature of floating-point multiplication; the hardware needs to obtain an intermediate product before subsequent precision optimization and format standardization. Specifically, the exponentiation unit and mantissa unit of multiplier 110 process different parts of the floating-point number. The exponentiation unit is used to calculate the exponent base of the result, while the mantissa unit performs large-scale fixed-point multiplication. The two units work precisely in timing to jointly construct the framework of the preliminary result.

[0127] The exponentiation operation starts with the exponents of the two operands extracted from the front end. After performing integer addition, a fixed bias value for the floating-point format is subtracted. Taking IEEE 754 single-precision floating-point numbers as an example, the 8-bit exponent field is represented using a 127 bias code. Therefore, the calculation process is: Result Exponent = Exponent A + Exponent B - 127. When the input includes denormalized numbers, the exponent must be adjusted to 1 instead of 0 according to the specification. At the same time, the hardware must detect exponent overflow (result exceeding 255) or underflow (result less than 0) and mark it for subsequent processes. Mantissa multiplication concurrent with exponentiation involves fixed-point multiplication of two mantissas with implicit leading bits. The actual mantissa of the normalized number is in the form of 1.M, so multiplying 24 significant digits (1 implicit bit + 23 decimal bits) will produce a 48-bit product. This can be achieved by constructing a compressed architecture such as a Wallace tree or Dadda tree. For example, first, a carry-preserving adder array is used to quickly generate a partial product, then a multi-level adder tree is used to compress the partial product into two vectors, and finally, a carry-passing adder is used to output the standard result. It is worth noting that the 48-bit product at this point still retains its original form, and its integer part may be in three states: 01.xx..., 10.xx..., or 11.xx... It has not yet been aligned with the normalized format, i.e., the preliminary calculation result. This preliminary calculation result, together with the calculated exponent base, constitutes the framework of the intermediate floating-point number.

[0128] Based on this, the multiplier 110 can focus on achieving high-speed arithmetic calculations, while delegating the precision optimization task to subsequent dedicated modules. In particular, in the fused multiply-add architecture, when performing the A×B+C operation, the intermediate product generated by the multiplier 110 can be directly fed into the adder as a high-precision operand, avoiding the precision loss caused by double rounding.

[0129] For example, after normalizing the preliminary calculation result, the multiplication result output by the floating-point arithmetic unit can be a normalized number, that is, the final multiplication result output by the floating-point arithmetic unit becomes a normalized number that strictly conforms to the IEEE 754 standard. First, normalization begins with the parallel computation of the exponent path. While the mantissas are multiplied, the exponent calculation unit receives the exponents of the two operands and performs the operation of exponent A + exponent B - exponent bias. The calculated preliminary exponent value is adjusted in conjunction with the normalization shift operation of the mantissa. When the effective bit information indicates that the mantissa needs to be shifted right by 1 bit, the preliminary exponent must be added by 1 to compensate for the doubling requirement caused by the halving of the mantissa value due to the right shift, thereby maintaining the mathematical equivalence of the entire floating-point value. If the prediction indicates that the mantissa needs to be shifted left by N bits, the preliminary exponent must be subtracted by N to ensure that the final result can be represented as a normalized number, ensuring that no matter how the mantissa is scaled to conform to the format 1.xxxx..., the value represented by the overall exponent-mantissa combination is still correct.

[0130] For example, refer to Figure 6 , Figure 6 This is a fifth structural schematic diagram of a floating-point arithmetic device provided in one embodiment of this application. The floating-point arithmetic device also includes an exponent operation module 140, a result synthesis module 150, an operand decomposition module 160, a special value processing module 170, and a rounding module 180. The operand decomposition module 160 is used to extract the sign bit, exponent part, and mantissa part of the input floating-point numbers src0 and src1 respectively through the getsign, getexp, and getmant modules.

[0131] For example, the operand decomposition module 160 is used to perform structural parsing and field extraction on the two input floating-point operands src0 and src1. Through in-depth understanding and hardware adaptation of the IEEE 754 standard floating-point format, the operand decomposition module 160 can be completed collaboratively by three parallel sub-modules. Among them, the getsign module is used to extract the sign flag from the highest bit of the 32-bit single-precision or 64-bit double-precision floating-point number, which determines the mathematical sign attribute of the final result. This can be accomplished by directly connecting to the highest bit pin of the input vector, but it is necessary to ensure that this sign information can be strictly synchronized with the corresponding data channel in the subsequent pipeline. The getexp module is used to extract the exponent field. For single-precision floating-point numbers, it is necessary to accurately isolate the 8 bits from bits 30 to 23. The exponent encoding, these 8 unsigned integers, not only represent the magnitude of the value but are also the primary basis for detecting special values ​​and denormalized numbers. This submodule can be composed of a multiplexer and bit concatenation logic. It needs to handle the pre-adjustment of the exponent bias and provide a clean input source for the subsequent exponent calculation unit. The getmant module needs to parse the mantissa from the remaining 22 bits (single precision) or 51 bits (double precision) of the low-order field. When the exponent field is detected to be non-zero and not all 1s, the module will automatically add a logic 1 before the highest bit of the mantissa, thereby expanding the actual effective bit width of the normalized number to 23 bits or 52 bits. When the exponent is all zero, it is determined to be a denormalized number, the mantissa remains unchanged and the implicit bit is 0, so that the subsequent mantissa calculation can process all types of valid numbers with a unified interface. The circuit implementation of the entire operand decomposition module 160 needs to optimize the timing path to ensure that the outputs of the sign, exponent, and mantissa channels are strictly aligned in time. Therefore, register retiming and pipeline technology can be used to balance the delay of each path.

[0132] For example, the floating-point arithmetic device also includes a special value processing module 170, which is used to detect and process special values ​​of floating-point numbers, including infinity, zero, and NaN.

[0133] For example, the special value processing module 170 detects abnormal patterns in the input data in real time by constructing a monitoring network that works in parallel with operand decomposition. The detection logic of the special value processing module 170 is based on the strict definition of the floating-point standard. When it detects that the exponent field of an operand is all 1s and the mantissa field is all 0s, it identifies the operand as infinity and distinguishes it as positive infinity or negative infinity based on its sign bit. When the exponent field is all 1s but the mantissa field is non-zero, it is confirmed as Not a Number (NaN). Here, it needs to be further distinguished as signaled NaN and silent NaN. Signaled NaN will trigger the exception handling process, while silent NaN will be directly propagated in the operation. When the exponent field is all 0s and the mantissa field is also all 0s, it is determined to be a zero value, which also needs to be distinguished as positive zero and negative zero. The detection of special values ​​can be implemented through multi-level combinational logic circuits. A multi-input AND gate is used to detect all 1s in the exponent field, and a multi-input NOR gate is used to detect all 0s in the mantissa field. Then, specific logic gate combinations are used to generate flag signals for various special values.

[0134] For example, the special value processing module 170 can not only be used for detection, but also, according to the floating-point arithmetic standard, when any operand is NaN, regardless of the value of the other operand, the result should return NaN, with priority given to returning semaphore NaN; when infinity is multiplied by zero, the result should be NaN; when two infinitys of the same sign are multiplied, the result is positive infinity, and when they have different signs, the result is negative infinity; and the result of multiplying zero by zero should be standard positive zero. The output of the special value processing module 170 can be a multi-bit status code indicating the special state category of the current operand combination, and a global special operation activation signal. When this signal is activated, it will take over the control of the entire floating-point arithmetic device, causing the regular mantissa multiplication and exponent calculation units to enter bypass mode, directly generating the sign, exponent, and mantissa fields of the final result according to predefined rules.

[0135] For example, the operand decomposition module 160 provides the data foundation for regular numerical calculations, while the special value handling module 170 ensures robustness and standard compliance even when encountering boundary conditions. Both modules need to consider power optimization strategies in the processor. By using gated clocks and operand isolation techniques, the clock and signal switching of regular computing units are promptly shut down when special values ​​are detected, thereby avoiding unnecessary dynamic power consumption. The latency of the entire front-end processing system directly affects the initial throughput of the floating-point arithmetic unit. Therefore, predictive execution techniques and early arbitration mechanisms can be used to initiate the prediction process for some special values ​​before operand decomposition is completed. This allows the floating-point arithmetic unit to achieve extremely high throughput performance, completing one multiplication operation per clock cycle while maintaining standard compliance.

[0136] For example, the floating-point arithmetic device further includes a rounding module 180, which is used to perform even rounding on the preliminary arithmetic result after normalization operation through valid bit information.

[0137] For example, when the normalized mantissa is ready to enter the rounding stage, its bits are divided into three regions: the most significant bit (including the implicit leading 1 and the subsequent precise mantissa bits), a guard bit, and a sticky bit formed by a logical OR operation of all lower significant bits. These three bits together constitute the complete information basis for the rounding decision. The guard bit carries the information of the most significant bit in the truncated part, equivalent to the first decimal place in decimal, while the sticky bit records whether there is any non-zero information in all lower significant bits, equivalent to indicating whether there are any significant digits after it. When the even rounding algorithm handles the middle case where the guard bit is 1 and the sticky bit is 0, it does not simply carry over. Instead, it checks the least significant bit (LSB) of the determined reserve. If the bit is 1, it carries over to make it 0 (moving closer to an even number). If the bit is 0, it discards the bit to maintain the even number state. This ensures that rounding errors can cancel each other out in a large number of statistical operations, avoiding the systematic deviations that may be caused by traditional rounding.

[0138] For example, the hardware circuit of rounding module 180 includes a multiplexer network and a carry propagation chain. When the guard bit is detected to be 1 and the sticky bit is also 1, an unconditional round-up operation is performed. The carry may propagate forward along the mantissa bits. In the most extreme case, the mantissa may change from an all-1 state to 10.00...0, triggering the rounding normalization requirement. At this time, the circuit starts an additional right shift operation. Since the carry propagation path directly determines the critical path delay of rounding module 180, the processor can use a parallel prefix tree structure to accelerate carry calculation, and at the same time use conditional selection logic to predict the carry result in advance, ensuring that all rounding decisions are completed within a single clock cycle. It is worth noting that rounding module 180 also needs to handle various boundary conditions. In this case, it needs to return an infinite result according to the standard, or when processing results in a non-normalized number range, the rounding behavior needs to take into account the precision loss characteristics of gradual underflow. The implementation of rounding module 180 also needs to cooperate with the exception flag generation circuit. When inaccurate rounding is detected, the corresponding status register bits need to be set to provide necessary system support for floating-point exception handling.

[0139] For example, the floating-point arithmetic device also includes a result synthesis module 150, which is used to recombine the processed sign bit, the calculated exponent, and the rounded mantissa to generate a floating-point multiplication result that meets the target precision, thus completing the entire multiplication operation process.

[0140] For example, the result synthesis module 150 first receives the processing results from different paths: the final result sign obtained from the sign calculation unit, the exponent value with compensated normalized shift obtained from the exponent adjustment path, and the final determined mantissa output from the rounding module 180. The synthesis process can perform bit splicing according to the bit width specification of the target precision. For single-precision floating-point numbers, it is necessary to accurately combine 1 bit sign, 8 bits exponent and 23 bits mantissa into a 32-bit output word. Here, because the sign, exponent and mantissa may go through processing paths of different lengths, pipeline balancing technology is used to ensure that they arrive at the synthesis point at the same time. The result synthesis module 150 also includes final quality check logic to verify whether the recombined floating-point number meets all format requirements, especially to ensure that the exponent of the normalized number is not in the reserved range of 0 to 255 (single precision), and to check whether the mantissa part retains the correct implicit bit handling after rounding; when an exponent overflow (exceeding the maximum value) is detected, an infinity with an appropriate sign should be returned according to the standard; when an exponent underflow (below the minimum value) is detected, a signed zero or a denormalized number should be returned.

[0141] For example, the output stage of the result synthesis module 150 also needs to handle interface protocols with other units of the processor, including ready signals, valid data flags, and possible error status outputs. In the processor, the output of the floating-point arithmetic unit needs to be written to the reordering buffer or directly committed to the register file, requiring the result synthesis module to cooperate with the instruction commit logic to stably output the calculation results at specific clock edges. The implementation of the result synthesis module 150 also needs to consider testability and observability requirements. Scan chains and observation points can be inserted at the output end to facilitate manufacturing testing and post-silicon debugging. In floating-point arithmetic units that support multiple floating-point formats, the result synthesis module 150 also needs to include format conversion logic, which can convert the internally unified high-precision intermediate results into the target precision output format according to the instruction requirements. Power management can be achieved through clock gating and operand isolation techniques to ensure that the relevant circuits are activated only when the output results are actually needed, avoiding unnecessary dynamic power consumption. In addition, the result synthesis module 150 also needs to be fully integrated with the processor's exception architecture. When any invalid operation, division by zero, overflow, underflow, or inaccurate exception is detected, the corresponding status flags can be accurately set, and complete context information can be provided for possible exception handling programs.

[0142] One embodiment of this application provides a floating-point fused multiply-accumulate arithmetic device, comprising:

[0143] In any of the above embodiments, the floating-point arithmetic device is used to perform a multiplication operation on the first floating-point operand and the second floating-point operand, and output the first normalized mantissa result and the corresponding product result exponent;

[0144] The operand alignment module is used to align the exponent of the first normalized mantissa result with the mantissa of the third floating-point operand.

[0145] The mantissa addition module is used to add the aligned first normalized mantissa result to the mantissa of the third floating-point operand to obtain the intermediate mantissa sum;

[0146] The second normalization module is used to normalize and round the intermediate mantissas to obtain the second normalized mantissa result.

[0147] In one embodiment of this application, the floating-point fused multiply-accumulate arithmetic device further includes a multiply-accumulate exponent processing module, which is used to calculate the fused multiply-accumulate exponent based on the product result exponent, the exponent of the third floating-point operand, and the secondary offset generated by normalizing the intermediate mantissa.

[0148] The multiply-accumulate result synthesis module is used to combine the second normalized mantissa result, the fused multiply-accumulate result exponent, and the fused multiply-accumulate sign bit determined according to the sign bits of the first, second, and third floating-point operands, and output the floating-point fused multiply-accumulate result.

[0149] refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of a floating-point fusion arithmetic device provided in one embodiment of this application. The floating-point fusion arithmetic device includes a floating-point arithmetic device, an operand alignment module, a mantissa addition module, a second normalization processing module, a multiplication-addition exponent processing module, and a multiplication-addition result synthesis module.

[0150] like Figure 8 As shown, Figure 8 This is a flowchart of a floating-point arithmetic method provided in one embodiment of this application. The floating-point arithmetic method may include, but is not limited to, steps S110, S120 and S130.

[0151] Step S110: Perform a multiplication operation on the mantissas of the first floating-point operand and the second floating-point operand to obtain the mantissa product;

[0152] Step S120: Executed in parallel with the multiplication operation, based on the effective bit information of the first floating-point operand and the second floating-point operand, the leading bit offset of the mantissa product is predicted;

[0153] Step S130: Shift the mantissa product according to the leading bit offset to obtain the first normalized mantissa result.

[0154] In one embodiment of the floating-point arithmetic method provided in this application, the arithmetic method may also include, but is not limited to, steps S140 and S150.

[0155] Step S140: Calculate the exponent of the product result based on the exponents of the first and second floating-point operands, the leading bit offset, and the offset value of the floating-point format.

[0156] Step S150: Combine the first normalized mantissa result, the product result exponent, and the product sign bit determined by the sign bits of the first and second floating-point operands into a floating-point multiplication result.

[0157] It is understood that the arithmetic method provided in the embodiments of this application can be applied to a floating-point arithmetic device, and the arithmetic method provided in the embodiments of this application can execute floating-point multiplication instructions, such as SIMT single-instruction multi-threaded floating-point multiplication instructions.

[0158] For example, the computation method provided in the embodiments of this application can execute the SIMT-based Half-Precision Floating-Point Multiplication Instruction (SIMT_F16_MUL).

[0159] The operands of the instructions are 16-bit half-precision floating-point numbers (fp16) conforming to the IEEE 754 standard, and their format definitions include:

[0160] Total number of bits: 16;

[0161] Sign bit (S): 1 bit (0 for positive, 1 for negative);

[0162] Exponent (E): 5 bits, bias value (expont_bias) is 15 (exponent range: -14 to +15, including normalized and denormalized numbers);

[0163] Mantissa (M): 10 bits, implying that the first bit is 1 (normalized number) or 0 (denormalized number).

[0164] For example, the computation method provided in the embodiments of this application can execute the SIMT bfloat16 floating-point multiplication instruction (SIMT-based BFloat16 Floating-Point Multiplication Instruction, SIMT_BF16_MUL).

[0165] The operands of the instructions are in bfloat16 (Brain Floating Point 16) format, which is not the IEEE 754 standard but is widely used in the AI ​​field. Its format definition includes:

[0166] Total number of bits: 16;

[0167] Sign bit (S): 1 bit (0 for positive, 1 for negative);

[0168] Exponent (E): 8 bits, bias value (expont_bias) is 127 (same as FP32, exponent range: -126 ~ +127);

[0169] Mantissa (M): 7 bits, implying that the first bit is 1 (normalized number) or 0 (denormalized number).

[0170] For example, the computation method provided in the embodiments of this application can execute the SIMT-based Single-Precision Floating-Point Multiplication Instruction (SIMT_FP32_MUL).

[0171] The operands of the instructions are 32-bit single-precision floating-point numbers conforming to the IEEE 754 standard, and their format definitions include:

[0172] Total number of bits: 32;

[0173] Sign bit (S): 1 bit (0 for positive, 1 for negative);

[0174] Exponent (E): 8 bits, bias value (expont_bias) is 127 (same as FP32, exponent range: -126 ~ +127);

[0175] Mantissa (M): 23 bits, implying that the first bit is 1 (normalized number) or 0 (denormalized number).

[0176] For example, when executing SIMT half-precision floating-point multiplication instructions, SIMT bfloat16 floating-point multiplication instructions, and SIMT single-precision floating-point multiplication instructions using the arithmetic methods provided in the embodiments of this application,

[0177] Operand types: FP16, Float, bfloat16;

[0178] Source operands src1, src2: register file, independent of threads;

[0179] Destination operand dst: register file, independent of threads;

[0180] The operational logic includes:

[0181] Execute on the i-th active thread in the warp:

[0182] Dst_i = src1_i x src2_i;

[0183] Signed computation: dst_i.S = src1_i.S XOR src2_i.S (same sign is positive, different signs are negative);

[0184] The mantissa calculation is performed by multiplier 110, and the effective bit analysis of the input floating-point number is performed in parallel with the multiplication operation by parallel prediction module 120 to obtain the leading bit offset. The leading bit offset is used to normalize the preliminary calculation result after the mantissa multiplication operation is completed so that the output multiplication result is a normalized number, wherein:

[0185] Exponent calculation: dst_i.E = src1_i.E + src2_i.E – exp_bias (subtract the bias value, and process the normalized number);

[0186] The last digit is calculated as follows: prod.M = (1.src1_i.M) × (1.src2_i.M);

[0187] Obtaining the leading one shift:

[0188] if(src1 exp=-0){

[0189] leading one shift = COUNT LEADING ZERO(srcl);

[0190] }else{

[0191] leading one shift = COUNT LEADING ZERO(src2);}

[0192] Normalization: prod m = prod M << leading one shift;

[0193] After normalization, the valid last digit (including the implicit bit) is retained, and the excess part is processed according to the rounding rules.

[0194] Special value handling includes:

[0195] When the input contains NaN, the result is NaN (propagation rule);

[0196] When the input is ±Inf, the result is ±Inf (same sign is positive, different sign is negative); Inf × 0 results in NaN;

[0197] When operating on denormalized numbers (E=0 and M≠0), it is necessary to find the leading one and perform a shift operation;

[0198] The precision and rounding rules adopt the even-rounding rule.

[0199] like Figure 9 As shown, Figure 9 This is a flowchart of a floating-point fused multiply-accumulate operation method provided in one embodiment of this application. The floating-point fused multiply-accumulate operation method may include, but is not limited to, steps S210 to S260.

[0200] Step S210: Perform a multiplication operation on the mantissas of the first floating-point operand and the second floating-point operand to obtain the mantissa product;

[0201] Step S220: Executed in parallel with the multiplication operation, the leading bit offset of the mantissa product is predicted based on the effective bit information of the first and second floating-point operands.

[0202] Step S230: Shift the mantissa product according to the leading bit offset to obtain the first normalized mantissa result;

[0203] Step S240: Calculate the exponent of the product result based on the exponents of the first and second floating-point operands, the leading bit offset, and the offset value of the floating-point format.

[0204] Step S250: Align the exponents of the first normalized mantissa result with the mantissa of the third floating-point operand and add them together to obtain the intermediate mantissa sum;

[0205] Step S260: Normalize and round the middle mantissa to obtain the second normalized mantissa result.

[0206] In one embodiment of this application, the floating-point fused multiply-accumulate operation method may include, but is not limited to, steps S270 to S280.

[0207] Step S270: Calculate the fused multiply-accumulate result exponent based on the product result exponent, the exponent of the third floating-point operand, and the secondary offset generated by normalizing the intermediate mantissa.

[0208] Step S280: Combine the second normalized mantissa result, the exponent of the fused multiply-accumulate result, and the fused multiply-accumulate sign bit determined according to the sign bits of the first, second, and third floating-point operands to form a floating-point fused multiply-accumulate result.

[0209] For example, the floating-point fused multiply-add method provided in this application can execute the SIMT-based Half-Precision Floating-Point Fused Multiply-Add Instruction (SIMT_FP16_MAD), where the operands of the instruction are the same as those of the SIMT half-precision floating-point multiplication instruction; the SIMT-based BFloat16 Floating-Point Multiply-Add Instruction (SIMT_BF16_MAD), where the operands of the instruction are the same as those of the SIMT bfloat16 floating-point multiplication instruction; and the SIMT-based Half-Precision Floating-Point Multiply-Add Instruction (SIMT_FP32_MAD), where the operands of the instruction are the same as those of the SIMT single-precision floating-point multiplication instruction.

[0210] For example, when executing SIMT half-precision floating-point fused multiply-accumulate instructions, SIMT bfloat16 floating-point fused multiply-accumulate instructions, and SIMT single-precision floating-point fused multiply-accumulate instructions using the arithmetic methods provided in the embodiments of this application,

[0211] The operational logic includes:

[0212] Execute on the i-th active thread in the warp:

[0213] Dst_i = src1_i x src2_i+src3_i

[0214] Multiplication stage:

[0215] Signed computation: dst_i.S = src1_i.S XOR src2_i.S (same sign is positive, different signs are negative);

[0216] By performing mantissa calculation and conducting effective bit analysis on the first input floating-point number in parallel with the multiplication operation through a parallel prediction module, a leading bit offset is obtained. This leading bit offset is used to normalize the preliminary calculation result after the multiplication operation is completed, ensuring that the output multiplication result is a normalized number. Specifically:

[0217] Exponent calculation: dst_i.E = src1_i.E + src2_i.E – exp_bias (subtract the bias value, and process the normalized number);

[0218] The last digit is calculated as follows: prod.M = (1.src1_i.M) × (1.src2_i.M);

[0219] Obtaining the leading one shift:

[0220] if(src1 exp=-0){

[0221] leading one shift = COUNT LEADING ZERO(srcl);

[0222] }else{

[0223] leading one shift = COUNT LEADING ZERO(src2);}

[0224] Normalization: prod m = prod M << leading one shift;

[0225] Special value handling includes:

[0226] When the input contains NaN, the result is NaN (propagation rule);

[0227] When the input is ±Inf, the result is ±Inf (same sign is positive, different sign is negative); Inf × 0 results in NaN;

[0228] When operating on denormalized numbers (E=0 and M≠0), it is necessary to find the leading one and perform a shift operation;

[0229] Addition phase:

[0230] Align to maximum EXP:

[0231] max_i.E = MAX(prod_i.E, src3_i.E);

[0232] if(prod_i.E==max_i.E) else src3_i.M << (max_i.E-src3_i.E);

[0233] else prod_i.M << (max_i.E-prod_i.E);

[0234] Adding the last two digits: Rules for fixed-point addition;

[0235] Normalization: Same as floating-point multiplication instructions;

[0236] The precision and rounding rules adopt the even-rounding rule.

[0237] Based on the operation methods of the above embodiments, the following presents various embodiments of the computer-readable storage medium and computer program product of this application.

[0238] In addition, one embodiment of this application provides a chip that integrates the floating-point arithmetic device or the floating-point fused multiply-accumulate arithmetic device of any of the above embodiments.

[0239] In addition, one embodiment of this application provides an electronic device including the chip of any of the above embodiments. The electronic device is any one of an artificial intelligence processor, a graphics processor, a data center accelerator card, an autonomous driving computing unit, or an edge computing device.

[0240] Furthermore, one embodiment of this application provides a computer-readable storage medium storing computer-executable instructions for performing the above-described arithmetic method. Exemplarily, the method steps in the arithmetic method described above are executed.

[0241] It is worth noting that, since the computer-readable storage medium of this application embodiment can execute the arithmetic method of any of the above embodiments, and the arithmetic method is applied to a floating-point arithmetic device, which includes a multiplier and a parallel prediction module, i.e., the floating-point arithmetic device of any of the above embodiments, the specific implementation method and technical effect of the computer-readable storage medium of this application embodiment can refer to the specific implementation method and technical effect of the floating-point arithmetic device of any of the above embodiments.

[0242] Furthermore, one embodiment of this application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the aforementioned arithmetic method. Exemplarily, the method steps in the arithmetic method described above are executed.

[0243] It is worth noting that, since the computer program product of this application embodiment can execute the operation method of any of the above embodiments, and the operation method is applied to a floating-point operation device, which includes a first multiplier, a parallel prediction module and a second multiplier, i.e., the floating-point operation device of any of the above embodiments, the specific implementation method and technical effect of the computer program product of this application embodiment can refer to the specific implementation method and technical effect of the floating-point operation device of any of the above embodiments.

[0244] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which may include computer storage media or non-transitory media and communication media or transient media. As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc DVD or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0245] In the several embodiments provided in this application, it should be understood that the disclosed systems, instruments, and methods can be implemented in other ways. For example, the instrument embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between instruments or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0246] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0247] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A floating-point arithmetic device, characterized in that, include: The multiplier is used to perform multiplication on the mantissas of the first and second floating-point operands to obtain the mantissa product; The parallel prediction module is used to predict the leading bit offset of the mantissa product based on the valid bit information of the first floating-point operand and the second floating-point operand while the multiplier is performing operations. The first normalization processing module is used to shift the mantissa product according to the predicted offset to obtain the first normalized mantissa result.

2. The floating-point arithmetic device according to claim 1, characterized in that, The parallel prediction module includes: Operand analysis unit is used to determine whether an operand is a denormalized number; The offset calculation unit is used to calculate the leading bit offset based on the mantissa of the denormalized operand.

3. The floating-point arithmetic device according to claim 2, characterized in that, The operand analysis unit determines whether an operand is a denormalized number by detecting whether the exponent field is zero and the mantissa field is non-zero.

4. The floating-point arithmetic device according to claim 1, characterized in that, The normalization processing module includes a barrel shifter, the number of shifts of which is controlled by the leading offset.

5. The floating-point arithmetic apparatus according to any one of claims 1 to 4, characterized in that, Also includes: The exponent calculation module is used to calculate the exponent of the product result based on the exponents of the first floating-point operand and the second floating-point operand, the leading bit offset, and the offset value of the floating-point format. The result synthesis module is used to combine the first normalized mantissa result, the product result exponent, and the product sign bit determined by the sign bits of the first floating-point operand and the second floating-point operand, and output the floating-point multiplication result.

6. A floating-point fused multiply-accumulate arithmetic device, characterized in that, include: The floating-point arithmetic apparatus as described in any one of claims 1 to 5 is used to perform a multiplication operation on a first floating-point operand and a second floating-point operand, and output a first normalized mantissa result and the corresponding exponent of the product result; The operand alignment module is used to align the exponent of the first normalized mantissa result with the mantissa of the third floating-point operand. The mantissa addition module is used to add the aligned first normalized mantissa result to the mantissa of the third floating-point operand to obtain the intermediate mantissa sum; The second normalization processing module is used to normalize and round the intermediate mantissa to obtain the second normalized mantissa result.

7. The floating-point fusion arithmetic apparatus according to claim 6, characterized in that, Also includes: The multiply-accumulate exponent processing module is used to calculate the fused multiply-accumulate exponent based on the product result exponent, the exponent of the third floating-point operand, and the secondary offset generated by normalizing the intermediate mantissa. The multiply-accumulate result synthesis module is used to combine the second normalized mantissa result, the exponent of the fused multiply-accumulate result, and the fused multiply-accumulate sign bit determined according to the sign bits of the first, second, and third floating-point operands, and output the floating-point fused multiply-accumulate result.

8. A floating-point arithmetic method, characterized in that, include: Perform a multiplication operation on the mantissas of the first and second floating-point operands to obtain the mantissa product; The multiplication operation is performed in parallel, and the leading bit offset of the mantissa product is predicted based on the valid bit information of the first and second floating-point operands. The mantissa product is shifted according to the leading bit offset to obtain the first normalized mantissa result.

9. The floating-point fused multiplication and addition method according to claim 8, characterized in that, Also includes: The product result exponent is calculated based on the exponents of the first and second floating-point operands, the leading bit offset, and the floating-point format offset. The first normalized mantissa result, the product result exponent, and the product sign bit determined by the sign bits of the first and second floating-point operands are combined to form the floating-point multiplication result.

10. A floating-point fused multiplication and addition operation method, characterized in that, include: Perform a multiplication operation on the mantissas of the first and second floating-point operands to obtain the mantissa product; The multiplication operation is performed in parallel, and the leading bit offset of the mantissa product is predicted based on the valid bit information of the first and second floating-point operands. The mantissa product is shifted according to the leading bit offset to obtain the first normalized mantissa result; The product result exponent is calculated based on the exponents of the first and second floating-point operands, the leading bit offset, and the floating-point format offset. The first normalized mantissa result is exponentially aligned with the mantissa of the third floating-point operand and then added to obtain the intermediate mantissa sum; The intermediate mantissas are normalized and rounded to obtain the second normalized mantissa result.

11. The floating-point fused multiplication-addition operation method according to claim 10, characterized in that, Also includes: The fused multiply-accumulate result exponent is calculated based on the product result exponent, the exponent of the third floating-point operand, and the secondary offset generated by normalizing the intermediate mantissa. The second normalized mantissa result, the exponent of the fused multiply-accumulate result, and the fused multiply-accumulate sign bit determined according to the sign bits of the first, second, and third floating-point operands are combined to form the floating-point fused multiply-accumulate result.

12. A chip, characterized in that, It integrates a floating-point arithmetic device or a floating-point fused multiply-accumulate arithmetic device as described in any one of claims 1 to 7.

13. An electronic device, characterized in that, Including the chip as described in claim 12, the electronic device is any one of an artificial intelligence processor, a graphics processor, a data center accelerator card, an autonomous driving computing unit, or an edge computing device.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the arithmetic method as described in any one of claims 8 to 11.

15. A computer program product, comprising a computer program or computer instructions, characterized in that, The computer program or the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or the computer instructions from the computer-readable storage medium and executes the computer program or the computer instructions, causing the computer device to perform the arithmetic method as described in any one of claims 8 to 11.

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