An ALU, an instruction execution method, a processor, a device, a medium and a program

Abstract

This disclosure provides an ALU, an instruction execution method, a processor, a device, a medium, and a program, relating to the field of computer technology, specifically information processing, deep learning, artificial intelligence, and chip technology. The ALU is integrated into the processor and includes a first data conversion module and a calculation module. The first data conversion module and the calculation module are connected, and the first data conversion module is also connected to a target register file. The first data conversion module receives first-precision data required for the calculation of a target instruction read from the target register file and converts the first-precision data into second-precision data; the precision of the first-precision data is lower than that of the second-precision data. The calculation module receives the second-precision data and executes the calculation operation of the target instruction based on the second-precision data. The embodiments of this disclosure can fully utilize hardware computing resources to improve instruction execution efficiency, thereby improving the overall execution performance of the arithmetic logic unit.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to information processing, deep learning, artificial intelligence, and chip technology. Background Technology

[0002] As LLM (Large Language Model) and other artificial intelligence technologies begin to demonstrate their capabilities in the multimodal field, LLM is being widely applied in various information processing scenarios such as healthcare, education, and intelligent communication to solve related tasks and accelerate and intelligentize business processes. For all types of artificial intelligence models, processor computing performance is crucial, directly impacting the AI ​​performance of LLM. Summary of the Invention

[0003] This disclosure provides an arithmetic logic unit, an instruction execution method, a processor, a device, a medium, and a program that can fully utilize hardware computing resources to improve instruction execution efficiency, thereby improving the overall execution performance of the arithmetic logic unit.

[0004] In a first aspect, embodiments of this disclosure provide an ALU (Automatic Language Runtime) integrated in a processor, comprising a first data conversion module and a computing module, wherein the first data conversion module and the computing module are connected, and the first data conversion module is further connected to a target register file, wherein: The first data conversion module is used to receive first-precision data required for the calculation of target instructions read from the target register file, and convert the first-precision data into second-precision data; wherein the data precision of the first-precision data is lower than that of the second-precision data. The calculation module is used to receive the second precision data and perform the calculation operation of the target instruction based on the second precision data.

[0005] Secondly, embodiments of this disclosure provide an instruction execution method applied to the ALU within a processor, the method comprising: Receive the first precision data required for calculating the target instruction read from the target register file, and convert the first precision data into second precision data; wherein the data precision of the first precision data is lower than the data precision of the second precision data; The calculation operation of the target instruction is performed based on the second precision data.

[0006] Thirdly, embodiments of this disclosure provide a processor including at least one ALU as described in the first aspect.

[0007] Fourthly, embodiments of this disclosure provide an electronic device, including at least one processor as described in the third aspect; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the instruction execution method provided in the second aspect embodiment.

[0008] Fifthly, embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the instruction execution method provided in the second aspect embodiment.

[0009] In a sixth aspect, embodiments of this disclosure also provide a computer program product, including a computer program that, when executed by a processor, implements the instruction execution method provided in the second aspect embodiment.

[0010] This embodiment of the disclosure configures a first data conversion module within the arithmetic logic unit (ALU), and configures the connection between the first data conversion module and the calculation module within the ALU, as well as the connection between the first data conversion module and the target register file. The first data conversion module receives first-precision data required for calculating the target instruction read from the target register file and converts this first-precision data into higher-precision second-precision data. Further, the calculation module receives the second-precision data and executes the calculation operation of the target instruction based on the second-precision data. Therefore, by performing data type conversion processing within the ALU before instruction calculation, the data conversion module can fully utilize hardware computing resources without increasing the number of instructions, thereby improving instruction execution efficiency and ultimately enhancing the overall execution performance of the ALU.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is a schematic diagram illustrating the connection relationship between shared memory and individual computing cores within a typical GPGPU in existing technologies. Figure 2 This is a schematic diagram of the internal structure of an ALU in the prior art; Figure 3This is a schematic diagram of the structure of an ALU provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another ALU structure provided in this embodiment of the disclosure; Figure 5 This is a flowchart of an instruction execution method provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a processor provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of an electronic device used to implement the instruction execution method of the embodiments of this disclosure. Detailed Implementation

[0013] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0014] LLM relies on massive computing power, making it crucial to improve its computational speed. However, when these computations run in CUDA (Compute Unified Device Architecture), threads within a block often exchange data via shared memory, posing a challenge to shared memory access. Insufficient shared memory bandwidth severely impacts performance. To mitigate this bottleneck, many algorithms employ low-precision storage and high-precision computation to alleviate the shared memory bandwidth constraint. However, this approach requires additional data type conversion instructions, such as deploying a separate data conversion module outside the ALU (Arithmetic Logic Unit) to perform precision conversion on data sent to the ALU according to its required precision. Because of the need for additional data type conversion instructions, the computational load on the CUDA core is indirectly increased. While the shared memory bandwidth issue is somewhat alleviated, the overall performance gain for the ALU is not significant.

[0015] Figure 1 This is a schematic diagram illustrating the connection relationship between shared memory and individual computing cores within a typical GPGPU in existing technology. For example, ... Figure 1As shown, multiple cores within the processor communicate with shared memory via register files and / or VRFs (Vector Register Files). Because there are many cores, but the communication bandwidth between shared memory and register files is very limited, insufficient bandwidth for accessing shared memory can easily create a performance bottleneck.

[0016] Currently, to address the aforementioned issues, related technologies typically employ high-precision data loading, high-precision CUDA core computation, and high-precision data storage. This approach places high demands on shared memory bandwidth, easily leading to memory access bottlenecks. Alternatively, a low-precision data loading method can be used, followed by precision conversion instructions to convert the low-precision data to high-precision data before high-precision computation. After computation, the high-precision data can be converted back to low-precision data. If data needs to be stored, it must be converted back to high-precision data for storage. This method requires additional data conversion instructions for low-to-high and high-to-low precision conversions. The increased number of instructions leads to decreased instruction execution efficiency due to increased instruction scheduling, instruction issuance bandwidth requirements, VRF bandwidth requirements, and additional computing power.

[0017] Figure 2 This is a schematic diagram of the internal structure of an ALU in the prior art. Currently, such as... Figure 2 As shown, in the existing ALU computation process, data type conversion and compute computation are parallel, with different instructions following different data paths. Although theoretically data type conversion and computation operations can be parallelized, due to output bandwidth limitations, the maximum IPC (Instructions Per Cycle) of the entire ALU is 1. Therefore, adding extra data type conversion instructions will degrade the overall execution performance of the ALU.

[0018] In one example Figure 3 This is a schematic diagram of the structure of an ALU provided in an embodiment of this disclosure, which can be integrated into a processor. Figure 3 As shown, the structure of the ALU 30 may include a first data conversion module 310 and a calculation module 320. The output of the first data conversion module 310 is connected to the calculation module 320. The first data conversion module 310 is also connected to a target register file, wherein: The first data conversion module 310 is used to receive the first precision data required for the calculation of the target instruction read from the target register file, and convert the first precision data into second precision data; wherein the data precision of the first precision data is lower than that of the second precision data; the calculation module 320 is used to receive the second precision data and perform the calculation operation of the target instruction according to the second precision data.

[0019] The target register file can be a register file storing scalar data or a vector register file storing vector data, as long as it can provide the ALU 30 with the data required for computation. This embodiment does not limit the specific type of the target register file. The first data conversion module 310 can be one of the functional modules within the ALU 30, used to perform precision conversion processing on the data required for instruction computation before the computation module performs the computation. The computation module 320 can be a module within the ALU 30 that provides computational functions, such as addition, subtraction, multiplication, or fused multiplication-addition. It can provide only a single computational function or complex fused instruction computation functions. Optionally, there can be one or more computation modules 320. This embodiment does not limit the types of computational functions that the computation module 320 can provide or the specific number of modules.

[0020] The target instruction can be the instruction currently being processed by the ALU. The first-precision data can be data read from the target register file and loaded into the ALU. The second-precision data can be data that the ALU's computation module can directly calculate and process.

[0021] Optional, such as Figure 3As shown, the input terminal of the first data conversion module 310 is connected to the output terminal of the target register file, and the output terminal of the first data conversion module 310 is connected to the input terminal of the calculation module 320, enabling it to receive multiple input data read from the target register file. Specifically, the processor housing the ALU 30 can drive the target register file to output the operands required by the target instruction to the input port of the ALU 30 according to the requirements of the target instruction, via the control unit. This is a parallel data transmission process coordinated by control signals. That is, the input port of the first data conversion module 310 of the ALU 30 can be connected to the read port of the target register file. To ensure the memory access bandwidth requirements, the target register file can store data in a low-precision manner. The processor's control unit controls the target register file to output the first-precision data required by the target instruction, which is the original data stored in the target register file. The processor's control unit outputs to the input port of the first data conversion module 310 within the ALU 30 through the read port of the target register file. After receiving the first-precision data required for the calculation of the target instruction read from the target register file, the first data conversion module 310 of the ALU 30 converts the lower-precision first-precision data into the higher-precision second-precision data required by the calculation module 320 for calculation. Furthermore, the first data conversion module 310 sends the second-precision data generated by the conversion process to the calculation module 320, which can then perform the calculation operation of the target instruction based on the received second-precision data to ensure the accuracy of the target instruction execution.

[0022] Therefore, the aforementioned ALU addresses the performance pain points of existing instruction execution by implementing a pipelined architecture for mixed-precision computing. Within the ALU, data type conversion operations and computation operations are pipelined and merged, allowing a single instruction to simultaneously complete both data type conversion and computation within the ALU. This ALU architecture eliminates the need for a separate external data conversion module and avoids consuming additional data paths within the ALU that would degrade overall execution performance. Since data type conversion operations within the ALU reuse existing computational resources, the area increase is minimal.

[0023] This embodiment of the disclosure configures a first data conversion module within the arithmetic logic unit (ALU), and configures the connection between the first data conversion module and the calculation module within the ALU, as well as the connection between the first data conversion module and the target register file. The first data conversion module receives first-precision data required for calculating the target instruction read from the target register file and converts this first-precision data into higher-precision second-precision data. Further, the calculation module receives the second-precision data and executes the calculation operation of the target instruction based on the second-precision data. Therefore, by performing data type conversion processing within the ALU before instruction calculation, the data conversion module can fully utilize hardware computing resources without increasing the number of instructions, thereby improving instruction execution efficiency and ultimately enhancing the overall execution performance of the ALU.

[0024] In one example Figure 4 This is a schematic diagram of another ALU structure provided in an embodiment of this disclosure. Figure 4 As shown, the ALU structure may further include a second data conversion module 330, the input of which is connected to the output of the calculation module 320, and the output of which is connected to the input of the target register file, wherein: The calculation module 320 can also be used to perform the calculation operation of the target instruction based on the second precision data, and then send the calculation result of the target instruction to the second data conversion module 330; wherein the data precision of the calculation result of the target instruction is the same as the data precision of the second precision data. The second data conversion module 330 is used to convert the calculation result of the target instruction into third precision data w, and send the third precision data w to the target register file; wherein the data precision of the third precision data is lower than the data precision of the second precision data. The data precision of the third precision data can be the same as or different from the data precision of the first precision data, and this embodiment of the present disclosure does not impose any limitations on this.

[0025] It should be noted that, in the embodiments of this disclosure, the data conversion operation of any data conversion module can achieve the corresponding data precision conversion as needed. For example, when the first data conversion module 310 processes instruction A, it can convert INT8 type first-precision data into FP16 type second-precision data. When the second data conversion module 330 processes instruction A, it can convert FP16 type second-precision data into INT4 type third-precision data. When the first data conversion module 310 processes instruction B, it can convert INT4 type first-precision data into FP32 type second-precision data. When the second data conversion module 330 processes instruction B, it can convert FP32 type second-precision data into INT4 type third-precision data. That is, the data converted by the data conversion module can be fixed-point data or floating-point data, and this embodiment of the disclosure does not impose any limitations on this.

[0026] Therefore, the ALU described above, by pipelining data type conversion operations with computation operations, can perform data type conversion before the instruction is computed, typically converting low-precision data to high-precision data. Simultaneously, it can also perform data type conversion after the computation instruction is executed, typically converting high-precision data to low-precision data. This allows for more efficient use of hardware computing resources without increasing the number of computation instructions, thereby improving instruction execution efficiency and ultimately enhancing the overall execution performance of the arithmetic logic unit.

[0027] In an optional embodiment of this disclosure, the first data conversion module 310 may further be used to: determine the baseline data precision of the target instruction in the calculation module; convert the first precision data into second precision data according to the baseline data precision of the target instruction in the calculation module; wherein the data precision of the second precision data is not lower than the baseline data precision.

[0028] The baseline data precision can be the minimum data precision required when the instruction is calculated.

[0029] When the first data conversion module 310 converts first-precision data to second-precision data, it can perform data conversion operations as needed according to the instruction's computational requirements. It is understandable that different computational precisions corresponding to different instructions in the ALU's computational module will result in slightly different execution precision and accuracy. Different types of instructions may also have different precision requirements. Therefore, the first data conversion module 310 can first determine the baseline data precision of the target instruction in the computational module 320. Based on the baseline data precision of the target instruction in the computational module, the first data conversion module 310 can convert the first-precision data to second-precision data. For example, if the baseline data precision of instruction A in the computational module 320 is FP32, the first data conversion module 310 can convert the first-precision data of instruction A to second-precision data of FP32 or FP64. If the baseline data precision of instruction B in the computational module 320 is FP16, the first data conversion module 310 can convert the first-precision data of instruction B to second-precision data of FP16, FP32, or FP64, and so on.

[0030] Optionally, if computing resources are plentiful, the first data conversion module 310 can convert the first-precision data of the target instruction into second-precision data with a higher precision than the reference data required by the target instruction, thereby improving computational accuracy. If computing resources are insufficient, the first data conversion module 310 can convert the first-precision data of the target instruction into second-precision data of the reference data precision type, in order to maintain computational performance.

[0031] The above technical solution converts the precision of the data required by the instruction in the ALU's calculation module according to the baseline data precision in the instruction's calculation module. This not only ensures the precision of instruction execution, but also fully improves the utilization rate of the ALU's hardware computing resources while ensuring the ALU's computing performance.

[0032] In an optional embodiment of this disclosure, the second data conversion module 330 may further be used to: determine the data precision type supported by the shared memory; determine the target data precision of the third precision data based on the data precision type supported by the shared memory and the current memory state of the shared memory; and convert the calculation result of the target instruction into third precision data of the target data precision.

[0033] Shared memory is used for rapid data exchange within processor thread blocks, significantly improving performance for computationally intensive tasks. The target data precision can be the data precision type corresponding to third-precision data.

[0034] In this embodiment, when the calculation result of the target instruction is converted into third-precision data by the second data conversion module 330, the data precision type supported by the shared memory can be determined first. It is understood that shared memory can support multiple data precision types simultaneously, therefore, third-precision data can also be converted to different data precision types as needed. Simultaneously, the current memory state of the shared memory can be further determined, such as the remaining memory space, etc., thereby determining the target data precision of the third-precision data based on the data precision types supported by the shared memory and the current memory state, thus converting the calculation result of the target instruction into third-precision data of the target precision. The advantage of this setup is that by selecting the data precision of the third-precision data stored in the shared memory from the data precision types supported by the shared memory based on the current memory state, the converted third-precision data can both meet the storage capacity of the shared memory, fully improving the space utilization of the shared memory, and maximizing the computational performance of the ALU.

[0035] In an optional embodiment of this disclosure, the second data conversion module 330 may further be used to: determine the precision bit width of each of the data precision types supported by the shared memory and the expected memory space occupied by the third precision data under each of the data precision types; determine the data precision type whose expected memory space is less than the current remaining memory space of the shared memory as a backup data precision type; and determine the backup data precision type with the largest precision bit width of the data precision type as the target data precision of the third precision data.

[0036] The estimated memory space occupied can be the estimated space occupied in shared memory for third-precision data when the corresponding data precision type is used.

[0037] It's understandable that the higher the precision of the ALU's output calculation result, the higher the ALU's calculation precision. Therefore, to ensure the ALU's calculation precision, the precision of the third-precision data can be maximized. To this end, when converting third-precision data, the bit width of each data precision type supported by shared memory and the expected memory space occupied by the third-precision data under each precision type can be determined. Generally, high-precision data (such as double-precision floating-point numbers) requires more memory space, while low-precision data (such as single-precision floating-point numbers) occupies less memory. Therefore, the higher the precision of the third-precision data, the larger the memory it may occupy in shared memory. Thus, data precision types whose expected memory space is less than the current remaining memory space in shared memory can be identified as available backup data precision types for the third-precision data, prioritizing successful storage of the third-precision data. After determining the available backup data precision types for the third-precision data, they can be sorted from high to low to select the backup data precision type with the largest bit width as the target data precision for the third-precision data.

[0038] The above technical solution uses the backup data precision type with the largest precision bit width as the target data precision of the third precision data. This allows for the priority allocation of high-precision data memory while avoiding over-allocation of memory, taking into account both the actual data volume and memory capacity limitations. This improves the computing performance of the ALU and ensures the storage performance of shared memory.

[0039] In an optional embodiment of this disclosure, the second data conversion module 330 may further be used to: determine the precision priority of each data precision type supported by the shared memory and the expected memory space occupied by each data precision type; determine the data precision type whose expected memory space is less than the current remaining memory space of the shared memory as a backup data precision type; and determine the backup data precision type with the highest precision priority of the data precision type as the target data precision of the third precision data.

[0040] To further enhance the intelligence of shared memory, precision priorities can be configured for each data precision type supported by shared memory as needed. A higher precision priority for a data precision type indicates greater importance of that type of data, and thus a greater priority for storage. Conversely, a lower precision priority indicates lower importance of that type of data, and thus a smaller priority for storage. Therefore, to ensure that important data is stored first, the precision priority of the data precision type for third-precision data can be maximized. To this end, when performing data transformation on third-precision data, the precision priority of each data precision type supported by shared memory and the expected memory space occupied by each data precision type can be determined. Data precision types whose expected memory space is less than the current remaining memory space of shared memory are designated as backup data precision types to ensure successful storage of third-precision data. After determining the available backup data precision types for third-precision data, the precision priorities of each backup data precision type can be sorted from high to low, thereby selecting the backup data precision type with the highest precision priority as the target data precision for the third-precision data.

[0041] The above technical solution uses the highest precision priority of the backup data precision type as the target data precision of the third precision data. This allows for the priority allocation of memory for high-precision data while taking into account data storage priority and memory capacity limitations, thus avoiding over-allocation of memory. This improves the computing performance of the ALU and ensures the storage performance of shared memory.

[0042] In an optional embodiment of this disclosure, the ALU may further include a first bypass module, the input of which is connected to the output of the target register file, and the output of which is connected to the input of the calculation module. The first bypass module is configured to: send the first precision data to the calculation module when it is determined that the first precision data is prohibited from being converted to higher precision; the calculation module is configured to receive the first precision data and perform the calculation operation of the target instruction based on the first precision data.

[0043] The first bypass module can be a module that provides bypass functionality. Optionally, the first bypass module can be integrated within the first data conversion module. That is, the first data conversion module can provide both data conversion and bypass functions simultaneously. Alternatively, the first bypass module can be configured in parallel with the first data conversion module. This disclosure does not limit the integration configuration of the first bypass module in the ALU.

[0044] Understandably, in some cases, the first-precision data sent to the ALU may not require precision conversion and can be directly processed for calculation. In such cases, if the first bypass module is integrated into the first data conversion module, the first data conversion module, upon receiving the first-precision data, can bypass it using the bypass function of the integrated first bypass module, sending the first-precision data to the calculation module. The calculation module then directly executes the calculation operation of the target instruction based on the first-precision data. The advantage of this setup is that it improves the ALU's compatibility and multi-precision data processing capabilities, thereby further enhancing the overall execution performance of the ALU.

[0045] In an optional embodiment of this disclosure, a second bypass module is further included. The input of the second bypass module is connected to the output of the calculation module, and the output of the second bypass module is connected to the output of the target register file. The second bypass module can be used to send the calculation result of the target instruction to the target register file when it is determined that the calculation result of the target instruction prohibits data precision conversion.

[0046] The second bypass module can be a module for providing bypass functionality. Optionally, the second bypass module can be integrated into the first data conversion module. That is, the second data conversion module can provide both data conversion and bypass functions simultaneously. Alternatively, the second bypass module can be configured in parallel with the second data conversion module. This disclosure does not limit the integration configuration of the second bypass module in the ALU.

[0047] Understandably, in some cases, the calculation result of the target instruction output by the ALU's calculation module may not require data precision conversion and can be output directly. In such cases, if the second bypass module is integrated into the second data conversion module, the second data conversion module, upon receiving the calculation result of the target instruction, can perform a bypass substitution operation through the bypass substitution function of the integrated second bypass module to directly send the calculation result of the target instruction to the target register file for storage. The advantage of this setup is that it improves the ALU's compatibility and multi-precision data processing capabilities, thereby further improving the overall execution performance of the ALU.

[0048] In a specific example, Table 1 lists the experimental results of ALU performance improvement in different application scenarios provided by the embodiments of this disclosure. For example, as shown in Table 1, taking floating-point data types as an example, the ALU can achieve equivalent bandwidth improvement effects of different multiples when processing and calculating various floating-point data types with different precisions. Experiments have verified that the ALU can also achieve equivalent bandwidth improvement effects when processing and calculating INT data types.

[0049] Table 1. List of experimental results on ALU performance improvement in different application scenarios. The above technical solution improves the internal structure of the ALU by deploying corresponding data conversion modules before and after the ALU's computation module. This enables a pipelined architecture for mixed-precision computing, merging data type conversion and computation operations within the ALU. This allows a single instruction to simultaneously complete both pre- and post-computation data type conversion and computation within the ALU. This ALU architecture eliminates the need for a separate external data conversion module and avoids consuming additional data paths within the ALU, thus preventing a reduction in overall ALU performance. Through hardware resource reuse, a significant increase in ALU equivalent bandwidth can be achieved with minimal area increment, and instruction translation can be performed at the compiler level. The improved ALU structure provided by this technical solution can significantly improve overall execution performance when applied to scenarios with shared memory access bottlenecks.

[0050] In one example Figure 5 This is a flowchart of an instruction execution method provided in an embodiment of this disclosure. This embodiment is applicable to pipelined architectures for mixed-precision computing within the ALU, where a single instruction simultaneously performs data type conversion and data computation. This method can be executed by the ALU configured within a processor, which is typically integrated into an electronic device. This electronic device can be a terminal device or a server device; this disclosure does not limit the specific type of electronic device. Correspondingly, as... Figure 5 As shown, the method includes the following operations: S510: Receive first precision data required for the calculation of the target instruction read from the target register file, and convert the first precision data into second precision data; wherein the data precision of the first precision data is lower than the data precision of the second precision data.

[0051] S520. Receive the second precision data through the calculation module, and perform the calculation operation of the target instruction based on the second precision data.

[0052] Specifically, the ALU may include a first data conversion module and a calculation module, which are connected. The first data conversion module is also connected to a target register file. When the ALU executes an instruction execution method, it can receive first-precision data required for the calculation of the target instruction read from the target register file by the first data conversion module, and convert the first-precision data into second-precision data with higher precision. Further, the calculation module receives the second-precision data and performs the calculation operation of the target instruction based on the second-precision data.

[0053] This embodiment of the disclosure receives first-precision data required for calculating the target instruction read from the target register file and converts the first-precision data into second-precision data with higher precision. Further, the calculation operation of the target instruction is executed based on the second-precision data. Therefore, by performing data type conversion processing within the data conversion module of the processor's arithmetic logic unit before instruction execution, hardware computing resources can be fully utilized to improve instruction execution efficiency without increasing the number of instructions, thereby improving the overall execution performance of the arithmetic logic unit.

[0054] Optionally, converting the first precision data into second precision data may include: determining the baseline data precision of the target instruction in the computing module; converting the first precision data into second precision data according to the baseline data precision of the target instruction in the computing module; wherein the data precision of the second precision data is not lower than the baseline data precision.

[0055] Specifically, when the first precision data is converted into second precision data by the first data conversion module, the first data conversion module can determine the baseline data precision of the target instruction in the calculation module; and the first precision data is converted into second precision data by the first data conversion module according to the baseline data precision of the target instruction in the calculation module.

[0056] Optionally, the above method may further include: converting the calculation result of the target instruction into third-precision data, and sending the third-precision data to the target register file; wherein the data precision of the third-precision data is lower than that of the second-precision data.

[0057] Specifically, the ALU may also include a second data conversion module, the input of which is connected to the output of the calculation module, and the output of which is connected to the input of the register file. The above method may also convert the calculation result of the target instruction into third-precision data through the second data conversion module and send the third-precision data to the register file.

[0058] Optionally, converting the calculation result of the target instruction into third-precision data may include: determining the data precision type supported by the shared memory; determining the target data precision of the third-precision data based on the data precision type supported by the shared memory and the current memory state of the shared memory; and converting the calculation result of the target instruction into third-precision data of the target data precision.

[0059] Specifically, when converting the calculation result of the target instruction into third-precision data, the second data conversion module can determine the data precision type supported by the shared memory; the second data conversion module can determine the target data precision of the third-precision data based on the data precision type supported by the shared memory and the current memory state of the shared memory; and the second data conversion module can convert the calculation result of the target instruction into third-precision data of the target data precision.

[0060] Optionally, determining the target data precision of the third precision data may include: determining the precision bit width of each data precision type supported by the shared memory and the expected memory space occupied by each data precision type; determining the data precision type whose expected memory space is less than the current remaining memory space of the shared memory as a backup data precision type; and determining the backup data precision type with the largest precision bit width as the target data precision of the third precision data.

[0061] Specifically, when determining the target data precision of the third precision data, the second data conversion module can determine the precision bit width of each data precision type supported by the shared memory and the expected memory space occupied by each data precision type; the second data conversion module can determine the data precision type whose expected memory space is less than the current remaining memory space of the shared memory as the backup data precision type; the second data conversion module can determine the backup data precision type with the largest precision bit width of the data precision type as the target data precision of the third precision data.

[0062] Optionally, determining the target data precision of the third precision data may include: determining the precision priority of each data precision type supported by the shared memory and the expected memory space occupied by each data precision type; determining the data precision type whose expected memory space is less than the current remaining memory space of the shared memory as a backup data precision type; and determining the backup data precision type with the highest precision priority as the target data precision of the third precision data.

[0063] Specifically, when determining the target data precision of the third precision data, the second data conversion module can determine the precision priority of each data precision type supported by the shared memory and the expected memory space occupied by each data precision type; the second data conversion module can determine the data precision type whose expected memory space is less than the current remaining memory space of the shared memory as a backup data precision type; and the second data conversion module can determine the backup data precision type with the highest precision priority of the data precision type as the target data precision of the third precision data.

[0064] Optionally, the above method may further include: if it is determined that the first precision data is prohibited from being converted to higher precision, performing the calculation operation of the target instruction based on the first precision data; if it is determined that the calculation result of the target instruction is prohibited from being converted to higher precision, sending the calculation result of the target instruction to the target register file.

[0065] Specifically, the ALU may include a first bypass module, the input of which is connected to the output of the target register file, and the output of which is connected to the input of the calculation module. The first bypass module can send the first precision data to the calculation module when it is determined that data precision conversion of the first precision data is prohibited. The calculation module receives the first precision data and performs the calculation operation of the target instruction based on the first precision data. The ALU may also include a second bypass module, the input of which is connected to the output of the calculation module, and the output of which is connected to the output of the target register file. The ALU can send the calculation result of the target instruction to the target register file when it is determined that data precision conversion of the calculation result of the target instruction is prohibited.

[0066] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information in this technical solution comply with relevant laws and regulations and do not violate public order and good morals.

[0067] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this disclosure.

[0068] In one example Figure 6 This is a schematic diagram of the structure of a processor provided in an embodiment of this disclosure, such as... Figure 6 As shown, the processor may include at least one ALU as described in any embodiment of this disclosure. It should be noted that... Figure 6This is merely a schematic diagram of one implementation method. The connection methods between each computing unit can be configured as needed, or the computing units can work independently. This disclosure does not limit the connection methods between the computing units within the processor.

[0069] In one example, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0070] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0071] like Figure 7 As shown, device 700 includes a computing unit 701, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 702 or a computer program loaded into random access memory (RAM) 703 from storage unit 708. The RAM 703 may also store various programs and data required for the operation of device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via bus 704. Input / output (I / O) interface 705 is also connected to bus 704.

[0072] Multiple components in device 700 are connected to I / O interface 705, including: input unit 706, such as keyboard, mouse, etc.; output unit 707, such as various types of monitors, speakers, etc.; storage unit 708, such as disk, optical disk, etc.; and communication unit 709, such as network card, modem, wireless transceiver, etc. Communication unit 709 allows device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0073] The computing unit 701 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as instruction execution methods.

[0074] Optionally, the instruction execution method applied to the ALU within the processor may include: receiving first-precision data required for the calculation of a target instruction read from a target register file, and converting the first-precision data into second-precision data; wherein the data precision of the first-precision data is lower than the data precision of the second-precision data; and performing the calculation operation of the target instruction based on the second-precision data.

[0075] For example, in some embodiments, the instruction execution method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by computing unit 701, one or more steps of the instruction execution method described above may be performed. Alternatively, in other embodiments, computing unit 701 may be configured to execute the instruction execution method by any other suitable means (e.g., by means of firmware).

[0076] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0077] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0078] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0079] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0080] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0081] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is established by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, also known as cloud computing servers or cloud hosts, which are hosting products within the cloud computing service ecosystem to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers integrated with blockchain technology.

[0082] This embodiment of the disclosure configures a first data conversion module within the arithmetic logic unit (ALU), and configures the connection between the first data conversion module and the calculation module within the ALU, as well as the connection between the first data conversion module and the target register file. The first data conversion module receives first-precision data required for calculating the target instruction read from the target register file and converts this first-precision data into higher-precision second-precision data. Further, the calculation module receives the second-precision data and executes the calculation operation of the target instruction based on the second-precision data. Therefore, by performing data type conversion processing within the ALU before instruction calculation, the data conversion module can fully utilize hardware computing resources without increasing the number of instructions, thereby improving instruction execution efficiency and ultimately enhancing the overall execution performance of the ALU.

[0083] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0084] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An arithmetic logic unit (ALU), said ALU being integrated in a processor, comprising a first data conversion module and a calculation module, the first data conversion module and the calculation module being connected, the first data conversion module being further connected to a target register file, wherein: The first data conversion module is used to receive first-precision data required for the calculation of target instructions read from the target register file, and convert the first-precision data into second-precision data; wherein the data precision of the first-precision data is lower than that of the second-precision data. The calculation module is used to receive the second precision data and perform the calculation operation of the target instruction based on the second precision data.

2. The ALU of claim 1, wherein, The first data conversion module is also used for: Determine the baseline data accuracy of the target instruction in the computing module; Based on the baseline data precision in the calculation module according to the target instruction, the first precision data is converted into the second precision data; The accuracy of the second precision data is not lower than that of the reference data.

3. The ALU according to claim 1 further includes a second data conversion module, wherein the input terminal of the second data conversion module is connected to the output terminal of the calculation module, and the output terminal of the second data conversion module is connected to the input terminal of the target register file, wherein: The calculation module is further configured to perform the calculation operation of the target instruction based on the second precision data, and then send the calculation result of the target instruction to the second data conversion module; wherein, the data precision of the calculation result of the target instruction is the same as the data precision of the second precision data; The second data conversion module is used to convert the calculation result of the target instruction into third-precision data and send the third-precision data to the target register file; The precision of the third precision data is lower than that of the second precision data.

4. The ALU of claim 3, wherein, The second data conversion module is also used for: Determine the data precision types supported by shared memory; The target data precision of the third precision data is determined based on the data precision types supported by the shared memory and the current memory state of the shared memory. The calculation result of the target instruction is converted into third-precision data of the target data precision.

5. The ALU of claim 4, wherein, The second data conversion module is also used for: Determine the precision bit width of each of the data precision types supported by the shared memory and the expected memory space occupied by the third precision data under each of the data precision types; The data precision type whose expected memory space is less than the current remaining memory space of the shared memory is determined as the spare data precision type; The backup data precision type with the largest precision bit width is determined as the target data precision of the third precision data.

6. The ALU of claim 4, wherein, The second data conversion module is also used for: Determine the precision priority of each data precision type supported by the shared memory and the expected memory space occupied by each data precision type; The data precision type whose expected memory space is less than the current remaining memory space of the shared memory is determined as the spare data precision type; The backup data precision type with the highest precision priority among the data precision types is determined as the target data precision of the third precision data.

7. The ALU according to claim 1, further comprising a first bypass module, wherein the input terminal of the first bypass module is connected to the output terminal of the target register file, and the output terminal of the first bypass module is connected to the input terminal of the computing module, the first bypass module being used for: If it is determined that the first precision data is prohibited from undergoing data precision conversion, the first precision data is sent to the calculation module; The calculation module is used to receive the first precision data and perform the calculation operation of the target instruction based on the first precision data.

8. The ALU according to claim 1, further comprising a second bypass module, wherein the input terminal of the second bypass module is connected to the output terminal of the computing module, and the output terminal of the second bypass module is connected to the output terminal of the target register file, the second bypass module being used for: If it is determined that the calculation result of the target instruction prohibits data precision conversion, the calculation result of the target instruction is sent to the target register file.

9. An instruction execution method applied to an ALU within a processor, the method comprising: Receive the first precision data required for calculating the target instruction read from the target register file, and convert the first precision data into second precision data; wherein the data precision of the first precision data is lower than the data precision of the second precision data; The calculation operation of the target instruction is performed based on the second precision data.

10. The method of claim 9, wherein, Converting the first precision data to second precision data includes: Determine the baseline data accuracy of the target instruction in the computing module; Based on the baseline data precision in the calculation module according to the target instruction, the first precision data is converted into the second precision data; The accuracy of the second precision data is not lower than that of the reference data.

11. The method of claim 9, further comprising: The calculation result of the target instruction is converted into third-precision data, and the third-precision data is sent to the target register file; The precision of the third precision data is lower than that of the second precision data.

12. The method according to claim 11, wherein, Converting the calculation result of the target instruction into third-precision data includes: Determine the data precision types supported by shared memory; The target data precision of the third precision data is determined based on the data precision types supported by the shared memory and the current memory state of the shared memory. The calculation result of the target instruction is converted into third-precision data of the target data precision.

13. The method according to claim 12, wherein, Determining the target data precision of the third precision data includes: Determine the precision bit width of each of the data precision types supported by the shared memory and the expected memory space occupied by each of the data precision types; The data precision type whose expected memory space is less than the current remaining memory space of the shared memory is determined as the spare data precision type; The backup data precision type with the largest precision bit width is determined as the target data precision of the third precision data.

14. The method according to claim 12, wherein, Determining the target data precision of the third precision data includes: Determine the precision priority of each data precision type supported by the shared memory and the expected memory space occupied by each data precision type; The data precision type whose expected memory space is less than the current remaining memory space of the shared memory is determined as the spare data precision type; The backup data precision type with the highest precision priority among the data precision types is determined as the target data precision of the third precision data.

15. The method of claim 9, further comprising: If it is determined that the first precision data is prohibited from undergoing data precision conversion, the calculation operation of the target instruction is performed based on the first precision data; If it is determined that the calculation result of the target instruction prohibits data precision conversion, the calculation result of the target instruction is sent to the target register file.

16. A processor comprising at least one ALU as described in any one of claims 1-8.

17. An electronic device comprising: At least one processor as described in claim 16; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the instruction execution method according to any one of claims 9-15.

18. A non-transitory computer-readable storage medium storing computer instructions, said computer instructions being configured to cause a computer to perform the instruction execution method of any one of claims 9-15.

19. A computer program product comprising a computer program / instructions, wherein, When the computer program / instruction is executed by the processor, it implements the instruction execution method as described in any one of claims 9-15.

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