A non-public key algorithm reconfigurable engine circuit
By designing a reconfigurable engine circuit for non-public key algorithms and employing reconfigurable computing technology to optimize data interaction and instruction storage, the performance and area issues of integrating non-public key cryptographic algorithms into low-power IoT chips have been resolved, enabling efficient and flexible information security services.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-04-03
- Publication Date
- 2026-06-26
AI Technical Summary
When integrating non-public key cryptographic algorithms into low-power IoT chips, existing technologies suffer from low performance, large area, and high power consumption, making it difficult to meet the needs of information security systems. Furthermore, with the development of quantum computing, security requirements are constantly increasing.
Design a non-public key algorithm reconfigurable engine circuit, which adopts reconfigurable computing technology and combines common basic operation structures, including reconfigurable arithmetic logic units, shared buffers, main instruction register buffers, reconfigurable instruction memory, master control state machine logic circuits, decoders and data channel routers, supports mixed granularity operations and flexible configuration, and optimizes data interaction and instruction storage.
It provides lightweight, high-performance, and flexible cryptographic algorithm services to meet the needs of IoT information security systems, reducing circuit area and power consumption while improving security levels.
Smart Images
Figure CN122293328A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically, it relates to a non-public key algorithm reconfigurable engine circuit. Background Technology
[0002] To provide general information security services, low-power general-purpose security chips for the Internet of Things (IoT) need to integrate and implement mainstream non-public key cryptographic algorithms configured in current IoT security system architectures. These include, but are not limited to, symmetric cryptographic algorithms such as 128-bit Advanced Encryption Standard (AES), SM4 block cipher, ZUC, and Triple Data Encryption (3DES), as well as hash algorithms such as Secure Hash Algorithm 2 (SHA2), Secure Hash Algorithm 3 (SHA3), and SM3. Given the limited CPU performance integrated into low-power IoT chips, the software implementations of these cryptographic algorithms typically have low performance, making it difficult to meet the performance requirements of information security systems or support the smooth operation of security applications. If all these cryptographic algorithms are implemented in hardware circuitry, even with area-optimized design for each algorithm, the total area of these algorithm circuits will still be large, leading to an excessively large overall chip area, high power consumption, and cost exceeding budget. Furthermore, with the increasing popularity of IoT applications and the rapid development of quantum computing, the demand for IoT security levels will also increase. Therefore, a circuit design technology is needed that can not only simultaneously implement multiple existing algorithms, but also quickly configure new algorithms with higher security levels according to new requirements and standards, in order to adapt to the rapid development and popularization of IoT. Reconfigurable computing technology has emerged to meet this need.
[0003] Given that the fundamental operational structures of non-public-key cryptographic algorithms typically include fixed-length shifts, bit-level AND, OR, and NOT operations, S-Box lookup tables, bit / byte position permutations, short integer operations such as addition, subtraction, and modular multiplication, LFSR, polynomial multiplication, multiplication over low-order finite fields, and inversion operations, the types of basic operational components for different operations are relatively fixed. The main differences lie in the operand width, shift quantity, S-Box content, execution order of each basic component, finite field parameter selection, round transformation loop count, round constant, and subkey extension length. These fundamental operational structure characteristics of non-public-key algorithms are particularly suitable for optimization using reconfigurable computing techniques. By hardwareifying different types of basic operational components and fixing the variable parts of these components through configuration data, different cryptographic algorithm hardware circuits can be constructed. Summary of the Invention
[0004] The purpose of this invention is to address the application requirements of low-power general-purpose security chips for the Internet of Things (IoT), combine the common basic operational structure of non-public key algorithms, and take into account the constraints of low power consumption and low circuit area. Based on reconfigurable computing technology and after thorough analysis of the common logical structure of the algorithms, this invention designs a lightweight, high-performance, and flexible coarse-grained general-purpose hardware implementation circuit for non-public key cryptographic algorithms. This circuit aims to provide flexible cryptographic algorithm services while ensuring that the performance of the cryptographic services meets the requirements of IoT information security systems.
[0005] The technical solution of the present invention is described in detail below.
[0006] This invention provides a reconfigurable engine circuit for a non-public key algorithm, comprising a reconfigurable arithmetic logic unit (RC_ALU), a shared buffer, a main instruction register buffer, a reconfigurable instruction memory, a master control state machine logic circuit, branch jump logic, a decoder, and a data channel router; wherein: The reconfigurable arithmetic logic unit RC_ALU is responsible for implementing the common basic operational logic of non-public key algorithms; The shared buffer consists of a register array and provides two memory access modes: short vector and long vector. It is used to store global parameters, messages to be hashed, intermediate results of operations, extended instructions, and S-Box data. The main instruction register buffer is used to store the main instruction data for RCCA1; The reconfigurable instruction memory uses multiple SRAM blocks to store the reconfigurable instructions that configure the RC_ALU; The main control state machine logic circuit is responsible for calling the decoder circuit, supervising the execution of the microcontroller's main instructions, maintaining the running status of RCCA1, and setting the status flag and interrupt signal. The decoder is responsible for calling the branch jump logic to achieve the orderly execution of the main instruction. Based on the completion flag of the reconfigurable arithmetic logic unit (RC_ALU) operation and the jump flag of the branch jump logic, it calculates and generates pointers to the main instruction and the next instruction of the reconfigurable instruction, and drives the instruction fetch logic to read the next main instruction and the reconfigurable instruction. The data channel router is responsible for multi-channel data retrieval from the shared buffer based on multiple sets of decoded data retrieval addresses and data retrieval types, and for writing multiple sets of calculation results into the shared buffer based on the decoded write address.
[0007] In this invention, multiple RC_ALU units are integrated in parallel within RCCA1, and small data exchange buffers are placed between each pair of reconfigurable arithmetic logic units (RC_ALUs). At the same time, the number of reconfigurable instruction memories is increased, but the number of main instructions is not increased.
[0008] In this invention, the reconfigurable arithmetic logic unit RC_ALU adopts a hybrid granularity reconfigurable operation unit, which supports mixed operations of long and short data vectors.
[0009] In this invention, the shared register array in the shared buffer provides two S-Box implementation methods: a small-scale S-Box based on the shared register array and a large-capacity S-Box based on SRAM.
[0010] In this invention, the main instruction data stored in the main instruction register buffer includes main instruction accompanying flags, and the number of flags is equal to the number of reconfigurable instructions.
[0011] In this invention, the main instruction performs three functions: first, it sets the initial value of the counter; second, it specifies the jump comparison conditions and executes the jump operation of the current instruction based on the comparison results; and third, it increments or decrements the current counter value to prepare for the jump mode.
[0012] In this invention, the jump modes supported by the main instruction include unconditional jump, jump when the operation result is non-zero, jump when the operation result is zero, jump when the operation result is 1, jump when the current counter is equal to the specified counter, jump mode when returning from a subfunction, and pre-calculated jump mode. Among them, the pre-calculated mode determines whether the jump condition is met one clock cycle in advance. If it is met, the address of the reconfigurable instruction memory will be generated in advance.
[0013] In this invention, reconfigurable instructions are defined in the form of Very Long Instruction Words (VLIW), which are used to decompose the round function of the grouping algorithm and the compression transformation function of the hash algorithm into a small number of VLIW instructions.
[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention designs a coarse-grained, compact, non-public-key algorithm reconfigurable circuit. This circuit boasts advantages such as flexible structure, powerful functionality, programmability and configurability, and cost-effectiveness, meeting the needs of general-purpose application scenarios for non-public-key algorithms in information security terminal systems. In this embodiment, the designed non-public-key algorithm reconfigurable circuit is logic synthesized using SMIC 28nm technology. Results show that its average performance is 1134.2 Mbps@353MHz, and its area is 0.189 mm². 2 This is significantly better than the solutions currently available in publicly available literature. Attached Figure Description
[0015] Figure 1 This is a circuit structure diagram of a reconfigurable engine for non-public key algorithms.
[0016] Figure 2 This is a schematic diagram of a reconfigurable instruction architecture. Detailed Implementation
[0017] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0018] This invention integrates multiple optimization techniques to achieve a lightweight, high-performance, and flexible coarse-grained algorithm reconfigurable circuit.
[0019] First, the shared register array, serving as the data interaction interface, provides both short-vector and long-vector memory access modes, balancing the flexibility and read / write efficiency of data access. Second, it offers two S-Box implementation methods: a small-scale S-Box based on the shared register array and a large-capacity S-Box based on SRAM. The former is suitable for algorithms with a small number and capacity of S-Boxes, offering high performance and single-cycle S-Box calls. The latter is suitable for algorithms with large S-Box capacity, where multiple S-Boxes are called in parallel during a single round function transformation or key expansion algorithm; its disadvantage is that the S-Box memory access cycle count is 2. Finally, branch jumps typically interrupt sequential access to reconfigurable instructions. Since reconfigurable instructions are stored in SRAM, each jump adds one SRAM read clock cycle. For branch instructions with predictable jump conditions, pre-setting the branch instruction by one instruction allows for pre-adjustment of the reconfigurable instruction memory read address, thereby reducing redundant clock cycles caused by jumps.
[0020] Furthermore, the storage capacity of the basic arithmetic unit and main instruction in the reconfigurable circuit for non-public-key algorithms has been optimized. Considering that the data width of basic operations in non-public-key algorithms is mainly 32-bit or 64-bit words, with a small number reaching 256 bits, a hybrid-granularity reconfigurable arithmetic unit was designed in the arithmetic logic unit of the reconfigurable basic arithmetic unit to support mixed operations of both long and short data vectors. To reduce the storage space requirement of the main instruction, a main instruction accompanying flag is set in the reconfigurable circuit for non-public-key algorithms. The number of flags equals the number of reconfigurable instructions. A flag of 1 indicates that the current main instruction is valid; otherwise, it indicates that there is no current main instruction, and only the reconfigurable instructions need to be executed sequentially. The main instruction is uniformly addressed and stored in a register set. The hardware provides a mapping circuit from the main instruction accompanying flag to the main instruction index for synchronous reading of the main instruction.
[0021] Based on the common characteristics of the basic computational components of non-public key algorithms, and employing a general reconfigurable computing architecture, this invention proposes, as follows: Figure 1 The circuit diagram shown is for a non-public key algorithm reconfigurable engine, codenamed RCCA1. (See diagram:) RC_ALU is a reconfigurable arithmetic logic unit responsible for implementing the common basic operational logic of non-public key algorithms.
[0022] The shared buffer consists of a register array and can be accessed in 256×64 bits or 32×512 bits. The shared buffer can store global parameters, messages to be hashed, intermediate results of calculations, extended instructions, and S-Box data. Compared with SRAM, it has the advantage of fast single-cycle memory access.
[0023] The main instruction register buffer is responsible for storing the main instruction data of RCCA1. The register buffer size is 128x32 bits.
[0024] The reconfigurable instruction memory uses multiple SRAM blocks to store the reconfigurable instructions configured for the RC_ALU. The SRAM access structure after splicing is 256x256 bits.
[0025] The master control state machine logic circuit is responsible for calling the decoder circuit, supervising the execution of the microcontroller's main instructions, maintaining the operating status of RCCA1, and setting the status flags and interrupt signals.
[0026] The decoder is responsible for calling the branch jump logic to ensure the orderly execution of the main instruction. Based on the completion flag of the RC_ALU operation and the jump flag of the branch jump logic, it calculates and generates pointers to the next instruction of the main instruction and reconfigurable instructions, and drives the instruction fetch logic to read the next main instruction and reconfigurable instructions.
[0027] The data channel router is responsible for multi-channel data retrieval based on multiple sets of decoded data retrieval addresses and data retrieval types, using a shared buffer structure of 256×64 bits or 32×512 bits, and simultaneously writing multiple sets of calculation results into the shared buffer based on the decoded write address.
[0028] If further improvement of RCCA1 performance is required, multiple RC_ALU units can be integrated in parallel within RCCA1, and small data exchange buffers can be placed between each pair of reconfigurable arithmetic logic units (RC_ALU). At the same time, the number of reconfigurable instruction memories can be increased without increasing the number of main instructions, which can effectively improve the performance of reconfigurable circuits for non-public key algorithms.
[0029] The reconfigurable arithmetic logic unit (RC_ALU) supports mixed operations of 64-bit and 256-bit word length arithmetic, hierarchical computation including masking, preprocessing, binarization, and post-processing, fast S-Box memory access, and mixed operations based on SRAM S-Box calls. It also supports reconfiguration of coarse-grained common arithmetic logic. The advantages of the coarse-grained RC_ALU circuit are its compact structure, small hardware circuit size, small configuration data volume, and fast execution speed of matched coarse-grained common logic.
[0030] The overall structure of the reconfigurable instruction set is as follows: Figure 2As shown, the current instruction consists of a main instruction acting on the microcontroller and arithmetically reconfigurable instructions (VLIW) acting on the RC_ALU. If the accompanying flag of the main instruction is 0, the current main instruction is empty, and the reconfigurable instructions are executed sequentially. If the accompanying flag of the main instruction is 1, the current main instruction is valid, and the hardware needs to calculate the index position of the main instruction in the main instruction register buffer based on the Hamming weight of the accompanying flag, and map the main instruction to the leftmost high-order bit of the current instruction. This method significantly compresses the storage capacity of the main instruction.
[0031] The main instruction performs three main functions: first, setting the initial value of the counter; second, specifying the jump comparison condition and executing the jump operation of the current instruction based on the comparison result; and third, incrementing or decrementing the current counter value to prepare for the jump mode. The main instruction supports setting up to 8 counters and configuring up to 7 sub-function return addresses, thus supporting nested function calls in microcontrollers and refactorable instructions running general For loops.
[0032] The main instruction supports jump modes including unconditional jump, jump when the result is non-zero, jump when the result is zero, jump when the result is 1, jump when the current counter equals the specified counter, and jump mode from a sub-function. The result comes from a shared buffer, which has a 256x64-bit structure. A slice of the main instruction provides the index value of a 64-bit result vector. Additionally, the main instruction supports a pre-computed jump mode. This mode checks if the jump condition is met one clock cycle in advance. If so, it generates the address of the reconfigurable instruction memory in advance. Pre-computed mode is typically used when the jump mode involves counter comparison to reduce the clock cycles of jump switching when running reconfigurable instructions in a For loop.
[0033] The detailed definition of the main instruction (MainInst) is shown in Table 1.
[0034] Table 1. Definition of the main instruction of the microcontroller
[0035]
[0036] Arithmetic reconfigurable instructions are defined in the form of Very Long Instruction Words (VLIW). The design idea is that each instruction should perform a sufficiently complex linear or nonlinear transformation function, and the round function of the grouping algorithm and the compression transformation function of the hash algorithm should be decomposed into a small number of VLIW instructions.
[0037] The Arithmetic Reconfigurable Instruction (RcInst) is shown in Table 2. The RcInst instruction is 256 bits long, with bit indices starting from 0. The RcInst instruction configures the RC_ALU for reconfigurability within a shared buffer organized in 256x64 bits. Since the operand addressing mode of the RcInst instruction is a 64-bit word, the index width of the read / write vector is 8 bits. The RC_ALU reconfigurable logic circuit receives 16 64-bit words at a time for parallel operation. To balance the flexibility of operand sourcing with the length requirement of the RcInst instruction, the eight 64-bit words of the opa operand are taken from the shared buffer in a completely random manner, occupying a 64-bit RcInst instruction encoding segment. The eight 64-bit words of the opb operand are taken from the shared buffer sequentially. The RcInst instruction only provides the index position of the first 64-bit word; the indices of the other 64-bit words are simply incremented by 1 from the base address index, thus requiring only 8 bits of encoding.
[0038] Table 2 Reconfigurable Instruction Definitions (64-bit Word Reconfigurable Transformations)
[0039] Furthermore, the non-public key algorithm reconfigurable circuit based on the design of this invention is synthesized using SMIC 28nm process. The synthesis tool used is the industry-popular Synopsys DesignCompiler software. In performance-first mode, the typical process library of SMIC 28nm is used for logic synthesis. The results show that the average algorithm performance of the algorithm reconfigurable circuit designed in this invention is 1134.2 Mbps@353MHz, and the area size is 0.189 mm2, both of which are better than the solutions in the currently published literature.
[0040] In summary, this invention provides a novel reconfigurable engine circuit for non-public key algorithms, which supports the non-public key cryptographic algorithms required by the aforementioned IoT security chips in a reconfigurable manner. Through this circuit architecture design and hardware implementation, it can be more flexible in structure, more powerful in function, more programmable and configurable than other reconfigurable engine circuits, and also more cost-effective. In low-cost application fields such as information security terminals, this invention has a significant cost advantage and practical value.
Claims
1. A non-public key algorithm reconfigurable engine circuit, characterized in that, It includes a reconfigurable arithmetic logic unit (RC_ALU), a shared buffer, a main instruction register buffer, a reconfigurable instruction memory, a master control state machine logic circuit, branch jump logic, a decoder, and a data channel router; wherein: The reconfigurable arithmetic logic unit RC_ALU is responsible for implementing the common basic operational logic of non-public key algorithms; The shared buffer, consisting of a shared register array, provides two memory access modes: short vector and long vector. It is used to store global parameters, messages to be hashed, intermediate results of operations, extended instructions, and S-Box data. The main instruction register buffer is used to store the main instruction data for RCCA1; The reconfigurable instruction memory uses multiple SRAM blocks to store the reconfigurable instructions that configure the RC_ALU; The main control state machine logic circuit is responsible for calling the decoder circuit, supervising the execution of the microcontroller's main instructions, maintaining the running status of RCCA1, and setting the status flag and interrupt signal. The decoder is responsible for calling the branch jump logic to achieve the orderly execution of the main instruction. Based on the completion flag of the reconfigurable arithmetic logic unit (RC_ALU) operation and the jump flag of the branch jump logic, it calculates and generates pointers to the main instruction and the next instruction of the reconfigurable instruction, and drives the instruction fetch logic to read the next main instruction and the reconfigurable instruction. The data channel router is responsible for multi-channel data retrieval from the shared buffer based on multiple sets of decoded data retrieval addresses and data retrieval types, and for writing multiple sets of calculation results into the shared buffer based on the decoded write address.
2. The non-public key algorithm reconfigurable engine circuit according to claim 1, characterized in that, Multiple RC_ALU units are integrated in parallel in RCCA1, and small data exchange buffers are placed between each pair of reconfigurable arithmetic logic units (RC_ALUs). This increases the number of reconfigurable instruction memories without increasing the number of main instructions.
3. The non-public key algorithm reconfigurable engine circuit according to claim 1, characterized in that, The reconfigurable arithmetic logic unit (RC_ALU) employs a hybrid-granularity reconfigurable operation unit, supporting mixed operations on both long and short data vectors.
4. The non-public key algorithm reconfigurable engine circuit according to claim 1, characterized in that, In the shared buffer, the shared register array provides two S-Box implementation methods: implementing a small-scale S-Box based on the shared register array and implementing a large-capacity S-Box based on SRAM.
5. The non-public key algorithm reconfigurable engine circuit according to claim 1, characterized in that, The main instruction register buffer stores the main instruction data, including the main instruction accompanying flags. The number of flags is equal to the number of reconfigurable instructions.
6. The non-public key algorithm reconfigurable engine circuit according to claim 1, characterized in that, The main instruction performs three functions: first, it sets the initial value of the counter; second, it specifies the jump comparison conditions and executes the jump operation of the current instruction based on the comparison results; and third, it increments or decrements the current counter value to prepare for the jump mode.
7. The non-public key algorithm reconfigurable engine circuit according to claim 1, characterized in that, The main instruction supports the following jump modes: unconditional jump, jump when the operation result is non-zero, jump when the operation result is zero, jump when the operation result is 1, jump when the current counter is equal to the specified counter, jump mode when returning from a subfunction, and pre-computed jump mode. Among them, the pre-computed mode checks whether the jump condition is met one clock cycle in advance. If it is met, the address of the reconfigurable instruction memory will be generated in advance.
8. The non-public key algorithm reconfigurable engine circuit according to claim 1, characterized in that, Reconfigurable instructions are defined in the form of Very Long Instruction Words (VLIW) to decompose the round function of the grouping algorithm and the compression transformation function of the hash algorithm into a small number of VLIW instructions.