Data processing method and system

Abstract

This application discloses a data processing method and system, belonging to the field of power protection technology. In this application, a memory and a processor are connected via a parallel bus, an intermediate latch is connected to the processor via a parallel bus, and functional modules such as a button unit and a display unit are connected to the intermediate latch. This allows the memory to interact with the processor via the parallel bus according to a first preset virtual address, and allows the functional modules such as the button unit and the display unit to interact with the processor via the parallel bus according to a second preset virtual address through the intermediate latch. Thus, during data visualization, the memory, button unit, and display unit can time-division multiplex the parallel bus to interact with the processor. When applied to relay protection devices, this can solve the problem of balancing I / O interface resource usage and visualization effect presentation.

Description

Technical Field

[0001] This application relates to the field of power protection technology, and in particular to a data processing method and system. Background Technology

[0002] Data visualization in relay protection devices can be achieved through a human-machine interface system based on a monochrome dot-matrix LCD (Liquid Crystal Display) and buttons. However, the data visualization scheme for relay protection devices faces challenges in interface resource allocation. If parallel communication is used between the main control MCU (Microcontroller Unit) and the LCD and buttons, it results in excessive consumption of the main control MCU's I / O (Input / Output) interface resources and a heavy burden on the main control MCU's CPU (Central Processing Unit), potentially affecting the core functions of the device. If serial communication is used between the main control MCU and the LCD and buttons, the refresh rate is slow, which may lead to poor display quality of the visualization page.

[0003] Therefore, how to balance the consumption of I / O interface resources and the presentation of visualization effects is an urgent problem to be solved. Summary of the Invention

[0004] The main objective of this application is to provide a data processing method and system that aims to at least partially solve the aforementioned technical problems.

[0005] Firstly, a data processing method is provided, applied to a data processing system. The data processing system includes a processor, a memory, functional modules, and an intermediate latch. The processor and the memory are connected via a parallel bus, the processor and the intermediate latch are connected via a parallel bus, and the intermediate latch is connected to the functional modules. The functional modules include a key unit and a display unit. The memory stores a preset relay protection database, which includes a pre-built relay protection container library, a relay protection element library, and a relay protection device operation database. Data processing methods include: The processor receives data processing instructions from the intermediate latch via the parallel bus. The data processing instructions are used to instruct the processor to obtain the target relay protection data and the target page type. The data processing instructions are sent to the intermediate latch by the key unit. The processor responds to the data processing instruction and retrieves the target relay protection data from the memory via the parallel bus based on the first preset virtual address. The target relay protection data is data in the relay protection database. The target relay protection data includes at least one of the target relay protection container, the target relay protection element, and the target operation data. The target relay protection container includes the target page container and the target menu container. The processor generates a menu configuration list based on the target page type and the target relay protection data; The processor, based on the menu configuration list, adds at least one of the target relay protection elements and target operation data to the corresponding target menu container, and adds each target menu container to the target page container to generate a target page; The processor sends the target page to the intermediate latch via a parallel bus based on the second preset virtual address; The intermediate latch forwards the target page to the display unit.

[0006] Secondly, embodiments of this application also provide a data processing system, including a processor, a memory, a functional module, and an intermediate latch; the processor and the memory are connected via a parallel bus, the processor and the intermediate latch are connected via a parallel bus, the intermediate latch is connected to the functional module, and the functional module includes a button unit and a display unit; The button unit is used to send data processing instructions to the intermediate latch; The display unit is used to receive the target page sent by the intermediate latch; The memory is used to store a preset relay protection database, which includes a pre-built relay protection container library, a relay protection element library, and an operation database of relay protection devices. Intermediate latches are used to latch data processing instructions and target pages; A processor for implementing any of the data processing methods described above.

[0007] Therefore, in this application, the memory and processor are connected via a parallel bus, an intermediate latch is connected to the processor via a parallel bus, and functional modules such as the button unit and display unit are connected to the intermediate latch. This allows the memory to interact with the processor via the parallel bus according to a first preset virtual address, and allows the functional modules such as the button unit and display unit to interact with the processor via the parallel bus according to a second preset virtual address through the intermediate latch. Thus, during data processing, the memory, button unit, and display unit can time-division multiplex the parallel bus to interact with the processor, allowing the processor to first receive data processing instructions from the button unit via the parallel bus, and then retrieve data from the memory via the parallel bus. The memory acquires the target relay protection data and target page type corresponding to the data processing instructions, generates the target page, and finally sends the target page to the display unit via a parallel bus. Compared to the memory and each functional module being connected to the main controller through different parallel interfaces, this saves processor I / O resources, reduces the processor's computing power burden, and avoids affecting other functions of the device used in the data processing system. Moreover, compared to the memory and each functional module being connected to the main controller through different serial interfaces, using a parallel bus avoids the problem of slow refresh rate, thereby avoiding visual page stuttering and insufficient dynamic response capability. When applied to relay protection devices, it can solve the problem of how to balance I / O interface resource occupation and visualization effect presentation.

[0008] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0011] Figure 1 A flowchart illustrating a data visualization method provided as an exemplary embodiment of this application; Figure 2 This is a schematic diagram of the structure of a data processing system provided in an exemplary embodiment of this application; Figure 3 Another schematic diagram of the data processing system provided in an exemplary embodiment of this application; Figure 4Circuit schematic of a processor provided as an exemplary embodiment of this application; Figure 5 A circuit schematic diagram of a first memory provided for an exemplary embodiment of this application; Figure 6 A circuit schematic diagram of a second memory provided for an exemplary embodiment of this application; Figure 7 A circuit schematic diagram of the first latch unit provided for an exemplary embodiment of this application; Figure 8 A circuit schematic diagram of the second latch unit provided as an exemplary embodiment of this application; Figure 9 A circuit schematic diagram of the third latch unit provided as an exemplary embodiment of this application; Figure 10 A circuit schematic diagram of an electrical sampling unit provided as an exemplary embodiment of this application; Figure 11 A circuit schematic diagram of the fourth latch unit provided as an exemplary embodiment of this application; Figure 12 A schematic diagram of a target page provided for an exemplary embodiment of this application.

[0012] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0014] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0015] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0016] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0017] Additionally, in this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to implement and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0018] To facilitate understanding of the implementation schemes provided in the embodiments of this application, the background technology of the data processing methods and systems provided in the embodiments of this application will be further explained first.

[0019] In addition to the aforementioned interface application issues, the data visualization system for relay protection devices also suffers from problems such as multiple menu levels, low information density, lack of graphical indicators, and inability to dynamically display key operational information such as switch open / close status, circuit breaker position, and disconnector status. These issues prevent users from accurately and quickly obtaining information about the power grid's operational status. Furthermore, the main interface of the data visualization system does not integrate dynamic displays of the device's own operational status, such as communication status, time synchronization status, and operation / alarm indicators. This makes it impossible for users to immediately determine the device's health, requiring manual queries through multiple menus for fault diagnosis, resulting in low response efficiency. Additionally, the lack of access control between operation monitoring functions and parameter setting functions makes it easy for users to accidentally enter the setting menu during routine inspections, increasing operational risks.

[0020] Next, the data processing system involved in the data processing method provided in the embodiments of this application will be described in detail.

[0021] This embodiment provides a data processing system that can be used in relay protection devices.

[0022] like Figure 2As shown, the data processing system may include a processor, a memory, functional modules, and an intermediate latch. The processor and memory are connected via a parallel bus, and the processor and the intermediate latch are also connected via a parallel bus. The intermediate latch is connected to the functional modules, which include a button unit and a display unit. The button unit is used to send data processing instructions to the intermediate latch. The display unit is used to receive the target page sent by the intermediate latch. The memory is used to store a preset relay protection database, which includes a pre-built relay protection container library, a relay protection element library, and a relay protection device operation database. The intermediate latch is used to latch data processing instructions or target pages. The processor is used to implement the data processing method of any of the embodiments described below.

[0023] In this embodiment, the processor can be an MCU, the parallel bus can be an FSMC (Flexible Static Memory Controller) or EXMC (External Memory Controller) high-speed bus, the button unit can be the buttons of a relay protection device, and the display unit can be an LCD monochrome dot matrix liquid crystal. The following explanation uses the FSMC high-speed bus as an example. In this data processing system, the memory is directly connected to the parallel bus, forming a direct connection layer. Each functional module is indirectly connected to the parallel bus through an intermediate latch, forming an indirect connection layer. Devices in the direct connection layer have high real-time requirements, need frequent access by the processor, and require strict timing guarantees. Therefore, the memory is directly connected to the processor through the parallel bus, allowing access using zero-wait or low-wait timing configurations to ensure real-time control and data acquisition accuracy. The button unit and display unit, among other indirect connection layers, require a certain delay to ensure more reliable data processing instructions and clearer target pages displayed by the display unit. Therefore, to avoid the indirect connection layer affecting the efficiency of the direct connection layer, each indirect connection layer can use an intermediate latch for data transfer. The intermediate latch can have a data latching function, used to latch the interactive data between the functional modules of the relay protection device and the processor when they communicate. For example, during data visualization, the intermediate latch needs to latch the data processing instructions issued by the button unit and the target page sent by the processor. The processor can pre-allocate specific preset virtual addresses to the memory and each functional module, and select the memory and each functional module by sending pointer operations of different preset virtual addresses to the parallel bus in a time-division multiplexing manner, thereby realizing read and write access to the memory and each functional module, and thus using the parallel bus to interact with the memory and each functional module in a time-division multiplexing manner. The preset virtual address can include a first preset virtual address and a second preset virtual address. The first preset virtual address is used to select the memory, and the second preset virtual address is used to select the intermediate latch. The first preset virtual address can include at least one sub-virtual address of the memory, and the second preset virtual address can include sub-virtual addresses of each functional module.

[0024] Therefore, during data processing, firstly, the processor can output the second preset virtual address corresponding to the button unit to the parallel bus, so that the intermediate latch selects the button unit according to the second preset virtual address. At this time, only the button unit can interact with the processor through the parallel bus based on the intermediate latch, and the processor receives the data processing instructions forwarded by the intermediate latch through the parallel bus. Then, in response to the data processing instructions, the processor outputs the first preset virtual address to the parallel bus to select the memory. At this time, only the memory can interact with the processor through the parallel bus, and the processor obtains the target relay protection data and target page type corresponding to the data processing instructions from the memory through the parallel bus. Finally, the processor generates the target page corresponding to the data processing instructions according to the target relay protection data and target page type, and outputs the second preset virtual address corresponding to the display unit to the parallel bus, so that the intermediate latch selects the display unit according to the second preset virtual address. At this time, only the display unit can interact with the processor through the parallel bus, and the processor sends the target page to the intermediate latch through the parallel bus, and the intermediate latch forwards the target page to the display unit for display.

[0025] Therefore, in this embodiment, during data processing, the memory, button unit, and display unit can time-division multiplex the parallel bus to interact with the processor. Compared to the memory and each functional module being connected to the main controller through different parallel interfaces, this saves the processor's I / O resources, reduces the processor's computing burden, and avoids affecting other functions of the device used in the data processing system. Furthermore, compared to the memory and each functional module being connected to the main controller through different serial interfaces, using a parallel bus avoids the problem of slow refresh rates, thus preventing visual page stuttering and insufficient dynamic response capabilities. Applied to relay protection devices, this solves the problem of balancing I / O interface resource usage and visualization effects. Moreover, by time-division multiplexing the parallel bus, the connection layers between the memory and each functional module and the processor can be reduced from multiple layers to fewer layers, resulting in neater circuit board wiring and a smaller area for the relay protection device.

[0026] In addition, in this embodiment, a parallel bus is used for data transmission, which results in faster transmission speed and ensures that there is no refresh switching when the operation page or display page is refreshed, resulting in a smoother user experience.

[0027] The following sections will further explain some possible implementation methods for the data processing system.

[0028] In some of these embodiments, such as Figure 3As shown, the functional module may also include a sampling unit, which is used to collect the operating data of the relay protection device. The sampling unit can be directly connected to the processor via a parallel bus, and sends the operating data to the processor via the parallel bus according to the second preset virtual address sent by the processor; alternatively, the sampling unit can be connected to an intermediate latch, which selects the operating data according to the second preset virtual address sent by the processor, first sending the operating data to the intermediate latch, and then sending the operating data to the processor via the parallel bus multiplexed by the intermediate latch.

[0029] In some specific embodiments, the sampling unit may include an input sampling unit for acquiring input data and an electrical sampling unit for acquiring electrical data. Both the input sampling unit and the electrical sampling unit are connected to an intermediate latch. The intermediate latch is also configured to selectively select the input sampling unit and the electrical sampling unit according to a second preset virtual address, to acquire input data and send it to the processor via a parallel bus, and to acquire electrical data and send it to the processor via a parallel bus. The processor is further configured to send the input data and electrical data to a memory for storage according to a first preset virtual address.

[0030] In this embodiment, the input data may include switching data connected to the relay protection device, and the electrical data may include current data, voltage data, frequency, and power factor data connected to the relay protection device. The input sampling unit may be a digital input chip, and the electrical sampling unit may be an AD (Analog-to-Digital) sampling chip. The processor may also pre-allocate a second preset virtual address for the input sampling unit and the electrical sampling unit, so as to obtain the input data and electrical data from the input sampling unit and the electrical sampling unit in a time-division multiplexing manner according to the second preset virtual address using a parallel bus, and store the obtained input data and electrical data in the memory according to the first preset virtual address.

[0031] In some embodiments, the memory may include a first memory and a second memory. The first memory, connected to the processor via a parallel bus, is used to store the relay protection database. The second memory, also connected to the processor via a parallel bus, is used to store the processor's intermediate operating data; wherein the intermediate operating data includes target relay protection data and target page types, and the target relay protection data includes at least one of the following: a target relay protection container corresponding to the data processing instructions, a target relay protection element, target operating data, and a target page.

[0032] In this embodiment, as Figure 3As shown, the first memory can be a NOR Flash (Not Or Flash Memory) chip, and the second memory can be an SRAM (Static Random Access Memory) chip. The first preset virtual address can include the first sub-virtual address of the first memory and the second sub-virtual address of the second memory, thereby directly mounting the first and second memories onto the parallel bus to time-share the parallel bus, enabling the processor to achieve smoother data access.

[0033] In some embodiments, the parallel bus may include an address bus unit, a control bus unit, and a data bus unit. For example, Figure 4 As shown, the address bus unit may include address bus interfaces FSMC_A0~FSMC_A21, the control bus unit may include control bus interfaces FSMC_NOE, FSMC_NWE, FSMC_NWAIT, FSMC_NBLK0, FSMC_NBLK1 and FSMC_NE1~FSMC_NE4, and the data bus unit may include data bus interfaces FSMC_D0~FSMC_D15.

[0034] Specifically, the processor is used to output a first preset virtual address and a second preset virtual address through the address bus unit, and to output a first chip select signal generated based on the first preset virtual address, a second chip select signal generated based on the second preset virtual address, and read / write control signals through the control bus unit. In this embodiment, the processor can output the first and second preset virtual addresses through the target address bus interface in the address bus unit, and output the first and second chip select signals respectively through different control bus interfaces in the control bus unit, so as to ensure that the processor interacts with a unique memory or functional module at the same time based on the combination of read / write control signals and preset virtual addresses. The number of target address bus interfaces can be determined according to the total number of memory and functional modules. It is understood that the processor can map different preset virtual addresses to chip select signals one-to-one to ensure that the processor interacts with a unique memory or functional module at the same time. In one example, such as Figure 3 As shown, the first and second preset virtual addresses can be output through the high-order address bus interfaces FSMC_A17~FSMC_A21 in the address bus interface, the first chip select signal and the second chip select signal can be output through the control bus interfaces FSMC_NE1~FSMC_NE4, and the read / write control signal can be output through at least one of the control bus interfaces FSMC_NOE, FSMC_NWE, FSMC_NWAIT, FSMC_NBLK0 and FSMC_NBLK1.

[0035] Additionally, the first preset virtual address may include a first sub-virtual address and a second sub-virtual address, and the first chip select signal may include a first sub-chip select signal and a second sub-chip select signal. The first memory includes a first address interface unit connected to the address bus unit, a first control interface unit connected to the control bus unit, and a first data interface unit connected to the data bus unit. Specifically, the first memory is used to interact with the processor via the first data interface unit and the data bus unit according to read / write control signals when it receives the first sub-virtual address and the first sub-chip select signal. The second memory includes a second address interface unit connected to the address bus unit, a second control interface unit connected to the control bus unit, and a second data interface unit connected to the data bus unit. Specifically, the second memory is used to interact with the processor via the second data interface unit and the data bus unit according to read / write control signals when it receives the second sub-virtual address and the second sub-chip select signal.

[0036] In this embodiment, as Figure 5 As shown, the first memory is a NOR Flash chip U1, the first address interface unit includes address interfaces A0~A21 connected to address bus interfaces FSMC_A0~FSMC_A21, and the first control interface unit includes a general interface NC and an output enable interface connected to control bus interfaces FSMC_NWAIT, FSMC_NOE, FSMC_NWE and FSMC_NE2 respectively. Write enable interface Chip select interface The first data interface unit includes data interfaces D0 to D15 connected to data bus interfaces FSMC_D0 to FSMC_D21; wherein, the control bus interface FSMC_NE2 is used to output the first sub-chip select signal; the processor may also include a system reset control interface SYSTEM_RESET, connected to the reset interface RESET of the first memory, for sending a reset signal to the first memory. Figure 6 As shown, the second memory is an SRAM chip U2. The second address interface unit includes address interfaces A0~A18 connected to address bus interfaces FSMC_A0~FSMC_A18. The second control interface unit includes output enable interfaces connected to control bus interfaces FSMC_NOE, FSMC_NWE, FSMC_NBLK0, FSMC_NBLK1 and FSMC_NE3 respectively. Write enable interface Low-byte enable interface High-byte enable interface Chip select interface The first data interface unit includes data interfaces D0 to D15, which are respectively connected to data bus interfaces FSMC_D0 to FSMC_D15; wherein, the control bus interface FSMC_NE3 is used to output the second sub-chip select signal. It can be understood that when the processor selects the NOR Flash chip U1, it outputs the first sub-virtual address to the address bus unit and the first sub-chip select signal to the control bus interface FSMC_NE2; when it selects the SRAM chip U2, it outputs the second sub-virtual address to the address bus unit and the second sub-chip select signal to the control bus interface FSMC_NE3.

[0037] In some other embodiments, the second preset virtual address may include a third sub-virtual address and a fourth sub-virtual address, and the second chip select signal may include a third sub-chip select signal generated based on the fourth sub-virtual address. The data processing system may also include a decoder, and the intermediate latch may include a first latch unit and a second latch unit. The decoder, connected to the processor via an address bus unit, is used to selectively output one of a first enable signal and a second enable signal based on the third and fourth sub-virtual addresses. The first latch unit, connected to the decoder and a key unit, and connected to the processor via a data bus unit, is used to receive a data processing instruction from the key unit in response to the first enable signal, and forward the data processing instruction to the processor via the data bus unit. The second latch unit, connected to the decoder and an input sampling unit, and connected to the processor via a data bus unit, is used to receive input data from the input sampling unit in response to the second enable signal, and forward the input data to the processor via the data bus unit. The input sampling unit, connected to the processor via a control bus unit, is used to send input data to the second latch unit in response to the third sub-chip select signal.

[0038] In this embodiment, compared to the memory, the data read / write operation of the button unit has a certain latency. To improve the efficiency of the processor accessing the button unit, a first latch unit can be used to identify the slow button state of the button unit through multiple fast acquisitions at intervals, thereby reducing the time the button unit occupies the parallel bus. The decoder can output a first enable signal based on the third sub-virtual address and a second enable signal based on the fourth sub-virtual address. The decoder can be selected based on the number of bits in the virtual address and the total number of latches in the first and second latch units. For example, as shown... Figure 7 As shown, the first latch unit may include a latch U3. The first set of transceiver interfaces A0~A7 of the latch U3 is connected to the data bus interfaces D0~D7, and the second set of transceiver interfaces B0~B7 is connected to the button module. The direction control interface DIR of the latch U3 is grounded, and the enable interface of the latch U3 is... Connected to a decoder, it is used to receive the first enable signal GPI_CS1. For example... Figure 8As shown, the second latch unit may include latches U4 to U7, and the second enable signal may include a first sub-enable signal GPI_CS2 and a second sub-enable signal GPI_CS3. The first set of transceiver interfaces A0 to A7 of latches U4 and U5 are respectively connected to data bus interfaces D0 to D15. The second set of transceiver interfaces B0 to B7 of latches U4 and U5 are connected to the data interfaces XDIN0 to XDIN15 of the input sampling unit. The direction control interface DIR of latches U4 and U5 is grounded, and the enable interface of latches U4 and U5 is also grounded. Connected to the decoder, it is used to receive the first sub-enable signal GPI_CS2. The first set of transceiver interfaces A0~A7 of latch U6 and the first set of transceiver interfaces A0~A7 of latch U7 are respectively connected to the data bus interfaces D0~D15. The second set of transceiver interfaces B0~B7 of latch U6 and the second set of transceiver interfaces B0~B7 of latch U7 are respectively connected to the data interfaces XDIN16~XDIN31 of the open-source sampling unit. The direction control interface DIR of latch U6 and latch U7 is grounded. The enable interface of latch U6 and latch U7 is... Connected to the decoder, it receives the second sub-enable signal GPI_CS3. It is understood that the input sampling unit is a 32-bit digital input chip. When the input sampling unit receives the third sub-chip select signal output by the processor through the control bus unit, it outputs the input data to latches U4~U7 through data interfaces XDIN0~XDIN31. The decoder also outputs the first sub-enable signal GPI_CS2 and the second sub-enable signal GPI_CS3 respectively, enabling latches U4 and U5 to be selected in relation to latches U6 and U7, thus sending the 32-bit input data to the processor. The third sub-chip select signal can be output through the control bus interface FSMC_NE4.

[0039] In some other embodiments, the second preset virtual address may further include a fifth sub-virtual address, and the second chip select signal may further include a fourth sub-chip select signal generated based on the fifth sub-virtual address. The data processing system may further include logic gate units, and the intermediate latch may further include a third latch unit. The logic gate unit, connected to the processor via a control bus unit, is used to output a third enable signal based on the fourth sub-chip select signal. The third latch unit, connected to the logic gate unit and the electrical sampling unit, and connected to the processor via a data bus unit, is used to receive electrical data from the electrical sampling unit in response to the third enable signal, and forward the electrical data to the processor via the data bus unit. The electrical sampling unit, connected to the logic gate unit, is used to send electrical data to the third latch unit in response to the third enable signal.

[0040] In this embodiment, the logic gate unit can be a NOT gate array, such as... Figure 9 and Figure 10 As shown, the third latch unit may include latches U8 and U9, and the electrical sampling unit may include an AD sampling chip U10. The first set of transceiver interfaces A0~A7 of latches U8 and U9 are respectively connected to the data bus interfaces FSMC_D0~FSMC_D15. The direction control interface DIR of latches U8 and U9 is connected to the control bus interface FSMC_NOE. The enable interface of latch U8... Enable interface of latch U9 The logic gate unit is connected to the control bus interface FSMC_NE1 to receive the third enable signal processed by the NOT gate array. The second set of transceiver interfaces B0~B7 of latch U8 and the second set of transceiver interfaces B0~B7 of latch U9 are connected to the data interfaces DB0~DB15 of AD sampling chip U10. The chip select interface of AD sampling chip U10... The logic gate unit is connected to the control bus interface FSMC_NE1 to receive the third enable signal processed by the NOT gate array. The direction control interface DIR of the AD sampling chip U10 is connected to the control bus interface FSMC_NOE to receive read / write control signals. The processor can output a fourth sub-chip select signal through the control bus interface FSMC_NE1, enabling the logic gate unit to control latches U8 and U9 according to the fourth sub-chip select signal, thus selecting latches U8 and U9.

[0041] Understandably, this is due to the enable interfaces of latches U3~U7. It is also enabled by a low level; therefore, the enable interface of latches U3~U7 It can also be connected to the decoder through logic gate units.

[0042] In some other embodiments, the second preset virtual address may further include a sixth sub-virtual address, and the second chip select signal may further include a fifth sub-chip select signal generated based on the sixth sub-virtual address. The processor is also configured to output a display control signal based on the sixth sub-virtual address. The intermediate latch may further include a fourth latch unit. The fourth latch unit, connected to both the processor and the display unit, is configured to receive a target page via a data bus unit and forward the target page to the display unit in response to the fifth sub-chip select signal and the display control signal.

[0043] In this embodiment, as Figure 11As shown, the fourth latch unit includes a latch U11. The transceiver interfaces A1 and A2 of the latch U11 are connected to the address bus interfaces FSMC_A0 and FSMC_A1, respectively, for receiving the fifth sub-chip select signal. The transceiver interfaces A0, A3, B0, B1, B2, and B3 of the latch U11 are connected to the processor, respectively, for receiving display control signals. The transceiver interfaces A4~A7 and B4~B7 of the latch U11 are connected to the data bus interfaces FSMC_D0~FSMC_D7, respectively, for receiving the target page. The transceiver interfaces A4~A7 and B4~B7 of the latch U11 are also connected to the display unit, for forwarding the target page to the display unit.

[0044] Based on the data processing system described above, this embodiment provides a data processing method applicable to the data processing system of any of the embodiments described above. Please refer to... Figure 1 The data processing method may include: The S101 processor receives data processing instructions from the intermediate latch via a parallel bus. These instructions instruct the processor to retrieve the target relay protection data and the target page type. The data processing instructions are sent to the intermediate latch by the key unit.

[0045] S102, in response to a data processing instruction, the processor retrieves target relay protection data from memory via a parallel bus based on a first preset virtual address. The target relay protection data is data from a relay protection database, and includes at least one of a target relay protection container, a target relay protection element, and target operation data. The target relay protection container includes a target page container and a target menu container.

[0046] S103, the processor generates a menu configuration list based on the target page type and target relay protection data.

[0047] S104, the processor, based on the menu configuration list, adds at least one of the target relay protection elements and target operation data to the corresponding target menu container, and adds each target menu container to the target page container to generate a target page; S105, the processor sends the target page to the intermediate latch via the parallel bus based on the second preset virtual address.

[0048] S106, the intermediate latch forwards the target page to the display unit.

[0049] It is understood that the data processing method provided in this embodiment is based on the same concept as the data processing system in the above embodiments. Therefore, the specific implementation of the time-division multiplexing of the parallel bus in the data processing method provided in this embodiment can refer to the implementation of the above data processing system, and will not be repeated here.

[0050] In addition, in this embodiment, different preset page types can be pre-stored in the memory, allowing the MCU to automatically assemble a target page that meets the requirements of the data processing instruction by recognizing the target page type corresponding to the data processing instruction and based on the target page type and target relay protection data. The preset page type is a classification identifier for the page, used to define the business purpose, display content, menu structure, and layout rules of the visualization page. Thus, different preset page types correspond to different numbers of menus, menu order, and menu display content (including any one of electrical data, input data, and relay protection elements). Furthermore, the MCU can also employ a menu management mechanism that combines relay protection containers with a linked list structure. This mechanism decomposes the page container and its corresponding menu content into several independent menu containers. A menu configuration linked list is generated based on the target page type and target relay protection data corresponding to the data processing instruction. The target page is then generated by calling at least one of the required target page container, target menu container, target electrical data, target input data, and target relay protection elements through the menu configuration linked list. Therefore, for different data processing instructions, multiple menu configuration lists can be generated according to the corresponding target page type and target relay protection data, and the display screen of the display unit can be switched according to the multiple menu configuration lists.

[0051] In some other embodiments, a relay protection container library can be pre-built before S101. When building the relay protection container library, the processor can first generate page containers based on the size information of the display area of ​​the display unit, preset page types, preset connection attributes of the preset page types, and operation indicator bar attributes, thus building a page container library corresponding to various preset page types. The preset page types include data display pages, parameter modification pages, fault prompt pages, menu navigation pages, and password confirmation pages. Then, based on each menu type in the preset page types, a menu container is generated, building a menu container library corresponding to various menu types. Finally, based on the page container library and the menu container library, the relay protection container library is obtained. The relay protection container library is then sent to the first memory via a parallel bus, so that the first memory stores the relay protection container library.

[0052] In this embodiment, before constructing the relay protection container library, the size information of the display area can be pre-set in the MCU, and a preset page type can be configured according to the usage scenario of the relay protection device. This allows the MCU to construct the relay protection container library based on the preset size information and preset page type. Specifically, data display pages can be used to display electrical data (e.g., voltage data, current data, power data) and input data (e.g., switch status, disconnector position), supporting real-time data refresh. Parameter modification pages can be used to modify the operating parameters of the power protection system where the relay protection device is located (e.g., protection settings, sampling frequency), and may include input boxes, confirmation / cancel buttons, and other menus. Fault warning pages can be used for fault early warning (e.g., warnings for short circuits, overloads, poor contact, etc.), and may include fault codes, fault descriptions, and handling suggestions. Menu navigation pages can be used to jump to other preset page types, and may include navigation menus, return buttons, and page indexes. Password confirmation pages can be used for permission verification, and may include password input boxes, verification buttons, and error messages. Preset connection attributes can be used to define the connection rules between page containers and menu containers, the communication protocol between containers, data transmission baud rate, etc., to ensure stable data interaction between containers. Operation indicator bar attributes can uniformly set the size, position, font, color, etc. of the operation indicator bar, and can include operation prompt text (e.g., "Click to confirm and save parameters," "Please handle faults promptly"). Page containers can include page coordinate parameters, element references, and variable associations, used to host and switch between different visual pages. Menu containers are used to separate menus from menu content, reducing the refresh sensation caused by page jumps and improving the modularity of the target page.

[0053] It is understood that the target page in this embodiment may include multi-level menus. A page container can be used to define the display area of ​​each level of menu as an independent menu container, which is a logical container with clear visual boundaries. The page container may include a hierarchical navigation bar indicator used to indicate key operation methods. The page container may also include a zero-level menu, a first-level menu, a second-level menu, and a third-level menu. The zero-level menu may include a persistent cancel key, a main menu, or a switch between the cancel key and the main menu. The zero-level menu may include all the key information required for the operation of the relay protection device; however, when a fault occurs, the zero-level menu can be forcibly covered by a fault warning information menu. The first-level menu can be called up by the cancel key and includes a core function entry text block. The second-level menu can expand to the side or inside of the main menu after it is selected, used to display more specific function categories. The third-level menu can be the final operation area or information display area, occupying the main part of the display unit's display area, used to display detailed information such as setting lists, measurement data, and switch status diagrams. Furthermore, by assigning permission tags to each target page, the permissions for different user accounts to access pages can be controlled when switching target pages.

[0054] In addition, different page containers, different menu containers, and page containers and menu containers can use elements such as highlights, shadows, connecting lines, or arrows to indicate subordinate and navigation relationships, allowing users to clearly distinguish menu hierarchy relationships.

[0055] In some other embodiments, a relay protection element library can be pre-constructed before S101. When constructing the relay protection element library, the processor can first generate electrical elements based on at least one of the electrical characteristics, physical attributes, and topology connection information of the relay protection device. These electrical elements are interface elements representing primary equipment, secondary equipment, measuring and sensing elements, or electrical connection relationships of the relay protection device. Then, logic elements are generated based on at least one of the protection logic, control strategy, timing relationships, and operation rules of the relay protection device. These logic elements are logic block diagram elements corresponding to the internal logic functions of the relay protection device. Finally, interactive elements are generated based on at least one of the interaction attributes and control attributes of the relay protection device. These interactive elements are interface elements providing operation instructions, visual feedback, data interaction, and navigation positioning. Then, the relay protection element library is constructed based on the electrical elements, logic elements, and interactive elements. Finally, the relay protection element library is sent to a first memory via a parallel bus so that the first memory stores the relay protection element library.

[0056] In this embodiment, the relay protection element library may include a custom element library pre-configured according to the actual usage scenario of the relay protection device. In the data processing scenario of the relay protection device, the custom elements in the custom element library may include electrical elements, electrical elements, and interactive elements of the relay protection device. Among them, the electrical elements can be pre-constructed based on at least one of the electrical characteristics, physical attributes, and topology connection information of the relay protection device. Electrical characteristics can refer to the electrical operating parameters, operating conditions, electrical constraints, and electrical response characteristics of relay protection devices and their supporting primary and secondary equipment in a power protection system. They are used to characterize the energized operating status, wiring adaptability, and electrical operating capability of relay protection devices and their supporting primary and secondary equipment. Electrical characteristics can include rated electrical parameters (e.g., rated voltage, rated current, rated frequency, rated power, insulation class), fault electrical characteristics (e.g., short-circuit withstand current, overload current threshold, zero-sequence current threshold, negative-sequence current characteristics, harmonic withstand characteristics), operating electrical quantities (e.g., operating voltage, return voltage, operating current, return current, braking coefficient, slope characteristics), circuit electrical attributes (e.g., AC / DC system, phase sequence attributes, polarity definition, grounding method, impedance parameters), electrical response characteristics (e.g., transient response speed, steady-state accuracy, electrical delay, break electrical withstand voltage, switching electrical capacity), and sampling electrical characteristics (e.g., sampling range, sampling accuracy, analog input / output electrical specifications), etc. Physical attributes can refer to the inherent physical characteristics of physical hardware such as relay protection devices, cabinets, plug-ins, and peripheral sensing elements, including their shape, structure, installation, materials, environmental adaptability, and mechanical structure. Physical attributes can include external structure (e.g., dimensions, weight, outline, panel layout, module arrangement), installation attributes (e.g., installation method, mounting hole positions, mounting spacing, fixing specifications), hardware structure (e.g., terminal arrangement, plug-in slot structure, physical form of wiring ports, cabinet cavity structure), environmental physical parameters (e.g., operating temperature range, humidity tolerance, dustproof and waterproof rating, shock resistance rating, altitude adaptability range), mechanical attributes (e.g., button travel, knob positions, circuit breaker opening and closing mechanical travel, contact mechanical life), and materials and heat dissipation (e.g., housing material, heat dissipation structure, thermal conductivity structure, flame retardant rating). Topology connection information can refer to the node relationships, hierarchical relationships, wiring flow, network topology, and port interconnection rules between the primary circuits, secondary control circuits, signal circuits, and communication circuits of the power protection system.Topology connection information may include loop topology (e.g., main loop branch relationship, series / parallel topology, bus hierarchy topology), port connection (e.g., input port corresponding device, output port mounted object, terminal interconnection mapping relationship), hierarchical topology (e.g., station area-bay-equipment three-level topology, subordinate connection relationship of upper and lower level protection devices), signal flow (e.g., analog quantity flow, digital quantity flow, trip command flow, interlocking signal flow), networking topology (e.g., station Ethernet topology, serial bus connection topology, local / remote control connection relationship), and interconnection constraints (e.g., interlock connection point, linkage connection node, spare connection reserved point).

[0057] In addition, logic elements can be pre-constructed based on at least one of the protection logic, control strategy, timing relationship, and operation rules of the relay protection device. Protection logic can provide the fault criteria, protection principles, and fault determination logic rules followed by the relay protection to achieve fault discrimination, fault determination, and fault differentiation. Protection logic can include main protection logic (e.g., instantaneous overcurrent protection, time-limited instantaneous overcurrent protection, overcurrent protection, zero-sequence protection, distance protection, differential protection criteria), backup protection logic (e.g., near backup, far backup activation logic, step-by-step tripping logic), fault determination logic (e.g., intra-zone / extra-zone fault discrimination, inter-turn fault, ground fault, phase-to-phase fault determination logic), blocking / opening logic (e.g., overvoltage blocking, directional blocking, oscillation blocking, reclosing open logic), and enabling / disabling logic (protection soft and hard pressure plate enabling / disabling logic, function enabling / disabling enabling logic). Control strategy can provide the decision-making and execution control scheme for the relay protection device to complete actions such as tripping, closing, interlocking tripping, interlocking disconnection, voltage regulation, and stability control. Control strategies can include tripping control strategies (e.g., single-phase tripping, three-phase tripping, failure-interlocked tripping, remote tripping strategies), reclosing control strategies (e.g., single reclosing, double reclosing, reclosing with no voltage detection / synchronization detection, and blocking reclosing strategies), interlocking control strategies (e.g., automatic transfer switch logic, segmented interlocking, load interlocking, and reactive power switching strategies), operation control strategies (e.g., local / remote control switching, manual / automatic mode strategies, and start / stop control strategies), and abnormal control strategies (e.g., device abnormal blocking, circuit abnormal shutdown, and light / heavy load regulation strategies). Timing relationships can refer to the sequence, time intervals, timing constraints, and timing coordination rules of the entire process of internal signal sampling, logic judgment, command issuance, action execution, and return reset of the relay protection device. Timing relationships can include sampling timing (e.g., analog quantity synchronous sampling timing, switch quantity change acquisition timing), logic operation timing (e.g., fault criterion operation order, multi-protection priority timing), action timing (e.g., fault initiation timing, delayed action timing, instantaneous action timing, inverse time-limit timing), linkage timing (e.g., tripping first / closing second timing, linkage tripping signal sequence timing), reset timing (e.g., fault clearing reset timing, manual reset / automatic reset timing), and coordination timing (e.g., multi-bay protection action coordination timing, upper and lower level protection time-limit coordination timing). Operating rules can be digital algorithms and data processing rules for relay protection devices, such as internal numerical calculations, logic operations, threshold comparisons, filtering calculations, and setting value conversions.The operating rules may include basic electrical operations (e.g., amplitude calculation, phase calculation, power calculation, impedance calculation, sequence component decomposition operation), filtering operations (e.g., mean filtering, sliding window filtering, Fourier filtering, difference operation rules), setpoint comparison operations (e.g., setpoint difference operation, threshold comparison operation, interval determination operation), time-limited operations (e.g., inverse time-limited I²t integration operation, delay accumulation operation, time-limited interpolation operation), fault-tolerant operations (e.g., abnormal data removal operation, data calibration operation, difference compensation operation), and logical operations (e.g., AND / OR / NOT / XOR logical operations, priority logical operations, condition nesting operations).

[0058] Finally, the interactive elements are pre-constructed based on at least one of the interactive attributes and control attributes of the relay protection device. Interactive attributes can be the human-machine interface, operation and maintenance interface, and configuration interface of the relay protection device, encompassing features such as human-machine information exchange, status display, information browsing, and data retrieval. Interactive attributes can include status interactive attributes (e.g., visual display attributes for operating status, fault status, alarm status, and maintenance status), data interactive attributes (e.g., real-time quantity browsing, historical data retrieval, fault waveform viewing, and setting value viewing attributes), interface browsing attributes (e.g., menu hierarchy navigation, pagination browsing, category retrieval, and device location browsing attributes), alarm interactive attributes (e.g., alarm pop-ups, alarm hierarchical display, alarm retrieval, and alarm tracing attributes), and view interactive attributes (e.g., topology diagram zooming, loop diagram dragging, and logic block diagram preview attributes). Control attributes can be attributes related to issuing control commands, modifying parameters, switching functions, and executing operations for operation and maintenance personnel, dispatch terminals, and local operation terminals, including permissions, methods, permission constraints, and operating procedures. Control attributes may include parameter control attributes (e.g., setting modification, coefficient setting, communication parameter configuration, time calibration attributes), function control attributes (e.g., protection activation / deactivation, pressure plate simulation activation / deactivation, function enable / disable control attributes), operation control attributes (e.g., local opening / closing, remote control opening / closing, test start / stop control attributes), access control attributes (e.g., administrator / maintenance / visitor hierarchical operation permissions, password management, operation lock attributes), debugging control attributes (e.g., simulated fault injection, transmission test start, loop point-to-point control attributes), and navigation and positioning control attributes (e.g., equipment rapid positioning, loop node positioning, fault point jump control attributes).

[0059] In summary, electrical characteristics can include the electrical parameters of the relay protection device and its supporting primary and secondary equipment, fault electrical quantities, operating electrical thresholds, sampling and circuit electrical characteristics. Physical attributes can include the hardware appearance, installation specifications, environmental tolerance, mechanical structure and physical hardware parameters of the relay protection device and its supporting primary and secondary equipment. Topology connection information can include the interconnection of equipment ports, circuit hierarchy, signal flow, and power network topology of the relay protection device and its supporting primary and secondary equipment. Protection logic can include various protection fault criteria of the relay protection device, fault determination within and outside the zone, and criteria for plate activation / deactivation and interlocking. Control strategies can include the action execution decision schemes of the relay protection device, such as tripping, reclosing, linkage switching, automatic transfer switch, and local / remote control. Timing relationships can include the time sequence and time constraint rules of the relay protection device's sampling, discrimination, action, reset, and multi-device coordination. Calculation rules can include the built-in data algorithm rules of the relay protection device, such as electrical quantity analysis, filtering, integration, logical judgment, and setting comparison. Interactive attributes can include attributes related to the display of human-machine information, such as the status display of the relay protection device, data viewing, alarm retrieval, and interface browsing. Control attributes can include attributes related to the operation of human-machine commands, such as parameter setting, remote control operation, function enabling / disabling, access control, and debugging operations of the relay protection device.

[0060] In one example, electrical elements may include circuit breaker elements, capacitor elements, transformer elements, motor elements, generator elements, inductor elements, battery elements, temperature controller elements, positioning connection status elements, network connection status elements, serial port connection status elements, delta connection elements, star connection elements, and incomplete delta connection elements in the power protection system where the relay protection device is located. Circuit breaker elements may include open and closed states, capacitor elements may include charging and discharging states, motor elements may include stop and running states, generator elements may include stop and running states, inductor elements may include charging and discharging states, and temperature controller elements may include humidity and temperature information. Logic elements may include AND gate elements, OR gate elements, NOT gate elements, NAND gate elements, NOR gate elements, XOR gate elements, greater than sign elements, equal to sign elements, less than sign elements, and delay line elements. The interactive graphic elements may include cursor indicator graphic elements, key function indicator graphic elements, data modification indicator graphic elements, operation error pop-up message graphic elements, operation limit violation prompt graphic elements, and device failure pop-up message graphic elements.

[0061] Additionally, it should be noted that the relay protection graphic element library may also include standard graphic element libraries such as standard Chinese character graphic element libraries and ASCII standard graphic element libraries.

[0062] like Figure 12As shown, 12a is the page container for data display, 12b is the page container after adding a menu container, and 12c is the target page obtained after adding target relay protection elements and / or target operation data.

[0063] In some embodiments, after the processor completes the construction of at least one of the relay protection container library, the relay protection element library, and the operational database, before S101, at least one of these three libraries can be sent to the first memory for storage via a parallel bus based on a first sub-virtual address. During data processing, intermediate operational data is sent to the second memory for storage via a parallel bus based on a second sub-virtual address; wherein the intermediate operational data includes at least one of the target relay protection container, the target relay protection element, the target operational data, and the target page.

[0064] In this embodiment, the data processing method provided is based on the same concept as the data processing system in the previous embodiment. Therefore, the data storage method implemented by the processor communicating with the first and second memories in this embodiment can refer to the description in the data processing system above, and will not be repeated here for the sake of brevity.

[0065] Therefore, the data processing method in this embodiment, by constructing a custom primitive library combined with a standard primitive library, can intuitively map the real-time operating status of the relay protection device and the power protection system it belongs to based on rich graphic elements. Furthermore, a complete menu navigation system can be implemented through menu navigation pages, optimizing the human-computer interaction path guidance for the data processing method. Moreover, the mechanism of separating page containers, menu containers, and menu content allows the page containers to adopt a multi-column layout design, significantly increasing the information carrying density within a limited display area, effectively reducing menu levels, and enhancing the visualization experience and ease of operation of the relay protection device.

[0066] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0067] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A data processing method, characterized in that, This system is applied to a data processing system, which includes a processor, a memory, functional modules, and an intermediate latch. The processor and the memory are connected via a parallel bus, and the processor and the intermediate latch are connected via the same parallel bus. The intermediate latch is connected to the functional modules, which include a button unit and a display unit. The memory stores a preset relay protection database, which includes a pre-built relay protection container library, a relay protection element library, and a relay protection device operation database. The data processing method includes: The processor receives data processing instructions from the intermediate latch via the parallel bus. The data processing instructions are used to instruct the processor to acquire target relay protection data and target page type. The data processing instructions are sent to the intermediate latch by the key unit. The processor, in response to the data processing instruction, retrieves the target relay protection data from the memory via the parallel bus based on a first preset virtual address; the target relay protection data is data in the relay protection database, and the target relay protection data includes at least one of a target relay protection container, a target relay protection element, and target operation data; the target relay protection container includes a target page container and a target menu container. The processor generates a menu configuration list based on the target page type and the target relay protection data; Based on the menu configuration list, the processor adds at least one of the target relay protection element and the target operation data to the corresponding target menu container, and adds each target menu container to the target page container to generate a target page; The processor sends the target page to the intermediate latch via the parallel bus based on the second preset virtual address; The intermediate latch forwards the target page to the display unit.

2. The data processing method according to claim 1, characterized in that, Before the processor receives data processing instructions from the intermediate latch via the parallel bus, the data processing method further includes: The processor generates page containers and constructs a page container library corresponding to various preset page types based on the size information of the display unit, preset page types, preset connection attributes of the preset page types, and operation indicator bar attributes; wherein, the preset page types include data display pages, parameter modification pages, fault prompt pages, menu navigation pages, and password confirmation pages; The processor generates a menu container based on the menu type in the preset page type, and constructs a menu container library corresponding to various menu types; The processor obtains the relay protection container library based on the page container library and the menu container library; The processor sends the relay protection container library to the memory for storage via the parallel bus based on the first preset virtual address.

3. The data processing method according to claim 1, characterized in that, Before the processor receives data processing instructions from the intermediate latch via the parallel bus, the data processing method further includes: The processor generates electrical primitives based on at least one of the electrical characteristics, physical attributes, and topology connection information of the relay protection device; wherein, the electrical primitives are interface elements representing the primary equipment, secondary equipment, measuring and sensing elements, and electrical connection relationships of the relay protection device; The processor generates logic primitives based on at least one of the protection logic, control strategy, timing relationship, and operation rules of the relay protection device; wherein, the logic primitives are logic block diagram elements corresponding to the internal logic functions of the relay protection device. The processor generates interactive primitives based on at least one of the interactive attributes and control attributes of the relay protection device; wherein the interactive primitives are interface elements that provide operation instructions, visual feedback, data interaction, and navigation positioning. The processor constructs the relay protection element library based on the electrical elements, the logic elements, and the interaction elements; The processor sends the relay protection primitive library to the memory for storage via the parallel bus based on the first preset virtual address.

4. The data processing method according to claim 1, characterized in that, The operating database stores the operating data of the relay protection device, and the functional module also includes a sampling unit connected to the intermediate latch. Before the processor receives data processing instructions from the intermediate latch via the parallel bus, the data processing method further includes: The processor obtains the running data from the intermediate latch via the parallel bus based on the second preset virtual address, and the running data is sent to the intermediate latch by the sampling unit; The processor constructs the runtime database based on the runtime data; The processor sends the running database to the memory for storage via the parallel bus based on the first preset virtual address.

5. The data processing method according to any one of claims 2-4, characterized in that, The memory includes a first memory and a second memory, the first preset virtual address includes a first sub-virtual address and a second virtual address, and the data processing method further includes: The processor sends at least one of the relay protection container library, the relay protection primitive library, and the running database to the first memory for storage via the parallel bus based on the first sub-virtual address; The processor sends intermediate running data to the second storage processor for storage via the parallel bus based on the second sub-virtual address; wherein, the intermediate running data includes at least one of the target relay protection container, the target relay protection element, the target running data, and the target page.

6. A data processing system, characterized in that, It includes a processor, a memory, a functional module, and an intermediate latch; the processor and the memory are connected via a parallel bus, the processor and the intermediate latch are connected via the parallel bus, and the intermediate latch is connected to the functional module, the functional module including a button unit and a display unit; The button unit is used to send data processing instructions to the intermediate latch; The display unit is used to receive the target page sent by the intermediate latch; The memory is used to store a preset relay protection database, which includes a pre-built relay protection container library, a relay protection element library, and a relay protection device operation database. The intermediate latch is used to latch the data processing instructions and the target page; The processor is configured to implement the data processing method as described in any one of claims 1 to 5.

7. The data processing system according to claim 6, characterized in that, The parallel bus includes an address bus unit, a control bus unit, and a data bus unit, and the memory includes a first memory and a second memory; The processor is specifically configured to output the first preset virtual address through the address bus unit and output a first chip select signal and a read / write control signal generated based on the first preset virtual address through the control bus unit; the first preset virtual address includes a first sub-virtual address and a second sub-virtual address, and the first chip select signal includes a first sub-chip select signal and a second sub-chip select signal. The first memory includes a first address interface unit connected to the address bus unit, a first control interface unit connected to the control bus unit, and a first data interface unit connected to the data bus unit. Specifically, the first memory is used to perform data interaction with the processor through the first data interface unit and the data bus unit according to the read / write control signal when it receives the first sub-virtual address and the first sub-chip select signal. The second memory includes a second address interface unit connected to the address bus unit, a second control interface unit connected to the control bus unit, and a second data interface unit connected to the data bus unit. Specifically, when the second sub-virtual address and the second sub-chip select signal are received, the second memory interacts with the processor through the second data interface unit and the data bus unit according to the read / write control signal.

8. The data processing system according to claim 7, characterized in that, The functional module also includes a sampling unit connected to the intermediate latch, the sampling unit including an input sampling unit for collecting input data; The processor is further configured to output the second preset virtual address through the address bus unit and output a second chip select signal generated according to the second preset virtual address through the control bus unit; the second preset virtual address includes a third sub-virtual address and a fourth sub-virtual address, and the second chip select signal further includes a third sub-chip select signal generated according to the fourth sub-virtual address; The data processing system also includes: The decoder, connected to the processor via the address bus unit, is used to selectively output one of a first enable signal and a second enable signal based on the third sub-virtual address and the fourth sub-virtual address. The intermediate latch includes: The first latch unit is connected to the decoder and the key unit, and is connected to the processor through the data bus unit. It is used to receive the data processing instruction issued by the key unit in response to the first enable signal, and forward the data processing instruction to the processor through the data bus unit. The second latch unit is connected to the decoder and the input sampling unit, and is connected to the processor through the data bus unit. It is used to receive the input data from the input sampling unit in response to the second enable signal, and forward the input data to the processor through the data bus unit. The input sampling unit is connected to the processor via the control bus unit and is used to send the input data to the second latch unit in response to the third sub-chip select signal.

9. The data processing system according to claim 8, characterized in that, The sampling unit further includes an electrical sampling unit for collecting electrical data, the second preset virtual address further includes a fifth sub-virtual address, and the second chip select signal further includes a fourth sub-chip select signal generated according to the fifth sub-virtual address; The data processing system also includes: The logic gate unit is connected to the processor through the control bus unit and is used to output a third enable signal according to the fourth sub-chip select signal; The intermediate latch also includes: The third latch unit is connected to the logic gate unit and the electrical sampling unit, and is connected to the processor through the data bus unit. It is used to receive electrical data from the electrical sampling unit in response to the third enable signal, and forward the electrical data to the processor through the data bus unit. The electrical sampling unit is connected to the logic gate unit and is used to send the electrical data to the third latch unit in response to the third enable signal.

10. The data processing system according to claim 9, characterized in that, The second preset virtual address also includes a sixth sub-virtual address, and the second chip select signal also includes a fifth sub-chip select signal generated based on the sixth sub-virtual address; The processor is also configured to output a page sending signal according to the sixth sub-virtual address; The intermediate latch also includes: The fourth latch unit, connected to the processor and the display unit respectively, is used to receive the target page through the data bus unit in response to the fifth sub-chip select signal and the page transmission signal, and forward the target page to the display unit.

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