Wafer test circuit board automated detection and repair system

Abstract

This invention discloses an automated inspection and repair system for wafer test circuit boards. Targeting impedance mismatch defects, it integrates multimodal data from optical, electrical, X-ray, and auxiliary sensing sensors. After preprocessing, alignment, and weighted fusion by a data fusion module, the defect detection module uses a lightweight multimodal model to identify, locate, classify, and grade defects. It also traces the cause of defects and calculates impedance deviation compensation based on process parameters, and can provide early warning of impedance anomaly trends based on LSTM and attention mechanisms. The system adaptively repairs defects according to the compensation amount through units such as laser circuit trimming, while a re-inspection unit adjusts repair parameters in real time. A digital twin module constructs a defect evolution model to achieve predictive maintenance and pre-optimization of repair parameters. An interaction and storage module completes data visualization, storage traceability, and remote control. This invention automates the entire process of impedance mismatch defect detection and repair, improves detection rate and repair accuracy, reduces manual intervention, and adapts to the high-frequency testing requirements of advanced processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and more particularly to an automated testing and repair system for wafer test circuit boards. Background Technology

[0002] Wafer test circuit boards (usually referring to dedicated circuit boards used in the wafer testing stage) are key hardware components in the semiconductor testing process. They are mainly used to perform electrical performance tests on each die on the wafer before the chip is cut and packaged. However, traditional testing methods often require a lot of manual operation and are difficult to process defects in the test results in real time.

[0003] If the wafer test circuit board has impedance mismatch defects, it will cause reflection, attenuation and timing deviation of high-speed test signals, resulting in test waveform distortion, increased signal crosstalk and distorted test results, which can easily lead to false chip failures and misjudgments of yield. At the same time, it will amplify the fluctuation of probe contact resistance, reduce test stability and repeatability, and fail to meet the high-frequency testing requirements of advanced processes. In addition, impedance mismatch will also cause local energy loss and temperature rise, accelerate probe card aging and failure, and may induce intermittent latent faults, which will seriously affect chip test accuracy and production yield.

[0004] However, existing technologies have significant shortcomings in detecting impedance mismatch defects, mainly in the following aspects: they rely primarily on offline static measurements, which cannot reflect the actual high-frequency dynamic operating state; they can only obtain overall impedance indicators, making it difficult to accurately locate defects; they use fixed threshold judgments, which are easily affected by environmental and process fluctuations, resulting in a high false alarm rate; they lack the fusion of optical, structural, and electrical multi-modal data, making it impossible to distinguish the true cause of impedance anomalies; they are not linked with ATE timing data, lacking early drift warning capabilities; and the detection results cannot support automated repair, making it difficult to meet the requirements of advanced processes in terms of overall detection accuracy, real-time performance, and engineering practicality.

[0005] Therefore, there is an urgent need to develop an automated inspection and repair system for wafer test circuit boards. This system should integrate multimodal data and combine dynamic time-series change analysis to detect defects in wafer test circuit boards and perform adaptive repair based on the detected defects. This would reduce manual intervention and improve the testing efficiency and accuracy of wafer test circuit boards. Summary of the Invention

[0006] To address the aforementioned issues, this invention provides an automated inspection and repair system for wafer test circuit boards. By integrating multimodal data and introducing a lightweight multimodal large model, dynamic timing analysis algorithm, and high-precision impedance testing technology, it achieves full-process automation for impedance mismatch defect detection and repair. This solves the pain points of existing technologies, such as impedance detection being detached from actual working conditions, inaccurate positioning, difficulty in determining the cause, and reliance on manual repair. It adapts to the mass production needs of advanced process high-frequency wafer test circuit boards, improves test stability and chip test yield, and reduces maintenance costs.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: This invention provides an automated inspection and repair system for wafer test circuit boards, including a communication connection: Data acquisition module: used to acquire multimodal data of wafer test circuit boards, including optical data, electrical data, internal structure data and auxiliary data; Data fusion module: used to preprocess the multimodal data, align the multimodal data by establishing a global three-dimensional coordinate system of the wafer test circuit board, extract multimodal feature vectors from the aligned data, and generate fused feature data after weighting; Defect detection module: Based on the built-in lightweight multimodal model, it identifies defects in the fused feature data, analyzes the causes based on the defect identification results, calculates the impedance deviation compensation amount by combining dynamic impedance time series data with the cause analysis results, and provides early warning based on dynamic thresholds. Adaptive Repair Module: Used to adaptively repair and re-inspect detected defects based on defect identification results and cause analysis results.

[0008] Preferably, the optical data includes 2D images and 3D contour data of the circuit board; the electrical data includes static impedance parameters and dynamic impedance timing data; and the auxiliary data includes temperature, humidity, vibration, and position data.

[0009] As a preferred approach, a multimodal feature weight allocation model is established. Based on the common causes of impedance mismatch defects in wafer test circuit boards, dynamic weights are assigned to different modal feature vectors. The modal feature vectors are then normalized and weighted and summed according to the dynamic weights to generate fused high-dimensional global feature data. The global feature data is then dimensionality-reduced and optimized to remove redundant features, retain core feature parameters, and output standardized, high-quality fused feature data.

[0010] Preferably, the defect detection module includes a defect identification unit, a defect cause tracing unit, and an impedance deviation calculation unit; Defect identification unit: Built-in lightweight multimodal model, used to identify, locate, classify and grade defects based on fused feature data, and obtain defect identification results; Cause tracing unit: used to correlate dynamic impedance timing data, internal structure data and process parameters, and analyze the cause of defects by combining defect identification results to obtain cause analysis results; Impedance deviation calculation unit: used to calculate the impedance deviation compensation amount based on dynamic impedance time series data and cause analysis results.

[0011] Even better, the dynamic impedance timing data, internal structure data, and process parameters are correlated, and the causes of defects are analyzed in conjunction with the defect identification results to obtain the cause analysis results, including the following steps: Construct a database linking dynamic impedance timing data, internal structure data, and process parameters; Based on the defect identification results, the dynamic impedance time series data, internal structure data and process parameters corresponding to the defect location in the associated database are matched, and dynamic features and structural features are extracted. Based on the dynamic and structural characteristics, the abnormal process parameters that exceed the standard threshold range are identified by comparing them with the standard threshold range of the process parameters. Based on the abnormal process parameters, and combined with a preset defect feature-process parameter correlation analysis model, the causal relationship between abnormal process parameters and defect features is analyzed. Based on the aforementioned causal relationship, and combined with the typical cause library of impedance mismatch defects, a comprehensive analysis is conducted on abnormal process parameters, defect dynamic characteristics, and defect structural characteristics to determine the core cause of impedance mismatch defects, while clarifying the evolution law and influencing factors of the defects. Integrate all analytical information to form and output causal analysis results that include core causes, abnormal process parameters, and defect evolution characteristics.

[0012] More preferably, based on dynamic impedance timing data and cause analysis results, the impedance deviation compensation is calculated, including the following steps: Based on dynamic impedance time series data, the actual impedance value, impedance drift peak, drift rate, and real-time deviation between the actual impedance value and the design standard impedance are extracted from the defect location across the entire operating frequency range. Simultaneously, the structural anomaly characteristics and associated abnormal process parameters corresponding to the defect location are extracted from the cause analysis results. Based on the extracted data, and combined with the preset impedance deviation-cause compensation mapping model, the corresponding compensation method and compensation coefficient are matched. Based on the compensation method and compensation coefficient, combined with the difference between the actual impedance value at the defect location and the design standard impedance, the peak impedance drift, and structural anomaly characteristic parameters, the compensation amount is calculated and corrected according to the abnormal process parameters. Based on the impedance deviation characteristics within the operating frequency range of the wafer test circuit board, the impedance deviation compensation amount adapted to the defect location across the entire frequency range is calculated and output.

[0013] Preferably, the defect detection module further includes a trend prediction unit, used to analyze dynamic impedance time-series data based on LSTM and attention mechanisms, capture abnormal impedance change trends, and provide early warnings in conjunction with dynamic thresholds, including the following steps: The dynamic impedance timing data of the wafer test circuit board across the entire operating frequency range is preprocessed and the timing dimension of the data is regularized to obtain a standardized dynamic impedance timing dataset. An impedance trend analysis network based on LSTM and attention mechanism is constructed to analyze a standardized dynamic impedance time series dataset and locate abnormal trend feature points in the impedance time series data. Based on the design standard impedance of the wafer test circuit board, combined with historical normal impedance timing data and the fluctuation range of the entire process, a dynamic threshold model is constructed using the sliding window statistical method and adaptive learning algorithm, and the threshold is dynamically updated according to the impedance data collected in real time. The actual impedance value and drift rate corresponding to the abnormal trend feature point are compared with the real-time threshold range output by the dynamic threshold model. If the actual impedance value exceeds the threshold range or the impedance drift rate reaches the preset abnormal warning threshold, it is determined that there is a risk of impedance abnormal evolution. When an impedance anomaly evolution risk is detected, an early warning signal is immediately triggered, and the specific characteristics of the abnormal trend are output. These characteristics include the anomaly start location, impedance drift rate, frequency adaptation range, and associated process parameters.

[0014] Preferably, the adaptive repair module includes a laser circuit trimming unit, a via repair unit, a probe precision calibration unit, a high-precision welding unit, a substrate dielectric compensation unit, and a re-inspection unit. Laser line trimming unit: Equipped with a high-precision pulsed laser with adaptive power adjustment, it performs laser trimming and polishing on the transmission line based on the impedance deviation compensation amount to correct the characteristic impedance of the line, targeting impedance mismatch defects such as abnormal line structure. Via Repair Unit: Targeting impedance mismatch defects such as via defects, it integrates high-precision laser drilling and micro-electroplating technology to open blocked vias, repair rough or copper-free via walls, and restore via conductivity and impedance stability. Precision probe calibration unit: In response to abnormal impedance mismatch defects in probe assemblies, it integrates a high-precision micro-robotic arm and thermal correction technology to calibrate probe tilt and height, and repair probe tip wear. High-precision welding unit: For welding and contamination-related impedance mismatch defects, it is equipped with a temperature-adaptive hot air welding module and an inert gas protection device to repair probe and pad cold solder joints, remove flux residues, and reduce contact resistance. Substrate dielectric compensation unit: To address abnormal impedance mismatch defects in substrate materials, a high-precision dielectric material coating technology is used to coat dielectric materials, adjust the dielectric constant, and restore the characteristic impedance of the circuit. Re-inspection unit: Used to perform multi-modal testing on the circuit board again after repair. By comparing the defect data before and after repair, it determines whether the repair is qualified and automatically records the re-inspection results and links them to the repair record.

[0015] Preferably, the re-inspection unit is also used to collect repair parameters in real time during the repair process and dynamically adjust the repair parameters based on the impedance deviation compensation algorithm, including the following steps: During the repair process, the core repair parameters of the laser line trimming unit, via repair unit, probe precision calibration unit, high-precision welding unit, and substrate dielectric compensation unit are collected in real time, as well as the dynamic impedance detection data of the repair area. The dynamic impedance detection data is compared with the impedance deviation compensation amount in real time to obtain the real-time impedance deviation value during the repair process. Based on the impedance deviation compensation algorithm, the real-time adjustment amount of each repair parameter is calculated according to the real-time impedance deviation value and the preset repair parameter-impedance deviation correlation model, and the repair parameters that deviate from the optimal value are adaptively and dynamically corrected.

[0016] As a preferred option, it also includes a digital twin module, which is used to build an impedance defect evolution model based on digital twin technology, realize the visualization of system status through real-time synchronization of virtual and real data, and perform predictive maintenance of impedance anomalies, virtual simulation of repair processes, and parameter pre-optimization based on the impedance defect evolution model.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: By integrating multimodal data from optics, electronics, X-rays, vibration, and temperature, this system solves the problems of traditional offline static testing being detached from actual working conditions and prone to missing latent impedance anomalies induced by dynamic / temperature changes. This significantly improves the detection rate of impedance mismatch defects. Simultaneously, vibration data is used to eliminate environmental interference, enhancing detection stability under complex conditions. The entire process, from data acquisition to re-inspection and verification, is automated, requiring no manual intervention. Early warning and precise repair extend the probe card's lifespan by over 30%, reducing probe card replacement and maintenance costs. By constructing an impedance defect evolution model using digital twins, it enables virtual simulation of predictive maintenance and repair processes for impedance anomalies, proactively mitigating repair risks and optimizing production process parameters to reduce impedance mismatch defects at the source, forming a closed-loop management system throughout the entire lifecycle. Attached Figure Description

[0018] Figure 1 This is a block diagram of the automated testing and repair system for wafer test circuit boards of the present invention; Figure 2 This is a flowchart of the defect cause tracing unit steps of the present invention; Figure 3 This is a flowchart of the impedance deviation calculation unit steps of the present invention; Figure 4 This is a flowchart of the trend prediction unit steps of the present invention. Detailed Implementation

[0019] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided.

[0020] The impedance mismatch defect addressed in this invention refers to various defects in wafer test circuit boards where the actual impedance values ​​of transmission lines, vias, probe contact areas, and power networks deviate from the design standard impedance (commonly 50Ω, 75Ω) by more than ±5% within the operating frequency range (1GHz-50GHz), or where the impedance values ​​drift with temperature, test pressure, and time (drift amount ≥3%), resulting in abnormal signal transmission and distorted test data.

[0021] Please see Figure 1 As shown, this invention provides an automated inspection and repair system for wafer test circuit boards, designed for the detection and repair of impedance mismatch defects, including a communication connection: Data acquisition module: used to acquire multimodal data of wafer test circuit boards, including optical data, electrical data, internal structure data and auxiliary data; The optical data includes 2D images and 3D contour data of the circuit board; the electrical data includes static impedance parameters and dynamic impedance timing data; and the auxiliary data includes temperature, humidity, vibration, and position data.

[0022] To avoid low defect detection rates due to single-modal data, this invention integrates optical, electrical, and X-ray detection methods, employing high-precision sensors and dedicated detection equipment to acquire multimodal data. The data acquisition module includes built-in optical detection, electrical detection, X-ray detection, and auxiliary sensing submodules, specifically: The optical inspection submodule consists of a 2D AOI inspection unit, a 3D AOI inspection unit, and a high-precision microscopic imaging unit, equipped with a ring-shaped shadowless light source, a high-resolution industrial camera, and a laser scanner. The 2D AOI unit acquires 2D images of the circuit board surface to detect surface defects (scratches, contamination, pad oxidation, solder balls, burrs, pinholes), open / short circuits, and line width / spacing deviations. The 3D AOI inspection unit uses structured light imaging technology to acquire 3D contour data of the circuit board surface, detecting probe height consistency (coplanarity ≤ 0.5μm), probe deformation (bending, tilt angle ≥ 0.1°), tip wear / chipping (≥ 0.3μm), board warping (warping ≤ 5μm / mm), and abnormal solder joint height. The microscopic imaging unit magnifies micro-defects (such as micro-bridging and tip micro-wear) (magnification ≥ 1000x), capturing subtle defect features and providing detailed support for algorithm recognition.

[0023] Electrical Testing Submodule: This submodule incorporates a high-precision impedance testing unit. It utilizes a high-frequency network analyzer (test frequency 1GHz-50GHz, impedance measurement accuracy ±0.1Ω), an LCR meter (measurement range 1mΩ-10MΩ, accuracy ±0.01%), and an impedance analyzer to collect core parameters such as characteristic impedance, return loss, insertion loss, crosstalk, contact resistance, and insulation resistance, covering critical locations including circuits, vias, probe contact areas, and power networks. It supports static testing (no-load, room temperature) and dynamic testing (simulating actual working conditions: high frequency, high current, temperature 23±5℃, probe dynamic contact pressure), addressing the limitation of existing technologies being detached from real-world conditions. Simultaneously, it deeply integrates with ATE testing equipment to collect impedance timing data (sampling frequency ≥200MHz) during probe contact and high-frequency signal transmission, capturing impedance drift, transient changes, and temperature-induced impedance fluctuations. A new temperature-impedance linkage acquisition feature allows simultaneous acquisition of impedance values ​​at different temperatures (20℃-40℃) to identify temperature-induced latent impedance mismatch defects.

[0024] X-ray inspection submodule: Employs micro-focus X-ray inspection equipment (focus size ≤ 5μm) and CT tomography unit to penetrate the circuit board substrate, collect internal structural data, and detect hidden defects, such as PCB substrate inner layer defects (delamination, bubbles, resin voids, open / short circuits in inner layer circuits, exposed fibers), via defects (rough hole walls, no copper in the hole, hole misalignment, hole blockage), and soldering defects (cold solder joints, bubbles inside the solder joint, weak soldering between the pad and the probe (hidden cold solder joints)).

[0025] Auxiliary sensing submodule: Equipped with temperature sensor, humidity sensor, and vibration sensor, it collects environmental parameters in real time (temperature controlled at 23±2℃, humidity at 45±5%RH) to avoid environmental factors affecting detection accuracy; it is also equipped with position sensor (positioning accuracy ≤0.1μm) to achieve precise positioning of circuit board and probe, providing position reference for detection and repair.

[0026] By collecting vibration data, the system can, on the one hand, eliminate interference from external and mechanical vibrations on impedance and contact resistance measurements, improve the accuracy of impedance mismatch defect detection, and reduce false alarm rates. On the other hand, through correlation analysis between vibration characteristics and impedance time-series data, it can assist in identifying mechanical structural defects such as probe loosening, solder joint microcracks, and substrate deformation, thereby improving the accuracy of impedance anomaly identification and location. Simultaneously, it can monitor mechanical stability during the repair process to avoid introducing new structural shifts and impedance anomalies, and can also perform long-term monitoring of the mechanical health status of the probe card, enabling early warning of impedance drift and enhancing the system's generalization ability and detection robustness under complex working conditions.

[0027] Data fusion module: connected to the data acquisition module, used to preprocess the multimodal data, align the multimodal data by establishing a global three-dimensional coordinate system of the wafer test circuit board, extract multimodal feature vectors from the aligned data, and generate fused feature data after weighting; For the 2D images, 3D contours and microscopic imaging data acquired by the optical inspection submodule, Gaussian filtering algorithm is used to remove image noise, histogram equalization is used to enhance the image, threshold segmentation algorithm is used to extract the grayscale, contour, texture and three-dimensional morphology features of the defect area, and the 3D contour data is normalized to unify the coordinate scale.

[0028] The static impedance parameters and dynamic impedance time series data collected by the electrical detection submodule are processed by wavelet denoising algorithm to remove signal interference. The systematic errors introduced by test fixtures and ambient temperature are eliminated by detrending and normalization processing. Effective electrical features such as deviation value and fluctuation rate of static impedance and peak value, valley value, drift rate and transient change characteristics of dynamic time series are extracted.

[0029] The internal structure tomographic scan data acquired by the X-ray inspection submodule is denoised using adaptive median filtering. The internal structural details of the substrate, vias, and solder joints are restored using a contrast enhancement algorithm. The morphology, size, and location features of latent defects such as delamination, bubbles, voids, and hole misalignment are extracted using an edge detection algorithm.

[0030] For the temperature, humidity, vibration, and location data collected by the auxiliary sensing submodule, an outlier removal algorithm is used to filter invalid data, frequency domain transformation is performed on the vibration data to extract vibration frequency and amplitude features, and temperature and humidity data are normalized to retain environmental characteristic parameters related to impedance anomalies.

[0031] Based on the high-precision position data (positioning accuracy ≤ 0.1μm) collected by the auxiliary sensing submodule, a global three-dimensional coordinate system for the wafer test circuit board is established. Using this coordinate system as a reference, coordinate calibration and registration algorithms are employed to uniformly map the local coordinates of optical, electrical, and X-ray data to the global coordinate system. This achieves precise matching between the surface feature positions of optical images and the corresponding positions of internal X-ray structures, precise correspondence between impedance anomaly measurement points of electrical detection and structural feature positions of optical and X-ray detection, and precise correlation between auxiliary data such as vibration and temperature and spatial positions. This ensures the consistency of multimodal data in spatial position, with a coordinate alignment error ≤ 0.2μm, providing a unified position reference for subsequent feature fusion and defect localization.

[0032] Structured feature extraction is performed on the preprocessed and coordinate-aligned multimodal data to transform the raw data into quantifiable and fusionable feature vectors: Surface structure feature vectors are extracted from optical data, including features such as linewidth and spacing, probe shape, pad status, and the location, size, and shape of surface defects; Electrical performance feature vectors are extracted from electrical data, including features such as static impedance, return loss, insertion loss, contact resistance, dynamic impedance drift rate, and transient change amplitude; Internal structure feature vectors are extracted from X-ray data, including features such as substrate dielectric properties, via conductivity, solder joint internal structure, and the location, size, and shape of latent defects; Environmental and operating condition feature vectors are extracted from auxiliary data, including features such as temperature, humidity, vibration frequency, vibration amplitude, and location coordinates.

[0033] A multimodal feature weighting model is established. Based on the common causes of impedance mismatch defects on wafer test circuit boards, dynamic weights are assigned to different modal feature vectors. The modal feature vectors are then normalized and weighted summed according to these dynamic weights to generate fused high-dimensional global feature data. This feature data simultaneously includes the surface structure, internal structure, electrical performance, and operating environment characteristics of the wafer test circuit board, completely preserving all valid information related to impedance mismatch defects. The fused global feature data undergoes dimensionality reduction optimization, eliminating redundant features and retaining core feature parameters, outputting standardized, high-quality fused feature data for the defect detection module to perform defect identification, cause analysis, and early warning.

[0034] For example, to address impedance mismatch caused by abnormal circuit structure or probe components, increase the weight of surface structure feature vectors; to address impedance mismatch caused by substrate delamination or via defects, increase the weight of internal structure feature vectors; to address impedance mismatch caused by contact resistance fluctuations or dynamic impedance drift, increase the weight of electrical performance feature vectors; and to address impedance anomalies caused by temperature and vibration interference, increase the weight of environmental and operating condition feature vectors.

[0035] Defect detection module: Connected to the data fusion module, it identifies defects in the fused feature data based on the built-in lightweight multimodal model, analyzes the causes based on the defect identification results, calculates the impedance deviation compensation amount by combining dynamic impedance time series data and cause analysis results, and provides early warning based on dynamic thresholds. The defect detection module includes a defect identification unit, a defect cause tracing unit, and an impedance deviation calculation unit; Defect identification unit: Built-in lightweight multimodal model, used to identify, locate, classify and grade defects based on fused feature data, and obtain defect identification results; Specifically, the lightweight multimodal model is a lightweight improved neural network model based on the Transformer architecture. This model takes the fused high-quality feature data output by the data fusion module as input. First, the model's multimodal feature encoding layer deeply encodes the dimensional features included in the fused features, such as surface structure, electrical performance, internal structure, environment, and operating conditions, extracting high-dimensional correlation features related to impedance mismatch defects. Then, through a feature decoding layer and a classification and localization network layer, combined with a sample feature library of impedance mismatch defects on wafer test circuit boards, the feature data is matched and analyzed to accurately identify impedance mismatch defects. Simultaneously, based on the auxiliary perception submodule... A global three-dimensional coordinate reference is used to locate the spatial position of defects on the wafer test circuit board. Based on the manifestation of the defects, they are classified into five types of causes: circuit structure abnormality, via defect, probe assembly abnormality, substrate material abnormality, and soldering and contamination abnormality. According to the deviation range of the actual impedance value from the design standard impedance and the amount of impedance drift, the defects are classified into three levels: minor (deviation ±5%-±8% / drift ≥3%), moderate (deviation ±8%-±12% / drift ≥5%), and severe (deviation >±12% / drift ≥8%). Finally, the defect identification results, location information, cause type and level classification are integrated to form a complete defect identification result and output it.

[0036] Please see Figure 2 As shown, the cause tracing unit is used to correlate dynamic impedance timing data, internal structure data, and process parameters, and analyze the causes of defects in conjunction with defect identification results to obtain cause analysis results. This includes the following steps: Construct a database linking dynamic impedance timing data, internal structure data, and process parameters; The process parameters cover key parameters such as etching temperature, dielectric layer coating thickness, electroplating parameters, and soldering temperature in the circuit board manufacturing stage, as well as probe piercing pressure, test environment temperature and humidity, and probe card usage frequency in the wafer testing stage.

[0037] Based on the defect identification results, the dynamic impedance time series data, internal structure data and process parameters corresponding to the defect location in the associated database are matched, and dynamic features and structural features are extracted. Based on the defect identification results, the spatial coordinates, cause type, defect level, and corresponding feature identifiers of impedance mismatch defects are extracted. Based on the location coordinates and feature identifiers, precise matching is performed in a pre-built association database. Dynamic impedance timing data, X-ray internal structure tomography data, and process parameters associated with the entire circuit board manufacturing and wafer testing process are retrieved for the defect location across the entire operating frequency band. Subsequently, feature extraction is performed on the dynamic impedance timing data obtained from the matching to obtain dynamic features such as impedance drift rate, transient change amplitude, and impedance deviation fluctuation range. At the same time, feature extraction is performed on the internal structure data to obtain structural features such as circuit structure deviation, via status, substrate dielectric properties, and probe morphology.

[0038] Based on the dynamic and structural characteristics, the abnormal process parameters that exceed the standard threshold range are identified by comparing them with the standard threshold range of the process parameters. Based on the abnormal process parameters, and combined with a preset defect feature-process parameter correlation analysis model, the causal relationship between abnormal process parameters and defect features is analyzed. Abnormal process parameters are matched with a pre-defined defect feature-process parameter correlation analysis model. This model stores quantitative causal mapping relationships between various typical defect features of impedance mismatch defects on wafer test circuit boards and various process parameters. Through this model, correlation matching and correlation analysis are performed on the abnormal process parameters and the dynamic and structural features corresponding to the defect location. This quantifies the influence of abnormal process parameters on defect features, clarifies the causal triggering logic between the two, and determines whether the abnormal process parameter is the direct cause of the impedance mismatch defect.

[0039] Based on the aforementioned causal relationship, and combined with the typical cause library of impedance mismatch defects, a comprehensive analysis is conducted on abnormal process parameters, defect dynamic characteristics, and defect structural characteristics to determine the core cause of impedance mismatch defects, while clarifying the evolution law and influencing factors of the defects. Based on the established causal relationship between abnormal process parameters and defect characteristics, a pre-stored library of typical causes of impedance mismatch defects is invoked. This library covers five core causes: abnormal circuit structure, via defects, probe assembly abnormalities, substrate material abnormalities, and welding and contamination abnormalities. It also includes typical defect characteristics, associated process parameters, and evolution patterns for each cause. Subsequently, abnormal process parameters, defect dynamic characteristics, and defect structural characteristics are input into the library for multi-dimensional matching and comprehensive analysis. Non-core causes are eliminated, and the root cause of the impedance mismatch defect is identified. At the same time, the evolution trend of dynamic impedance time series data is combined to clarify the development pattern of the defect with time, temperature, and test pressure, as well as key influencing factors. This provides accurate causal basis for subsequent impedance deviation compensation calculations and process optimization.

[0040] Integrate all analytical information to form and output causal analysis results that include core causes, abnormal process parameters, and defect evolution characteristics.

[0041] Please see Figure 3 As shown, the impedance deviation calculation unit is used to calculate the impedance deviation compensation amount based on dynamic impedance time series data and cause analysis results, including the following steps: Based on dynamic impedance time series data, the actual impedance value, impedance drift peak, drift rate, and real-time deviation between the actual impedance value and the design standard impedance are extracted from the defect location across the entire operating frequency range. Simultaneously, the structural anomaly characteristics and associated abnormal process parameters corresponding to the defect location are extracted from the cause analysis results. Based on the extracted data, and combined with the preset impedance deviation-cause compensation mapping model, the corresponding compensation method and compensation coefficient are matched. The extracted data, including actual impedance deviation, structural anomaly characteristics, and abnormal process parameters, are input into a pre-defined impedance deviation-cause compensation mapping model. This model pre-stores five core causes: circuit structure anomalies, via defects, probe assembly anomalies, substrate material anomalies, and welding and contamination anomalies. These correspond to different compensation methods such as circuit trimming, probe calibration, and dielectric compensation, as well as compensation coefficients for different impedance deviation ranges and drift characteristics. Based on the core cause and deviation characteristics of the defect, the optimal compensation method and compensation coefficient for that defect are matched and obtained.

[0042] Based on the compensation method and compensation coefficient, combined with the difference between the actual impedance value at the defect location and the design standard impedance, the peak impedance drift, and structural anomaly characteristic parameters, the compensation amount is calculated and corrected according to the abnormal process parameters. Based on the impedance deviation characteristics within the operating frequency range of the wafer test circuit board, the impedance deviation compensation amount adapted to the defect location across the entire frequency range is calculated and output.

[0043] The impedance deviation calculation unit optimizes the corrected compensation amount across the entire operating frequency range of the wafer test circuit board, taking into account the impedance deviation characteristics at each frequency point. It calculates the impedance deviation compensation amount that is uniformly adapted to the defect location across the entire frequency range. This compensation amount includes the compensation dimension, compensation value, compensation accuracy requirements, and frequency adaptation range. Finally, the compensation amount is output to the adaptive repair module, providing accurate repair parameters for each repair execution unit and ensuring that the impedance value at the defect location stably returns to the design standard range after repair.

[0044] Please see Figure 4 As shown, the defect detection module also includes a trend prediction unit, used to analyze dynamic impedance time-series data based on LSTM and attention mechanisms, capture abnormal impedance change trends, and provide early warnings in conjunction with dynamic thresholds, including the following steps: The dynamic impedance timing data of the wafer test circuit board across the entire operating frequency range is preprocessed and the timing dimension of the data is regularized to obtain a standardized dynamic impedance timing dataset. An impedance trend analysis network based on LSTM and attention mechanism is constructed to analyze a standardized dynamic impedance time series dataset and locate abnormal trend feature points in the impedance time series data. An impedance trend analysis network based on LSTM and attention mechanism is constructed. A standardized dynamic impedance time series dataset is input into the network. The time series features of impedance time series are extracted through multi-layer LSTM units to capture the continuous evolution of impedance values ​​with time, temperature and test pressure. Then, the attention mechanism layer assigns weights to the time series features, strengthens the weights of abnormal features such as impedance drift, slow shift and transient change, weakens the influence of normal fluctuation features, and accurately locates abnormal trend feature points in impedance time series data.

[0045] Based on the design standard impedance of the wafer test circuit board, and combined with historical normal impedance time series data and the fluctuation range of the entire process, a dynamic threshold model is constructed using the sliding window statistical method and adaptive learning algorithm. The threshold is dynamically updated according to the impedance data collected in real time. This adapts to the impedance fluctuation characteristics of different operating conditions and different batches of circuit boards, avoiding misjudgment and missed judgment caused by fixed thresholds. The actual impedance value and drift rate corresponding to the abnormal trend feature point are compared with the real-time threshold range output by the dynamic threshold model. If the actual impedance value exceeds the threshold range or the impedance drift rate reaches the preset abnormal warning threshold, it is determined that there is a risk of impedance abnormal evolution. When an impedance anomaly evolution risk is detected, an early warning signal is immediately triggered, and the specific characteristics of the abnormal trend are output. These characteristics include the anomaly initiation location, impedance drift rate, frequency adaptation range, and associated process parameters. This provides accurate data support for subsequent defect tracing and early intervention, enabling early real-time warning of impedance mismatch defects.

[0046] Adaptive Repair Module: Connected to the defect detection module, it is used to adaptively repair and re-inspect detected defects based on defect identification results and cause analysis results; The adaptive repair module includes a laser circuit trimming unit, a via repair unit, a probe precision calibration unit, a high-precision welding unit, a substrate dielectric compensation unit, and a re-inspection unit. Laser Line Trimming Unit: Targeting impedance mismatch defects caused by abnormal line structure, it is equipped with a high-precision pulsed laser with adaptively adjustable power (laser trimming accuracy ≤0.1μm). Based on the impedance deviation compensation, it performs laser trimming and polishing on transmission lines on wafer test circuit boards that have line width / spacing deviations or line burrs. It can also be combined with plasma cleaning process to remove the oxide layer of the line before completing the laser trimming. By adjusting the physical structure parameters of the line, the characteristic impedance of the line is corrected so that the line impedance returns to the design standard range. Via Repair Unit: Targeting impedance mismatch defects in vias, this unit integrates high-precision laser drilling and micro-electroplating technologies to clear blocked vias, repair rough or missing copper via walls, and restore via conductivity and impedance stability. Specifically, it uses laser drilling to clear blocked vias in the circuit board, laser polishing to reshape rough via walls, and then micro-electroplating to deposit a uniformly thick conductive copper layer on the via walls. This repairs via conductivity issues caused by missing copper or via misalignment, restoring the structural integrity and electrical continuity of the vias, eliminating the impact of abnormal via impedance on overall signal transmission, and ensuring stable via impedance with no significant signal reflection.

[0047] The probe precision calibration unit addresses abnormal impedance mismatch defects in probe assemblies by integrating a high-precision micro-robotic arm and thermal correction technology. It calibrates probe tilt and height, repairs probe tip wear, improves probe contact stability, and reduces contact impedance. Specifically, the micro-robotic arm precisely calibrates the spatial attitude and height of tilted or offset probes, restoring the coplanarity of the probe array to ≤0.5μm. Laser polishing repairs wear and chipping defects at probe tips, enabling automated replacement of severely worn probes. Simultaneously, it precisely calibrates the contact pressure between the probe and the wafer pad, reducing probe contact impedance and suppressing contact impedance fluctuations, thereby improving the stability and reliability of probe contact.

[0048] High-precision welding unit: Addressing impedance mismatch defects caused by welding and contamination, it features a temperature-adaptive hot air welding module equipped with an inert gas protection device. This module repairs cold / sting solder joints between the probe and pads, removes flux residue, and reduces contact impedance. Specifically, it uses hot air welding to re-weld and repair cold / sting solder joints between the probe and pads, utilizing inert gas protection to prevent oxidation during the welding process. Simultaneously, it integrates plasma cleaning to remove flux residue, surface oil, and metal particle contamination from the solder joints, reducing contact resistance in the welding area and eliminating impedance drift caused by poor welding and surface contamination, ensuring the stability of the solder joint contact impedance.

[0049] Substrate dielectric compensation unit: Addressing impedance mismatch defects caused by abnormal substrate materials, this unit employs high-precision dielectric material coating technology to coat dielectric materials, adjust the dielectric constant, and restore the characteristic impedance of the circuit. Specifically, it coats areas with uneven dielectric thickness on the circuit board substrate with a dielectric material having the same dielectric constant as the substrate base, precisely adjusting the substrate's dielectric layer thickness and dielectric properties. For areas with micro-bubbles inside the substrate, air is first removed by laser drilling, followed by filling with dielectric material to repair the substrate structure. By correcting the substrate's dielectric parameters, it eliminates the characteristic impedance drift caused by abnormal substrate dielectric properties, restoring the overall impedance stability of the circuit board.

[0050] Re-inspection unit: It has a bidirectional communication connection with the defect detection module and is used to perform multimodal testing on the circuit board again after the repair is completed. By comparing the defect data before and after the repair, it determines whether the repair is qualified and automatically records the re-inspection results and associates them with the repair record.

[0051] The acceptance criteria are set as follows: defects are completely eliminated, or the defect level is reduced to minor after repair (without affecting test performance), and electrical parameters meet the standards (contact resistance ≤10mΩ, impedance matching error ≤5%). If the defect remains moderate / severe after repair, it will be automatically repaired again (up to 2 times); if it still fails to meet the standards, it will be judged as a non-conforming product and included in the non-conforming product management system. The re-inspection results are automatically recorded and linked to the repair records to form a complete "test-repair-re-inspection" closed-loop data for easy traceability.

[0052] The re-inspection unit is also used to collect repair parameters in real time during the repair process and dynamically adjust the repair parameters based on the impedance deviation compensation algorithm, including the following steps: During the repair process, the core repair parameters of the laser line trimming unit, via repair unit, probe precision calibration unit, high-precision welding unit, and substrate dielectric compensation unit are collected in real time, as well as the dynamic impedance detection data of the repair area. The core repair parameters include laser power, repair rate, electroplated copper layer thickness, probe calibration angle and contact pressure, welding temperature and duration, dielectric material coating thickness and rate, etc.

[0053] The dynamic impedance detection data is compared with the impedance deviation compensation amount in real time to obtain the real-time impedance deviation value during the repair process. Based on the impedance deviation compensation algorithm, the real-time adjustment amount of each repair parameter is calculated according to the real-time impedance deviation value and the preset repair parameter-impedance deviation correlation model, and the repair parameters that deviate from the optimal value are adaptively and dynamically corrected.

[0054] If the real-time impedance deviation is too large, the adjustment range of the corresponding repair parameter is increased according to the algorithm result; if the real-time impedance deviation is close to the target value, the adjustment range is decreased and fine calibration is performed. The preset repair parameter-impedance deviation correlation model is a pre-constructed multivariate mapping relationship model. For five types of impedance mismatch defects—circuit structure anomalies, via defects, probe assembly anomalies, substrate material anomalies, and welding and contamination anomalies—a quantitative causal relationship is established between the core repair parameters of each repair unit and the impedance deviation of the corresponding area. This provides a calculation basis for the impedance deviation compensation algorithm, realizes the adaptive dynamic adjustment of the repair parameters, and ensures that the impedance value after repair stably returns to the design standard range.

[0055] It also includes a digital twin module, which is bidirectionally connected to the data acquisition module, data fusion module, defect detection module, and adaptive repair module. It is used to build an impedance defect evolution model based on digital twin technology, realize the visualization of system status through real-time synchronization of virtual and real data, and perform predictive maintenance of impedance anomalies, virtual simulation of repair process, and parameter pre-optimization based on the impedance defect evolution model.

[0056] Based on the design drawings, material parameters, structural dimensions, and impedance design standards of the wafer test circuit board, and by integrating multimodal data, process parameters, and historical defect data, a virtual twin containing the physical structure, electrical characteristics, material characteristics, and mechanical characteristics of the circuit board is constructed. Based on historical impedance defect data, an impedance defect evolution model is trained to reproduce the evolution of impedance mismatch defects of different causes and levels over time, temperature, and test pressure.

[0057] By interacting with the system's various detection and repair modules in real time, the entire process data, including dynamic impedance time-series data, defect identification results, repair parameters, environmental temperature and humidity, and vibration data collected from the physical terminal, is synchronized to the virtual twin in real time. This dynamically updates the virtual model's state parameters, creating a visualized mirror of the wafer test circuit board's impedance status, defect location, repair progress, and system operating status. Based on the impedance defect evolution model, the system simulates and extrapolates the real-time dynamic impedance time-series data, predicting impedance change trends over a future period. This allows for early warnings of potential impedance drift and structural degradation risks, enabling predictive maintenance of impedance anomalies.

[0058] Before performing physical repair, the defect identification results and impedance deviation compensation amount are input into the virtual twin. Virtual simulation is performed on each repair process to simulate the impedance correction effect under different repair parameters. The optimal repair parameter combination is selected and parameter pre-optimization is completed. The optimized parameters are then sent to each repair execution unit to ensure repair accuracy and efficiency and achieve intelligent control of virtual-physical closed loop.

[0059] It also includes an interaction and storage module, which has bidirectional communication connections with the data acquisition module, data fusion module, defect detection module, adaptive repair module, and digital twin module. It has functions such as visual interactive display, full-process data storage, data traceability and analysis, remote control and early warning information linkage. Through industrial touch terminals, it can display the system operation status such as impedance detection, defect identification, and repair progress in real time, realize the structured storage and multi-dimensional traceability of data in the entire process of detection, repair, and re-inspection, and can automatically generate production management statistical reports. At the same time, it supports remote monitoring, parameter configuration and early warning information push, providing data support and interaction guarantee for system human-machine collaboration, production line management and process optimization.

[0060] The overall workflow is described below based on the technical solution of this embodiment: Material loading and pretreatment: The test circuit board of the wafer to be tested is precisely positioned by the automated loading mechanism and transported to the testing station. The system automatically collects ambient temperature and humidity parameters and performs temperature compensation calibration to ensure impedance detection accuracy.

[0061] Multimodal impedance sensing: Static impedance testing: The high-precision impedance testing unit collects static impedance parameters of the circuit, vias, and probe contact areas, compares them with the design standards, and makes a preliminary judgment on whether there are impedance mismatch defects. Dynamic impedance testing: Simulates actual high-frequency operating conditions, collects impedance drift and transient change characteristics in ATE timing data, and captures dynamic impedance mismatch defects; Structural feature detection: The optical detection submodule and the X-ray detection submodule simultaneously acquire structural data of circuits, vias, probes, and substrates to capture structural anomalies that cause impedance mismatch; The data is synchronously transmitted to the data fusion module for preprocessing and fusion.

[0062] Defect Identification and Root Cause Location: Impedance mismatch defects are identified and their severity is determined using a lightweight multimodal model. Dynamic impedance time-series data, internal structure data, and process parameters are correlated, and the causes of defects are analyzed based on the defect identification results, generating a root cause analysis report. Impedance time-series data is monitored in real time based on a dynamic time-series analysis algorithm. If early drift anomalies are detected, a warning signal is issued based on a dynamic threshold. The system automatically determines the repairability of defects; minor / moderate defects are sent to the repair station, while severe defects are sent to the non-conforming product area.

[0063] Adaptive Repair and Re-inspection: The adaptive repair module calls the corresponding repair unit to perform repair based on the cause and level of the defect, and collects repair parameters in real time during the repair process. It dynamically adjusts the repair parameters based on the impedance deviation compensation algorithm. After the repair is completed, the circuit board is subjected to multi-modal testing again. The system automatically compares the re-inspection data with the pass standard to determine whether the repair is qualified. Qualified products are sent to the unloading station, and unqualified products are repaired again (up to 2 times). If they are still unqualified, they are included in the unqualified product management. At the same time, the re-inspection results are automatically recorded and linked to the repair record.

[0064] Data archiving and report generation: The system automatically archives data from the entire process of detection, cause, repair, and re-inspection, and generates impedance defect statistical reports for operators to query and export, providing support for production process optimization.

[0065] The above embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. An automated testing and repair system for wafer test circuit boards, characterized in that, Including communication connections: Data acquisition module: used to acquire multimodal data of wafer test circuit boards, including optical data, electrical data, internal structure data and auxiliary data; Data fusion module: used to preprocess the multimodal data, align the multimodal data by establishing a global three-dimensional coordinate system of the wafer test circuit board, extract multimodal feature vectors from the aligned data, and generate fused feature data after weighting; Defect detection module: Based on the built-in lightweight multimodal model, it identifies defects in the fused feature data, analyzes the causes based on the defect identification results, calculates the impedance deviation compensation amount by combining dynamic impedance time series data with the cause analysis results, and provides early warning based on dynamic thresholds. Adaptive Repair Module: Used to adaptively repair and re-inspect detected defects based on defect identification results and cause analysis results.

2. The automated testing and repair system for wafer test circuit boards according to claim 1, characterized in that, The optical data includes 2D images and 3D contour data of the circuit board; the electrical data includes static impedance parameters and dynamic impedance timing data; and the auxiliary data includes temperature, humidity, vibration, and position data.

3. The automated testing and repair system for wafer test circuit boards according to claim 1, characterized in that, A multimodal feature weight allocation model is established. Based on the common causes of impedance mismatch defects in wafer test circuit boards, dynamic weights are assigned to different modal feature vectors. The modal feature vectors are normalized and weighted and summed according to the dynamic weights to generate fused high-dimensional global feature data. The global feature data is then dimensionality-reduced and optimized to remove redundant features, retain core feature parameters, and output standardized, high-quality fused feature data.

4. The automated testing and repair system for wafer test circuit boards according to claim 1, characterized in that, The defect detection module includes a defect identification unit, a defect cause tracing unit, and an impedance deviation calculation unit; Defect identification unit: Built-in lightweight multimodal model, used to identify, locate, classify and grade defects based on fused feature data, and obtain defect identification results; Cause tracing unit: used to correlate dynamic impedance timing data, internal structure data and process parameters, and analyze the cause of defects by combining defect identification results to obtain cause analysis results; Impedance deviation calculation unit: used to calculate the impedance deviation compensation amount based on dynamic impedance time series data and cause analysis results.

5. The automated inspection and repair system for wafer test circuit boards according to claim 4, characterized in that, By correlating dynamic impedance timing data, internal structure data, and process parameters, and combining this with defect identification results, the causes of defects are analyzed to obtain the cause analysis results, including the following steps: Construct a database linking dynamic impedance timing data, internal structure data, and process parameters; Based on the defect identification results, the dynamic impedance time series data, internal structure data and process parameters corresponding to the defect location in the associated database are matched, and dynamic features and structural features are extracted. Based on the dynamic and structural characteristics, the abnormal process parameters that exceed the standard threshold range are identified by comparing them with the standard threshold range of the process parameters. Based on the abnormal process parameters, and combined with a preset defect feature-process parameter correlation analysis model, the causal relationship between abnormal process parameters and defect features is analyzed. Based on the aforementioned causal relationship, and combined with the typical cause library of impedance mismatch defects, a comprehensive analysis is conducted on abnormal process parameters, defect dynamic characteristics, and defect structural characteristics to determine the core cause of impedance mismatch defects, while clarifying the evolution law and influencing factors of the defects. Integrate all analytical information to form and output causal analysis results that include core causes, abnormal process parameters, and defect evolution characteristics.

6. The automated inspection and repair system for wafer test circuit boards according to claim 4, characterized in that, Based on the dynamic impedance time series data and the cause analysis results, the impedance deviation compensation is calculated, including the following steps: Based on dynamic impedance time series data, the actual impedance value, impedance drift peak, drift rate, and real-time deviation between the actual impedance value and the design standard impedance are extracted from the defect location across the entire operating frequency range. Simultaneously, the structural anomaly characteristics and associated abnormal process parameters corresponding to the defect location are extracted from the cause analysis results. Based on the extracted data, and combined with the preset impedance deviation-cause compensation mapping model, the corresponding compensation method and compensation coefficient are matched. Based on the compensation method and compensation coefficient, combined with the difference between the actual impedance value at the defect location and the design standard impedance, the peak impedance drift, and structural anomaly characteristic parameters, the compensation amount is calculated and corrected according to the abnormal process parameters. Based on the impedance deviation characteristics within the operating frequency range of the wafer test circuit board, the impedance deviation compensation amount adapted to the defect location across the entire frequency range is calculated and output.

7. The automated testing and repair system for wafer test circuit boards according to claim 4, characterized in that, The defect detection module also includes a trend prediction unit, used to analyze dynamic impedance time-series data based on LSTM and attention mechanisms, capture abnormal impedance change trends, and provide early warnings in conjunction with dynamic thresholds, including the following steps: The dynamic impedance timing data of the wafer test circuit board across the entire operating frequency range is preprocessed and the timing dimension of the data is regularized to obtain a standardized dynamic impedance timing dataset. An impedance trend analysis network based on LSTM and attention mechanism is constructed to analyze a standardized dynamic impedance time series dataset and locate abnormal trend feature points in the impedance time series data. Based on the design standard impedance of the wafer test circuit board, combined with historical normal impedance timing data and the fluctuation range of the entire process, a dynamic threshold model is constructed using the sliding window statistical method and adaptive learning algorithm, and the threshold is dynamically updated according to the impedance data collected in real time. The actual impedance value and drift rate corresponding to the abnormal trend feature point are compared with the real-time threshold range output by the dynamic threshold model. If the actual impedance value exceeds the threshold range or the impedance drift rate reaches the preset abnormal warning threshold, it is determined that there is a risk of impedance abnormal evolution. When an impedance anomaly evolution risk is detected, an early warning signal is immediately triggered, and the specific characteristics of the abnormal trend are output. These characteristics include the anomaly start location, impedance drift rate, frequency adaptation range, and associated process parameters.

8. The automated testing and repair system for wafer test circuit boards according to claim 1, characterized in that, The adaptive repair module includes a laser circuit trimming unit, a via repair unit, a probe precision calibration unit, a high-precision welding unit, a substrate dielectric compensation unit, and a re-inspection unit. Laser line trimming unit: Equipped with a high-precision pulsed laser with adaptive power adjustment, it performs laser trimming and polishing on the transmission line based on the impedance deviation compensation amount to correct the characteristic impedance of the line, targeting impedance mismatch defects such as abnormal line structure. Via Repair Unit: Targeting impedance mismatch defects such as via defects, it integrates high-precision laser drilling and micro-electroplating technology to open blocked vias, repair rough or copper-free via walls, and restore via conductivity and impedance stability. Precision probe calibration unit: In response to abnormal impedance mismatch defects in probe assemblies, it integrates a high-precision micro-robotic arm and thermal correction technology to calibrate probe tilt and height, and repair probe tip wear. High-precision welding unit: For welding and contamination-related impedance mismatch defects, it is equipped with a temperature-adaptive hot air welding module and an inert gas protection device to repair probe and pad cold solder joints, remove flux residues, and reduce contact resistance. Substrate dielectric compensation unit: To address abnormal impedance mismatch defects in substrate materials, a high-precision dielectric material coating technology is used to coat dielectric materials, adjust the dielectric constant, and restore the characteristic impedance of the circuit. Re-inspection unit: Used to perform multi-modal testing on the circuit board again after repair. By comparing the defect data before and after repair, it determines whether the repair is qualified and automatically records the re-inspection results and links them to the repair record.

9. The automated testing and repair system for wafer test circuit boards according to claim 8, characterized in that, The re-inspection unit is also used to collect repair parameters in real time during the repair process and dynamically adjust the repair parameters based on the impedance deviation compensation algorithm, including the following steps: During the repair process, the core repair parameters of the laser line trimming unit, via repair unit, probe precision calibration unit, high-precision welding unit, and substrate dielectric compensation unit, as well as the dynamic impedance detection data of the repair area, are collected in real time. The dynamic impedance detection data is compared with the impedance deviation compensation amount in real time to obtain the real-time impedance deviation value during the repair process. Based on the impedance deviation compensation algorithm, the real-time adjustment amount of each repair parameter is calculated according to the real-time impedance deviation value and the preset repair parameter-impedance deviation correlation model, and the repair parameters that deviate from the optimal value are adaptively and dynamically corrected.

10. The automated inspection and repair system for wafer test circuit boards according to claim 1, characterized in that, It also includes a digital twin module, which is used to build an impedance defect evolution model based on digital twin technology, realize the visualization of system status through real-time synchronization of virtual and real data, and perform predictive maintenance of impedance anomalies, virtual simulation of repair processes and parameter pre-optimization based on the impedance defect evolution model.

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