Bitcell, in-memory computing circuit for majority function, and in-memory computing method

Abstract

This disclosure relates to a bit base, in-memory calculation circuitry for a majority function, and an in-memory calculation method. A bit base (BC) includes: a variable resistor and a first transistor connected in series between two terminal nodes; and a second transistor also connected between the two terminal nodes. The gates of the first and second transistors are respectively connected to first and second word lines (WL) for a row. The circuitry includes an array of BCs. In each column, the BC is connected in a stack between a sense amplifier (SA) and a bottom device (FD). During a read operation, the FD connects the stack to ground. Additionally, first and second WL voltages on the first and second WLs for each row cause the first transistor of the BC to be on and the second transistor off for any selected row, and the first transistor off and the second transistor on for any unselected row. The SA compares a sense current from the stack with a medium reference current to simultaneously calculate the majority function.

Description

Technical Field

[0001] This disclosure relates to in-memory computing, and more specifically to embodiments of bit cells, embodiments of in-memory computing circuitry (including arrays of these bit cells) for computing majority functions, and embodiments of associated in-memory computing methods. Background Technology

[0002] Historically, software solutions have been used to compute complex functions (e.g., for artificial intelligence (AI) applications). Recently, dedicated analog in-memory computation (AiMC) circuits have been developed for some of these complex functions (e.g., the multiply-accumulate (MAC) function). However, having such dedicated AiMC circuits for other complex functions may be advantageous.

[0003] For example, hyperdimensional computation (HDC) has become an alternative to neural networks in AI applications. In HDC, vectors represent features (referred to as feature vectors in this paper) and are encoded together using, for example, a series of XOR operations and a majority function to create hypervectors. Typically, the XOR function compares two inputs and outputs a single output. If the inputs are different, the output is a logical value 1, and if the inputs are the same, the output is a logical value 0. The majority function is a function that outputs a logical value 1 when more than half of the inputs have a logical value 1 and a logical value 0 when more than half of the inputs have a logical value 0. Hypervectors can be used for classification lookups. Classification lookups are a type of machine learning (ML) method where a model is used to predict the correct label for input data. Currently, software solutions are used to solve for these XOR and majority functions in HDC. Unfortunately, because each feature vector can be very long (e.g., more than 10,000 bits or more), executing the software (including vector retrieval, vector processing, and hypervector creation) can be program-intensive and can consume a significant amount of power. Summary of the Invention

[0004] This article discloses embodiments of bit primitives, in-memory computation circuitry for majority functions, and in-memory computation methods for majority functions.

[0005] An embodiment of the bit base may include a variable resistor and a first transistor connected in series between a first terminal node and a second terminal node. The first gate of the first transistor may be connected to a first word line. The bit base may also include a second transistor connected between the first terminal node and the second terminal node. The second gate of the second transistor may be connected to a second word line.

[0006] Embodiments of the in-memory computing circuit may include an array of bit bases arranged in columns and rows. The in-memory computing circuit may further include: first word lines for each row; and second word lines for each row. Each bit base may include a variable resistor and a first transistor connected in series between a first terminal node and a second terminal node. The first gate of the first transistor may be connected to the first word line for the row. Each bit base may further include a second transistor connected between the first terminal node and the second terminal node. The second gate of the second transistor may be connected to the second word line for that row.

[0007] Embodiments of the in-memory computation method may include storing bit values ​​in bit bases of an array of bit bases arranged in columns and rows. Each bit base may include a variable resistor and a first transistor connected in series between a first end node and a second end node. A first gate of the first transistor may be connected to a first word line for the row. Each bit base may also include a second transistor connected between the first end node and the second end node. A second gate of the second transistor may be connected to a second word line for the row. The bit bases in the columns may be connected in series to form a bit base stack, and the method may further include performing a read operation to simultaneously compute a majority function pointing to a bit value stored in a selected row of the bit base stack.

[0008] It should be noted that all aspects, examples, and features of the disclosed embodiments mentioned in the foregoing summary can be combined in any technically possible manner. That is, two or more aspects of any disclosed embodiment, including those described in the summary section, can be combined to form embodiments not specifically described herein. Details of one or more embodiments are set forth in the drawings and the following description. Other features, objects, and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0009] This disclosure will be better understood through the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0010] Figure 1 This is a schematic diagram showing a disclosed embodiment of the bit-based primitive;

[0011] Figure 2A-2C These are cross-sectional views showing example resistive random access memory type variable resistors under different resistance states;

[0012] Figure 3A and 3B These are cross-sectional views of example magnetic tunnel junction variable resistors under different resistance conditions;

[0013] Figure 4A and 4B These are cross-sectional views showing example phase-change memory type variable resistors under different resistance conditions;

[0014] Figure 5 This is a schematic diagram illustrating a general disclosed embodiment of an in-memory computing circuit;

[0015] Figure 6-8 They are shown separately. Figure 5 A schematic diagram of the various configurations of some components in the circuit;

[0016] Figure 9 It shows that it can be incorporated into Figure 5 A schematic diagram of an alternative example of a reference signal generator in a circuit; and

[0017] Figure 10 This is a flowchart illustrating a disclosed embodiment of the in-memory computation method. Detailed Implementation

[0018] As mentioned above, recently, dedicated analog in-memory computation (AiMC) circuits have been developed for some of these complex functions, such as the multiply-accumulate (MAC) function. However, it may be advantageous to have such dedicated AiMC circuits for other complex functions, such as the majority function.

[0019] In view of the above, this document discloses an embodiment of a uniquely configured bit base. The bit base may include: a variable resistor (which can be programmed or erased to have a low resistance state (LRS) or a high resistance state (HRS) respectively) connected in series between two end nodes, and a first transistor (also referred to herein as a read / write access transistor). The bit base may also include a second transistor (also referred herein as a read bypass transistor) also connected between the two end nodes. Within the bit base, a first gate of the first transistor may be connected to a first word line for a row, and a second gate of the second transistor may be connected to a second word line for the same row. As discussed in more detail below, the bit base may also include additional transistors respectively connected to additional word lines to enable write operations to point to the variable resistor therein (e.g., to switch the variable resistor between a low resistance state (LRS) (e.g., for storing a "1" bit value) and a high resistance state (HRS) (e.g., for storing a "0" bit value).

[0020] This document also discloses embodiments of, for example, in-memory computing circuitry suitable for computing majority functions, and associated in-memory computing methods. The in-memory computing circuitry may include an array of such bit bases arranged in columns and rows. In each column, the bit bases may be end-to-end nodes connected in series between a sense amplifier for that column and a footer device (forming a bit base stack). In this in-memory computing circuitry, read operations can be performed to simultaneously compute multiple majority functions. The majority functions are associated with corresponding columns and are based on bit values ​​stored in bit bases in the same selected row of the bit base stack located in these columns. To perform the read operation, the footer devices may all be switched on to simultaneously connect the bit base stack to ground and initiate current flow through the bit base stack. First and second word line voltages applied to the first and second word lines of the selected row cause the first transistor of the bit base in the selected row to turn on and the second transistor to turn off. Applying opposing first and second word line voltages to the first and second word lines of any unselected row causes the first transistor in the bit base of the unselected row to turn off and the second transistor to turn on (in order to bypass the variable resistors in those bit bases). The resistance of each bit base stack is sensed by a sense amplifier connected thereto. The sensed resistance of each bit base stack will depend on the different resistance states (LRS or HRS) of the variable resistors in the bit bases of the selected row, but not on the resistance states of the variable resistors in the bit bases of the unselected row. Each sense amplifier compares the sensed resistance (e.g., as indicated by the sensed current (Isen)) with a reference resistance (e.g., as indicated by the reference current (Iref), which is equal to the sensed resistance expected when half of the variable resistors in the bit bases of the selected row are in LRS and half are in HRS. Thus, the data output signal (Dout) from each sense amplifier will indicate whether the majority of the variable resistors in the bit bases of the selected row in the bit base stack stores a "1" bit value or a "0" bit value.

[0021] More specifically, Figure 1 This is a schematic diagram illustrating a disclosed embodiment of a bit base (hereinafter referred to as bit base 100). As discussed in more detail below, bit base 100 may be included in an array of bit bases in an in-memory computing circuit.

[0022] Bit base 100 may include a variable resistor 105. The variable resistor 105 may be any type of resistor now known or later developed with selectively variable resistance, specifically, it may switch between at least two different resistance states, including a high resistance state (HRS) and a low resistance state (LRS). HRS may indicate a storage bit with a first bit value (e.g., a "0" bit value), and LRS may indicate a storage bit with a second bit value (e.g., a "1" bit value). Such variable resistors include, but are not limited to, resistive random access memory (RRAM) type variable resistors (e.g., also known as memristors), magnetic tunnel junction (MTJ) type variable resistors, and phase change memory (PCM) type variable resistors.

[0023] Figure 2A-2C These are cross-sectional views showing an example RRAM-type variable resistor 105A under different resistance states. This type of RRAM-type variable resistor 105A is typically also a back-to-office (BEOL) multilayer structure, comprising a dielectric layer 213 (e.g., hafnium oxide (HfO)). x Two metal layers 212 and 214 are separated by a (or some other suitable oxide layer, also referred to as a switching layer). Depending on the bias conditions on metal layers 212 and 214 during a write operation, ions in dielectric layer 213 can migrate to: (a) break up the conductive filament 215 between metal layers 212 and 214, causing the RRAM-type variable resistor 105A to be in HRS, thereby storing a bit value (e.g., logic value "0") (e.g., see [reference]). Figure 2A (a) or (b) growing a conductive filament 215 extending between metal layers 212 and 214 in dielectric layer 213, such that the RRAM-type variable resistor 105A is in LRS, thereby storing different bit values ​​(e.g., logic value "1") (see, for example, see...). Figure 2B Optionally, different bias conditions can be used to achieve one or more different resistance states between HRS and LRS. For example, as Figure 2C As shown, optional specific bias conditions on metal layers 212 and 214 can be used to achieve a medium resistance state (MRS) located in the halfway between LRS and HRS.

[0024] Figure 3A and Figure 3BThese are cross-sectional views showing an example MTJ-type variable resistor 105B in different resistance states. Such MTJ-type variable resistors 105B are typically BEOL multilayer structures, comprising a free ferromagnetic layer 314 (also called a switchable layer) and a fixed ferromagnetic layer 312 (also called a pinned layer) separated by a thin dielectric layer 313 (e.g., a thin oxide layer or some other suitable type of dielectric layer). Depending on the bias conditions on the ferromagnetic layers 312 and 314 during write operations, the MTJ-type variable resistor 105B can operate in an antiparallel resistance (RAP) state (i.e., HRS, as shown in the image). Figure 3A As shown) and the parallel resistance (RP) state (i.e., LRS, as shown) Figure 3B Switch between (as shown).

[0025] Figure 4A and 4B These are cross-sectional views showing an example PCM-type variable resistor 105C under different resistance states. This type of PCM-type variable resistor utilizes a phase change material 411 (e.g., a chalcogenide) having a programmable structural phase exhibiting different resistances. Depending on the bias conditions at the opposite terminals of the resistor and the resulting local temperature, the PCM can operate in an amorphous phase (i.e., HRS, as shown in the diagram). Figure 4A (as shown) and crystalline phase (i.e., LRS, as shown) Figure 4B Switch between (as shown).

[0026] Such variable resistors and the bias conditions required to switch their resistance states during write operations are known in the art. Therefore, more specific details are omitted in this specification to allow the reader to focus on the prominent aspects of the disclosed embodiments relating to, for example, the structure of bit base 100 itself and its incorporation in in-memory computing circuitry.

[0027] Refer again Figure 1Bit base 100 may further include a first transistor 110 (also referred to herein as a read / write access transistor). A variable resistor 105 and the first transistor 110 may be electrically connected in series between a pair of end nodes (i.e., first end node 102.1 and second end node 102.2). Bit base 100 may further include a second transistor 120 (also referred herein as a bypass transistor), which is electrically connected in parallel with the variable resistor 105 and the first transistor 110 between end nodes 102.1-102.2. The first transistor 110 and the second transistor 120 may be field-effect transistors (FETs). The first transistor 110 may include at least a first channel region 113 laterally located between first source / drain regions 112 and a first gate 115 adjacent to the first channel region 113. The first gate 115 may be electrically connected to a first word line (WL1) such that the on / off state of the first transistor 110 depends on the first word line voltage (VWL1) on WL1. Similarly, the second transistor 120 may include at least a second channel region 123 laterally located between the second source / drain regions 122 and a second gate 125 adjacent to the second channel region 123. The second gate 125 may be electrically connected to a second word line (WL2) such that the on / off state of the second transistor 120 depends on the second word line voltage (VWL2) on WL2.

[0028] Bit base 100 may also include a third transistor 130 and a fourth transistor 140 (also referred to as an additional access transistor) which can be used to facilitate write operations to the variable resistor 105 (e.g., to switch the resistance state of the variable resistor 105). The third transistor 130 and the fourth transistor 140 may also be FETs. The third transistor 130 may include at least a third channel region 133 laterally located between a third source / drain region 132 (which is connected to the source line (SL) and the first terminal node 102.1) and a third gate 135 adjacent to the third channel region 133. The third gate 135 may be electrically connected to a third word line (WL3) such that the on / off state of the third transistor 130 depends on the third word line voltage (VWL3) on WL3. The fourth transistor 140 may include at least a fourth channel region 143 laterally located between a fourth source / drain region 142 (which is connected to the bit line (BL) and the second terminal node 102.2) and a fourth gate 145 adjacent to the third channel region 133. The fourth gate 145 may be electrically connected to the fourth word line (WL4) such that the on / off state of the fourth transistor 140 depends on the fourth word line voltage (VWL4) on WL4.

[0029] In some embodiments, as shown in the figures, the four transistors 110, 120, 130, and 140 can all be N-type field-effect transistors (NFETs) (as shown). That is, in each of the four transistors 110, 120, 130, and 140, the source / drain regions can have N-type conductivity at a relatively high level of conductivity, and the channel region can have P-type conductivity at a relatively low level of conductivity (or alternatively, an intrinsic channel region). In this embodiment, WL1 and WL2 can be connected to receive a read / write select signal (Sel) for setting VWL1 and an inverted read / write select signal (Selb) for setting VWL2, respectively. WL3 and WL4 can both receive the same read select signal (WSel). Thus, in memory operation, if the first transistor 110 is on, the second transistor 120 will be off, or vice versa, and the third and fourth transistors 130 and 140 will both be on or both off.

[0030] For example, during a read operation, end nodes 102.1 and 102.2 can be connected to the positive power supply voltage rail and the ground rail, respectively. If bit base 100 is in the selected row during the read operation, Sel can be high, Selb can be low, and WSel can be low. Consequently, the first transistor 110 is turned on, and the second transistor 120, the third transistor 130, and the fourth transistor 140 are turned off. As a result, current can flow between end nodes 102.1 and 102.2 through the variable resistor 105 and the first transistor 110. If bit base 100 is in an unselected row during the read operation, Sel can be low, Selb can be high, and WSel can be low. Consequently, the second transistor 120 is turned on, and the first transistor 110, the third transistor 130, and the fourth transistor 140 are turned off. As a result, current can flow around the variable resistor 105 between end nodes 102.1 and 102.2 through the second transistor 120.

[0031] If bit base 100 is located in a selected row and column for a write operation (e.g., for writing LRS or HRS into the variable resistor 105), then SL and BL can be biased (depending on the desired resistance state being written into the programmable resistor, if necessary). Sel and WSel can be high, and Selb can be low. This turns on the first transistor 110, the third transistor 130, and the fourth transistor 140, and turns off the second transistor 120. As a result, the source line voltage (VSL) on SL is applied to one terminal of the variable resistor 105 through the third transistor 130 and the first terminal node 102.1, and the bit line voltage (VBL) on BL is applied to the opposite terminal of the variable resistor 105 through the fourth transistor 140, the second terminal node 102.2, and the first transistor 110 to achieve the desired resistance state.

[0032] In other embodiments (not shown), the conduction type of one or more of transistors 110, 120, 130, and 140 may be changed. For example, in one alternative embodiment, the first and second transistors 110 and 120 may be PFETs. In another alternative embodiment, the first transistor 110 may be an NFET, and the second transistor 120 may be a PFET (or vice versa). It should be understood that in any of these alternative embodiments, the voltage levels of VWL1 and VWL2 will differ from the voltage levels of VWL1 and VWL2 discussed above regarding the embodiment where all transistors are NFETs. For example, in the embodiment where both the first transistor 110 and the second transistor 120 are PFETs, a low Sel and a high Selb would be required to simultaneously turn on the first transistor 110 and turn off the second transistor 120 (or vice versa). In embodiments where the first transistor 110 is an NFET and the second transistor 120 is a PFET (or vice versa), the same Sel can be used to control the on / off state of the two transistors, and in this case, the first gate 115 of the first transistor 110 and the second gate 125 of the second transistor 120 can be electrically connected to the same word line.

[0033] Figure 5 This is a schematic diagram illustrating a general disclosed embodiment of an in-memory computing circuit (hereinafter referred to as structure 500). Structure 500 may include bit primitives 100 (e.g., as described in detail above and...). Figure 1 (As shown) array. Bit base 101 can be arranged by columns (e.g., see columns C0-Cy) and rows (e.g., see rows R0-Rx). Figure 6-8 It shows them in more specific and detailed terms. Figure 5 A schematic diagram showing the various configurations of some components of the structure 500. For example... Figure 5-8As shown, within each column, all bit bases 100 can be electrically connected in series (e.g., end-to-end) so that each column includes a stack of bit bases (i.e., a stack of bit bases connected in series).

[0034] As described in more detail below, structure 500 can also be configured to improve the performance of a majority of functions associated with data stored in bit primitives (more specifically, in the same selected rows therein) in a stack of bit primitives.

[0035] For example, structure 500 may include multiple word lines, each for a line. These word lines may include a first word line (WL1), a second word line (WL2), a third word line (WL3), and a fourth word line (WL4). This is consistent with the above description regarding each individual bit base 100 (e.g., Figure 1 As shown) and still discussed Figure 6-8 In the same manner, as shown in more detail in the schematic diagram, in a given row: WL1 for that row can be electrically connected to the first gate 115 of all first crystals 110 in all bit bases 100 in that row; WL2 for that row can be electrically connected to the second gate 125 of all second crystals 120 in all bit bases 100 in that row; WL3 for that row can be electrically connected to the third gate 135 of all third crystals 130 in all bit bases 100 in that row; and WL4 for that row can be electrically connected to the fourth gate 145 of all fourth crystals 140 in all bit bases 100 in that row.

[0036] WL1 for each row can be connected to receive a row-specific first word line voltage (VWL1), specifically a row-specific read / write select signal (Sel), and WL2 for each row can be connected to receive a row-specific second word line voltage (VWL2), specifically a row-specific inverted read / write select signal (Selb). In some embodiments (e.g., see...), Figure 6-8 In this configuration, structure 500 may include: a selection signal input node 501 for each WL1 of each row, which is used to receive a row-specific Selb; and an inverter 502 for each row. Each inverter 502 for a row may be electrically connected between the selection signal input node 501 for that row on the WL1 and the WL2 for the same row (i.e., for outputting to the WL2 and applying Selb).

[0037] Structure 500 may also include source lines (SL) and bit lines (BL) for each column. This is consistent with the above description regarding each individual bit base 100 (e.g., Figure 1In the same manner discussed (as shown), the third transistor 130 of all bit bases 100 in the same column can be electrically connected to SL for that column, and the fourth transistor 140 of all bit bases 100 in the same column can be electrically connected to BL for that column. To avoid clutter in the figures and to allow the reader to focus on the prominent aspects of the disclosed embodiments (e.g., aspects relating to in-memory computation, specifically, the performance of read operations for simultaneously solving multiple functions), from... Figure 6-8 The SL and BL used for columns, as well as the third and fourth transistors 130-140 of the bit base 101 connected thereto, are omitted.

[0038] Structure 500 may also include additional components (e.g., controllers and peripheral circuitry) connected to the array to facilitate the performance of memory operations therein (e.g., by establishing specific read-dependent or write-dependent bias conditions on the WL, SL, and BL of the bit primitives connected to the array). Controllers and peripheral circuitry configured to facilitate the performance of memory operations are known in the art. Therefore, their details have been omitted from this specification and drawings to allow the reader to focus on the prominent aspects of the disclosed embodiments (e.g., aspects relating to in-memory computation, specifically, the performance of read operations for simultaneously solving multiple functions).

[0039] Structure 500 may include sensing circuitry 550. Sensing circuitry 550 may include a reference signal generator 560 configured (as discussed in more detail below) to generate and output a reference signal (Ref). Ref may, for example, include a reference voltage (Vref) and a reference current generated from Vref. Sensing circuitry 550 may also include a plurality of sensing amplifiers 551 electrically connected to one end of each bit stack of the column and electrically connected to the reference signal generator 560 to receive Ref.

[0040] Specifically, each sense amplifier 551 may be connected between the bit primitive stack and the positive power supply voltage rail (e.g., at the positive power supply voltage level (VDD)), and may also be connected to a reference signal generator 560 to receive Ref. For example, each sense amplifier 551 may include: a first terminal 552 (also referred to herein as a sense signal node), which is connected to apply a sense voltage (Vsen) to one end of the bit primitive stack (e.g., from end node 102.1 of the first primitive 101 in R0) to generate a sense current (Isen); a second terminal 553 (also referred herein as a reference signal node), which is electrically connected to receive Ref (and thus receive Vref and Iref generated by Vref); and a data output signal node 554, which outputs a data output signal (Dout) based on the result of a comparison between Iref and Isen.

[0041] In some embodiments, each sense amplifier 551 for each column may include a P-type field-effect transistor (PFET) 572 and an N-type field-effect transistor (NFET) 571 connected in series between a positive supply voltage rail 599 at a positive supply voltage level (i.e., at VDD) and a first terminal 552, as described above, connected to the bit base stack for that column (e.g., at end node 102.1 of bit base 101 in row R0 of the bit base stack for that column). Each sense amplifier 551 may also include a comparator 576 (e.g., an operational amplifier). The comparator 576 may have a non-inverting input (+) and an inverting input (-), the non-inverting input (+) connected to a second terminal 553 to receive Ref (and thus Vref and Iref), and the inverting input (-) connected to an intermediate node 575 at the junction between the PFET 572 and the NFET 571. The gates of PFET 572 and NFET 571 can be connected to receive Ref (and thus Vref and Iref) and bias voltage (Vbias) (e.g., received from bias voltage generator 569), respectively, so that Isen is generated and a sense voltage (Vsen) is generated at intermediate node 575.

[0042] It should be noted that, in order to perform most functions, as discussed in more detail below, the voltage level of Vref can be a medium voltage. This medium voltage can be determined such that if half of the programmable resistors of the bit bases in a certain number of selected rows of a single bit base stack are in LRS and the other half are in HRS, then Iref (which is generated according to Vref) corresponds to the expected reference current from that bit base stack. Therefore, when Iref is compared with Isen by the sense amplifier 551, if Isen is less than Iref, Dout can be low, indicating that most of the variable resistors of the bit bases in the selected rows of the bit base stack have HRS. Furthermore, if Isen is greater than Iref, Dout can be high, indicating that most of the variable resistors of the bit bases in the selected rows of the bit base stack have LRS. Various different techniques can be used to generate Ref with such Vref (and thus such Iref).

[0043] For example, in some embodiments, such as Figure 6 and Figure 7 As shown, the array of bit bases may further include a reference column (Cref) of reference bit bases 100R. Each reference bit base 100R may include a reference resistor 105r having a medium resistance state (MRS). That is, the resistance of the reference resistor 105r may be between the resistance of the variable resistor 105 in the HRS state and the resistance of the variable resistor 105 in the LRS state. In some embodiments (such as...) Figure 7 In the example shown, the reference resistor 105r can be another variable resistor programmable to the MRS. In other embodiments (such as...) Figure 8 In the example shown, reference resistor 105r can be a fixed resistor with the MRS. In any case, reference bit base 100R can be configured to be substantially the same as bit base 100 (e.g., reference resistor 105r and first transistor 110 can be connected in series between end nodes, and second transistor 120 can also be connected in parallel between end nodes with reference resistor 105r and first transistor 110). However, it should be noted that in embodiments where reference resistor 105r is a fixed resistor, write operations are not required. Therefore, reference columns SL or BL are not required, and there will be no third and fourth transistors in reference bit base 100R. In any case, reference bit bases 100R can be electrically connected in series to form a reference bit base stack. The reference bit base stack can be connected between reference signal generator 560 (opposite to the sense amplifier) ​​and additional bottom device 580. In an embodiment with such a reference column, the reference signal generator 560 may include an additional PFET 562 and an additional NFET 561 connected in series between the positive supply voltage rail 599 and the reference bit base stack (e.g., at the end node of the reference bit base 100R in row R0). The gate of the additional PFET 562 may be connected to a reference signal output node 565 located at the junction between the additional PFET 562 and the additional NFET 561. The gate of the additional NFET 561 may be connected to receive Vbias (e.g., from the bias voltage generator 569). As a result, Ref (including Vref and Iref generated according to Vref) may be generated at the reference signal output node 565 and output to the second terminal 553 of each sense amplifier 551.

[0044] Alternatively, any other suitable technique can be used to generate Refs (including Vrefs and Irefs, as described in detail above). For example, in other embodiments, Ref generation, including Vref generation, can be based on a lookup table. Figure 9This is a schematic diagram illustrating another example of a reference signal generator 560 that can be incorporated into structure 500. The reference signal generator 560 may include a lookup table (LUT) 920. The LUT 920 may be filled with data indicating different numbers of selected rows and data indicating different Vref levels to be used depending on the number of selected rows. The reference signal generator 560 may also include a variable voltage source 940 and control logic 930 communicating with the LUT 920, the controller, and the variable voltage source 940. The control logic 930 may receive an input signal indicating the total number of selected rows to be used during a read operation, may identify a specific Vref level associated with that number of selected rows in the LUT 920, and may output a control signal 935 to the variable voltage source 940 indicating that specific Vref level, so that the variable voltage source 940 outputs a Ref with the correct Vref. Generally, circuit structures including an LUT, a variable voltage source, and control logic are known in the art, wherein the control logic controls the voltage output from the variable voltage source based on information obtained from the LUT. Therefore, details thereof have been omitted from this specification to allow the reader to focus on the prominent aspects of the disclosed embodiments.

[0045] In any case, structure 500 may also include bottom devices 580 for each column. For example... Figure 5-8 As shown, each bit stack for each column can be electrically connected between the sense amplifier 551 for that column and the bottom device 580 for that column. Therefore, each column includes a bit stack (i.e., a stack of bit stacks 101 connected in series) connected at one end to the sense amplifier 551 and at the opposite end to the bottom device 580. Specifically, within each column, the first bit stack at R0 can be electrically connected to the sense amplifier 551 for that column, and the last bit stack at Rx can be electrically connected to the bottom device 580 for that column.

[0046] Each bottom device 580 for each column can be controllable to connect the bit base stack to ground 598 or disconnect the bit base stack from ground 598, as discussed below. For example, each bottom device 580 may include an NFET. The NFET may include: source / drain regions connected to the last bit base in the column in question at Rx and ground 598, respectively; and a gate connected to receive a read enable signal (RDen). Alternatively, all bottom devices 580 may be connected to receive the same RDe, such that they simultaneously connect the bit base stack to ground or disconnect it from ground. Alternatively, the bottom devices 580 may have any other suitable bottom device configuration. For example, each bottom device 580 may include multiple stacks of NFETs located between the bit base stack and ground and controlled by the same RDe. Alternatively, each bottom device may include a transmission gate comprising an NFET and a PFET connected in parallel between the bit base stack and ground 598 and controlled by RDe and RDenb, respectively.

[0047] As described above, structure 500 can be configured such that read operations can be used to solve multiple majority functions simultaneously. The majority functions can be associated with corresponding columns and can be based on bit values ​​stored in bit bases within the same selected row of bit base stacks located in these columns. During such read operations, WL1 for all selected rows receives a row-specific Sel that turns on all first transistors of all bit bases in the selected row, and WL2 for these same selected rows receives a row-specific Selb that turns off all second transistors 120 of bit bases 101 in the selected row. Simultaneously, WL1 for all unselected rows receives a row-specific Sel that turns off all first transistors of all bit bases in the unselected rows, and WL2 for these same unselected rows receives a row-specific Selb that turns on all second transistors 120 of bit bases 101 in the unselected rows. For example, if the first transistor 110 and the second transistor 120 in each bit base 101 are NFETs, then WL1 and WL2 for each selected row can receive high Se1 and low Selb, respectively, while WL1 and WL2 for each unselected row can receive low Se1 and high Selb, respectively. Additionally, RDen can switch states (e.g., to high in the case of the bottom NFET device) to electrically connect the entire column of bit base stacks to ground. As a result, current begins to flow from the positive power supply voltage rail 599 through the bit base 101 in each bit base stack to ground 598. The current flow within each bit base stack flows through the variable resistor 105 in the bit base 101 of the selected row (where the first transistor 110 is on and the second transistor is off), but bypasses the variable resistor 105 in any bit base 101 of the unselected row (where the first transistor 110 is off and the second transistor 120 is off). Depending on the resistance state of the variable resistor 105 in the selected row of the bit base stack for each column, the sensed current (Isen) will change (e.g., if more variable resistors 105 are in HRS, then Isen will be lower, and if more variable resistors 105 are in LRS, then Isen will be higher).

[0048] During a read operation, each sense amplifier 551 for each column can receive Ref (e.g., from reference signal generator 560, as discussed in more detail above), can apply Vsen to the bit base stack of that column (e.g., from end node 102.1 of the first base 101 in R0), can compare Iref generated from Vref with Isen generated from Vsen, and can output Dout based on the result of the comparison, as discussed above. Therefore, Dout from each sense amplifier 551 for each column is a solution to a majority function of the stored bit values ​​of the bit bases in only selected rows of the bit base stack of that column.

[0049] It should be noted that during the above-described read operation, the Vbias of the sensing amplifier 551 (e.g., as...) Figure 7 and 8 The voltage at the top of each bit base stack (as shown) can be set to approximately Vtn, which is higher than the target voltage Vsen to be applied at the top of each bit base stack during sensing. When the first transistor 110 and the second transistor 120 in each bit base 101 are NFETs, this target voltage should not be too high, or the Vgs of the stacked NFETs closest to the sensing amplifier 551 will have a low Vgs and a higher resistance. Ideally, the target voltage at the top of the bit base stack should be <1 / 2 VDD. Furthermore, it should be noted that NFET 571 is used as a source voltage follower within the sensing amplifier 551 to regulate the voltage at the top of the bit base stack, and PFET 572 is used as a current mirror within the sensing amplifier 551 to pull up the reference current. An intermediate node 575, located between PFET 572 and NFET 571 and also connected to the inverting input of comparator 576, responds to the difference in current flowing through PFET 572 and NFET 571. Additionally, it should be noted that during the aforementioned read operation, the additional PFET 562 of the reference signal generator 560 (which is connected to the reference bit primitive stack in the reference column, such as...) Figure 7-8 (Shown) is used as a diode, which is connected to serve as the reference side of the current mirror. The Vgs of PFET 562 in reference signal generator 560 and PFET 572 in sense amplifier 551 should be stabilized to the position where each PFET is biased to drive the reference current.

[0050] Figure 10 This demonstrates the use of the detailed description above and through Figure 1-9The flowchart illustrates a disclosed embodiment of an in-memory computation method performed in any of the different embodiments of structure 500. Specifically, the method may include storing bit values ​​in bit primitives 100 within an array of bit primitives in structure 500 (see process 1002). The method may also include performing a read operation as described above to simultaneously compute a majority function pointing to the bit values ​​stored in the same selected row of the stack of bit primitives in the columns of the array (see process 1004). Optionally, this in-memory computation method can be used for hyperdimensional computation (HDC) in AI applications. In this case, at process 1002, the bit values ​​of feature vectors (e.g., bound feature vectors) may be stored sequentially in the bit primitives of rows in the array. Thus, the bit primitives in each row store different feature vectors. Then, in process 1004, a read operation is performed to simultaneously compute a majority function pointing to the bit values ​​stored in the same selected row of the stack of bit primitives in the columns of the array. Thus, each majority function points to the bit value stored at the same bit position within different feature vectors stored in different selected rows. For example, the majority function associated with C0 points to the bit value stored at the first position within different feature vectors in different selected rows; the majority function associated with C1 points to the bit value stored at the second position within different feature vectors in different selected rows; and so on. Therefore, the outputs of these majority functions can be compiled sequentially (e.g., Dout from C0, Dout from C1, etc.) to form a hypervector for subsequent classification lookup.

[0051] It should be understood that the terminology used herein is for describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Moreover, as used herein, when oriented and shown in figures, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “under,” “under,” “above,” “overlapping,” “parallel,” “vertical,” etc., are intended to describe relative positions (unless otherwise stated), and terms such as “touches,” “directly contacts,” “adjacent,” “directly adjacent,” “closely adjacent,” etc., are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, when elements are oriented and shown in a figure, to indicate that one element is located to the side of another element, rather than above or below it. For example, an element laterally adjacent to another element will be beside the other element, an element laterally directly adjacent to another element will be directly beside the other element, and an element laterally surrounding another element will be adjacent to and bound to the outer wall of the other element. All corresponding structures, materials, actions, and equivalents of the means or steps plus functional elements in the following claims are intended to include any structures, materials, or actions used to perform a function in combination with other elements of the specific claims.

[0052] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with either surface-mount or buried interconnects, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes the integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0053] The descriptions of various disclosed embodiments are given for illustrative purposes and are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications of techniques found in the market, or improvements to techniques, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A bit base, comprising: A variable resistor and a first transistor are connected in series between a first terminal node and a second terminal node, wherein the first gate of the first transistor is connected to a first word line; and A second transistor is connected between the first terminal node and the second terminal node, wherein the second gate of the second transistor is connected to the second word line.

2. The bitcell of claim 1, wherein, The variable resistor is any one of resistive random access memory type variable resistor, magnetic tunnel junction type variable resistor, and phase change memory type variable resistor.

3. The bit base according to claim 1, further comprising: A third transistor is connected between the first terminal node and the source line, wherein the third gate of the third transistor is connected to a third word line; and A fourth transistor is connected between the second terminal node and the bit line, wherein the fourth gate of the fourth transistor is connected to the fourth word line.

4. The bitcell of claim 3, wherein, The first transistor, the second transistor, the third transistor, and the fourth transistor are N-type field-effect transistors.

5. The bit base according to claim 1, wherein The resistance state of the variable resistor can switch between at least a high resistance state and a low resistance state (below the high resistance state) based on the word line voltage levels on the first word line, the second word line, the third word line, the fourth word line, the source line, and the bit line. The high resistance state indicates the first value stored in the variable resistor, and the second resistance state indicates the second value stored in the variable resistor.

6. The bitcell of claim 5, wherein, During memory operation, the first word line is connected to receive a first word line voltage, and the second word line is connected to receive a second word line voltage that is inversely related to the first word line voltage, such that one of the first transistor and the second transistor is turned on.

7. The bitcell of claim 5, wherein, The low resistance state indicates a "1" bit value stored in the variable resistor, and the high resistance state indicates a "0" bit value stored in the variable resistor.

8. The bit base according to claim 5, wherein The resistance state of the variable resistor can switch between a high resistance state, a low resistance state, and a medium resistance state, wherein the medium resistance state is between the high resistance state and the low resistance state. When the variable resistor has the medium resistance state, the bit base can be used as a reference bit base.

9. An in-memory computing circuit, comprising: An array of bit primitives arranged by columns and rows; The first word line of the row is used respectively; as well as The second word lines for the rows are respectively, wherein each bit base includes: A variable resistor and a first transistor are connected in series between a first end node and a second end node, wherein the first gate of the first transistor is connected to a first word line for a row; and A second transistor is connected between the first terminal node and the second terminal node, wherein the second gate of the second transistor is connected to a second word line for the row.

10. The in-memory computing circuit of claim 9, wherein, The variable resistor is any one of resistive random access memory type variable resistor, magnetic tunnel junction type variable resistor, and phase change memory type variable resistor.

11. The in-memory computing circuit according to claim 9, wherein, Each bit base also includes: A third transistor is connected between the first terminal node and the source line for the column, wherein the third gate of the third transistor is connected to the third word line for the row; and A fourth transistor, connected between the second terminal node and the bit line for the column, wherein the fourth gate of the fourth transistor is connected to the fourth word line for the row, and The in-memory computing circuit further includes: Sensing amplifiers for the columns respectively; and Each bit in the column is electrically connected in series between the sense amplifier for that column and the bottom device.

12. The bitcell of claim 10, wherein, The first transistor, the second transistor, the third transistor, and the fourth transistor are N-type field-effect transistors.

13. The in-memory computing circuit according to claim 9, in, The resistance state of the variable resistor can switch between at least a high resistance state and a low resistance state below the high resistance state, and The high resistance state indicates the first value stored in the variable resistor, and the second resistance state indicates the second value stored in the variable resistor.

14. The in-memory computing circuit according to claim 13, wherein, The low resistance state indicates a "1" bit value stored in the variable resistor, and the high resistance state indicates a "0" bit value stored in the variable resistor.

15. The in-memory computing circuit according to claim 14, in, During read operations of a majority of functions used to simultaneously compute bit values ​​stored in selected rows of a stack of bit bases pointing to the column: The first word line and the second word line of the selected row receive a first word line voltage and a second word line voltage, so that all first transistors of all bit bases in the selected row are turned on and all second transistors of the bit bases in the selected row are turned off. The first and second word lines for any unselected row receive opposite first and second word line voltages, such that all first transistors of all bit bases in the unselected row are turned off and all second transistors of the bit bases in the unselected row are turned on. The bottom device receives a read enable signal to electrically connect the stack of bit primitives in the column to ground, and Each sense amplifier for each column compares the sensed current from the bit stack of that column with a reference current and outputs the corresponding data output signal. Wherein, the reference current is equal to the expected sensed current level when half of the bit bases in the selected row of the bit base stack stores the "1" bit value, and The corresponding data output signal indicates whether a majority of the bit bases in the bit base stack store the "1" bit value.

16. The in-memory computing circuit according to claim 15, wherein, Each sense amplifier for each column includes a first input terminal connected to one end of the bit stack, a second input terminal connected to receive the reference voltage node, and a data output signal node.

17. The in-memory computing circuit according to claim 15, in, The array also includes a reference column of reference bit bases, each reference bit base including a reference resistor having a medium resistance state between a high resistance state and a low resistance state, and The reference bit primitives in the reference column are electrically connected in series to form a reference bit primitive stack between the reference signal generator for the reference column and the additional bottom device.

18. The in-memory computing circuit according to claim 17, wherein, The reference resistor has either a fixed resistance or a variable resistance.

19. The in-memory computing circuit according to claim 17, in, Each sensing amplifier for each column includes: A P-type field-effect transistor and an N-type field-effect transistor are connected in series between the positive power supply voltage rail and the bit base stack for that column; and A comparator having a non-inverting input and an inverting input, the non-inverting input being connected to receive the reference voltage, and the inverting input being connected to an intermediate node at the junction between the P-type field-effect transistor and the N-type field-effect transistor. The gates of the P-type field-effect transistor and the N-type field-effect transistor are respectively connected to the reference signal output node of the reference signal generator and the bias voltage generator; The reference signal generator includes an additional P-type field-effect transistor and an additional N-type field-effect transistor connected in series between the positive power supply voltage rail and the reference bit stack, and further includes the reference signal output node located at the junction between the additional P-type field-effect transistor and the additional N-type field-effect transistor. The gates of the additional P-type field-effect transistor and the additional N-type field-effect transistor are respectively connected to the reference signal output node and the bias voltage generator.

20. An in-memory computation method, comprising: The bit values ​​are stored in the bit bases of an array of bit bases arranged in columns and rows. Each bit base element includes: A variable resistor and a first transistor are connected in series between a first end node and a second end node, wherein the first gate of the first transistor is connected to a first word line for a row; and A second transistor is connected between the first terminal node and the second terminal node, wherein the second gate of the second transistor is connected to a second word line for that row, and The bit bases in the column are connected in series to form a bit base stack; and Perform a read operation to simultaneously compute a majority function pointing to the bit values ​​stored in the selected row of the bit stack.

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