A sleep mode ram retention voltage generation circuit and method

Abstract

The application relates to the technical field of low-power consumption of integrated circuits, and discloses a RAM (Random Access Memory) voltage maintaining circuit and method in a sleep mode, which comprises a reference current generating module, a current mirror array module, a core voltage generating module and a digital calibration control module; the reference current generating module generates nanampere reference current; the current mirror array module outputs programmable mirror current; the core voltage generating module converts the mirror current into output voltage VOUT; and the digital calibration control module compares Vto with Vref when the chip is working, and outputs a calibration signal to adjust the mirror current. The core voltage generating module comprises a PVT self-adaptive bias structure composed of NMOS and PMOS tubes, so that the output voltage is automatically adjusted according to process, voltage and temperature. The application adopts an intermittent working mode of "calibration during working and maintaining during sleeping", and combines an open-loop source follower architecture, so that typical static power consumption of 50nA, PVT self-adaptive adjustment, rapid awakening and extremely small chip area are realized, and the application can be widely applied to super-low-power-consumption devices such as the Internet of Things.

Description

Technical Field

[0001] This invention relates to the field of low-power integrated circuit technology, and in particular to a RAM holding voltage generation circuit and method in sleep mode. Background Technology

[0002] With the proliferation of portable and battery-powered devices such as the Internet of Things (IoT), wearable devices, and implantable medical devices, extremely high demands are being placed on the power consumption of integrated circuits. These devices typically operate in a discontinuous mode, spending most of their time in standby or sleep mode, only briefly waking up to perform tasks when triggered by an event. Examples include environmental monitoring sensor nodes periodically collecting temperature and humidity data, smartwatches displaying the time when the wrist is raised, and wireless headphones waiting to connect in standby mode.

[0003] In these application scenarios, to achieve extremely low system power consumption in sleep mode, the power supply to most of the digital logic circuits (such as the CPU and DSP) inside the chip is typically completely cut off. However, the random access memory (RAM) inside the chip, used to store critical configuration information, operating status, and sensor data, must remain powered on to prevent data loss, thereby enabling rapid state recovery and continuous operation after wake-up. This area that still requires power in sleep mode is called the "holding domain" or "normally open domain." The circuit that powers the RAM holding domain is usually called the RAM holding voltage generation circuit.

[0004] In existing technologies, the most common solution is to design a low-dropout linear regulator (LDO) specifically optimized for low quiescent current (IQ), such as... Figure 2 As shown, the core structure of this LDO typically includes: a reference source module (such as a bandgap reference) for generating a stable reference voltage or current; an error amplifier operating in the subthreshold region to reduce power consumption; a large-size PMOS or NMOS power transistor as the regulation transistor; and a feedback loop composed of a resistor divider network for setting the output voltage. In addition, a power gating switch is integrated to completely shut off the power to the non-holding domain during deep sleep. This approach aims to provide the RAM with a continuous, stable low voltage in sleep mode to ensure no data loss.

[0005] While the LDO-based solutions described above meet the RAM power supply requirements to some extent, their limitations are becoming increasingly apparent in modern applications that strive for extremely low power consumption. The main technical issues are as follows:

[0006] The first technical challenge is reducing static power consumption to the nanoamp level. To obtain accurate and stable output voltage, traditional LDOs must rely on high-precision reference sources (such as bandgap references) and closed-loop error amplifiers. Bandgap references themselves typically consume hundreds of nanoamps to microamps of current. Even when designed in the subthreshold region, the error amplifier's static current is difficult to reduce to below tens of nanoamps, and it requires additional current to ensure loop stability. This results in the total static current of the entire LDO circuit typically being in the hundreds of nanoamps or even microamps. For IoT devices with target standby currents of only tens of nanoamps, this power consumption becomes the main bottleneck for system standby power consumption, severely limiting battery life and making it difficult to meet the requirement of over ten years of battery operation.

[0007] The second technical problem is the lack of adaptive PVT adjustment capability. The threshold voltage (VTH) of MOSFETs manufactured using standard CMOS processes drifts significantly with changes in process angle, power supply voltage, and temperature. The minimum voltage required for RAM data retention (i.e., the holding voltage) also varies with PVT and is closely related to the characteristics of the relevant MOSFETs on the chip. Existing solutions typically provide a fixed output voltage. To ensure no data loss under the worst PVT conditions, designers must allow for a large voltage margin. This results in the actual voltage supplied to the RAM being much higher than its required minimum holding voltage under most typical conditions, causing unnecessary power consumption. Conversely, insufficient margin may lead to RAM data loss under certain PVT conditions.

[0008] The third technical problem is the large circuit area overhead. To achieve stable loops and low-pass filtering at nanoampere currents, traditional LDO designs require huge on-chip resistors (tens of megaohms or even hundreds of megaohms) and capacitors (tens of picofarads). These passive components occupy a large amount of chip area, significantly increasing manufacturing costs and hindering the achievement of high integration and low cost goals.

[0009] Therefore, those skilled in the art urgently need a technical solution for RAM holding voltage generation that can simultaneously achieve ultra-low static power consumption (nanoampere level), PVT adaptive adjustment, and extremely small area overhead. Summary of the Invention

[0010] The core technical problem solved by this invention is that existing technologies face an irreconcilable contradiction between static power consumption, data reliability (PVT adaptability), and chip area when implementing RAM data retention in sleep mode.

[0011] To address the aforementioned core issues, this invention designs a novel RAM holding voltage generation circuit and method in sleep mode. Its purpose is to break through the power consumption, area, and reliability bottlenecks of traditional LDOs through innovative circuit architecture and working mechanism, providing an extremely optimized power solution for low-power chips.

[0012] This power supply solution is a technical solution that integrates a nanoampere-level reference source, digital calibration dynamic compensation, PVT adaptive bias, and seamless switching; its core components are summarized as follows:

[0013] First, an innovative stacked current mirror structure is used to generate an ultra-micro reference current source of only 12.5nA, which minimizes power consumption from the source.

[0014] Secondly, an open-loop LDO architecture based on a source follower was constructed, which avoids the dependence of traditional closed-loop LDOs on error amplifiers and huge feedback resistors.

[0015] More importantly, the circuit incorporates an overlapping diode connection structure composed of NMOS and PMOS transistors (such as NM19 / PM21, NM17 / PM18). This structure can automatically select the transistor with the higher threshold voltage as the bias according to the PVT condition, thereby achieving adaptive adjustment of the RAM holding voltage.

[0016] Meanwhile, the power solution also includes a set of digital calibration logic. During normal chip operation, the output voltage is monitored by a comparator, and the programmable current mirror array (Calib<3:0>) is successively adjusted to accurately calibrate the output voltage value in sleep mode. After calibration, the digital logic is turned off, and the calibration result is stored. When the chip enters sleep mode, the circuit seamlessly switches to the calibrated open-loop state to provide the RAM with a precise and PVT-adaptive holding voltage with nanoamp-level quiescent current.

[0017] This power solution cleverly schedules the power-intensive calibration work during normal chip operation, while only the core circuitry with the lowest power consumption is retained in sleep mode. This achieves extremely high accuracy while maintaining extremely low standby power consumption and a very small chip area.

[0018] To achieve the above objectives, the specific technical solution of the present invention is a RAM holding voltage generation circuit in sleep mode, comprising:

[0019] A reference current generation module is used to generate a nanoampere-level reference current;

[0020] A current mirror array module, connected to the reference current generation module, is used to receive the reference current and output a programmable adjustable mirror current;

[0021] The core voltage generation module is connected to the current mirror array module and is used to convert the mirrored current into a stable output voltage VOUT to power the RAM.

[0022] The digital calibration control module, connected to the core voltage generation module and the current mirror array module, is used to output a calibration signal to adjust the output current of the current mirror array module during normal chip operation, based on the comparison result between the monitoring point voltage Vto of the output voltage VOUT and the reference voltage Vref, until Vto reaches the target value, and then shuts down after calibration to save power consumption.

[0023] The core voltage generation module includes a PVT adaptive bias submodule;

[0024] The PVT adaptive bias submodule consists of at least one NMOS transistor and one PMOS transistor connected in an overlapping source-drain configuration. It is used to automatically select the transistor with a larger threshold voltage as the bias diode according to the current process, voltage and temperature conditions, so that the output voltage VOUT can be adaptively adjusted according to the threshold voltage of the RAM cell.

[0025] The core voltage generation module includes:

[0026] The first NMOS transistor, NM16, has its gate and drain connected to the output of the current mirror array module.

[0027] The second NMOS transistor NM18 has its gate connected to the gate of the first NMOS transistor NM16, its drain connected to the main power supply VDD, and its source used as the output voltage monitoring point Vto, with its substrate shorted to the source.

[0028] The PVT adaptive bias submodule consists of a load circuit composed of a third NMOS transistor NM17, a first PMOS transistor PM18, and a first resistor R12, connected between the source of the first NMOS transistor NM16 and ground, and is used to provide bias for the first NMOS transistor NM16.

[0029] The drain of the first PMOS transistor PM18 is connected to the drain of the third NMOS transistor NM17, the gate of the first PMOS transistor PM18 is connected to the source of the third NMOS transistor NM17, and the gate of the third NMOS transistor NM17 is connected to the source of the first PMOS transistor PM18 and the source of the first NMOS transistor NM16.

[0030] The digital calibration control module includes:

[0031] The comparator has its non-inverting input connected to the output voltage monitoring point Vto and its inverting input connected to the reference voltage Vref.

[0032] A voltage calibration digital logic circuit, the input of which is connected to the output of the comparator, and the output of which outputs a multi-bit calibration signal Calib connected to the current mirror array module;

[0033] The voltage calibration digital logic circuit is used to adjust the calibration signal Calib by successive approximation logic according to the output of the comparator, so that Vto approaches and reaches Vref.

[0034] The reference voltage Vref is provided by a reference voltage generation circuit;

[0035] The reference voltage generation circuit includes: a current source IS, a second PMOS transistor PM19, a fourth NMOS transistor NM21, a second adjustable resistor R14, and a fifth NMOS transistor NM22;

[0036] The reference voltage Vref is generated at the source of the second PMOS transistor PM19, and its value is set to be increased by a certain margin from the threshold voltage of the MOS transistor in the RAM cell, and is adjusted by the second adjustable resistor R14.

[0037] The digital calibration control module also includes a mode switching switch for controlling the chip to switch between normal operation mode and sleep mode; the mode switching switch includes:

[0038] The first switching transistor NM19 is connected between the output monitoring point Vto and the final output voltage VOUT of the core voltage generation module, and its conduction or de-conduction is controlled by the first control signal swp.

[0039] The second switching transistor NM20 is connected between the adjustable load resistor R13 inside the core voltage generation module and ground, and is controlled by the second control signal swn.

[0040] The first control signal swp and the second control signal swn are complementary signals.

[0041] When the chip enters sleep mode, the first control signal swp controls the first switch NM19 to turn on, and the second control signal swn controls the second switch NM20 to turn off. At the same time, the DLDO module that supplies power to the chip's digital logic is turned off and enters a high-impedance state. The core voltage generation module provides a holding voltage to the RAM via the first switch NM19.

[0042] A method for generating RAM holding voltage in sleep mode, the method being implemented based on the aforementioned circuit, includes the following stages:

[0043] Calibration phase: During normal chip operation, the second switch NM20 is turned on and the first switch NM19 is turned off. The digital calibration control module is started. By comparing the output voltage monitoring point Vto with the reference voltage Vref, the output current of the current mirror array module is adjusted until Vto reaches the target value. Then the digital calibration control module is turned off.

[0044] Hold Phase: When the chip enters sleep mode, the second switch NM20 is turned off, the first switch NM19 is turned on, and the DLDO module is turned off so that its output is in a high impedance state. The core voltage generation module continuously provides a stable hold voltage to the RAM according to the state set in the calibration phase.

[0045] The calibration phase adjusts the output current of the current mirror array using a successive approximation method:

[0046] When Vto is less than Vref, the value of the calibration signal Calib is decreased to increase the output current, thereby increasing Vto;

[0047] When Vto is greater than Vref, the value of the calibration signal Calib is increased to reduce the output current, thereby reducing Vto;

[0048] When the comparator output is detected to alternate between "0" and "1", it is determined that Vto is close to the target voltage, and the calibration ends.

[0049] Compared with existing technologies (especially such as Figure 2 Compared with the conventional low-power LDO shown, the technical solution disclosed in this application has the following non-obvious technical features:

[0050] First, this application employs a PVT-adaptive "overlapping" bias structure, whereas existing technologies typically use a fixed bandgap reference voltage or simple diode interconnects to generate bias. This invention creatively employs an "overlapping" structure formed by interconnecting NMOS and PMOS transistors (e.g., Figure 1 (NM19, PM21, NM17, PM18 in the example). This structure can automatically select the transistor with a larger threshold voltage VTH as the bias diode according to the specific PVT conditions, thereby generating a bias voltage that changes in the same direction as the threshold voltage of the MOS transistor in the RAM cell. This design idea of ​​automatically tracking PVT changes by using device competition is completely absent in traditional LDOs.

[0051] Second, this application employs a digital calibration and open-loop hold mechanism based on "intermittent operation." Traditional LDOs operate continuously in closed loop during sleep mode to achieve voltage regulation; however, this invention overturns this model by adopting a strategy of "calibrating during operation and holding open-loop during sleep." When the chip is operating normally, the comparator and digital logic are activated to perform precise digital calibration on the open-loop voltage generation circuit (by adjusting the current through Calib<3:0>). After calibration, the entire calibration link (including the comparator and most of the digital logic) is completely shut down. After entering sleep mode, the circuit only relies on the calibrated open-loop state (i.e., a fixed bias current and a PVT adaptive structure) to output a holding voltage. This mechanism, which separates high-power operation from low-power state, is key to achieving a 50nA-level quiescent current, and its concept exceeds the scope of conventional low-power design.

[0052] Third, this application utilizes a combination of current mirror array and source follower to achieve precise numerical control. Existing technologies typically change the output voltage by adjusting the voltage division ratio of the feedback resistor. This invention uses a programmable current mirror array (PM15 / 16 / 17) and a digital calibration signal (Calib<3:0>) to precisely control the current flowing into the core voltage generation module, and then generates the output voltage through the source follower (NM18 follows NM16). This method of controlling the open-loop voltage by finely adjusting the bias current digitally achieves dynamic compensation for PVT fluctuations, and does not require the introduction of large resistors and error amplifiers, resulting in a novel architecture.

[0053] Fourth, this application employs a unique combination of an NMOS source follower and a PMOS / NMOS overlapping load. In the core voltage generation module, the source voltage of NM16 is determined by its load (the overlapping structure composed of PM18, NM17, and R12), while NM18, as a source follower, has its source voltage following the source of NM16. This load structure is also PVT adaptive, ensuring the robustness of the core bias point. This multi-level, adaptive bias transfer method has not been disclosed in existing literature and patents.

[0054] Fifth, this application achieves seamless switching between working and sleep modes in less than 1 microsecond through a seamless fast switching circuit for working / sleep modes, using complementary switching signals (swp / swn) and dedicated switching transistors (NM19, NM20), combined with the high-impedance design of the DLDO output. In particular, when waking from sleep mode, even if the DLDO output voltage starts to rise, NM18 can quickly replenish current when its voltage is lower than the holding voltage, preventing VOUT from undershooting and ensuring absolute data safety. This meticulous switching logic that considers transient response is the key to ensuring system reliability.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] 1. This invention achieves a balance between data reliability and low power consumption through adaptive PVT adjustment. By introducing an overlapping bias structure of NMOS and PMOS, the RAM holding voltage automatically adjusts with changes in process technology, voltage, and temperature, always following the minimum holding voltage requirement of the RAM cell. This not only eliminates the risk of data loss due to PVT fluctuations but also avoids the power redundancy caused by the margin in traditional fixed voltage solutions, minimizing power consumption while ensuring data reliability.

[0057] 2. This invention achieves ultra-low quiescent power consumption in the nanoampere range. By employing a 12.5nA ultra-micro reference current source, an open-loop source follower architecture, and an intermittent operation strategy of "calibrating during operation and maintaining during sleep," only the core voltage generation circuit operates in sleep mode, and all branch currents are in the nanoampere range, with a typical total quiescent current as low as 50nA. This is more than an order of magnitude lower than traditional microampere or hundreds of nanoampere LDO solutions, significantly extending the lifespan of battery-powered devices.

[0058] 3. This invention significantly reduces chip area and lowers costs. Due to its innovative open-loop structure, it eliminates the need for the large feedback resistors and compensation capacitors found in traditional LDOs. Digital calibration replaces the need for high-precision analog components, and active devices such as current mirrors and source followers enable voltage generation and regulation, thereby drastically reducing the area occupied by on-chip resistors and capacitors and significantly lowering chip manufacturing costs.

[0059] 4. This invention enables fast wake-up and seamless switching. During the sleep and wake-up switching process, the circuit maintains uninterrupted voltage and suppresses voltage undershoot through the fast response mechanism of NM18, ensuring that the switching time is less than 1 microsecond and there is no risk of data loss, thus meeting the requirements of modern SoC for fast response and real-time performance.

[0060] 5. This invention exhibits strong system robustness. The multi-branch current mirror design and modular structure enhance the overall robustness of the circuit. Digital calibration logic can compensate for device aging effects caused by long-term operation, further enhancing the long-term stability of the system. Attached Figure Description

[0061] Figure 1 This is a circuit diagram of the voltage generation circuit described in Embodiment 1 of the present invention;

[0062] Figure 2 This is a circuit diagram of the conventional voltage generation circuit described in this invention;

[0063] Figure 3 This is a flowchart of the method described in Embodiment 3 of the present invention. Detailed Implementation

[0064] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings; Example 1

[0065] A RAM holding voltage generation circuit for chip sleep mode, using an overlapping structure of PMOS and NMOS transistors, as shown below. Figure 1 The NM19, PM21, NM17, and PM18 transistors automatically match the PVT and select the transistor with the larger VTH as its bias diode, thus achieving adaptive adjustment of the PVT.

[0066] Furthermore, during chip operation, digital logic and comparators are used to precisely calibrate the voltage generated by ultra-low-power analog circuitry (nanoampere-level current mirror), and the calibration results are stored for intermittent operation during sleep mode to ensure accurate output. Additionally, a low-power source follower (LDO) architecture and an nA-level reference generation circuit enable precise control of RAM holding voltage and extremely low power consumption, while ensuring data reliability and fast wake-up capability.

[0067] In this embodiment, the ultra-low power reference and current source architecture is as follows:

[0068] A 12.5nA ultra-micro reference current source is used, implemented through a subthreshold MOSFET and a resistor network, to provide a nanoampere-level current basis for the entire circuit;

[0069] The current mirror array (PM15 / 16 / 17) mirrors the reference current proportionally, outputting an adjustable current of 6.25nA-100nA, which significantly reduces the static power consumption of the core voltage generation module. The typical static current of the entire circuit is 50nA, which is much lower than that of traditional circuit structures.

[0070] In this embodiment, the process of digital calibration, dynamic compensation, and adaptive voltage output is as follows:

[0071] After the chip circuit switches to DLDO operating mode Figure 1 When NM19 is off and NM20 is on, the output voltage Vto is calibrated against the reference Vref by the comparator, and a 4-bit calibration signal Calib<3:0> is output by digital logic to gradually adjust the output current of the current mirror array.

[0072] When Vto is less than the output "0" of the comparator vref, the voltage calibration logic control circuit decrements Calib<3:0> by one, increases the output current of the current mirror array, and thus increases the voltage vto.

[0073] When Vto is greater than the comparator output "1" for vref, the voltage calibration logic control circuit increments Calib<3:0> by one, reducing the output current of the current mirror array and thus reducing the Vto voltage. The voltage calibration logic control circuit determines if the most recent comparator outputs are 0101, indicating that Vto is close to the target voltage VREF. It then ends the calibration and shuts down the calibration circuit to save power. This achieves dynamic calibration of PVT fluctuations.

[0074] In this embodiment, the digital calibration control module controls the chip's switching mechanism between normal operation mode and sleep mode as follows:

[0075] When the chip switches from sleep mode to operating mode, the DLDO output turns on, and VOUT rises from the holding voltage until it reaches the DLDO output voltage. Furthermore, because the voltage holding circuit uses an open-loop NMOS follower architecture, when VOUT rises... Figure 1 When the NM18 is turned off, and the DLDO output fluctuates below the holding voltage provided by the NM18, the NM18 will promptly replenish current to ensure that VOUT does not fluctuate significantly. After VOUT stabilizes, the switching transistors swp / swn, in conjunction with the inverter, turn off the NM19, achieving seamless switching between normal and sleep modes. When the chip switches from normal mode to sleep mode, the switching transistors swp / swn, in conjunction with the inverter, turn on the NM19 and turn off the DLDO, making its output high impedance. Due to circuit leakage, VOUT slowly drops to the holding voltage provided by the NM18, with a switching time of <1µs, ensuring no data loss.

[0076] It should be noted that the circuit in this embodiment adopts a modular connection design. The functional modules work together through electrical connections to achieve low-power, high-precision voltage output, which is used to maintain RAM stored values ​​and configuration parameters when the chip is powered off. For example... Figure 1 As shown, the overall connection relationship of the circuit is as follows:

[0077] The left side is the reference current generation module, which generates a high-precision reference current of 12.5nA;

[0078] The middle section is a current mirror array module, which receives the reference current and outputs a programmable adjustable mirror current (6.25nA-100nA).

[0079] The right side is the core voltage generation module, which converts the mirrored current into a stable output voltage VOUT;

[0080] Below is the digital calibration control module. After the chip enters the working mode, Figure 1When the NM19 is turned off, the chip switches to DLDO power supply. The calibration circuit adjusts the mirror current by comparing the output voltage with the reference voltage and outputting the calib<3:0> calibration signal until Vto is greater than and closest to the target voltage.

[0081] The upper right corner indicates that the chip has entered working mode, supplying power to the digital circuits, including the storage circuits, via the DLDO module.

[0082] In this embodiment, the internal and inter-module connections of the circuit are implemented as follows:

[0083] First, the reference current generation module, which consists of PMOS transistors PM11, PM12, PM13, and PM14, NMOS transistors NM11, NM12, NM13, and NM14, and resistor R11, uses a stacked current mirror structure to achieve a 12.5nA reference current output.

[0084] The sources of PM11 and PM12 are both connected to the main power supply VDD, and their gates are shorted and connected to the drain of PM11 to form the first-stage PMOS current mirror.

[0085] The sources of PM13 and PM14 are connected to the drains of PM11 and PM12, respectively, and their gates are shorted and connected to the drain of PM13, forming a second-stage stacked PMOS current mirror.

[0086] The drains of NM11 and NM12 are connected to the drains of PM13 and PM14 respectively, and their gates are shorted and connected to the drain of NM11 to form a second-stage stacked NMOS current mirror.

[0087] The drains of NM13 and NM14 are connected to the sources of NM11 and NM12 respectively, and their gates are shorted and connected to the drain of NM13 to form the first-stage NMOS current mirror.

[0088] The source of NM13 is connected to one end of resistor R11, and the other end of R11 is grounded. The source of NM14 is grounded.

[0089] The gate of PM13 serves as the stacked bias terminal for the reference current and is connected to the gate of PM16<3:0> in the current mirror array module. The gate of PM11 serves as the mirror bias terminal for the reference current and is connected to the gate of PM15<3:0> in the current mirror array module.

[0090] Secondly, the current mirror array module, composed of PMOS transistors PM15<3:0>, PM16<3:0>, and PM17<3:0>, enables programmable mirror output of the reference current.

[0091] The sources of PM15<3:0> are all connected to the main power supply VDD, and their drains are connected to the sources of PM16<3:0> respectively. The drains of PM16<3:0> are connected to the sources of PM17<3:0> respectively.

[0092] The gate of PM15<3:0> is connected to the gate of PM11, and the gate of PM16<3:0> is connected to the gate of PM13.

[0093] The gates of PM17<3:0> are connected to 4-bit digital calibration signals Calib<3:0> respectively to achieve gate-controlled conduction adjustment;

[0094] All drains of PM17<3:0> are shorted, serving as a mirror current output terminal, and connected to the gate, drain, and one end of capacitor C12 of the NM16 core voltage generation module.

[0095] The other end of capacitor C12 is grounded, serving as a filter node to ensure stable output voltage.

[0096] Secondly, the core voltage generation module, which consists of NMOS transistors NM16, NM17, NM18, NM19, and NM20, resistor R12, adjustable resistor R13, switching transistor signals swp and swn, and output capacitor C11, realizes current-to-voltage conversion and mode switching.

[0097] The gate and drain of NM16 are connected to the output of the current mirror array and one end of C12, and are connected to the gate of NM18. The source is connected to the source of PM18 and the gate of NM17.

[0098] The drain of PM18 is connected to the drain of NM17, and its gate is connected to the source of NM17.

[0099] The source of NM17 is grounded through resistor R12;

[0100] The drain of NM18 is connected to the main power supply VDD, and the source is connected to the source of NM19 and one end of the adjustable resistor R13. The substrate and source of NM18 are shorted to avoid substrate bias effect of MOS. The gate of NM18 is connected to the gate of NM16, and its source follows the source of NM16.

[0101] The drain of NM19 is used as the output terminal VOUT, and the gate is connected to swap. When the chip enters sleep mode, DLDO is turned off and its output is designed to be high impedance. NM19 is turned on and VOUT is equal to vto.

[0102] The other end of the adjustable resistor R13 is connected to the drain of NM20. The gate of NM20 receives the switch control signal swn, and the source is grounded.

[0103] One end of the output capacitor C11 is connected to VOUT, and the other end is grounded to stabilize the output voltage.

[0104] The SWP signal is converted into a SWN signal by an inverter, realizing complementary control between SWP and SWN to ensure seamless switching between normal and power-down modes.

[0105] Finally, the digital calibration control module, which consists of a comparator and voltage calibration digital logic circuitry, calibrates the VTO voltage to the target voltage when the chip enters its operating mode, powered by the DLDO, with swp="0" and NM19 disabled.

[0106] The non-inverting input of the comparator is connected to the source of the NM18 (i.e., the output voltage monitoring point Vto), and the inverting input is connected to the external reference voltage Vref;

[0107] The comparator's output is connected to the input of the voltage calibration digital logic circuit;

[0108] The output of the voltage calibration digital logic circuit is a 4-bit calibration signal Calib<3:0>, which is connected to the gate of PM17<3:0> in the current mirror array.

[0109] Vref is generated as follows: One end of the current source IS is connected to the power supply VDD, and the other end flows into the source of PM19, outputting the Vref reference voltage. The drain of PM19 is connected to the drain of NM211, and the gate of NM21 is connected to the source of PM19. The gate of PM19 is connected to the source of NM21 and one end of the adjustable resistor R14. The other end of R14 is connected to the drain of NM22. The source of NM22 is grounded, and its gate is connected to swn. Vref is designed to increase the voltage by a certain margin compared to VTH of the corresponding PMOS or NMOS transistor in the RAM. The voltage value is adjusted by R14. This design allows VOUT to be dynamically adjusted according to process technology, temperature, and voltage.

[0110] In this embodiment, the overall working connection logic of the circuit is as follows:

[0111] Normal operating mode: swp is low, swn is high, NM19 is off, and NM20 is on. The comparator monitors the deviation between Vto and Vref in real time. The digital logic output Calib<3:0> adjusts the conduction state of PM17<3:0> to compensate for voltage deviations caused by process, temperature, and power supply variations, until Vto is higher than Vref and closest to Vref, at which point calibration stops. The adjustable resistor R13 can be configured to account for the leakage current of the circuit required to retain power after power loss, further improving the accuracy of the Vto voltage.

[0112] In the DLDO power-down retention mode (also known as sleep mode), when swp is high and swn is low, NM19 is turned on, NM20 is turned off, and DVDD is turned off, its output is high impedance. At this time, the chip is in an extremely low power consumption working mode. The source output of NM18 provides the RAM with the power-down retention voltage after DLDO is turned off through the NM19 switching transistor. The core voltage generation module continuously outputs VOUT.

[0113] The chip's cyclic switching between operating mode and power-down mode (sleep mode) ensures that the low-power holding voltage generation circuit is calibrated in operating mode and outputs an accurate holding voltage in sleep mode, maintaining normal data retention in the memory cells. This allows the chip to maintain extremely low power consumption in sleep mode. On-chip periodic adjustment of the output voltage is achieved, eliminating the effects of process variations, temperature, and power supply changes, thus improving system stability. Example 2

[0114] A RAM voltage generation circuit for chip sleep mode, particularly for IoT sensor nodes (40nm; CMOS), used in environmental monitoring sensor SoCs, is battery powered and operates cyclically to maintain environmental data and calibration parameters collected in SRAM.

[0115] Process node: 40nm SMIC CMOS;

[0116] The RAM holds a typical voltage of 0.5V, varying from 0.4V to 0.6V.

[0117] RAM operating voltage: 1.2V;

[0118] RAM leakage current: <1uA;

[0119] Static power consumption of the power-down retention circuit: <150nA (typical value 50nA);

[0120] The low-power holding voltage generation circuit has a dynamically adjustable output voltage VOUT range of 0.4-0.6.

[0121] Adjustable preload resistor R13: 500kΩ-2MΩ.

[0122] Everything else is the same as in Example 1. Example 3

[0123] A method for generating RAM hold voltage in sleep mode, the method being implemented based on the circuit described in the embodiment, such as... Figure 3 As shown, it includes the following stages:

[0124] Calibration phase: During normal chip operation, the second switch (NM20) is turned on and the first switch (NM19) is turned off. The digital calibration control module is started. By comparing the output voltage monitoring point Vto with the reference voltage Vref, the output current of the current mirror array module is adjusted until Vto reaches the target value. Then the digital calibration control module is turned off.

[0125] Hold Phase: When the chip enters sleep mode, the second switch (NM20) is turned off, the first switch (NM19) is turned on, and the DLDO module is turned off so that its output is in a high impedance state. The core voltage generation module continuously provides a stable hold voltage to the RAM according to the state set in the calibration phase.

[0126] The calibration phase adjusts the output current of the current mirror array using a successive approximation method:

[0127] When Vto is less than Vref, the value of the calibration signal Calib is decreased to increase the output current, thereby increasing Vto;

[0128] When Vto is greater than Vref, the value of the calibration signal Calib is increased to reduce the output current, thereby reducing Vto;

[0129] When the comparator output is detected to alternate between "0" and "1", it is determined that Vto is close to the target voltage, and the calibration ends.

[0130] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, the phrase "comprising an element defined as..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0131] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A RAM holding voltage generation circuit in sleep mode, characterized in that, include: A reference current generation module is used to generate a reference current in the nanoampere range; A current mirror array module, connected to the reference current generation module, is used to receive the reference current and output a programmable adjustable mirror current; The core voltage generation module is connected to the current mirror array module and is used to convert the mirrored current into a stable output voltage VOUT to power the RAM. The digital calibration control module, connected to the core voltage generation module and the current mirror array module, is used to output a calibration signal to adjust the output current of the current mirror array module during normal chip operation, based on the comparison result between the monitoring point voltage Vto of the output voltage VOUT and the reference voltage Vref, until the monitoring point voltage Vto reaches the target value, and then turn off after calibration to save power consumption. The core voltage generation module includes a PVT adaptive bias submodule; The PVT adaptive bias submodule is composed of at least one NMOS transistor and one PMOS transistor connected in a manner with their source and drain overlapping each other. It is used to automatically select the transistor with a larger threshold voltage as the bias diode according to the current process, voltage and temperature conditions, so that the output voltage VOUT can be adaptively adjusted according to the threshold voltage of the RAM cell. The core voltage generation module includes: The first NMOS transistor, NM16, has its gate and drain connected to the output of the current mirror array module. The second NMOS transistor NM18 has its gate connected to the gate of the first NMOS transistor NM16, its drain connected to the main power supply VDD, and its source used as the monitoring point voltage Vto of the output voltage VOUT, with its substrate shorted to the source. The PVT adaptive bias submodule consists of a load circuit composed of a third NMOS transistor NM17, a first PMOS transistor PM18, and a first resistor R12, connected between the source of the first NMOS transistor NM16 and ground, and is used to provide bias for the first NMOS transistor NM16.

2. The circuit according to claim 1, characterized in that, The drain of the first PMOS transistor PM18 is connected to the drain of the third NMOS transistor NM17, the gate of the first PMOS transistor PM18 is connected to the source of the third NMOS transistor NM17, and the gate of the third NMOS transistor NM17 is connected to the source of the first PMOS transistor PM18 and the source of the first NMOS transistor NM16.

3. The circuit according to claim 1, characterized in that, The digital calibration control module includes: The comparator has its non-inverting input connected to the monitoring point voltage Vto and its inverting input connected to the reference voltage Vref. A voltage calibration digital logic circuit, the input of which is connected to the output of the comparator, and the output of which outputs a multi-bit calibration signal Calib connected to the current mirror array module; The voltage calibration digital logic circuit is used to adjust the calibration signal Calib by successive approximation logic according to the output of the comparator, so that the monitoring point voltage Vto approaches and reaches the reference voltage Vref.

4. The circuit according to claim 3, characterized in that, The reference voltage Vref is provided by a reference voltage generation circuit; The reference voltage generation circuit includes: a current source IS, a second PMOS transistor PM19, a fourth NMOS transistor NM21, a second adjustable resistor R14, and a fifth NMOS transistor NM22; The reference voltage Vref is generated at the source of the second PMOS transistor PM19, and its value is set to be increased by a certain margin from the threshold voltage of the MOS transistor in the RAM cell, and is adjusted by the second adjustable resistor R14.

5. The circuit according to claim 1, characterized in that, The digital calibration control module also includes a mode switching switch for controlling the chip to switch between normal operation mode and sleep mode; the mode switching switch includes: The first switching transistor NM19 is connected between the output monitoring point voltage Vto and the final output voltage VOUT of the core voltage generation module, and its conduction or de-conduction is controlled by the first control signal swp. The second switching transistor NM20 is connected between the adjustable load resistor R13 inside the core voltage generation module and ground, and is controlled by the second control signal swn. The first control signal swp and the second control signal swn are complementary signals.

6. The circuit according to claim 5, characterized in that, When the chip enters sleep mode, the first control signal swp controls the first switch NM19 to turn on, and the second control signal swn controls the second switch NM20 to turn off. At the same time, the DLDO module that supplies power to the chip's digital logic is turned off and enters a high-impedance state. The core voltage generation module provides a holding voltage to the RAM via the first switch NM19.

7. A method for generating RAM holding voltage in sleep mode, said method being implemented based on the circuit according to any one of claims 1 to 6, characterized in that, Includes the following stages: Calibration phase: During normal chip operation, the second switch NM20 is turned on and the first switch NM19 is turned off. The digital calibration control module is started. By comparing the monitoring point voltage Vto of the output voltage VOUT with the reference voltage Vref, the output current of the current mirror array module is adjusted until the monitoring point voltage Vto reaches the target value. Then the digital calibration control module is turned off. Hold Phase: When the chip enters sleep mode, the second switch NM20 is turned off, the first switch NM19 is turned on, and the DLDO module is turned off so that its output is in a high impedance state. The core voltage generation module continuously provides a stable hold voltage to the RAM according to the state set in the calibration phase.

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