Dynamic bandwidth allocation system, server, dynamic bandwidth allocation method

Abstract

This disclosure discloses a dynamic bandwidth allocation system, a dynamic bandwidth allocation method, and a server, relating to the field of server technology. The dynamic bandwidth allocation system includes a processing unit, a management controller, a configuration storage unit, and a selection unit. The processing unit has at least one high-speed interconnect bus interface. The configuration storage unit stores link bandwidth configuration information for the high-speed interconnect bus interface. In response to server power-on, the management controller retrieves the corresponding link bandwidth configuration information from the configuration storage unit based on a mode selection signal and provides this information to the processing unit. The processing unit configures the link bandwidth of the corresponding high-speed interconnect bus interface according to the link bandwidth configuration information. By decoupling bandwidth allocation information from traditional hardware circuitry, and implementing dynamic and flexible allocation of high-speed interconnect bus interface link bandwidth in a software-defined manner, the system solves the problem of maintenance and reconfiguration difficulties caused by fixed hardware bandwidth configuration.

Description

Technical Field

[0001] This disclosure relates to the field of server technology, and in particular to dynamic bandwidth allocation systems, servers, and dynamic bandwidth allocation methods. Background Technology

[0002] With the rapid development of big data, artificial intelligence, and cloud computing, servers need to support diverse business demands characterized by high concurrency, low latency, and high bandwidth. In traditional server architecture design, the bandwidth allocation of high-speed interconnect buses (such as PCIe) relies on static configuration using hardware resistor networks. For example, the physical bandwidth of each PCIe port of the CPU is fixed at x16, but it can be split into various modes such as x8x8 and x4x4x4x4 depending on the needs of the access devices. This splitting information (bifurcation signal) is preset through a combination of pull-up and pull-down resistors on the board. The CPU reads this signal through the I2C bus during the power-on initialization phase and completes the bandwidth allocation.

[0003] However, the fixed bandwidth allocation method in hardware lacks flexibility. The same expansion card cannot adapt to different bandwidth requirements, resulting in the need to design multiple versions of hardware for different configurations, which increases material and production costs. At the same time, a large number of independent configuration signal lines occupy valuable PCB layout space, increasing design difficulty and risk. When replacing modules with different bandwidth requirements (such as GPUs) during maintenance, the expansion card containing them must also be replaced, which is cumbersome and costly. Summary of the Invention

[0004] This disclosure provides a dynamic bandwidth allocation system, server, and dynamic bandwidth allocation method to at least solve the problems of complex design and difficult maintenance caused by bandwidth allocation relying on hard-coded hardware in related technologies.

[0005] In a first aspect, this disclosure provides a dynamic bandwidth allocation system applied to a server. The dynamic bandwidth allocation system includes: a processing unit, a management controller, a configuration storage unit, and a selection unit. The processing unit has at least one high-speed interconnect bus interface. The management controller is communicatively connected to the processing unit. The configuration storage unit is communicatively connected to the management controller. The selection unit is used to generate a mode selection signal.

[0006] The configuration storage unit stores link bandwidth configuration information for at least one high-speed interconnect bus interface. The management controller, in response to server power-on, retrieves the corresponding link bandwidth configuration information from the configuration storage unit based on a mode selection signal and provides this information to the processing unit. The processing unit configures the link bandwidth of the corresponding high-speed interconnect bus interface according to the link bandwidth configuration information.

[0007] The dynamic bandwidth allocation system provided in this application, compared with the existing technology where bandwidth configuration information is hard-coded onto the PCB by hardware resistors, stores the link bandwidth configuration information in the form of data in a programmable configuration storage unit. The management controller acts as an intelligent intermediary to acquire and forward the information, making bandwidth allocation a function that can be dynamically adjusted by the management controller. This achieves a leap from hardware-defined to software-defined, solves the problem that the same board cannot adapt to multiple bandwidth requirements, and reduces hardware design complexity and production costs.

[0008] Secondly, this disclosure also provides a server, including the aforementioned dynamic bandwidth allocation system.

[0009] This server has the same beneficial technical effects as the dynamic bandwidth allocation system provided in the first aspect, which will not be elaborated here.

[0010] Thirdly, this disclosure also provides a dynamic bandwidth allocation method, which is applied to a server. The dynamic bandwidth allocation method includes at least the following steps.

[0011] The management controller responds to the server powering on by acquiring a mode selection signal.

[0012] The management controller obtains the link bandwidth configuration information of at least one high-speed interconnect bus interface from the configuration storage unit based on the mode selection signal.

[0013] The management controller provides link bandwidth configuration information to the processing unit, so that the processing unit can configure the link bandwidth of the corresponding high-speed interconnect bus interface according to the link bandwidth configuration information.

[0014] This dynamic bandwidth allocation method has the same beneficial technical effects as the dynamic bandwidth allocation system provided in the first aspect, and will not be described in detail here.

[0015] Fourthly, this disclosure also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described dynamic bandwidth allocation methods when executing the computer program.

[0016] This electronic device has the same beneficial technical effects as the dynamic bandwidth allocation method provided by the third party, which will not be elaborated here.

[0017] Fifthly, this disclosure also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described dynamic bandwidth allocation methods.

[0018] The computer-readable storage medium has the same beneficial technical effects as the dynamic bandwidth allocation method provided by the third aspect, which will not be elaborated here.

[0019] Sixthly, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described dynamic bandwidth allocation methods.

[0020] This computer program product has the same beneficial technical effects as the dynamic bandwidth allocation method provided by the third party, which will not be elaborated here. Attached Figure Description

[0021] To more clearly illustrate the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a structural block diagram of the dynamic bandwidth allocation system provided in the embodiments of this disclosure; Figure 2 A partial structural diagram of a dynamic bandwidth allocation system provided in an embodiment of this disclosure; Figure 3 for Figure 2 A magnified view of a portion of the image; Figure 4 for Figure 2 A magnified view of a portion of the image; Figure 5 Another partial structural diagram of the dynamic bandwidth allocation system provided in the embodiments of this disclosure; Figure 6 for Figure 5 A magnified view of the local structure; Figure 7 for Figure 5 A magnified view of the local structure; Figure 8 for Figure 5 A magnified view of the local structure; Figure 9 A schematic diagram of the processor; Figure 10 A schematic diagram of the encoding and combinational logic of CPU address, VPP address and Bifurcation information; Figure 11 A schematic diagram illustrating the encoding of PCIe link bandwidth configuration information for the server. Figure 12 This diagram illustrates the mapping of address, instruction encoding, and bandwidth configuration information for an I / O expander chip. Detailed Implementation

[0023] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this disclosure.

[0024] It should be noted that, in the description of this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this disclosure are used to distinguish similar objects and are not used to describe a particular order or sequence.

[0025] Some embodiments of this disclosure provide a dynamic bandwidth allocation system, which can be applied to electronic devices, such as PCs, laptops, mobile phones, tablets, servers, switches, routers, embedded devices, and other electronic devices with computing capabilities.

[0026] To enable those skilled in the art to better understand the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments. For ease of understanding, key terms will first be explained.

[0027] Processing unit 1 is a hardware module with data processing capabilities, such as a central processing unit (CPU). The CPU has multiple high-speed interconnect bus interfaces 11. These high-speed interconnect bus interfaces 11 refer to physical interfaces used for high-speed data transfer between boards or chips, such as PCIe (Peripheral Component Interconnect Express) interfaces. Each PCIe port physically has a fixed maximum link width; for example, x16 represents 16 data channels. It supports splitting x16 into various sub-link widths such as x8x8, x4x4x4x4, and x2x2x2x2x2x2x2x2 through bandwidth configuration information to accommodate the needs of different devices such as GPUs, HCA cards, DPUs, and NVMe hard drives.

[0028] Management Controller 2 refers to an embedded system independent of Processing Unit 1, possessing management functions, such as a Baseboard Management Controller (BMC). The BMC is adapted based on the Open BMC code library and incorporates various bus drivers (such as I2C and eSPI), register sets (such as the bifurcation register, SEL register, and key register), and an embedded operating system. The BMC is powered by the server's standby power supply (which has its own independent power supply) and can operate even before the server's main power is turned on. Therefore, it can respond to the server's power-on signal and execute the startup process for monitoring, configuring, and managing server hardware.

[0029] Configuration storage unit 3 is a non-volatile memory used to store link bandwidth configuration information, such as electrically erasable programmable read-only memory (EEPROM), the contents of which can be read and written via the I2C bus.

[0030] Selection unit 4 is a hardware or software module used to generate a mode selection signal. The mode selection signal is a binary signal used to indicate to the management controller 2 which configuration storage unit 3 should retrieve configuration information from.

[0031] Link bandwidth configuration information, also known in the field as bandwidth information, is a binary code used to instruct the processing unit how to split a physical port into multiple sub-ports. For example, the code "10" represents x16, and the code "01" represents x8.

[0032] In some embodiments, such as Figure 1 As shown, the dynamic bandwidth allocation system includes: a processing unit 1, a management controller 2, a configuration storage unit 3, and a selection unit 4. The processing unit 1 has at least one high-speed interconnect bus interface 11. The management controller 2 is communicatively connected to the processing unit 1. The configuration storage unit 3 is communicatively connected to the management controller 2. The selection unit 4 is used to generate a mode selection signal.

[0033] The dynamic bandwidth allocation system is applied to the server. Configuration storage unit 3 stores link bandwidth configuration information for at least one high-speed interconnect bus interface 11. Management controller 2, in response to server power-on, retrieves the corresponding link bandwidth configuration information from configuration storage unit 3 based on a mode selection signal and provides the link bandwidth configuration information to processing unit 1. Processing unit 1 configures the link bandwidth of the corresponding high-speed interconnect bus interface 11 according to the link bandwidth configuration information.

[0034] For example, processing unit 1 and management controller 2 establish a communication connection via an eSPI (Enhanced Serial Peripheral Interface) bus. eSPI is a high-speed, low-latency serial bus suitable for transmitting small amounts of critical configuration data in the early stages of system power-up.

[0035] For example, the configuration storage unit 3 is connected to the management controller 2 via an I2C (Inter-Integrated Circuit) bus. The I2C bus is a two-wire serial bus that includes a clock line (SCL) and a data line (SDA) and supports multi-master and multi-slave communication.

[0036] For example, the I2C bus rate can be configured to standard mode (100Kbps) or fast mode (400Kbps). The eSPI bus rate is up to 1Gbps with microsecond latency.

[0037] For example, the selection unit 4 is connected to the general purpose input / output (GPIO) pin of the management controller 2, and transmits mode selection information to the management controller by outputting a high-level or low-level signal.

[0038] The interaction relationships and workflows among the various components of the dynamic bandwidth allocation system described in this embodiment are as follows: When the server is powered on, the standby power supply supplies power to the management controller 2, and the management controller starts up. After startup, the management controller first reads the level signal output by the selection unit 4 to obtain the mode selection signal. Subsequently, the management controller 2 reads the corresponding link bandwidth configuration information from the configuration storage unit 3 according to the mode selection signal provided by the selection unit 4, and temporarily stores it in the internal register.

[0039] When the user presses the power button or starts the server main power supply via remote wake-up service, processing unit 1 begins to perform power-on self-test (POST). In the early stage of POST (PEI stage), processing unit 1 reads the link bandwidth configuration information from the register of management controller 2. Based on this information, processing unit 1 completes the link bandwidth configuration of the corresponding high-speed interconnect bus interface through its built-in bandwidth splitting control module, and performs link training in subsequent stages to enable the interface to work at the specified bandwidth.

[0040] The dynamic bandwidth allocation system provided in this embodiment stores link bandwidth configuration information in the form of data in the programmable configuration storage unit 3, and the management controller 2 acts as an intelligent intermediary to acquire and forward it. This makes bandwidth allocation a function that can be dynamically adjusted by the management controller 2, realizing a fundamental leap from hardware definition to software definition, liberating hardware design, and making link bandwidth a parameter that can be flexibly adjusted through the management interface. This provides the possibility for all subsequent improvements to enhance flexibility and simplify operation and maintenance.

[0041] Compared to the solution where bandwidth configuration is hard-coded on the PCB through a network of physical resistors, requiring hardware modifications to change the configuration (bandwidth configuration information is implemented through a network of pull-up / pull-down resistors on the PCB, requiring four independent signal lines for each PCIe port, resulting in a large number of PCB traces and a complex layout), the dynamic bandwidth allocation system provided in this embodiment migrates this information from physical traces to programmable memory, directly eliminating these signal lines and related resistors and buffer chips. This reduces the difficulty of hardware design and manufacturing costs at the physical level, while also freeing up PCB routing space.

[0042] In traditional solutions, once the resistance soldering is completed, the bandwidth configuration is fixed and cannot be modified online. If different downlink devices with varying bandwidth requirements need to be adapted, the entire board must be replaced. In this embodiment, the contents of the configuration storage unit can be rewritten through the management controller, allowing the same physical board to flexibly adapt to various bandwidth needs without requiring changes to the hardware design.

[0043] Based on these flexible modification capabilities, maintenance personnel no longer need to enter the data center to disassemble and replace cards. They can simply upload the new configuration file through the management controller's remote interface (such as Web or IPMI) to complete the bandwidth allocation change. This reduces the maintenance and reconfiguration time for large-scale servers from hours to minutes, significantly lowering maintenance costs.

[0044] By eliminating a large number of signal lines and discrete components, potential points of failure on the PCB are reduced. At the same time, configuration information is stored in digital form, unaffected by signal crosstalk or level drift, and is deterministically read by the management controller at system startup, avoiding configuration errors caused by poor soldering or resistor accuracy deviations in traditional hardware solutions.

[0045] In some embodiments, such as Figure 2 and Figure 3 As shown, the processing unit 1 includes: a central processing unit (CPU) of the server, used to perform data calculation and device interconnection management.

[0046] For example, the high-speed interconnect bus interface 11 can be a PCIe port. The PCIe port supports the PCIe 4.0 / 5.0 protocol, with a default physical bandwidth configuration of x16, which can be split into multiple link widths such as x8x8, x4x4x4x4, and x2x2x2x2, depending on the link bandwidth configuration information. It adapts to the bandwidth requirements of different devices such as HCA cards (Host Channel Adapters), DPUs (Data Processing Units), GPUs (General Purpose Computing Graphics Processors), accelerator cards, and hard drives.

[0047] For example, the processing unit 1 has a built-in channel splitting signal (bifurcation signal) processing module, which can receive the link bandwidth configuration information (i.e., the combination of bifurcation signals) transmitted by the management controller 2, and complete the bandwidth splitting and initialization of the PCIe link in the PEI stage of POST (Power-On Self-Test), and perform link training in the DXE stage to ensure stable link communication.

[0048] In some embodiments, such as Figure 2 and Figure 3 As shown, the management controller 2 includes a baseboard management controller (BMC). The baseboard management controller is adapted based on the Open BMC code library and has built-in various bus drivers (I2C, eSPI, etc.), register groups (bifurcation register, SEL register, key register) and an embedded operating system.

[0049] For example, the baseboard management controller is used to implement "configuration reading - information processing - command issuance".

[0050] For example, it is used to respond to the server power-on signal, determine the configuration read path based on the mode selection signal, access the configuration storage unit through the first communication bus to read the link bandwidth configuration information and decrypt and verify it, perform address matching and logical operations on the distributed configuration information to generate a complete configuration, transmit the configuration information to the processing unit through the second communication bus, and manage the write protection status of the configuration storage unit in response to the configuration update command.

[0051] Taking a dual-socket Intel Birch Stream platform server as an example, the BMC internally has a 50-byte bifurcation register to store the collected bifurcation information, such as... Figure 10As shown, each PCIe port's bifurcation information requires 5 bytes of space to store. Of these, 2 bytes are address bits, storing the CPU and VPP addresses; 3 bytes are data bits: two are used to store the high 8 bits and low 8 bits of the PCIe port's bifurcation respectively, and one is used to store the bifurcation ultimately provided to the CPU. This bifurcation is obtained by logically operating on the high 8 bits and low 8 bits of the bifurcation. All reserved bits are set to 0.

[0052] To implement the scheme switching function, the BMC requires a 1-byte SEL register to store the scheme selection information. This register is write-protected. When write protection is enabled, the value of the register is locked and cannot be changed. When write protection is disabled, the value can be modified through Linux OS commands or IPMI commands within the BMC, or by reading the hardware status of the SEL_GPI pin.

[0053] During normal power-on, if write protection of the SEL register is disabled, after the BMC powers on and starts up, the BMC will scan the status of SEL_GPIO within 1 second and write it into the SEL register. The BMC contains a 1-byte key register to store the key used to parse information read from the first memory and all second memories.

[0054] The internal register structure of EEPROM (first memory) is roughly the same as the bifurcation register structure of BMC, such as Figure 11 As shown, it consists of 40 bytes, but unlike the first memory, it does not contain a byte for storing the complete bifurcation. In addition, the first memory contains a 1-byte key for encryption; all data read from the first memory must be added to this key.

[0055] In some embodiments, such as Figure 2 , Figure 3 and Figure 7 As shown, the configuration storage unit 3 includes a first memory and at least one second memory. The first memory is located on the server's motherboard MB, and the at least one second memory is located on the server's function board. The mode selection signal is used to instruct the management controller 2 to obtain link bandwidth configuration information from the first memory (centralized mode) or from at least one second memory (distributed mode).

[0056] For example, the internal register structure of the first memory consists of 40 bytes, with each PCIe port corresponding to 5 bytes (2 bytes of address bits and 3 bytes of data bits), which corresponds to the internal bifurcation register structure of the BMC.

[0057] For example, the register size of the second memory depends on the maximum number of PCIe ports that the function board can actually adapt to. For each half PCIe port that can be adapted (i.e., one octet), three bytes of registers are added to store the I2C address of the IO expander chip, the input port read instruction, and the bifurcation information of the octet.

[0058] For example, the first memory is an electrically erasable programmable read-only memory (EEPROM).

[0059] For example, the first memory is located on the server motherboard, such as an EEPROM chip soldered onto the motherboard PCB, for centrally storing all or most of the link bandwidth configuration information of the high-speed interconnect bus interfaces.

[0060] For example, the second memory is an electrically erasable programmable read-only memory.

[0061] For example, the second memory is located on a function board (e.g., a Riser card, a backplane, or a GPU expansion board). Each function board is independently configured with an EEPROM chip to store the bandwidth configuration information required by the port or link to which the board is connected.

[0062] The first memory, a centralized storage medium, is located on the motherboard MB and stores the bandwidth information of all PCIe ports, supporting a one-to-one mapping between CPU serial number, PCIe port identifier, and bandwidth configuration. The second memory, a distributed storage medium, is located on the function boards (Riser cards, backplanes). That is, each function board is independently configured with EEPROM to store its own corresponding link bandwidth configuration information.

[0063] Therefore, the first memory is suitable for scenarios with fixed device configurations. The second memory is suitable for decoupled architecture scenarios with flexible combinations of multiple devices.

[0064] In summary, the centralized storage of the first storage device is suitable for scenarios with fixed server configurations and a single type of equipment, and the configuration management is unified and convenient. The distributed storage of the second storage device is suitable for scenarios with flexible combinations of multiple devices under a decoupled server architecture. Each functional board comes with its own configuration, and there is no need to reconfigure the motherboard when replacing devices, thus avoiding the problem of "multi-device configuration conflicts" in centralized storage.

[0065] Compared to traditional multi-device scenarios that require designing dedicated hardware configuration circuits for each functional board, this embodiment stores configuration information in a second memory. The same functional board can be adapted to different bandwidth requirements by modifying the configuration, eliminating the need to design multiple hardware boards, significantly reducing hardware redundancy and lowering R&D and production costs. When adding a new functional board, only the corresponding configuration information needs to be written to the second memory, and the management controller 2 can automatically match it through the address recognition unit. No modification to the motherboard hardware or management controller software is required, achieving plug-and-play modular expansion and improving the server's scalability.

[0066] Of course, in a decoupled architecture scenario with flexible combination of multiple devices, bandwidth allocation information can also be read through the first memory. The above is only an illustrative description of some possible implementations of this disclosure and is not intended to limit this disclosure.

[0067] Both the first and second memories support write protection. Their write protection signals (WP) are connected to the GPIO pins of the management controller 2 or the IO expander chip, respectively. Write protection is only lifted during configuration updates to ensure configuration security. See below for details; further explanation is omitted here.

[0068] In some embodiments, when the mode selection signal indicates that configuration information is to be obtained from at least one second memory, the dynamic bandwidth allocation system further includes an address identification unit 5, which is disposed on a function board and connected to the management controller 2.

[0069] The address identification unit 5 is used to provide the identification information (CPU serial number) of the processing unit connected to the function board and the port identification information (VPP address) of the bus interface.

[0070] In some embodiments, the management controller 2 is further configured to read the identification information of the processing unit and the port identification information of the bus interface from the address identification unit 5, and associate and match them with the link bandwidth configuration information read from the corresponding second memory.

[0071] Address identification unit 5 is set on functional boards such as Riser card and backplane to provide device location information to management controller 2, ensuring that the link bandwidth configuration information in configuration storage unit 3 can be accurately matched to the corresponding PCIe port of processing unit 1.

[0072] Specifically, in a server architecture with multiple CPUs, multiple PCIe ports, and multiple function boards, the dual positioning information of "CPU serial number + PCIe port identifier" provided by the address identification unit 5 enables the management controller 2 to accurately bind the configuration information in the second memory to the corresponding port of the processing unit 1, thus solving the configuration misalignment problem caused by the lack of traditional address identification.

[0073] The standardized design of the address identification unit 5 allows multiple functional boards to be connected to the server motherboard simultaneously. The management controller 2 polls the address identification units 5 of each board to match the configuration information, supporting collaborative work of multiple devices such as HCA cards, DPUs, GPUs, and hard drives, and adapting to the high concurrency requirements of heterogeneous computing.

[0074] Address recognition unit 5 uses a standardized IO expander chip (such as PCA9555 or PCA9548), which can be adapted to the address definitions of different platforms through software configuration. This eliminates the need to design dedicated address recognition circuits for different platforms, reduces hardware design complexity and cost, and improves system compatibility.

[0075] To distinguish between the CPU serial number and the PCIe port, the Dynamic Bandwidth Allocation (VPP) system reserves three bits for the CPU address and four bits for each octet. The CPU address represents the CPU serial number (e.g., a single-socket server has only CPU0, while a dual-socket server has both CPU0 and CPU1), and is represented by three address bits (Addr0-Addr2). The VPP address represents which eight bits of which PCIe port the CPU belongs to (e.g., in the Intel platform, PE0_ABCD represents the lower eight bits of PCIe port 0, and PE3_EFGH represents the higher eight bits of PCIe port 0), and is represented by four address bits (Addr0-Addr3).

[0076] Table 1

[0077] As shown in Table 1, a single-socket server has only CPU0; a dual-socket server has both CPU0 and CPU1, and so on.

[0078] For example, the identification information of the processing unit includes the CPU serial number (e.g., CPU0, CPU1), which is used to represent the server CPU core to which the function board is connected. It is represented by a 3-bit address signal (Addr0-Addr2). For example, Addr0=0, Addr1=0, and Addr2=0 correspond to CPU0.

[0079] The VPP address is used to identify which octet of the CPU's PCIe port this octet belongs to.

[0080] Table 2

[0081] Taking the Intel platform as an example, as shown in Table 2, in the PEX_YZZZ format, X = the PCIe port number (0 / 1 / 2 / 3 / 4 / 5, etc., representing an independent PCIe controller port), YZZZ represents the channel bit segment of that port, ABCD corresponds to the lower eight bits of the port (e.g., a core channel group with an x8 bit width), and EFGH corresponds to the higher eight bits of the port (e.g., a port with an x16 bit width, which, together with the lower eight bits, forms a complete x16 channel). For example, PE0_ABCD is the lower eight bits of PCIe port 0, and PE3_EFGH is the higher eight bits of PCIe port 0.

[0082] For example, the port identification information of the bus interface includes the VPP address, which is used to characterize the CPU PCIe port to which the function board is connected and the high / low eight bits of the port (e.g., PE0_ABCD is the low eight bits of PCIeport0, and PE0_EFGH is the high eight bits of PCIeport0), and is characterized by a 4-bit address signal (Addr0-Addr3).

[0083] Table 3

[0084] Taking the AMD platform as an example, as shown in Table 3, its PCIe ports use the identification format [P / G]X_YZ. Here, [P / G] represents the PCIe controller group (e.g., P is the basic controller group, G is the extended controller group, used to distinguish different PCIe control modules on the platform); X is the port number within the corresponding controller group (0 / 1 / 2 / 3, representing independent PCIe controller ports within the group); YZ represents the channel bit segment of the port. For example, AB corresponds to the lower four bits of the port, and CD corresponds to the higher four bits of the port. The combination of these two bits constitutes the complete x8-bit wide PCIe channel of the port.

[0085] Combining the VPP Addr (4-bit address code) in Table 3, for example, P0_AB is the lower four-bit channel of port0 of the P basic controller group, and the corresponding VPP Addr (Addr0-3) is 0000; P0_CD is the higher four-bit channel of port0 of the P group, and the corresponding VPP Addr is 0001. The two together constitute the complete x8 bit-width PCIe channel of port0 of the P group.

[0086] Similarly, P1_AB is the lower four-bit channel of port1 in group P (corresponding to VPP Addr 0010), and P1_CD is the higher four-bit channel of port1 in group P (corresponding to VPP Addr 0011). The combination of the two forms the x8 channel of port1 in group P.

[0087] G0_AB is the lower four-bit channel of port0 in the G extended controller group (corresponding to VPP Addr 1000), and G0_CD is the higher four-bit channel of port0 in the G group (corresponding to VPP Addr 1001). The two are combined to form the x8 channel of port0 in the G group. The ports in the subsequent G1~G3 groups also follow the combination logic of "AB (lower four bits) + CD (higher four bits)" and correspond to different VPP Addr codes.

[0088] The VPP Addr in Table 3 is a hardware-level channel identification identifier. It accurately distinguishes each PCIe channel group through a 4-bit code, ensuring that the PCIe signals of devices such as hard drives and expansion cards can be matched to the corresponding controller port channels, thereby achieving signal adaptation and stable transmission of the devices.

[0089] In some embodiments, such as Figures 2 to 8 As shown, the address identification unit 5 includes an I / O expander chip, which is mounted on the function board and connected to the management controller 2. The I / O expander chip is used to receive level signals from the motherboard MB; wherein, the level signals include the identification information of the processing unit and the port identification information of the bus interface.

[0090] For example, the input of the IO expander chip is connected to the address signal line on the server motherboard to receive CPU address and VPP address level signals (high level is 1, low level is 0) from the motherboard.

[0091] The chip communicates with the management controller 2 (BMC) via the I2C bus, converting the received analog level signals into digital information and storing it in its internal registers. The management controller 2 can obtain the CPU serial number and PCIe port identification information by sending a read command via the I2C bus. The IO expander chip has anti-interference capabilities, effectively filtering noise during the transmission of level signals to avoid address information errors; it also supports long-distance signal transmission, adapting to cable connection scenarios between server motherboards and function boards.

[0092] The IO expander chip communicates with the management controller 2 via the I2C bus. Its input terminal is connected to the address signal line of the server motherboard, receiving the CPU address and VPP address level signals from the motherboard, converting them into digital information, and transmitting them to the management controller 2 for configuration information matching.

[0093] I / O expander chips, such as the PCA9555 or PCA9548, are industry-standard devices that are compatible with the signal level standards of mainstream server platforms such as Intel and AMD. They can be directly ported to servers with different architectures, improving the portability and versatility of the technical solution.

[0094] The chip's input terminals (Addr0-Addr2 / Addr3) are connected to the CPU address and VPP address signal lines on the motherboard, receiving level signals (high level = 1, low level = 0) transmitted from the motherboard. The chip communicates with the Business Controller 2 (BMC) via the I2C bus, supporting transmission rates of 100Kbps / 400Kbps to ensure fast address information transmission. The chip converts the received analog level signals into digital signals and stores them in its internal registers. The Business Controller 2 can obtain the CPU serial number and PCIe port identification information by sending read commands via the I2C bus.

[0095] The I / O expander chip possesses anti-interference capabilities, effectively filtering noise during level signal transmission to prevent address information errors and ensure accurate configuration matching. Simultaneously, the chip supports long-distance signal transmission, adapting to cable connection scenarios between server motherboards and function boards (such as a riser card connected to the motherboard via a high-speed cable). A single I / O expander chip can support the acquisition and transmission of multiple address signals (e.g., the PCA9555 supports 16 I / O inputs), eliminating the need for independent transmission circuits for each address signal, significantly reducing PCB routing space on the motherboard and function boards, and simplifying layout.

[0096] In some embodiments, the selection unit 4 is used to generate a mode selection signal to control the configuration reading path of the management controller 2.

[0097] Selection unit 4 is used to generate a mode selection signal to control the configuration read path of management controller 2. Selection unit 4 includes at least two optional forms: hardware DIP switches and software programmable registers.

[0098] For example, the selection unit 4 includes a hardware DIP switch, which is connected to the management controller 2 and is used to generate a hardware level signal representing a first mode or a second mode as a mode selection signal.

[0099] This method provides the reliability of physical isolation, is suitable for environments with extremely high requirements for configuration stability, has a fast response speed, and requires no software intervention.

[0100] For example, such as Figure 2 As shown, the hardware DIP switch, as a small physical switch component, is directly connected to the server motherboard MB. Its output is connected to the SEL_GPIO pin of the management controller 2, providing physical isolation and reliability, which is suitable for production environments with extremely high requirements for configuration stability.

[0101] At the same time, high and low level signals are generated through the DIP switch state. For example, when the DIP switch is closed, a low level (0) is output, representing the first mode (centralized); when the DIP switch is open, a high level (1) is output, representing the second mode (distributed). The first memory or the second memory can be selected accordingly. The signal transmission does not require software relay, the response speed is fast, and no software intervention is required, which is suitable for scenarios without remote management requirements.

[0102] For example, the selection unit 4 includes a software programmable register, which is located inside the management controller 2 and is used to store and modify the value representing the first mode or the second mode as a mode selection signal via software instructions.

[0103] The software programmable register is integrated inside the management controller 2. It is used to store and modify the value representing the first mode or the second mode through software instructions as a mode selection signal. It supports remote modification through IPMI instructions and BMC web interface, and has write protection function. When write protection is enabled, the mode selection is locked to prevent accidental operation and facilitate automated operation and maintenance and rapid switching.

[0104] In some embodiments, such as Figures 2 to 8 As shown, the dynamic bandwidth allocation system also includes a first communication bus and a second communication bus. The management controller 2 is used to access the first memory or the second memory through the first communication bus, and to provide the link bandwidth configuration information to the processing unit 1 in the early stage of the power-on self-test performed by the processing unit 1 through the second communication bus.

[0105] For example, the first communication bus is an I2C bus. The management controller 2 accesses the first memory (EEPROM on the motherboard) and the second memory (EEPROM on the function board) via the I2C bus, and simultaneously reads the address information of the address identification unit 5 (IO expander chip). The I2C bus supports communication between multiple master devices and multiple slave devices, distinguishing different memory units and address identification units through device addresses. The transmission rate can be configured to standard mode (e.g., 100Kbps) or fast mode (e.g., 400Kbps).

[0106] For example, the second communication bus is an eSPI bus. The management controller 2 transmits the link bandwidth configuration information to the processing unit 1 (CPU) via the eSPI bus. The bus rate is up to 1Gbps and the latency is as low as microseconds. It can quickly complete the transmission of configuration information during the PEI stage (early initialization stage) of the server POST and provide the link bandwidth configuration information to the processing unit 1 without affecting the system startup speed.

[0107] The I2C bus is mature, stable, and simple to wire, making it suitable for short-distance transmission of configuration and address information, meeting the communication needs of storage units and address identification units. The eSPI bus boasts high speed and low latency, solving the configuration transmission time problem caused by the low transmission rate of the traditional LPC bus. It ensures that configuration information is transmitted in the early stages of POST, allowing processing unit 1 to obtain configuration information in a timely manner, complete bandwidth initialization, and not affect system startup speed. Both I2C and eSPI are standardized buses in the server field, natively supported by most server CPUs, BMCs, EEPROMs, and IO expander chips, eliminating the need for additional dedicated communication chips and reducing hardware modification costs. The multi-slave design of the I2C bus allows management controller 2 to communicate with multiple secondary memories and address identification units 5 simultaneously without polling and waiting one by one, improving the efficiency of configuration information acquisition and adapting to scenarios where multi-functional boards are connected simultaneously.

[0108] In some embodiments, the management controller 2 is configured to allocate a first default bandwidth configuration to a target high-speed interconnect bus interface 11 if its complete port identification information cannot be matched from any functional board. In other embodiments, the management controller 2 is configured to allocate a second default bandwidth configuration to the link corresponding to the unmatched portion of the port identification information if only a portion of the port identification information of a target high-speed interconnect bus interface is matched.

[0109] When the management controller 2 retrieves the configuration from the second memory, it executes the default bandwidth allocation logic. Specifically, the management controller 2 first determines whether the two CPU and VPP addresses corresponding to the PCIe port in the bandwidth register have appeared during the polling of all boards' PCA9555 / 9554. If neither the CPU address nor the VPP address corresponding to a target high-speed interconnect bus interface 11 (PCIe port) has been polled (i.e., neither of the two octets of the port is matched / connected to any functional board or is a direct connection to an OCP card), the management controller 2 writes both the high octets and low octets of bandwidth information to 10, thus allocating a x16 full bandwidth configuration (first default bandwidth configuration). If only part of the port identification information is matched (i.e., the PCIe port is only connected to some functional boards, such as the high octets connected and the low octets not connected), the management controller 2 writes the byte of bandwidth information corresponding to the missing octets to 01, thus allocating a x8 bandwidth configuration (second default bandwidth configuration) to the unmatched part. If both octets appear, then directly fill in the configuration in their respective second memory.

[0110] Next, management controller 2 right-shifts the lower eight bits of the bandwidth information by two bits and performs an OR operation with the higher eight bits of the bandwidth information. The result is then filled into the byte containing the complete bandwidth information for final CPU use. This logic is implemented based on a truth table, covering all commonly used bandwidth allocation topologies, and requires no additional customization for the x8x2x2x2x2 allocation method. In floating mode, it allocates the maximum bandwidth by default.

[0111] This design avoids PCIe ports from malfunctioning due to missing function boards or configuration information, ensuring that the server can maintain basic functions even when some devices are not connected, thus improving system fault tolerance.

[0112] The default configuration can adopt the maximum available bandwidth principle. The default bandwidth of x16 or x8 can meet the needs of most basic services without requiring manual configuration by the user. This avoids wasting bandwidth resources and solves the unreasonable design of disabling ports without configuration in the past. For special scenarios such as direct connection to OCP cards and access of some devices, users do not need to configure bandwidth additionally. The management controller automatically allocates the default bandwidth, reducing the operational complexity of maintenance personnel and improving maintenance efficiency.

[0113] In complex server architectures with multiple CPUs and multiple PCIe ports, configuration misalignment can easily occur without address identification (for example, misassigning information that should be configured for CPU0 port 0 to CPU1 port 1). This embodiment defines the CPU address and VPP address directly through hardware level signals, establishing a unique correspondence between the board and the CPU port at the lowest physical level, fundamentally eliminating the possibility of configuration misalignment.

[0114] The default bandwidth allocation logic ensures that even if some cards are not inserted or some cables are not connected, the system can still allocate reasonable bandwidth (x16 or x8) to the missing links, thus guaranteeing that the system can start and run normally, rather than directly disabling ports and causing failures. This is of great value for rapid deployment, troubleshooting, and hot-swapping scenarios in data centers.

[0115] I / O expander chips are industry-standard devices that are low-cost and compatible with multiple platforms. Through a unified address recognition circuit design, there is no need to customize dedicated recognition hardware for different platforms or different numbers of ports, significantly reducing the engineering investment required for solution porting and adaptation.

[0116] When replacing or adding functional boards, simply connect the address signal lines correctly to the input terminals of the new board's I / O expander chip and write the matching configuration information into its EEPROM. The management controller will then automatically recognize and match the new board. No modifications to the motherboard wiring or management controller firmware are required, significantly reducing the complexity and error probability of system maintenance.

[0117] In some embodiments, the management controller 2 is further configured to, in response to a configuration update instruction, release the write protection state of the configuration storage unit 3, write the updated link bandwidth configuration information into the configuration storage unit 3, and restore the write protection state of the configuration storage unit 3 after the writing is completed.

[0118] Meanwhile, the management controller 2 is also used to perform key verification on the received update data in response to the configuration update command, and after the key verification is successful, to remove the write protection state of the configuration storage unit and perform a write operation.

[0119] The management controller 2 has an internal key register for storing decryption keys. Encryption keys are also stored in the first and second memories. Uploaded configuration files (bin files) must contain encrypted information matching the memory keys. When the bin file is read into the BMC's DRAM via BMC Web or IPMI commands, the BMC verifies the encryption register against its decryption register. Only after successful verification can write protection deactivation and write operations proceed.

[0120] The specific steps for removing and restoring write protection are as follows: For the first memory, the BMC pulls the WP pin of U4 high to remove write protection; after the write is completed, the BMC pulls the WP pin of U4 low to restore write protection.

[0121] For the second memory, the BMC accesses U9 (PCA9555) via an I2C switch, writes U9 IO0_0_0 PIN to 1, thereby removing the write protection of U6; after the write is completed, it writes U9 IO0_0_0 PIN to 0, restoring the write protection.

[0122] No server restart is required after the configuration update is complete. The new configuration will take effect the next time the system is powered on or when the configuration is reloaded via IPMI commands.

[0123] The key verification mechanism ensures that only authorized personnel with the correct key can write configuration files to the configuration storage unit. Even if an attacker gains network access to the management controller, they cannot successfully update the configuration without the key.

[0124] During production or maintenance, operations and maintenance personnel may mistakenly select the wrong configuration file. Key verification will automatically block mismatched files before writing, preventing system configuration corruption due to human error.

[0125] Each failed verification is logged in the system event log for easy auditing and tracing of abnormal operations. Successful update operations also leave traceable log records, meeting the security compliance requirements of the data center.

[0126] The configuration update process does not require a server restart (the update only affects the next power-on), and running services are unaffected, improving system availability. Both bin file and IPMI command methods cater to the operating habits of both ordinary users and professional operations and maintenance personnel, simplifying the batch configuration management process for multiple servers. In some embodiments, both the first and second memories have write-protect pins (WP). The management controller is connected to the write-protect pin via a general-purpose input / output (GPIO) interface. The management controller 2 is configured to output a write-protect signal (e.g., pull WP high) via the GPIO interface when updated link bandwidth configuration information needs to be written to the first or second memory; and to output a write-protect signal (e.g., pull WP low) after the write operation is complete.

[0127] For example, users can upload configuration files (bin format) through the BMC web interface or send IPMI commands to trigger the configuration update process; the management controller 2 has a built-in key register, and the uploaded configuration files must contain encrypted information. The write operation can only be performed after the key is verified to prevent malicious configuration injection.

[0128] Management controller 2 controls the write protection status (WP signal) of configuration storage unit 3 via GPIO pins or I2C bus. During an update, the WP signal is pulled high to release write protection, and after the write is complete, the WP signal is pulled low to lock the configuration. After the configuration update is completed, there is no need to restart the server. Management controller 2 uses the updated configuration information the next time the system powers on or when the configuration is reloaded via IPMI commands, improving the convenience of operation and maintenance.

[0129] This design enables the dynamic bandwidth allocation system in this embodiment to remotely and online update configurations without physical contact with the server, adapting to the operational needs of large-scale server clusters. Both bin files and IPMI commands are supported, catering to the operating habits of both ordinary users and professional maintenance personnel. Dual protection, including key verification and write protection, prevents configuration files from being tampered with or accidentally written, ensuring the security and integrity of the configuration update process. New configurations take effect without restarting the server, avoiding service interruptions due to configuration updates and improving server availability. Furthermore, the unified configuration update interface simplifies the batch configuration management process across multiple servers.

[0130] Centralized storage (first storage) is suitable for scenarios with fixed server configurations and a single type of equipment, offering unified and convenient configuration management. Distributed storage (second storage) is suitable for scenarios with flexible combinations of multiple devices in a decoupled architecture. Each functional card comes with its own configuration, eliminating the need to reconfigure the motherboard when replacing cards, thus avoiding the "multi-device configuration conflict" problem that may occur with centralized storage. The coexistence of these two modes allows a single hardware platform to cover all scenarios from low-end fixed configurations to high-end decoupled architectures.

[0131] Distributed storage allows the same functional board to adapt to different bandwidth requirements by modifying its onboard EEPROM content, eliminating the need to design multiple hardware boards for each bandwidth requirement. This significantly reduces the number of board types and lowers R&D, production, and material management costs. When adding a new functional board, only the corresponding configuration information needs to be written to the second memory, and the management controller 2 can automatically match it through the address recognition unit, without modifying the motherboard hardware or management controller software, achieving plug-and-play modular expansion.

[0132] Write protection pins, combined with GPIO control of the management controller, ensure that configuration information can only be modified under authorized and verified instructions. Write protection is always enabled during normal operation, preventing tampering with the contents of the configuration memory unit even in the event of software errors or malicious attacks, thus guaranteeing system configuration security at the hardware level.

[0133] The multi-slave design of the I2C bus allows the management controller 2 to communicate simultaneously with multiple secondary memories and address identification units 5 without polling them one by one, thus improving the efficiency of configuration information acquisition. Furthermore, both I2C and eSPI are standardized buses in the server field, natively supported by the vast majority of server CPUs, BMCs, EEPROMs, and IO expander chips, eliminating the need for additional dedicated communication chips and reducing hardware modification costs.

[0134] In some embodiments, updating bifurcation information (link bandwidth configuration information) in the first memory is taken as an example.

[0135] The bin file to be written to the first memory is read into the BMC's DRAM via BMC web or IPMI commands, and its encryption register is verified against the BMC's decryption register. Upon successful verification, the BMC pulls the WP pin of the first memory high, disabling write protection. The I2C channel connected to the first memory by the BMC executes a sequential write command operation on address 1001_111 (0x4F), updating the bifurcation information stored in the first memory. After the update is complete, the first memory sends a completion command to the BMC. Upon receiving this command, the BMC pulls the WP pin of the first memory low, enabling write protection.

[0136] Unlike the first memory, the size of the bifurcation register in the second memory depends on the maximum number of PCIe ports that the board can actually adapt to. For every half PCIe port that can be adapted, the register will have three more bytes.

[0137] like Figure 12 As shown, the new information corresponding to the three-byte register for each half of the PCIe port is the I2C address of the PCA9555 / 9554, the read instruction for input port 0 / 1, and the bifurcation information corresponding to these eight bits.

[0138] Combination Figures 2 to 8 The BMC first reads the information from port 0 / 1 of the PCA9555 / 9554 connected to the CPU and VPP addr, then reads the information from the second memory and compares the two. For the portions where the 9555 / 9554 address and the read command of the input port match, it performs a matching operation on the CPU addr & VPP addr – the eight-bit bifurcation information – and fills the matching result into the BMC's bifurcation register. Similarly, U4 internally contains a 1-byte key for encryption; all data read from U4 needs to be added to this key.

[0139] When reading link bandwidth configuration information from the second memory, there may be situations where all or half of the downlink cards for certain PCIe ports are not present, making it impossible to read complete bifurcation information. Special logic processing is required for this situation. The BMC first checks whether the two CPU & VPP addrs corresponding to the PCIe port in the bifurcation register have appeared during the polling of all PCA9555 / 9554 cards. If neither has appeared, it means that the PCIe port is not connected to any card or has a direct connection to an OCP, and the bytes storing the high and low eight bits of bifurcation information are both written to 10, i.e., configured as x16. If one appears, it means that the other eight bits of the PCIe port are not connected to any card or have a direct connection to an OCP, and the bytes corresponding to the missing eight bits of bifurcation information are written to 01, i.e., configured as x8. If both appear, they are filled directly.

[0140] For example, taking updating the bifurcation information (link bandwidth configuration information) in the second memory as an example, the bin file to be written to the second memory is first read into the BMC's DRAM via BMC web or IPMI commands, and the encrypted register in it is verified against the BMC's decryption register. After successful verification, the BMC accesses U9 via the I2C switch and writes the U9IO0_0_0 PIN to 1, disabling write protection. The BMC then executes a sequential write command operation on address 1001_011 (0x4B) via the I2C switch to update the bifurcation information stored in the second memory. After the update is completed, the second memory sends a completion command to the BMC. Upon receiving the command, the BMC writes the U9 IO0_0_0 PIN to 0, enabling write protection.

[0141] The above embodiments are all based on the truth table in Table 4, covering commonly used bandwidth allocation topologies. There is no need to make special bandwidth customization for the x8x2x2x2x2 allocation method, and the maximum bandwidth is allocated by default in the floating state. There is no need to make special bandwidth customization for the case of direct cable connection to the OCP card.

[0142] Table 4

[0143] Embodiments of this disclosure also provide a dynamic bandwidth allocation method, which is applied to a server.

[0144] In some embodiments, the dynamic bandwidth allocation method includes: S1, Management Controller 2 responds to the server power-on and acquires the mode selection signal.

[0145] Specifically, the BMC reads the hardware DIP switch status through the SEL_GPIO pin or reads the value of the internal software programmable register to obtain the mode selection signal and determine the configuration read path (read the first memory or the second memory).

[0146] S2, the management controller 2 obtains the link bandwidth configuration information of at least one high-speed interconnect bus interface 11 from the configuration storage unit 3 based on the mode selection signal.

[0147] In the first mode, the BMC accesses the first memory via the I2C bus, reads the full bifurcation information, decrypts it with a key, and writes it to its own bifurcation register. In the second mode, the BMC polls the address identification unit 5 (IO expander chip) of each functional board via the I2C switch to obtain the CPU address and VPP address, then accesses the corresponding second memory to read the bifurcation information, writes it to the bifurcation register after matching, and allocates default bandwidth to the ports with missing configurations.

[0148] S3. The management controller 2 provides the link bandwidth configuration information to the processing unit 1 so that the processing unit 1 can configure the link bandwidth of the corresponding high-speed interconnect bus interface 11 according to the link bandwidth configuration information.

[0149] During the PEI phase of POST in processing unit 1, the BMC transmits the complete link bandwidth configuration information in the bifurcation register to the CPU via the eSPI bus. After receiving the configuration information, the CPU configures the link bandwidth (such as x16, x8x8, etc.) of the corresponding PCIe root port through the built-in bifurcation signal processing module, and completes the link training in the DXE phase to ensure that the bandwidth configuration takes effect.

[0150] In summary, the dynamic bandwidth allocation method provided in this embodiment follows a logical sequence of "power-on - identification - configuration - activation." The execution timing and data transmission path of each step are clearly defined, avoiding a chaotic configuration process and ensuring the accuracy and reliability of bandwidth configuration. From mode selection and configuration reading to bandwidth configuration, the entire process requires no manual operation, solving the cumbersome process of traditional bandwidth configuration that requires manual hardware adjustments or BIOS parameter modifications, thus improving server deployment and maintenance efficiency. The method is compatible with both centralized and distributed configuration storage modes, supports multiple platforms and server architectures, and can be ported to various servers. It synergizes with the hardware design of the dynamic bandwidth allocation system to maximize its technological value.

[0151] In some embodiments, obtaining link bandwidth configuration information of at least one high-speed interconnect bus interface 11 from the configuration storage unit 3 based on the mode selection signal includes: S21. When the mode selection signal indicates the first mode, the management controller 2 obtains the link bandwidth configuration information from the first memory set on the motherboard.

[0152] S22. When the mode selection signal indicates the second mode, the management controller 2 obtains link bandwidth configuration information from at least one second memory located on the function board.

[0153] In some embodiments, when the mode selection signal indicates a second mode, the dynamic bandwidth allocation method further includes: The management controller reads the identification information of the processing unit and the port identification information of the bus interface from the address identification unit set on the function board; The management controller will associate and match the identification information and port identification information it reads with the link bandwidth configuration information read from the corresponding second memory.

[0154] In some embodiments, the dynamic bandwidth allocation method further includes: When no complete port identification information is found for a target high-speed interconnect bus interface, the management controller assigns a first default bandwidth configuration to the target high-speed interconnect bus interface.

[0155] In some embodiments, the dynamic bandwidth allocation method further includes: When only part of the port identification information is matched for a target high-speed interconnect bus interface, the management controller allocates a second default bandwidth configuration to the links corresponding to the unmatched parts.

[0156] In some embodiments, the dynamic bandwidth allocation method further includes: In response to the configuration update command, the management controller performs key verification on the received update data. Only after the key verification is successful will the write protection status of the configuration storage unit be removed and the write operation be performed.

[0157] The beneficial technical effects of the above-mentioned dynamic bandwidth allocation method can be found in the previous description of the dynamic bandwidth allocation system, and will not be repeated here.

[0158] In summary, the dynamic bandwidth allocation method provided in some embodiments of this disclosure follows the logical sequence of "power-on → identification → acquisition → configuration". Each step is automatically completed by the management controller, without the need for manual jumper settings, BIOS option modifications, or additional software installation, thus achieving complete automation of bandwidth allocation.

[0159] By using mode selection signals, this method is compatible with both centralized and distributed storage configurations. It is suitable for both traditional fixed-configuration servers and scenarios with flexible combinations of multiple devices in a decoupled architecture, demonstrating good platform adaptability.

[0160] The default bandwidth allocation procedure ensures that the system can still obtain effective bandwidth configuration and start normally even in the event of missing cards or configurations, which significantly improves the system's fault tolerance and deployment flexibility.

[0161] The configuration update and key verification steps enable operations and maintenance personnel to remotely and securely modify bandwidth allocation schemes without downtime or hardware replacement, significantly improving the maintainability of large-scale clusters.

[0162] Compared to technical solutions where bandwidth configuration is fixed by hardware pull-up and pull-down resistors, requiring the design of multiple boards for different bandwidth requirements, leading to wasted R&D resources and soaring maintenance costs, the dynamic bandwidth allocation system provided in this disclosure stores configuration information in EEPROM. Multi-level bandwidth configuration can be achieved through software modification without hardware changes, significantly reducing the types of boards and lowering R&D, production, and modification costs.

[0163] Server decoupled architecture requires independent separation and combination of modules such as memory, computing, and IO. The dynamic bandwidth allocation system provided in this disclosure adopts a "centralized + distributed" dual storage design, which supports both simple configuration of a single device and distributed configuration of multiple devices. It is perfectly compatible with devices with different connection media such as Riser cards and backplanes, and meets the diverse needs of heterogeneous computing scenarios.

[0164] After the server is powered on, the management controller 2 automatically starts the configuration process and quickly transmits configuration information through a standardized bus. The processing unit 1 completes the bandwidth configuration in the early stage of POST without manual intervention, which improves the configuration efficiency. At the same time, the write protection of the configuration storage unit and the key verification mechanism of the management controller prevent the configuration from being maliciously tampered with and ensure the stability of system operation.

[0165] Processing Unit 1 is compatible with a variety of different server platforms and supports different architectures such as single-socket, dual-socket, quad-socket, and eight-socket. Its standardized design for storage units and management controllers makes it portable to various electronic devices involving bandwidth allocation, such as PCs and laptops, significantly expanding the application scenarios of the technology.

[0166] Embodiments of this disclosure also provide an electronic device including a memory and a processor, the memory storing a computer program, the processor being configured to run the computer program to perform the steps in any of the above embodiments of the dynamic bandwidth allocation method.

[0167] The processor can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a complex programmable logic device (CPLD). The processor can also adopt a multi-core architecture.

[0168] Embodiments of this disclosure also provide a computer-readable storage medium storing a computer program configured to execute the steps in any of the above-described embodiments of the dynamic bandwidth allocation method when run.

[0169] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0170] Embodiments of this disclosure also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described embodiments of the dynamic bandwidth allocation method.

[0171] Embodiments of this disclosure also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described embodiments of the dynamic bandwidth allocation method.

[0172] The above embodiments encapsulate the same technical logic as the method described above into an executable program, enabling the method to be deployed and distributed as software on various hardware platforms. This reduces the device dependency of the solution implementation; any electronic device with basic computing capabilities can obtain dynamic bandwidth allocation capabilities by loading the program. It facilitates version management and batch updates, allowing functional upgrades to be achieved by distributing new program versions. It aligns with the software-defined hardware trend of modern data center automated operation and maintenance, providing a standardized carrier for large-scale deployment.

[0173] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0174] The foregoing has provided a detailed description of a dynamic bandwidth allocation system, server, and method. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of these embodiments are only intended to aid in understanding the method and core ideas of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications to this disclosure without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this disclosure.

Claims

1. A dynamic bandwidth allocation system, characterized in that, Applied to electronic devices; the dynamic bandwidth allocation system includes: a processing unit, a management controller, a configuration storage unit, and a selection unit; The processing unit has at least one high-speed interconnect bus interface; The management controller is communicatively connected to the processing unit; The configuration storage unit is communicatively connected to the management controller; The selection unit is used to generate a mode selection signal; The configuration storage unit is used to store link bandwidth configuration information for at least one of the high-speed interconnect bus interfaces; The management controller is used to respond to the power-on of the server, obtain the corresponding link bandwidth configuration information from the configuration storage unit based on the mode selection signal, and provide the link bandwidth configuration information to the processing unit; The processing unit is used to configure the link bandwidth of the corresponding high-speed interconnect bus interface according to the link bandwidth configuration information.

2. The dynamic bandwidth allocation system according to claim 1, characterized in that, The configuration storage unit includes a first memory and at least one second memory; The first memory is located on the motherboard of the server; The at least one second memory is disposed on the functional board of the server; The mode selection signal is used to instruct the management controller to obtain the link bandwidth configuration information from the first memory or from the at least one second memory.

3. The dynamic bandwidth allocation system according to claim 2, characterized in that, When the mode selection signal indicates that configuration information is retrieved from the at least one second memory, the dynamic bandwidth allocation system further includes: The address recognition unit is mounted on the function board and connected to the management controller; The address identification unit is used to provide the identification information of the processing unit to which the function board is connected and the port identification information of the bus interface.

4. The dynamic bandwidth allocation system according to claim 3, characterized in that, The management controller is also used to read the identification information of the processing unit and the port identification information of the bus interface from the address identification unit, and associate and match them with the link bandwidth configuration information read from the corresponding second memory.

5. The dynamic bandwidth allocation system according to claim 3 or 4, characterized in that, The address recognition unit includes: An IO expander chip is mounted on the function board and connected to the management controller; The I / O expander chip is used to receive level signals from the motherboard; wherein the level signals include the identification information of the processing unit and the port identification information of the bus interface.

6. The dynamic bandwidth allocation system according to claim 5, characterized in that, The input terminal of the IO expander chip is connected to the address signal line on the server motherboard.

7. The dynamic bandwidth allocation system according to claim 1, characterized in that, The selection unit includes: A hardware DIP switch is connected to the management controller; the hardware DIP switch is used to generate a hardware level signal representing a first mode or a second mode as the mode selection signal.

8. The dynamic bandwidth allocation system according to claim 1, characterized in that, The selection unit includes: A software-programmable register is located inside the management controller; the software-programmable register is used to store and modify, via software instructions, a value representing the first mode or the second mode as the mode selection signal.

9. The dynamic bandwidth allocation system according to claim 2, characterized in that, The dynamic bandwidth allocation system also includes a first communication bus and a second communication bus; The management controller is used to access the first memory or the second memory through the first communication bus, and to provide the link bandwidth configuration information to the processing unit in the early stage of the power-on self-test performed by the processing unit through the second communication bus.

10. The dynamic bandwidth allocation system according to claim 3, characterized in that, The management controller is configured to assign a first default bandwidth configuration to a target high-speed interconnect bus interface if, for a target high-speed interconnect bus interface, its complete port identification information cannot be matched from any of the function boards.

11. The dynamic bandwidth allocation system according to claim 3, characterized in that, The management controller is used to allocate a second default bandwidth configuration to the links corresponding to the unmatched port identification information when only a portion of the port identification information of a target high-speed interconnect bus interface is matched.

12. The dynamic bandwidth allocation system according to claim 1, characterized in that, The management controller is further configured to, in response to a configuration update instruction, release the write protection state of the configuration storage unit, write the updated link bandwidth configuration information into the configuration storage unit, and restore the write protection state of the configuration storage unit after the writing is completed.

13. The dynamic bandwidth allocation system according to claim 12, characterized in that, The management controller is also configured to, in response to a configuration update command, perform key verification on the received update data, and, after the key verification is successful, release the write protection state of the configuration storage unit and perform a write operation.

14. The dynamic bandwidth allocation system according to claim 2 or 12, characterized in that, Both the first memory and the second memory have write-protect pins; The management controller is connected to the write-protect pin via a general-purpose input / output interface; The management controller is configured to output a write-protection signal via the general-purpose input / output interface when it is necessary to write updated link bandwidth configuration information to the first memory or the second memory; and to output a write-protection recovery signal after the write is completed.

15. A server, characterized in that, include: The dynamic bandwidth allocation system as described in any one of claims 1 to 14.

16. A dynamic bandwidth allocation method, characterized in that, Applied to servers, the dynamic bandwidth allocation method includes: The management controller responds to the server powering on by acquiring a mode selection signal; Based on the mode selection signal, the management controller obtains the link bandwidth configuration information of at least one high-speed interconnect bus interface from the configuration storage unit; The management controller provides the link bandwidth configuration information to the processing unit, so that the processing unit can configure the link bandwidth of the corresponding high-speed interconnect bus interface according to the link bandwidth configuration information.

17. The dynamic bandwidth allocation method according to claim 16, characterized in that, The step of obtaining link bandwidth configuration information for at least one high-speed interconnect bus interface from the configuration storage unit based on the mode selection signal includes: When the mode selection signal indicates the first mode, the management controller obtains the link bandwidth configuration information from the first memory located on the motherboard; When the mode selection signal indicates the second mode, the management controller obtains the link bandwidth configuration information from at least one second memory located on the function board.

18. The dynamic bandwidth allocation method according to claim 17, characterized in that, When the mode selection signal indicates the second mode, the dynamic bandwidth allocation method further includes: The management controller reads the identification information of the processing unit and the port identification information of the bus interface from the address identification unit set on the function board; The management controller will read the identification information and port identification information and match them with the link bandwidth configuration information read from the corresponding second memory.

19. The dynamic bandwidth allocation method according to claim 18, characterized in that, The dynamic bandwidth allocation method further includes: When a complete port identification information cannot be matched for a target high-speed interconnect bus interface, the management controller assigns a first default bandwidth configuration to the target high-speed interconnect bus interface.

20. The dynamic bandwidth allocation method according to claim 18, characterized in that, The dynamic bandwidth allocation method further includes: When only part of the port identification information is matched for a target high-speed interconnect bus interface, the management controller allocates a second default bandwidth configuration to the links corresponding to the unmatched parts.

21. The dynamic bandwidth allocation method according to claim 16, characterized in that, The dynamic bandwidth allocation method further includes: In response to a configuration update command, the management controller performs key verification on the received update data. Only after the key verification is successful does it release the write protection state of the configuration storage unit and perform a write operation.

22. A server, characterized in that, include: Memory, used to store computer programs; A processor for executing a computer program to implement the steps of the dynamic bandwidth allocation method as described in any one of claims 16-21.

23. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program; When the computer program is executed by the processor, it implements the steps of the dynamic bandwidth allocation method as described in any one of claims 16-21.

24. A computer program product, characterized in that, include: A computer program, when executed by a processor, implements the steps of the dynamic bandwidth allocation method as described in any one of claims 16-21.

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