An electronic load, device, and apparatus

Abstract

This application provides an electronic load, apparatus, and device. The electronic load includes a first load unit. The first load unit includes a processing module and a sampling module. The processing module processes an input signal and outputs a first control signal. A first module of the processing module is electrically connected to a first input terminal of the processing module. The sampling module samples a signal under test. The control terminal of the sampling module is electrically connected to the output terminal of the processing module, the input terminal of the sampling module is electrically connected to the power supply under test, the output terminal of the sampling module is grounded, and the sampling module is also electrically connected to a second input terminal of the processing module. The sampling signal of the sampling module is related to the first control signal and is also related to the power signal of the power supply under test. This application aims to improve the accuracy of the verification results of the power supply under test.

Description

Technical Field

[0001] This application relates to the field of chip verification, and more particularly to an electronic load, device, and apparatus. Background Technology

[0002] In chip design, chip performance verification is crucial. Typically, EDA software is used to simulate and obtain the required current, voltage, and related slope parameters for the chip. Hardware designers then use these electrical parameters to perform EVB (Electronic Power Controller) design and conduct current and voltage tests using electronic loads. However, existing electronic loads are typically large, box-type devices, and using such loads for power supply testing can lead to inaccurate results. Summary of the Invention

[0003] In view of this, embodiments of this application provide an electronic load, apparatus, and device, which aim to improve the accuracy of the verification results of the power supply under test.

[0004] In a first aspect, embodiments of this application provide an electronic load, including: a first load unit. The first load unit includes: a processing module and a sampling module. The processing module is used to process an input signal and output a first control signal. A first module of the processing module is electrically connected to a first input terminal of the processing module. The sampling module is used to sample a signal under test. The control terminal of the sampling module is electrically connected to the output terminal of the processing module, the input terminal of the sampling module is electrically connected to the power supply under test, the output terminal of the sampling module is grounded, and the sampling module is also electrically connected to a second input terminal of the processing module. The sampling signal of the sampling module is related to the first control signal, and the sampling signal of the sampling module is related to the power supply signal of the power supply under test.

[0005] In this embodiment, the processing module converts the input signal into a first control signal. The first control signal controls the sampling module. The sampling signal of the sampling module is related to the first control signal and also to the power signal of the power supply under test. Therefore, the sampling signal can be used to determine whether the power signal meets the design expectations. Thus, this embodiment of the application can verify the working performance of the power supply under test through the processing module and the sampling module, which helps to reduce the noise and power consumption generated by the electronic load, thereby improving the accuracy of the verification results of the power supply under test.

[0006] In one possible implementation of the first aspect, the electronic load is integrated on a PCB.

[0007] In this implementation, the electronic load is integrated onto the PCB, which helps reduce its size and thus shortens the connection between the electronic load and the power supply under test. Shortening the connection reduces parasitic parameters, thereby improving the accuracy of the verification results.

[0008] In one possible implementation of the first aspect, the shape of the PCB where the electronic load is located is the same as the shape of the chip to be verified, and the size of the PCB where the electronic load is located is the same as the size of the chip to be verified.

[0009] In this implementation, the shape and size of the PCB are the same as those of the chip to be verified, which can better simulate the verification environment of the chip to be verified, thereby improving the accuracy of the verification results of the power supply under test.

[0010] In one possible implementation of the first aspect, the PCB containing the electronic load is electrically connected to the power supply under test via an external wire, the length of which is less than a preset threshold.

[0011] In this implementation, the length of the connecting line is less than a preset threshold, which can reduce the adverse effects of parasitic parameters generated by the connecting line on the verification results of the power supply under test, thereby improving the accuracy of the verification results of the power supply under test.

[0012] In one possible implementation of the first aspect, the processing module includes: an operational amplifier and a power conversion circuit; a first input terminal of the operational amplifier is a first input terminal of the processing module; a second input terminal of the operational amplifier is a second input terminal of the processing module; the output terminal of the operational amplifier is electrically connected to the input terminal of the power conversion module, and the output terminal of the power conversion module is the output terminal of the processing module.

[0013] In this implementation, the operational amplifier amplifies the input signal, and the power conversion circuit converts the input signal into a first control signal with driving capability. This first control signal controls the acquisition module's acquisition signal, ultimately enabling the determination of whether the performance of the power supply under test meets design expectations based on the acquired signal.

[0014] In one possible implementation of the first aspect, the sampling module includes: a first transistor and a sampling resistor; the control terminal of the first transistor is the control terminal of the sampling module, the first terminal of the first transistor is the input terminal of the sampling module, the second terminal of the first transistor is electrically connected to the first terminal of the sampling resistor, and the second terminal of the sampling resistor is the output terminal of the sampling module.

[0015] In this implementation, the first control signal controls the first transistor to operate in the linear amplification region. When the first transistor operates in the linear amplification region, its internal channel resistance is variable, and therefore the current flowing through its channel is also variable. This makes the current flowing through the first transistor controllable.

[0016] In one possible implementation of the first aspect, a feedback module is also included, wherein the sampling module is electrically connected to the second input terminal of the processing module through the feedback module.

[0017] The negative feedback module is used to make the output signal of the processing module more stable.

[0018] Secondly, embodiments of this application also provide a chip verification apparatus, which includes the electronic load provided in the first aspect.

[0019] The chip verification apparatus provided in this application can improve the accuracy of the verification results of the power supply under test.

[0020] In one possible implementation of the second aspect, the chip verification apparatus further includes the power supply under test.

[0021] The chip verification device includes a power supply under test, which facilitates integration, thereby reducing parasitic parameters and improving the accuracy of the verification structure of the power supply under test.

[0022] Thirdly, embodiments of this application also provide an apparatus, the apparatus including the electronic load provided in the first aspect.

[0023] In this embodiment, the processing module converts the input signal into a first control signal capable of driving the sampling module. The sampling signal is related to the first control signal and also to the power signal of the power supply under test (UTP). Therefore, changing the input signal can change the sampling signal, and the sampling signal can be used to determine whether the power signal of the UTP meets expectations. Thus, this embodiment can verify the performance of the UTP using only the processing module and the sampling module, which helps reduce noise and power consumption generated by the electronic load, thereby improving the accuracy of the UTP verification results. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of an electronic load provided for an embodiment of this application; Figure 2 A schematic diagram of a first load unit provided in an embodiment of this application; Figure 3 A schematic diagram of an input signal provided in an embodiment of this application; Figure 4The embodiments provided in this application are related to Figure 3 A schematic diagram of a first control signal corresponding to the input signal; Figure 5 A schematic diagram of an input signal provided in an embodiment of this application; Figure 6 The embodiments provided in this application are related to Figure 5 A schematic diagram of a first control signal corresponding to the input signal; Figure 7 A schematic diagram of an electronic load provided for an embodiment of this application; Figure 8 A schematic diagram of a verification device provided in an embodiment of this application; Figure 9 A schematic diagram of a verification device provided in an embodiment of this application; Figure 10 This is a schematic diagram of a verification device provided in an embodiment of this application.

[0026] Label Explanation 100 Electronic load; 200 First load unit; 210 Processing module; 211 Operational amplifier; 212 Power conversion module; 220 Sampling module; 221 First transistor; 222 Sampling resistor; 230 Feedback module; 231 Feedback resistor; 300 Chip verification device; 301 Power supply under test. Detailed Implementation

[0027] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0028] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0029] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0031] The inventors discovered that in related technologies, the box-type electronic load itself has high power consumption and noise, leading to inaccurate measurement results. Furthermore, the box-type electronic load is typically connected to the power module on the EVB verification board using a connecting cable, and the electronic load is used to test the power module on the EVB verification board. However, the connecting cable between the electronic load and the EVB verification board generates significant parasitic parameters, which affect the simulation of chip voltage and current slope parameters, thus impacting the accuracy of the power supply design.

[0032] like Figure 1 As shown in the figure, this application embodiment provides an electronic load 100, including: a first load unit 200. The first load unit 200 includes: a processing module 210 and a sampling module 220.

[0033] Processing module 210 processes the input signal and outputs a first control signal. The first module of processing module 210 is electrically connected to its first input terminal. The first input terminal of processing module 210 receives the input signal, which can be generated by a signal generating device. The input signal simulates the signal generated by the chip under test, which is required to verify the operating performance of the power supply under test. Processing module 210 converts the input signal into a first control signal with driving capability. The first control signal drives sampling module 220. In one possible implementation, processing module 210 can convert the input signal into a first control signal with driving capability through amplification and conversion processes.

[0034] In one possible implementation, the input signal includes a signal that undergoes a preset change within a preset time period. For example, the input signal may include a square wave voltage signal with a period of 100ms, a starting point of 0V, a peak value of 210mV, and preset rise and fall times. It should be noted that this implementation is merely an illustrative example of the input signal and is not intended to limit its scope. That is, the input signal can also be other types of signals, such as a sinusoidal voltage signal.

[0035] The sampling module 220 is used to sample the signal under test. The control terminal of the sampling module 220 is electrically connected to the output terminal of the processing module 210, and the input terminal of the sampling module 220 is electrically connected to the power supply under test (PST), which provides a power signal to the electronic load 100. The PST is also used to provide a power signal to the chip under test during chip verification. The purpose of verifying the PST is to determine whether it meets design expectations. If the PST meets design expectations, it ensures that during verification, it can provide a power signal to the chip under test that meets design expectations. The output terminal of the sampling module 220 is grounded, and the sampling module 220 is also electrically connected to the second input terminal of the processing module 210. The sampling module 220 is controlled by a first control signal. The sampling module 220 is used to acquire sampling signals, which can characterize the current, voltage, slew rate, and other simulation parameters of the electronic load 100 used to verify the chip. In one possible implementation, the sampling signals can be displayed using an oscilloscope.

[0036] The sampling signal of the sampling module 220 is related to the first control signal, and the sampling signal of the sampling module 220 is related to the power supply signal of the power supply under test.

[0037] The sampling signal of sampling module 220 is related to the first control signal, meaning that the sampling signal changes with the change of the first control signal. The sampling signal of sampling module 220 is also related to the power supply signal of the power supply under test, meaning that when the power supply signal of the power supply under test changes, the sampling signal also changes. Therefore, the sampling signal can be controlled by controlling the input signal, and based on the sampling signal, it can be determined whether the operating performance of the power supply under test meets expectations; that is, based on the sampling signal, it can be determined whether the power supply under test is consistent with the design expectations.

[0038] In this embodiment, the processing module 210 converts the input signal into a first control signal capable of driving the sampling module 220. The sampling signal is related to the first control signal and also to the power signal of the power supply under test. Therefore, changing the input signal can change the sampling signal, and the sampling signal can be used to determine whether the power signal of the power supply under test meets expectations. Thus, this embodiment can verify the operating performance of the power supply under test using only the processing module 210 and the sampling module 220, which helps reduce noise and power consumption generated by the electronic load 100, thereby improving the accuracy of the verification results.

[0039] In one embodiment of this application, the electronic load 100 is integrated on a PCB (Printed Circuit Board). Integrating the electronic load 100 on the PCB allows for a reduction in its size, thereby shortening the connection line between the electronic load 100 and the power supply under test. Shortening the connection line reduces parasitic parameters, thus improving the accuracy of the verification results.

[0040] In one implementation of this embodiment, the shape of the PCB where the electronic load 100 is located is the same as the shape of the chip to be verified. Furthermore, the dimensions of the PCB where the electronic load 100 is located are the same as the dimensions of the chip to be verified.

[0041] The electronic load 100 is integrated on a PCB with the same shape and dimensions as the chip under test. During power supply verification, the electronic load 100 can be directly mounted at the chip location on the EVB verification board. Therefore, the electronic load 100 can completely mimic the verification environment of the chip under test; that is, the connection between the electronic load 100 and the power supply under test is a direct reuse of the connection between the chip under test and the power supply under test. This avoids the generation of additional parasitic parameters on the connection lines, thereby improving the accuracy of the power supply verification results.

[0042] In one possible implementation, the chip to be verified includes several pins, and the PCB containing the electronic load 100 also includes several pins. The pins of the chip to be verified correspond one-to-one with the pins of the PCB. This one-to-one correspondence includes a one-to-one correspondence between the shape and the pin arrangement. For example, the chip to be verified may have 100 pins, and the PCB containing the electronic load 100 may have 100 pins. The length, width, and height of the pins of the chip to be verified are equal to the length, width, and height of the pins on the PCB, respectively, and the projection of the chip to be verified along a direction perpendicular to the EVB verification board completely coincides with the projection of the PCB along the same direction.

[0043] In one possible implementation, the PCB containing the electronic load 100 is electrically connected to the power supply under test via an external wire, the length of which is less than a preset threshold.

[0044] Specifically, when the length of the external connection equals a preset threshold, the negative impact of parasitic parameters generated by the external connection on the test results reaches a preset value. When the negative impact of parasitic parameters generated by the external connection on the test results reaches a preset value, it will significantly affect the verification results of the power supply under test. Technicians can determine the preset value based on the application scenario of the chip under test and actual application requirements, and determine the preset threshold of the connection line based on the preset value and the electrical parameters of the connection line (e.g., resistivity, cross-sectional area, connection method with the power supply under test, etc.).

[0045] In this implementation, the length of the connecting line is less than the preset threshold of the connecting line, which ensures that the parasitic parameters generated by the connecting line will not have a significant impact on the verification results of the power supply under test, thereby ensuring the working performance of the power supply under test and ultimately improving the accuracy of the verification results of the chip under test.

[0046] like Figure 2 As shown, in one embodiment of this application, the processing module 210 includes: an operational amplifier 211 and a power conversion circuit 212. The first input terminal of the operational amplifier 211 is the first input terminal of the processing module 210. The second input terminal of the operational amplifier 211 is the second input terminal of the processing module 210. The output terminal of the operational amplifier 211 is electrically connected to the input terminal of the power conversion module, and the output terminal of the power conversion module is the output terminal of the processing module 210.

[0047] In this embodiment, operational amplifier 211 is used to amplify the input signal. Although operational amplifier 211 can amplify the voltage value of the input signal, its output current is relatively weak, meaning the output signal lacks driving capability. Therefore, the output signal of operational amplifier 211 is input to power conversion circuit 212. Power conversion circuit 212 amplifies the current and obtains a driving voltage that can turn on the driving module, thereby converting the signal, which lacks driving capability, into a first control signal that drives the sampling module 220.

[0048] In this embodiment, the operational amplifier 211 and the power conversion circuit 212 are used to convert the input signal into a first control signal with driving capability. The circuit structure is simple and has low power consumption, which can help reduce the overall power consumption of the electronic load 100 and its own parasitic parameters, thereby improving the accuracy of the verification results of the power supply under test.

[0049] like Figure 3 As shown, the input signal is a voltage square wave. After processing by the processing module 210, the first control signal obtained is as follows: Figure 4 As shown. (Through) Figure 4 It can be concluded that the first control signal has good driving capability.

[0050] like Figure 5 As shown, the input signal is a voltage sine wave. After processing by the processing module 210, the resulting first control signal is as follows: Figure 6 As shown. (Through) Figure 6 It can be concluded that the first control signal has good driving capability.

[0051] like Figure 2 As shown, in one embodiment of this application, the sampling module 220 includes a first transistor 221 and a sampling resistor 222. The control terminal of the first transistor 221 is the control terminal of the sampling module 220, the first terminal of the first transistor 221 is the input terminal of the sampling module 220, the second terminal of the first transistor 221 is electrically connected to the first terminal of the sampling resistor 222, and the second terminal of the sampling resistor 222 is the output terminal of the sampling module 220.

[0052] In one possible implementation of this embodiment, the first terminal of the first transistor 221 is electrically connected to the power supply under test, and the control terminal of the first transistor 221 is electrically connected to the output terminal of the operational amplifier 211. The control terminal of the first transistor 221 receives a first control signal. The first control signal controls the first transistor 221 to operate in the linear amplification region. When the first transistor 221 operates in the linear amplification region, its internal channel resistance is variable, and therefore the current flowing through its channel is also variable. This makes the current flowing through the first transistor 221 controllable. In one possible implementation, the first transistor 221 is an NMOS transistor.

[0053] When the first transistor 221 operates in the linear amplification region, its channel current I With gate voltage The relationship between the power supply voltage VDD of the power supply under test and the following conditions must be satisfied: in, For electron mobility, The capacitance per unit area of ​​the gate oxide layer. The aspect ratio is 4.5. This is the voltage difference between the gate voltage and the source voltage. Threshold voltage, VDD is the voltage difference between the drain voltage and the source voltage.

[0054] The first terminal of sampling resistor 222 is the acquisition node for the sampling signal. By acquiring the sampling signal at this node, it can be determined whether the power supply under test meets expectations. For example, the specific details of the sampling signal can be obtained by connecting this acquisition node to an oscilloscope. The specific details of the acquired signal include: current, voltage, slew rate, etc.

[0055] In this embodiment, the sampling module 220 has a simple circuit structure, low power consumption, and few parasitic parameters, which helps to reduce the overall power consumption and parasitic parameters of the electronic load 100, and ultimately helps to improve the accuracy of the verification results of the power supply under test.

[0056] like Figure 7 As shown, in one embodiment of this application, the electronic load 100 further includes a feedback module 230, and the sampling module 220 is electrically connected to the second input terminal of the processing module 210 through the feedback module 230.

[0057] The function of the feedback module 230 is to make the output signal of the processing module 210 more stable.

[0058] like Figure 2 As shown, in one possible implementation, the feedback module 230 includes a feedback resistor 231, with its first end electrically connected to the first end of the sampling resistor 222, and its second end electrically connected to the second input terminal of the processing module 210. In another possible implementation, the second input terminal of the processing module 210 is the second input terminal of the operational amplifier 211.

[0059] In this embodiment, the electronic load 100 includes a plurality of first load units 200. The plurality of first load units 200 are used to detect a plurality of power supplies under test. For example, one of the plurality of first load units 200 is used to detect one power supply under test.

[0060] The EVB verification board includes multiple power supplies, and the performance of each power supply needs to be tested. Therefore, multiple first load units 200 are required to verify multiple power supplies under test.

[0061] like Figure 8 As shown, this application embodiment also provides a chip verification device 300, including the electronic load 100 of any of the foregoing embodiments.

[0062] The chip verification device 300 can be an EVB (Evaluation Board, Reference Design Evaluation Board) verification board.

[0063] The chip verification apparatus provided in this application can improve the accuracy of the verification results of the power supply under test.

[0064] In one possible implementation, the electronic load 100 is detachably mounted within the chip verification device 300.

[0065] like Figure 9 As shown, in one possible implementation, the chip verification device 300 also includes a power supply under test 301.

[0066] In the chip verification device, the power supply under test and the electronic load 100 are electrically connected through internal wiring, such as through PCB traces, which helps to reduce parasitic parameters and ensure the accuracy of the verification results of the power supply under test.

[0067] like Figure 10 As shown, in one possible implementation, the chip verification device 300 further includes a plurality of power supplies under test 301, and the electronic load 100 includes a plurality of first load units 200, with each power supply under test corresponding to a first load unit 200.

[0068] The chip verification device 300 includes multiple power supplies under test (UTPs) 301 and an electronic load 100 including a first load unit 200 corresponding to each UTP 301. Therefore, the chip verification device 300 can verify multiple UTPs simultaneously, saving verification cycles, shortening verification time, and improving verification efficiency.

[0069] This application also provides an apparatus including the electronic load 100 provided in any of the foregoing embodiments. The apparatus can be an electronic load 100 apparatus independent of the EVB verification board.

[0070] The device provided in this application embodiment can verify the working performance of the power supply under test using only the processing module 210 and the sampling module 220, which helps to reduce the noise and power consumption generated by the electronic load 100, thereby improving the accuracy of the verification results of the power supply under test.

Claims

1. An electronic load, characterized by, include: First load unit; The first load unit includes: A processing module is used to process the input signal and output a first control signal. The first module of the processing module is electrically connected to the first input terminal of the processing module. A sampling module is used to sample the signal to be tested; the control terminal of the sampling module is electrically connected to the output terminal of the processing module, the input terminal of the sampling module is electrically connected to the power supply to be tested, the output terminal of the sampling module is grounded, and the sampling module is also electrically connected to the second input terminal of the processing module. The sampling signal of the sampling module is related to the first control signal, and the sampling signal of the sampling module is related to the power supply signal of the power supply under test.

2. Electronic load according to claim 1, characterized in that, The electronic load is integrated on the PCB.

3. The electronic load according to claim 2, characterized in that, The shape of the PCB where the electronic load is located is the same as the shape of the chip to be verified, and the size of the PCB where the electronic load is located is the same as the size of the chip to be verified.

4. The electronic load according to claim 3, characterized in that, The PCB containing the electronic load is electrically connected to the power supply under test via an external wire, the length of which is less than a preset threshold.

5. The electronic load according to claim 1, characterized in that, The processing module includes: an operational amplifier and a power conversion circuit; the first input terminal of the operational amplifier is the first input terminal of the processing module; the second input terminal of the operational amplifier is the second input terminal of the processing module; the output terminal of the operational amplifier is electrically connected to the input terminal of the power conversion module, and the output terminal of the power conversion module is the output terminal of the processing module.

6. The electronic load according to claim 1, characterized in that, The sampling module includes: a first transistor and a sampling resistor; the control terminal of the first transistor is the control terminal of the sampling module, the first terminal of the first transistor is the input terminal of the sampling module, the second terminal of the first transistor is electrically connected to the first terminal of the sampling resistor, and the second terminal of the sampling resistor is the output terminal of the sampling module.

7. The electronic load according to claim 1, characterized in that, It also includes a feedback module, through which the sampling module is electrically connected to the second input terminal of the processing module.

8. A chip verification device, characterized in that, Includes the electronic load as described in any one of claims 1-7.

9. The apparatus according to claim 8, characterized in that, It also includes the power supply under test.

10. A device, characterized in that, The device includes the electronic load as described in any one of claims 1-7.

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