An asynchronous register read-write method

Abstract

The application discloses an asynchronous register read-write method, which comprises the following steps: S1, performing a write operation on a register in a first clock domain; S2, converting the write operation register into a pulse signal with a data bit width of one bit in the first clock domain; S3, converting the pulse signal generated in the step S2 into a pulse signal with a bit width of one bit in a second clock domain; and S4, taking the pulse signal generated in the step S3 as a start signal to decode and execute a register operation instruction in the second clock domain. The method can reliably read or write a register in the second clock domain from the first clock domain.

Description

Technical Field

[0001] This disclosure relates to the field of digital integrated circuit design, and in particular to the reading and writing of asynchronous registers. Background Technology

[0002] In practical integrated circuit engineering, it is often necessary to read and write data in different clock domains. Since the registers that need to be read and written are in another clock domain, how to reliably read and write them is a real engineering problem faced by integrated circuit digital design.

[0003] like Figure 1 As shown, this is a widely used asynchronous register read / write technique called FIFO (First In, First Out). The FIFO method can reliably transfer data from one clock domain to another. However, the FIFO method has two main problems: 1. Data transmission is unidirectional. Either the first clock domain continuously sends data while the second clock domain continuously receives data, or the first clock domain continuously receives data while the second clock domain continuously sends data. It cannot simultaneously send data to and receive data from the second clock domain. 2. The FIFO method can only read or write data sequentially; it cannot write data to or read data from a specified address. Summary of the Invention

[0004] To address the shortcomings of the aforementioned related technologies, this invention provides an asynchronous register read / write method, the process of which is as follows: Figure 2 As shown, Step S1: Write the operation execution register within the first clock domain; Step S2: Within the first clock domain, convert the write operation execution register into a pulse signal with a data bit width of one bit; Step S3: In the second clock domain, convert the pulse signal generated in step S2 into a pulse signal with a bit width of one bit in the second clock domain; Step S4: In the second clock domain, the pulse signal generated in step S3 is used as the start signal to decode and execute the register operation instruction.

[0005] Register operation instructions contain the register data to be operated on, the register address, and the register operation (register read or register write).

[0006] As described in

[0004] , the operation execution register address number is greater than the operation command address register number.

[0007] As can be seen, the operation command register was already written when the operation execution register was written, and the data in the entire operation command register was stable. Furthermore, the operation command register contained complete register data, addresses, and operation category information that needed to be operated on within the second clock domain, thus fulfilling the necessary conditions for operating on registers within the second clock domain.

[0008] By converting write operation execution commands into a one-bit pulse signal and transmitting it to the second clock domain, data errors caused by metastability during cross-clock domain transmission can be avoided. This is a classic scheme for transmitting signals across clock domains.

[0009] It should be noted that when the pulse signal is transmitted from the first clock domain to the second clock domain, and a pulse signal synchronized with the second clock domain is regenerated in the second clock domain, the operation command register data has been fully established, and there will be no situation where the second clock domain register collects an erroneous signal.

[0010] Using the pulse signal in the second clock domain as the start signal, the state machine or other digital circuit in the second clock domain is started, and the registers in the second clock domain are operated simultaneously according to the established and stable operation command data.

[0011] As can be seen from the detailed explanation of the operation steps of this invention above, this invention avoids the transmission of multi-bit signals across clock domains and transforms the reading and writing of signals in the second clock domain from the first clock domain to synchronous reading and writing within the second clock domain. This achieves the goal of reliable reading and writing of asynchronous registers.

[0012] Therefore, the method of the present invention can reliably read or write to registers in the second clock domain from the first clock domain at a specified address. Attached Figure Description

[0013] Figure 1 Architecture diagram of the FIFO method used for asynchronous register reads and writes.

[0014] Figure 2 An explanatory diagram illustrating the overview of the implementation steps of the method of the present invention.

[0015] Figure 3 The figure below illustrates a preferred embodiment of the method of the present invention. Detailed Implementation

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0017] In integrated circuit design engineering, it is often necessary to read and write asynchronous registers, for example, to read or write other registers in the chip via serial port protocols (I2C, SPI, UART, etc.). However, registers in different clock domains should not be read or written across clock domains in principle. This necessitates a timing arrangement, or method / protocol, that is higher than the register timing requirements, so that registers in different clock domains can meet the timing requirements and reliably receive or transmit data.

[0018] The most common method for asynchronous register read / write across clock domains is FIFO. For example... Figure 1 As shown, the principle of FIFO is to use a first-in, first-out (FIFO) data entry method to ensure that the data being read has been stably established before it is read, and that the register being written to is not read before it is written to. This higher-level timing arrangement allows registers to be reliably transmitted even though they are not in the same clock domain.

[0019] However, asynchronous register reads and writes in a FIFO are typically unidirectional. That is, the first clock domain can only perform either a read or a write operation on registers in the second clock domain; it cannot simultaneously read from and write to registers within the second clock domain. Based on its operating principle, a FIFO can only sequentially transfer data within its memory cells across clock domains; it cannot perform reads or writes to specified addresses.

[0020] In reality, reading and writing asynchronous registers, as well as reading and writing asynchronous registers at a specified address, are very practical design requirements.

[0021] Example 1 is an implementation case of a preferred asynchronous register read / write method of the present invention, such as... Figure 1 As shown, in this embodiment, the first clock domain is the serial interface protocol clock, and the second clock domain is another register array within the chip. In actual chip use, all configurations within the chip require configuring register values ​​via the serial interface. If it is necessary to configure a register value within the second clock domain, it also needs to be done via the serial port protocol within the first clock domain. This creates the need for reading and writing registers in the asynchronous clock domain.

[0022] In this embodiment, the operation instructions are separated into three actual registers: register data, register address, and register operation, with addresses 8'h01, 8'h02, and 8'h03 respectively. The operation execution register is a single actual register with address 8'h04. In this embodiment, the frequency of the second clock is significantly higher than the frequency of the first clock.

[0023] When the serial port protocol write operation is executed in the register, the action of writing the serial port protocol to the register is converted into a pulse signal with a width of one bit in the first clock domain. This pulse signal is then transmitted across the clock domain to the second clock domain.

[0024] After receiving a single pulse signal from the first clock domain, the second clock domain will convert this pulse signal into a pulse signal synchronized with the second clock domain, and then use this pulse signal as the start signal for operation within the second clock domain.

[0025] Since serial port protocol reads and writes registers in ascending order of register address, it can be seen that when writing to the execution register (address 8'h04), the data in the instruction registers (addresses 8'h01, 8'h02, 8'h03) has already been written and is stable. The start pulse signal in the second clock domain is at the execution register (address 8'h04), so when the second clock domain decodes the instruction register in the first clock domain, the data in the instruction register is stable and established. During write operations, the circuit system in the second clock domain only needs to complete the stable and reliable operation instructions in the first clock domain. During read operations, because the clock speed of the second clock domain is much faster than that of the first clock domain, the second clock domain has already written the data to the buffer register before the data in the first clock domain is written to the register. The data in the second clock domain is already established, and the read operation can be completed reliably.

[0026] Because the serial port protocol will not operate the operation command register again after the operation command is written, until the next operation command is to be executed, and the write operation is executed after the write operation command, the register signals related to the operation command have been established, so the asynchronous write operation of this invention is absolutely reliable.

[0027] In this embodiment, during a read operation, the state machine in the second clock domain loads the register value in the second clock domain into the buffer register. The value of the buffer register will not change until the next read operation occurs. Therefore, the asynchronous read operation of this invention is absolutely reliable.

Claims

1. An asynchronous register read / write method, characterized in that, include: Step S1: Write the operation execution register within the first clock domain; Step S2: Within the first clock domain, convert the write operation execution register into a pulse signal with a data bit width of one bit; Step S3: In the second clock domain, convert the pulse signal generated in step S2 into a pulse signal with a bit width of one bit in the second clock domain; Step S4: In the second clock domain, the pulse signal generated in step S3 is used as the start signal to decode and execute the register operation instruction; The operation instructions include the register data, register address, and register operation (register read or register write) to be performed.

2. The asynchronous register read / write method according to claim 1, characterized in that, The address of the operation execution register is greater than the address of the operation instruction register.

3. The asynchronous register read / write method according to claim 2, characterized in that, The data register, address register, and operation register can be combined into one actual register, or they can be combined in pairs into one actual register, or they can be separated into three actual registers.

4. The asynchronous register read / write method according to claim 1, characterized in that, The operation of the instruction register and operation execution register within the first clock domain is performed using serial port protocols, including I2C, SPI, and UART protocols.

5. The asynchronous register read / write method according to claim 1, characterized in that, The second clock frequency is greater than the first clock frequency.

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