A verification method, device and equipment of an integrated circuit and a storage medium

Abstract

The application discloses a kind of integrated circuit verification method, device, equipment and storage medium, comprising: obtaining the verification description data corresponding to the integrated circuit to be measured, and the structured labeling of verification description data;Verification description data includes hardware architecture data and verification component configuration data;The labeled verification description data is input into the database sequence of multilevel, and the verification description data is processed by database sequence, and the parameter configuration file corresponding to the integrated circuit to be measured is output;Parameter configuration file is input into functional plug-in, and according to parameter configuration file and pre-integrated tool package, the test set corresponding to the integrated circuit to be measured is generated;Simulation is run to test set, and according to the running result, the verification report corresponding to the integrated circuit to be measured is generated.The technical scheme of the embodiment of the application can improve the verification efficiency of large-scale integrated circuit, guarantee the accuracy of verification result, and improve the reusability of verification method.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for verifying integrated circuits. Background Technology

[0002] As integrated circuit designs become larger and project iteration cycles become shorter, rapid and accurate verification of integrated circuits is crucial.

[0003] Existing technologies for verifying integrated circuits require verification personnel to manually input the integrated circuit's architecture information line by line into multiple technical knowledge domain frameworks. Furthermore, when using script-driven automated verification, a large amount of configuration information must be manually entered. This process is not only time-consuming and labor-intensive, but also prone to inconsistencies due to the information being scattered across multiple independent files and lacking unified data source management. Secondly, because different verification personnel may have different data description formats, naming conventions, and technical knowledge domains, existing verification methods lack unified data annotation standards and structured storage solutions. This makes it difficult to reuse verification methods across projects and teams, resulting in low collaboration efficiency among verification personnel and a lack of standardized data processing solutions for Artificial Intelligence (AI) tools. Finally, existing verification environments are highly coupled with the design of the integrated circuit under test. When the design of the integrated circuit under test changes, the verification environment needs significant modifications, making it difficult to support flexible migration of verification methods. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and storage medium for verifying integrated circuits, which can improve the verification efficiency of large-scale integrated circuits, ensure the accuracy of verification results, and enhance the reusability of verification methods.

[0005] According to one aspect of the present invention, a method for verifying an integrated circuit is provided, comprising: Obtain the verification description data corresponding to the integrated circuit under test, and perform structured annotation on the verification description data; the verification description data includes hardware architecture data and verification component configuration data; The labeled verification description data is input into a multi-level database sequence. The verification description data is processed through the database sequence, and the parameter configuration file corresponding to the integrated circuit under test is output. The parameter configuration file is input into the function plugin, which generates a test set corresponding to the integrated circuit under test based on the parameter configuration file and the pre-integrated toolkit. The test set is simulated and run, and a verification report corresponding to the integrated circuit under test is generated based on the running results.

[0006] According to another aspect of the present invention, an integrated circuit verification apparatus is provided, comprising: The data annotation module is used to acquire the verification description data corresponding to the integrated circuit under test and to perform structured annotation on the verification description data; the verification description data includes hardware architecture data and verification component configuration data; The data weaving module is used to input the labeled verification description data into a multi-level database sequence, process the verification description data through the database sequence, and output the parameter configuration file corresponding to the integrated circuit under test. The test set generation module is used to input the parameter configuration file into the function plugin, and the function plugin generates the test set corresponding to the integrated circuit under test according to the parameter configuration file and the pre-integrated toolkit. The test set execution module is used to simulate the test set and generate a verification report for the integrated circuit under test based on the execution results.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to perform the integrated circuit verification method according to any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the integrated circuit verification method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the integrated circuit verification method according to any embodiment of the present invention.

[0010] The technical solution provided by this invention improves the verification efficiency of large-scale integrated circuits, ensures the accuracy of verification results, and enhances the reusability of verification methods by acquiring verification description data corresponding to the integrated circuit under test (ICT). The verification description data includes hardware architecture data and verification component configuration data. The annotated verification description data is input into a multi-level database sequence, processed by the database sequence, and outputs a parameter configuration file corresponding to the ICT. This parameter configuration file is then input into a functional plugin, which generates a test set corresponding to the ICT based on the parameter configuration file and a pre-integrated toolkit. The test set is then simulated, and a verification report is generated based on the simulation results.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of an integrated circuit verification method provided according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating a scenario applicable to an integrated circuit verification method provided in an embodiment of the present invention; Figure 3 This is a flowchart of another integrated circuit verification method provided according to an embodiment of the present invention; Figure 4 This is a flowchart of a method for processing data using a multi-level database sequence according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an integrated circuit verification device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device that implements the verification method for integrated circuits according to embodiments of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] Figure 1 This is a flowchart illustrating a method for verifying integrated circuits according to an embodiment of the present invention. This embodiment is applicable to verifying the performance of large-scale integrated circuits. The method can be executed by an integrated circuit verification device, which can be implemented in hardware and / or software and configured in an electronic device, such as... Figure 1 As shown, the method includes: Step 110: Obtain the verification description data corresponding to the integrated circuit under test, and perform structured annotation on the verification description data; the verification description data includes hardware architecture data and verification component configuration data.

[0017] In this embodiment, optionally, hardware architecture data corresponding to the integrated circuit under test can be extracted from the project daily report, design acceptance report, hardware design architecture specification, and Register Transfer Level (RTL) source code corresponding to the integrated circuit under test. This includes, but is not limited to, module hierarchy and interconnection topology information, interface type and protocol specification information of each module (e.g., Advanced Peripheral Bus (APB) protocol, Advanced eXtensible Interface (AXI) protocol, Advanced High Performance Bus (AHB) protocol, etc.), address space mapping relationship, clock domain and frequency configuration information, module operating mode and parameter configuration range, etc.

[0018] Optionally, the configuration data of the verification components corresponding to the integrated circuit under test can be extracted from the verification knowledge framework, verification intellectual property (IP) library, and existing verification environment information corresponding to the integrated circuit under test. This includes, but is not limited to, the testbench component type and master / slave relationship, the interface binding information of each verification component, the constraint definition, the coverage model structure, and the configuration information of the checker and scoreboard.

[0019] In one embodiment of this invention, the aforementioned hardware architecture data and verification component configuration data can be automatically extracted using a preset script or an AI-assisted model; this embodiment does not impose any limitations on this. The preset script stores key extraction fields for parsing RTL source code and design documents, and the AI-assisted model can be pre-trained based on natural language processing algorithms.

[0020] In this step, after obtaining the verification description data corresponding to the integrated circuit under test, the verification description data can be uniformly and structurally annotated according to the pre-built annotation process. The advantage of this setup is that, compared to the existing technology where verification personnel need to manually enter the architecture information into multiple independent files one by one, it can significantly reduce the time spent on inputting verification information, achieve one-time annotation and multiple references, and avoid the inconsistency problem caused by repeated input of information in multiple files. Secondly, by annotating the verification description data in a structured manner, a mapping relationship between the verification description data and the annotation labels can be established, realizing the traceability of the entire chain from the key functional information in the integrated circuit product specifications to the underlying hardware implementation, test set generation to test result display. This makes it easier for verification personnel to accurately assess the functional coverage of the integrated circuit under test, promptly identify verification blind spots, and provide standardized data input for the local deployment of AI tools, enabling AI tools to generate more reliable output results based on accurate, complete, and structured verification description data.

[0021] Step 120: Input the labeled verification description data into a multi-level database sequence, process the verification description data through the database sequence, and output the parameter configuration file corresponding to the integrated circuit under test.

[0022] In this embodiment, the labeled verification description data can be input into a hierarchical structured database sequence. The output of the previous layer of the database sequence can be used as the input data for the next layer, thereby forming a multi-level data weaving structure. Optionally, the database sequence is used to store a collection of structured data files in JSON format.

[0023] The advantage of this setup is that, by adopting a cascaded data weaving structure, when the design specifications of the IC under test change, only the description data at the source of the database needs to be modified. The modified data can be automatically propagated to all downstream configuration files and test sets through the data weaving structure. Compared with the existing technology where the verification environment needs to be significantly modified when the design of the IC under test changes, this reduces the coupling between the verification environment and the design of the IC under test, and improves the flexibility of the verification method.

[0024] Step 130: Input the parameter configuration file into the function plugin. The function plugin generates the test set corresponding to the integrated circuit under test based on the parameter configuration file and the pre-integrated toolkit.

[0025] In this embodiment, the toolkit pre-integrated by the functional plugin may include various functional components for generating the final test set based on the parameter configuration file.

[0026] Optionally, the functional plugins can be registered with the verification system through a unified plugin registration interface. This interface can define plugin identifiers, input declarations, output declarations, execution entry points, and priorities. The plugin identifier is a globally unique plugin name and version number; the input declaration is a list of database inputs required by the plugin, declaring which layers' database files the plugin depends on; the output declaration is the type and format of the output files generated by the plugin; and the execution entry point is the name of the plugin's main execution function. When the verification system starts, the plugin manager can scan the plugin registration directory and load all plugins that conform to the registration interface specifications.

[0027] In this embodiment, a data read interface, a data write-back interface, and a change notification interface can be deployed between the functional plugin and the database sequence. The functional plugin can read data from a specified layer or module in the database sequence through the data read interface, and supports filtering data based on conditions and selecting key fields. The functional plugin can write the plugin execution results back to the database sequence through the data write-back interface, supporting append, update, and overwrite write modes. The written-back data can be used by other plugins or subsequent processes. When writing data back, the functional plugin can use the change notification interface to notify other plugins that depend on the database sequence to synchronize and update the corresponding data.

[0028] In one specific implementation method Figure 2 This is a schematic diagram illustrating a scenario applicable to the verification method for an integrated circuit in this embodiment, as shown below. Figure 2 As shown, the functional plugin may include a special function information extraction guidance framework, special function scripts, and template toolkits.

[0029] The special function information extraction guidance framework is used to provide information extraction templates and guidance specifications for different verification tasks, assisting verification personnel in quickly obtaining the required data from the project database (i.e., the database sequence) and storing the data in the special function information database.

[0030] The specialized function scripts and template toolkit may include: file processing scripts, test set generation scripts, configuration information lookup and cache transfer scripts, and verification report generation scripts. Specifically, the file processing scripts are used to parse and convert database files; the test set generation scripts are used to automatically generate test sets; the configuration information lookup and cache transfer scripts are used to retrieve configuration information from the database sequence and accelerate data transfer through a caching mechanism; and the verification report generation scripts are used to summarize test simulation results and generate structured verification reports.

[0031] The advantage of this setup is that by inputting the parameter configuration file into the functional plugin, the efficiency of test set generation can be greatly improved. Compared with the existing method of manually writing test cases, it can reduce the workload of verification personnel, increase the coverage of test sets, and ensure the reliability of verification results.

[0032] Step 140: Run the simulation on the test set and generate a verification report for the integrated circuit under test based on the results.

[0033] In this step, such as Figure 2 As shown, the test set can be simulated and run based on a pre-configured operating environment, and a script can be generated based on the running results and the verification report of the integrated function plug-in to automatically generate the verification report corresponding to the integrated circuit under test.

[0034] Optionally, the configuration process of the runtime environment may include configuring the simulation toolchain, setting compilation options, and managing runtime parameters, etc., and this embodiment does not impose any limitations on this.

[0035] The technical solution provided by this invention improves the verification efficiency of large-scale integrated circuits, ensures the accuracy of verification results, and enhances the reusability of verification methods by acquiring verification description data corresponding to the integrated circuit under test (ICT). The verification description data includes hardware architecture data and verification component configuration data. The annotated verification description data is input into a multi-level database sequence, processed by the database sequence, and outputs a parameter configuration file corresponding to the ICT. This parameter configuration file is then input into a functional plugin, which generates a test set corresponding to the ICT based on the parameter configuration file and a pre-integrated toolkit. The test set is then simulated, and a verification report is generated based on the simulation results.

[0036] Figure 3 A flowchart of another integrated circuit verification method provided in an embodiment of the present invention is shown below. Figure 3 As shown, the method includes: Step 210: Obtain the verification description data corresponding to the integrated circuit under test; the verification description data includes hardware architecture data and verification component configuration data.

[0037] Step 220: Establish a unified tagging system based on the existing data tags in the hardware architecture data; use the unified tagging system to perform structured annotation on the hardware architecture data and verification component configuration data.

[0038] The advantage of this setup is that by establishing a unified labeling system using existing data labels in the hardware architecture data, it can ensure that the meaning of the labeled labels is consistent with the common terminology in the hardware design and verification fields. By using this labeling system to perform structured labeling of hardware architecture data and verification component configuration data, standardized data description specifications can be provided, solving the problem of inconsistent data formats caused by differences in the description habits of verification personnel, thereby improving the collaboration efficiency of verification personnel.

[0039] Step 230: Perform integrity verification on the tags corresponding to the hardware architecture data and the verification component configuration data respectively; and / or, use a cross-reference verification algorithm to verify the tags corresponding to the hardware architecture data and the verification component configuration data respectively.

[0040] Step 240: Input the annotated verification description data into the basic information layer database, address space layer database, constraint layer database, configuration layer database, and parameter layer database in sequence, and output the parameter configuration file through the parameter layer database.

[0041] In this embodiment, the multi-level database sequence includes a basic information layer database, an address space layer database, a constraint layer database, a configuration layer database, and a parameter layer database.

[0042] Optional, such as Figure 4 As shown, the annotated verification description data is sequentially input into the basic information layer database, address space layer database, constraint layer database, configuration layer database, and parameter layer database. The parameter layer database outputs a parameter configuration file, including: S241. Input the clock domain labeling data into the basic information layer database, and output the clock domain frequency mapping table through the basic information layer database. In this step, the clock domain annotation data may include time domain name, frequency value, operating mode identifier, etc. Specifically, clock domain data scattered across multiple annotation records can be aggregated by clock domain name, grouped by operating mode, and a global clock domain partitioning table can be generated. Then, the frequency values ​​of the same clock domain under different operating modes are checked for consistency to ensure that there are no frequency configuration conflicts. After the clock domain annotation data is input into the basic information layer database, the clock domain frequency mapping table output by the basic information layer database is in the format {"clock_domains": [{"name": "clk_cpu","modes":{"normal":"1GHz","low_power":"500MHz"}}, ...]}.

[0043] S242. Input the address allocation label data and clock domain frequency mapping table into the address space layer database, and output the address mapping table through the address space layer database; the address mapping table contains clock domain association information. In this step, specifically, after the address allocation annotation data and clock domain frequency mapping table are input into the address space layer database, the address space layer database can construct a global address mapping table based on the module annotation information, including base address, address range, address offset, etc., and associate it with the clock domain information of the basic information layer database to annotate the clock domain to which each address space belongs, generate address decoding rules, and at the same time perform overlap detection and legality verification on the address spaces.

[0044] Optionally, the address mapping table contains clock domain association information, in the format {"address_spaces":[{"module": "A", "base_addr": "0x1000","size": "0x100","clock_domain": "clk_cpu"}, ...]}.

[0045] S243. Input the constraint annotation data and address mapping table into the constraint layer database, and output the constraint file set through the constraint layer database; In this step, specifically, after the constraint annotation data and address mapping table are input into the constraint layer database, the constraint layer database can automatically generate address range constraints (such as legal address range and alignment requirements) for each module based on the address mapping table, and generate timing constraints for cross-clock domain access based on clock domain association information. Finally, the protocol compliance constraints, data width constraints, etc. are merged with the automatically generated constraints and conflict detection is performed to obtain a complete constraint file set.

[0046] Optionally, the constraint file set format is {"module":"A","constraints": {"addr_range":{"min":"0x1000","max":"0x10FF"},"timing": {"setup": "1ns","hold":"0.5ns"},"protocol":{"burst_type":["FIXED","INCR","WRAP"]}}}.

[0047] S244. Input the verification component annotation data and constraint file set into the configuration layer database, and output the test bench configuration file set through the configuration layer database. In this step, specifically, after inputting the verification component annotation data and constraint file set into the configuration layer database, the configuration layer database can determine the component type (master / slave), component quantity, and interface binding relationship of each module test bench based on the verification component annotation data, and bind the constraint file set to the corresponding test bench component to determine the constraint conditions that need to be applied to each component. Finally, the connection topology and signal mapping relationship between the test bench components are determined, and the test bench configuration file set is generated accordingly.

[0048] Optionally, the testbench configuration file set format is {"module": "A", "testbench": {"type":"master","num":20,"interfaces":["S_IF","B_IF"],"constraint_ref": "A_constraint.json", "connections": [...]}}.

[0049] S245. Input the parameter annotation data and test bench configuration file set into the parameter layer database, and output the parameter configuration file through the parameter layer database.

[0050] In this step, specifically, after inputting the parameter annotation data and test bench configuration file set into the parameter layer database, the parameter layer database can fill in specific simulation parameters for each component according to the test bench component type and interface protocol, including bus protocol parameters (such as burst length, data width), port configuration parameters, working mode parameters, etc. Then, based on the constraint file set, all parameters are validated for legality and filled with default values, thereby obtaining the parameter configuration file.

[0051] Optionally, the parameter configuration file format is {"module":"A","params": {"protocol": "APB", "data_width": 32, "addr_width": 12,"timeout": "100ns","burst_support":false}}.

[0052] Step 250: Input the parameter configuration file into the function plugin. The function plugin generates the test set corresponding to the integrated circuit under test based on the parameter configuration file, the pre-integrated test set template, and the test set generation script.

[0053] Step 260: Simulate the test set and generate a structured verification report for the integrated circuit under test by generating a script based on the running results and the pre-integrated verification report through the functional plugin.

[0054] The technical solution provided by this invention improves the verification efficiency of large-scale integrated circuits, ensures the accuracy of verification results, and enhances the reusability of verification methods by acquiring verification description data corresponding to the integrated circuit under test (ICT). This verification description data includes hardware architecture data and verification component configuration data. A unified tagging system is established based on existing data tags in the hardware architecture data. The unified tagging system is used to structurally annotate the hardware architecture data and verification component configuration data, and the integrity of the tags corresponding to the hardware architecture data and verification component configuration data is verified. Alternatively, a cross-reference verification algorithm is used to verify the tags corresponding to the hardware architecture data and verification component configuration data. The annotated verification description data is sequentially input into a basic information layer database, an address space layer database, a constraint layer database, a configuration layer database, and a parameter layer database. A parameter configuration file is output from the parameter layer database. This parameter configuration file is input into a functional plugin. The functional plugin generates a test set corresponding to the ICT based on the parameter configuration file, a pre-integrated test set template, and a test set generation script. The test set is then simulated and run. The functional plugin generates a structured verification report corresponding to the ICT based on the running results and a pre-integrated verification report generation script.

[0055] Based on the above implementation methods, Table 1 presents a comparison chart of performance differences. As shown in Table 1, the integrated circuit verification method provided in this embodiment differs from the existing IP eXtensible Architecture for Tool Integration (IP-XACT) standard in the following ways regarding the description of verification data: (1) Information coverage and (2) Data organization. Table 1

[0056] As shown in Table 1, the integrated circuit verification method provided in this embodiment can effectively solve the technical problems in the prior art, such as cumbersome and error-prone verification information entry, inconsistent data description standards, poor consistency of multi-person collaborative verification, insufficient decoupling between the verification environment and the integrated circuit under test, and lack of standardized data infrastructure for AI tools. It can also improve the verification efficiency of large-scale integrated circuits, ensure the accuracy of verification results, and improve the reusability of verification methods.

[0057] Figure 5 This is a schematic diagram of the structure of an integrated circuit verification device provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the device includes: a data annotation module 310, a data weaving module 320, a test set generation module 330, and a test set running module 340.

[0058] The data annotation module 310 is used to acquire the verification description data corresponding to the integrated circuit under test and to perform structured annotation on the verification description data; the verification description data includes hardware architecture data and verification component configuration data. The data weaving module 320 is used to input the labeled verification description data into a multi-level database sequence, process the verification description data through the database sequence, and output the parameter configuration file corresponding to the integrated circuit under test. The test set generation module 330 is used to input the parameter configuration file into the function plugin, and the function plugin generates the test set corresponding to the integrated circuit under test according to the parameter configuration file and the pre-integrated toolkit. The test set running module 340 is used to simulate the test set and generate a verification report corresponding to the integrated circuit under test based on the running results.

[0059] The technical solution provided by this invention improves the verification efficiency of large-scale integrated circuits, ensures the accuracy of verification results, and enhances the reusability of verification methods by acquiring verification description data corresponding to the integrated circuit under test (ICT). The verification description data includes hardware architecture data and verification component configuration data. The annotated verification description data is input into a multi-level database sequence, processed by the database sequence, and outputs a parameter configuration file corresponding to the ICT. This parameter configuration file is then input into a functional plugin, which generates a test set corresponding to the ICT based on the parameter configuration file and a pre-integrated toolkit. The test set is then simulated, and a verification report is generated based on the simulation results.

[0060] Based on the above embodiments, the multi-level database sequence includes a basic information layer database, an address space layer database, a constraint layer database, a configuration layer database, and a parameter layer database.

[0061] Data annotation module 310 includes: The tag system construction unit is used to establish a unified tag system based on the existing data tags in the hardware architecture data; and to use the unified tag system to perform structured annotation on the hardware architecture data and verification component configuration data. The tag verification unit is used to perform integrity verification on the tags corresponding to the hardware architecture data and the verification component configuration data respectively; and / or, to use a cross-reference verification algorithm to verify the tags corresponding to the hardware architecture data and the verification component configuration data respectively.

[0062] Data weaving module 320 includes: The multi-layer database processing unit is used to sequentially input the labeled verification description data into the basic information layer database, the address space layer database, the constraint layer database, the configuration layer database, and the parameter layer database, and output the parameter configuration file through the parameter layer database. The time-domain data processing unit is used to input clock domain labeled data into the basic information layer database and output a clock domain frequency mapping table through the basic information layer database. The address data processing unit is used to input address allocation label data and clock domain frequency mapping table into the address space layer database, and output the address mapping table through the address space layer database; the address mapping table contains clock domain association information. The constraint data processing unit is used to input constraint annotation data and address mapping table into the constraint layer database, and output constraint file set through the constraint layer database; The component data processing unit is used to input the verification component annotation data and constraint file set into the configuration layer database, and output the test bench configuration file set through the configuration layer database; The parameter data processing unit is used to input parameter annotation data and test bench configuration file sets into the parameter layer database, and output parameter configuration files through the parameter layer database.

[0063] Test set generation module 330 includes: The template processing unit is used to generate a test set corresponding to the integrated circuit under test by means of the functional plug-in, based on the parameter configuration file, the pre-integrated test set template and the test set generation script.

[0064] Test suite running module 340 includes: The verification report generation unit is used to simulate the test set and generate a structured verification report for the integrated circuit under test based on the simulation results and the pre-integrated verification report generation script through the functional plug-in.

[0065] The above-described apparatus can execute the methods provided in all the foregoing embodiments of the present invention, and has the corresponding functional modules and beneficial effects for executing the above methods. Technical details not described in detail in the embodiments of the present invention can be found in the methods provided in all the foregoing embodiments of the present invention.

[0066] Figure 6A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0067] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) or a random access memory (RAM), communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 12 or loaded from the storage unit 18 into the random access memory 13. The random access memory 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, the read-only memory 12, and the random access memory 13 are interconnected via a bus 14. Input / output (I / O) interfaces are also connected to the bus 14.

[0068] Multiple components in electronic device 10 are connected to input / output interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0069] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processing (DSP) processors, and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as integrated circuit verification methods.

[0070] In some embodiments, the integrated circuit verification method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via read-only memory 12 and / or communication unit 19. When the computer program is loaded into random access memory 13 and executed by processor 11, one or more steps of the integrated circuit verification method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the integrated circuit verification method by any other suitable means (e.g., by means of firmware).

[0071] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0072] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0073] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0074] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0075] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0076] A computing system can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and Virtual Private Servers (VPS) in terms of management difficulty and weak business scalability.

[0077] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for verifying integrated circuits, characterized in that, The method includes: Obtain the verification description data corresponding to the integrated circuit under test, and perform structured annotation on the verification description data; the verification description data includes hardware architecture data and verification component configuration data; The labeled verification description data is input into a multi-level database sequence. The verification description data is processed through the database sequence, and the parameter configuration file corresponding to the integrated circuit under test is output. The parameter configuration file is input into the function plugin, which generates a test set corresponding to the integrated circuit under test based on the parameter configuration file and the pre-integrated toolkit. The test set is simulated and run, and a verification report corresponding to the integrated circuit under test is generated based on the running results; The multi-level database sequence includes a basic information layer database, an address space layer database, a constraint layer database, a configuration layer database, and a parameter layer database. The labeled verification description data is input into a multi-level database sequence. The verification description data is processed through the database sequence, and the parameter configuration file corresponding to the integrated circuit under test is output. This includes: inputting the labeled verification description data into the basic information layer database, the address space layer database, the constraint layer database, the configuration layer database, and the parameter layer database in sequence, and outputting the parameter configuration file through the parameter layer database.

2. The method according to claim 1, characterized in that, The annotated verification description data is sequentially input into the basic information layer database, address space layer database, constraint layer database, configuration layer database, and parameter layer database. The parameter layer database then outputs a parameter configuration file, including: Input the clock domain annotation data into the basic information layer database, and output the clock domain frequency mapping table through the basic information layer database; The address allocation label data and clock domain frequency mapping table are input into the address space layer database, and the address mapping table is output through the address space layer database; the address mapping table contains clock domain association information. Input the constraint annotation data and address mapping table into the constraint layer database, and output the constraint file set through the constraint layer database; Input the verification component annotation data and constraint file set into the configuration layer database, and output the test bench configuration file set through the configuration layer database; Input the parameter annotation data and test bench configuration file set into the parameter layer database, and output the parameter configuration file through the parameter layer database.

3. The method according to claim 1, characterized in that, The functional plugin generates a test set corresponding to the integrated circuit under test based on the parameter configuration file and the pre-integrated toolkit, including: The functional plugin generates a test set corresponding to the integrated circuit under test based on the parameter configuration file, the pre-integrated test set template, and the test set generation script.

4. The method according to claim 1, characterized in that, The verification description data is structured and annotated, including: Establish a unified tagging system based on the existing data tags in the hardware architecture data; The hardware architecture data and verification component configuration data are structured and labeled using the unified tagging system.

5. The method according to claim 4, characterized in that, After using the unified tagging system to structurally annotate the hardware architecture data and verification component configuration data, the method further includes: Perform integrity checks on the tags corresponding to the hardware architecture data and the verification component configuration data, respectively; and / or, A cross-reference verification algorithm is used to verify the tags corresponding to the hardware architecture data and the verification component configuration data, respectively.

6. The method according to claim 1, characterized in that, The test set is simulated and run, and a verification report corresponding to the integrated circuit under test is generated based on the running results, including: The test set is simulated and run. Based on the running results and the pre-integrated verification report, the functional plugin generates a script to generate a structured verification report for the integrated circuit under test.

7. A verification device for integrated circuits, characterized in that, The device includes: The data annotation module is used to acquire the verification description data corresponding to the integrated circuit under test and to perform structured annotation on the verification description data; the verification description data includes hardware architecture data and verification component configuration data; The data weaving module is used to input the labeled verification description data into a multi-level database sequence, process the verification description data through the database sequence, and output the parameter configuration file corresponding to the integrated circuit under test. The test set generation module is used to input the parameter configuration file into the function plugin, and the function plugin generates the test set corresponding to the integrated circuit under test according to the parameter configuration file and the pre-integrated toolkit. The test set execution module is used to simulate the test set and generate a verification report for the integrated circuit under test based on the execution results. The multi-level database sequence includes a basic information layer database, an address space layer database, a constraint layer database, a configuration layer database, and a parameter layer database. The labeled verification description data is input into a multi-level database sequence. The verification description data is processed through the database sequence, and the parameter configuration file corresponding to the integrated circuit under test is output. This includes: inputting the labeled verification description data into the basic information layer database, the address space layer database, the constraint layer database, the configuration layer database, and the parameter layer database in sequence, and outputting the parameter configuration file through the parameter layer database.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the verification method for the integrated circuit according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the verification method for the integrated circuit according to any one of claims 1-6.

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