A test system for reading and writing performance and abnormal power-off recovery capability of a memory card

Abstract

The purpose of this application is to provide a test system for the read / write performance and abnormal power failure recovery capability of a memory card. The system includes: a device under test and the memory card installed therein, a main control computer, a data acquisition module, a programmable DC power supply and a high-speed solid-state relay. It realizes automated, repeatable and high-precision closed-loop verification of the long-term reliability, abnormal power failure response capability and data integrity recovery capability of the memory card in the real use scenario of the device under test.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a testing system for the read / write performance and abnormal power-loss recovery capability of a memory card. Background Technology

[0002] In existing technologies, local storage (typically using MicroSD cards) is a crucial element in ensuring video data security, particularly in fields like smart security cameras and dashcams. However, as a NAND Flash-based storage medium, local storage cards are inherently limited by their physical characteristics, making them highly susceptible to file system corruption or data loss during abnormal power outages (such as power failures or accidental insertion / removal). Currently, industry testing of camera storage cards primarily focuses on two aspects: first, basic compatibility testing—verifying whether the camera can recognize and read / write storage cards of different brands and capacities; and second, simple aging testing—observing whether the storage card exhibits obvious malfunctions such as write failures through prolonged continuous recording. These current testing methods still have significant shortcomings: they cannot quantify the performance degradation of storage cards after long-term use (such as decreased write speed), and they cannot effectively simulate and verify the robustness of the camera firmware's file system recovery mechanism and the maximal protection of users' critical recorded data under frequent real-world "abnormal power outage" scenarios. Therefore, existing technologies for testing local memory cards in devices such as smart security cameras and dashcams still have the following technical shortcomings: There is a lack of quantitative assessment of the performance of memory cards throughout their entire lifecycle. For example, existing tests cannot simulate the complete process from a new card to the end of its lifespan, and cannot predict in advance problems such as stuttering and frame drops that may occur after long-term use. It is impossible to effectively verify the reliability of data under abnormal power failure. For example, existing tests are mostly static functional checks, lacking the ability to accurately inject abnormal power failure events during dynamic recording and to perform automated and refined analysis of data recovery results after power failure. The testing process is highly dependent on manual labor, which is inefficient and subjective. For example, the entire testing process requires a lot of manual intervention and visual inspection, making it difficult to achieve large-scale, highly consistent automated testing and failing to meet the needs of modern intelligent manufacturing. Summary of the Invention

[0003] One objective of this application is to provide a test system for the read / write performance and abnormal power failure recovery capability of a memory card, with the aim of performing automated, repeatable, and high-precision closed-loop verification of the long-term reliability, abnormal power failure response capability, and data integrity recovery capability of the memory card in the real-world usage scenarios of the device under test.

[0004] According to one aspect of this application, a test system for the read / write performance and abnormal power-loss recovery capability of a memory card is provided. The system includes: a device under test (DUT) and the DUT installed therein, a main control computer, a data acquisition module, a programmable DC power supply, and a high-speed solid-state relay. The main control computer controls the device under test to enter a high-intensity recording mode, and at the same time starts the log collection service program of the data acquisition module to record the timestamp sequence of all I / O events and return the file system operation log. When the power-down trigger condition is met, the main control computer outputs a high-level pulse signal to the programmable DC power supply, driving the high-speed solid-state relay to cut off the power supply circuit of the device under test within 1 millisecond, so that the device under test is instantly powered down. After the preset power outage duration is maintained in the power-off state, the main control computer sends a low-level signal again to cause the high-speed solid-state relay to close again and restore power supply; After the device under test is powered on, the firmware's built-in file system self-test program is automatically executed to perform a self-test on the storage card under test, and the data acquisition module synchronously records the mount log during the restart mount process; After the device under test completes startup and re-enters recording mode, the main control computer obtains complete logs and metadata before and after the power failure from the data acquisition module, performs data integrity verification, and quantifies all verification results into a data integrity score. A structured test report is generated by summarizing the context information, recovery time, and data integrity verification score for each power outage event.

[0005] Furthermore, in the above system, the device under test is an intelligent device with a camera function, and has a memory card slot inside for installing the memory card under test; The programmable DC power supply is connected to the input terminal of the high-speed solid-state relay via a set of wires, and the output terminal of the high-speed solid-state relay is connected to the power input terminal of the device under test via another set of wires. The main control computer is connected to the control terminal of the high-speed solid-state relay through a digital I / O interface, with a response time of less than 10 microseconds; at the same time, it establishes communication links with the data acquisition module and the device under test through USB / network data interfaces respectively. The data acquisition module is connected to the debug port or video stream output port of the device under test via a USB 3.0 or Ethernet interface, and is used to capture kernel logs, file system operation logs and video frame metadata in real time. The system also includes an environmental simulation chamber with an internal support frame for fixing the device under test. The environmental simulation chamber is a constant temperature and humidity chamber, and temperature and humidity sensors are integrated on the chamber walls. The signal output terminals of the temperature and humidity sensors are connected to the environmental monitoring unit of the main control computer through an analog input channel.

[0006] Furthermore, the system further includes a power-down control unit, which is composed of the programmable DC power supply, the high-speed solid-state relay, the power input terminal of the device under test, and the digital I / O interface of the main control computer. The positive output terminal of the programmable DC power supply is connected to the common terminal COM of the high-speed solid-state relay, the normally open terminal NO of the high-speed solid-state relay is connected to the positive terminal of the power input terminal of the device under test, and the negative output terminal of the programmable DC power supply is directly connected to the negative terminal of the power input terminal of the device under test, thus forming a complete power supply circuit for the device under test. The control signal terminal of the high-speed solid-state relay is connected to a GPIO pin in the digital I / O interface of the host computer via a shielded twisted-pair cable. This GPIO pin is configured in push-pull output mode, outputting a 3.3V or 5V logic level to drive the internal optocoupler isolation circuit of the high-speed solid-state relay. The high-speed solid-state relay is selected with a response time of less than 10 microseconds, a conduction voltage drop of less than 0.1V, and a maximum load current of not less than 5A, ensuring that the power supply circuit of the device under test can be completely cut off within 1 millisecond after a power-down command is triggered.

[0007] Furthermore, in the above system, the main control computer continuously parses the file system operation logs returned by the data acquisition module. When it detects that the file system operation logs contain information indicating that the file system is performing a modification write storage operation or a log commit operation, it is determined to be a critical write node, triggering the main control computer to immediately output a high-level pulse signal to the programmable DC power supply through the digital I / O interface.

[0008] Furthermore, in the above system, the data acquisition module establishes a bidirectional data channel with the device under test via a USB / network data interface; The data acquisition module has an embedded Linux system running a log acquisition service program. This program communicates with the UART debug port of the device under test via a USB CDC virtual serial port protocol, receiving and caching kernel print information and file system operation logs in real time. Simultaneously, the data acquisition module connects to the video stream server of the device under test via an RTSP client protocol, subscribes to the main stream or sub-stream, and parses the timestamp, frame type, and sequence number fields in the H.264 / H.265 NAL unit header of each video frame to form a structured record of video stream metadata. All collected file system operation logs and metadata are stored in the local SSD of the data acquisition module after being aligned with timestamps, and are synchronized to the database of the main control computer in real time via TCP / IP protocol.

[0009] Furthermore, in the above system, when it is necessary to simulate the impact of high temperature and high humidity environment on the reliability of the memory card under test, the device under test is fixed on a non-metallic bracket inside the environment simulation chamber. The temperature control range inside the environmental simulation chamber is -10℃ to +70℃, and the humidity control range is 20%RH to 95%RH. The temperature and humidity sensor is installed inside the environmental simulation chamber near the device under test. The real-time measurement value of the temperature and humidity sensor is transmitted to the environmental monitoring unit of the main control computer via RS485 bus. The main control computer sends control commands to the controller of the environmental simulation chamber to adjust the temperature and humidity according to the preset environmental stress profile, thereby realizing closed-loop control of the temperature and humidity in the environmental simulation chamber.

[0010] Furthermore, in the above system, the data integrity verification includes the following steps: Compare the timestamp of the last video frame before the power outage with the timestamp of the first video frame after the power outage, and calculate whether the time interval before and after the power outage exceeds the preset time threshold. If so, it is determined that there is a recording interruption. Check if the CRC32 checksum of the last video file before the power outage is consistent with the actual checksum of the video file after the power outage. If not, mark it as corrupted data. Verify that there are any incomplete transaction rollback records in the file system operation log; The total number of video files before and after the power outage is counted to determine if some files were lost due to the power outage. If the total number of video files decreases, it indicates that some files were lost.

[0011] Furthermore, in the above system, the main control computer operates based on a test control platform developed in Python. This test control platform integrates a log parsing engine, a power failure trigger decision-maker, a data verification module, and a report generator. The preset test strategy loaded by the main computer includes the number of aging cycles, the duration of each recording round, the video encoding bitrate, the power failure trigger conditions, and environmental parameters. The preset test strategy is configured to have multiple aging and power failure cycles. The data acquisition module adopts an FPGA+ARM architecture; The firmware of the device under test needs to have open debug ports and RTSP stream permissions, and support recording start and stop control via network commands; All hardware connections in this system use shielded cables and are properly grounded to avoid electromagnetic interference affecting the accuracy of power-down timing. The main control computer, the data acquisition module, and the controller of the environmental simulation chamber in the system are all connected to the same local area network and time synchronization is achieved through the NTP protocol to ensure that the timestamps of all events have microsecond-level alignment accuracy.

[0012] Furthermore, the system described above also includes: The high-speed solid-state relay is replaced with an electronic switching circuit composed of an N-channel MOSFET. The electronic switching circuit is integrated inside the device under test and is remotely controlled by the host computer to achieve power-off. The gate of the electronic switching circuit is connected to the digital I / O interface of the host computer after optocoupler isolation. The source of the electronic switching circuit is connected to the power input terminal of the device under test. The drain of the electronic switching circuit is connected to the positive output terminal of the programmable DC power supply. The freewheeling diode of the electronic switching circuit is connected in parallel across the MOSFET to absorb the back electromotive force of the inductive load.

[0013] Furthermore, in the above system, the recording parameters in the high-intensity recording mode include resolution, frame rate, bitrate, and loop coverage mode. The mount log includes bad block scan results and inode repair record set video file index reconstruction logs.

[0014] Compared with existing technologies, this application provides a testing system for the read / write performance and abnormal power-loss recovery capability of a memory card. The system includes: a device under test (DUT) and the DUT installed therein, a main control computer, a data acquisition module, a programmable DC power supply, and a high-speed solid-state relay. The main control computer controls the DUT to enter a high-intensity recording mode and simultaneously starts the log acquisition service program of the data acquisition module to record the timestamp sequence of all I / O events and return the file system operation log. When a power-loss trigger condition is met, the main control computer outputs a high-level pulse signal to the programmable DC power supply, driving the high-speed solid-state relay to cut off the power supply circuit of the DUT within 1 millisecond, causing the DUT to instantly lose power. After the power-loss state is maintained for a preset power-off duration, the main control computer sends another signal... A low-level signal causes the high-speed solid-state relay to close again, restoring power supply. After the device under test (DUT) is powered on, the firmware's built-in file system self-test program automatically performs a self-test on the DUT. The data acquisition module simultaneously records the mounting log during the restart and mounting process. After the DUT completes startup and re-enters recording mode, the main control computer obtains the complete logs and metadata before and after the power outage from the data acquisition module and performs data integrity verification, quantifying all verification results into a data integrity score. The context information, recovery time, and data integrity verification score of each power outage event are summarized to generate a structured test report, realizing automated, repeatable, and high-precision closed-loop verification of the long-term reliability, abnormal power outage response capability, and data integrity recovery capability of the memory card in the real-world usage scenario of the DUT. Attached Figure Description

[0015] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This diagram illustrates the overall structure of a memory card read / write performance and abnormal power-loss recovery capability testing system according to one aspect of this application. Figure 2 A circuit connection diagram of the power-loss control unit in a test system for the read / write performance and abnormal power-loss recovery capability of a memory card according to one aspect of this application is shown. Figure 3 This diagram illustrates the data interaction between the data acquisition module and the device under test in a test system for the read / write performance and abnormal power loss recovery capability of a memory card according to one aspect of this application. Figure 4 This diagram illustrates the layout of a test system including an environmental simulation chamber in a test system for testing the read / write performance and abnormal power loss recovery capability of a memory card according to one aspect of this application. Figure 5The diagram shows the workflow timing of a memory card read / write performance and abnormal power-loss recovery capability testing system according to one aspect of this application. Detailed Implementation

[0016] The present application will now be described in further detail with reference to the accompanying drawings.

[0017] In a typical configuration of this application, the terminal, the device of the service network, and the trusted party all include one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0018] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0019] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0020] like Figure 1 As shown, Figure 1 A schematic diagram of the overall structure of a test system for the read / write performance and abnormal power loss recovery capability of a memory card, as proposed in one aspect of this application, is provided. The system includes: a device under test (DUT) and the memory card installed therein, a main control computer, and a data acquisition module (corresponding to...). Figure 1The system includes a high-speed data acquisition and monitoring module, a programmable DC power supply, a high-speed solid-state relay, and an optional environmental simulation chamber. The device under test (DUT) includes, but is not limited to, intelligent devices with camera capabilities, such as smart cameras and smart vehicle recorders. The DUT's memory card slot contains the memory card under test. The positive and negative output terminals of the programmable DC power supply are connected to the DUT's power input terminals via normally open contacts of the high-speed solid-state relay. The control terminal of the high-speed solid-state relay is connected to the digital I / O interface of the host computer, with a response time of less than 10 microseconds. The host computer communicates with the data acquisition module via Ethernet or USB 3.0. The data acquisition module accesses the DUT's debug port or video stream output port via a USB CDC virtual serial port or RTSP stream protocol, capturing kernel logs, file system operation logs (such as ext4 journal records), and video frame metadata in real time. The environmental simulation chamber is a constant temperature and humidity chamber with internal supports for fixing the DUT. Temperature and humidity sensors are integrated into the chamber walls, and feedback signals are connected to the host computer's environmental monitoring unit.

[0021] The specific testing workflow in this system is as follows: The main control computer controls the device under test to enter a high-intensity recording mode, and simultaneously starts the log acquisition service program of the data acquisition module to record the timestamp sequence of all I / O events and return it to the file system operation log. Here, the main control computer loads a preset test strategy, which defines the number of aging cycles, the duration of each recording round, the video encoding bitrate, power failure trigger conditions (such as detecting that the file system is performing an fsync operation), and environmental parameters. After the system starts, the main control computer uses network commands to put the device under test into the high-intensity recording mode, and the data acquisition module begins recording the timestamp sequence of all I / O events. The recording parameters in the high-intensity recording mode include resolution, frame rate, bitrate, and loop coverage mode.

[0022] When the power-down trigger condition is met, the main control computer outputs a high-level pulse signal to the programmable DC power supply, driving the high-speed solid-state relay to cut off the power supply circuit of the device under test within 1 millisecond, so that the device under test is instantly powered down. After the power failure state is maintained for a preset power failure duration, the main control computer sends a low-level signal again to cause the high-speed solid-state relay to close again and restore power supply. It should be noted that the preset power failure duration includes, but is not limited to, any time length with any value. In a preferred embodiment of this application, the preset power failure duration is preferably 5 seconds, etc.

[0023] After the device under test is powered on, the firmware's built-in file system self-test program (used for file self-testing and repair, etc.) is automatically executed to perform a self-test on the storage card under test. The data acquisition module synchronously records the mount log during the restart and mounting process. The mount log includes bad block scan results and inode repair record set video file index reconstruction log.

[0024] After the device under test completes startup and re-enters recording mode, the main control computer obtains the complete logs and metadata before and after the power outage from the data acquisition module, and performs data integrity verification, such as comparing the number of files before and after the power outage, the start and end timestamps of each recording segment, the integrity of key frames and CRC check values, etc., to determine whether the data is lost or damaged, and quantifies all the verification results into a data integrity score. Finally, the system summarizes the context information, recovery time, and data integrity verification score of each power outage event to generate a structured test report, and stores the structured test report in the database.

[0025] In the embodiments of this application, the components in the system construct a reproducible, quantifiable, and automated storage reliability verification platform through precise timing coordination and data closed-loop feedback.

[0026] In the embodiments of this application, the concept of "full lifecycle" of memory cards is introduced into testing for the first time. This not only enables the detection of early faults but also predicts performance bottlenecks after long-term use, ensuring the comprehensiveness of the test. By precisely injecting abnormal power outages during dynamic recording, the test highly replicates the pain points of real users, making the test results more valuable and authentic. The entire testing process is highly automated, with the system handling everything from power outage triggering to result analysis, eliminating human interference and ensuring the consistency and objectivity of the test. Multiple devices can be tested in parallel, greatly improving testing efficiency and meeting the needs of large-scale production. Through testing with this system, firmware versions with more robust file system recovery mechanisms and more reliable memory card combinations can be selected, fundamentally protecting user data security, improving product quality and user experience, and enhancing brand trust.

[0027] Following the above embodiments of this application, one aspect of this application proposes a test system for the read / write performance and abnormal power loss recovery capability of a memory card. The purpose is to conduct automated, repeatable, and high-precision closed-loop verification of the long-term reliability, abnormal power loss response capability, and data integrity recovery capability of memory cards (such as MicroSD cards) in real-world use scenarios of smart devices with camera functions.

[0028] like Figure 1 As shown, the system consists of the device under test, a programmable DC power supply, a main control computer, and a data acquisition module (corresponding to...). Figure 1The system comprises a high-speed data acquisition and monitoring module and an optional environmental simulation chamber. The device under test (DUT) is an intelligent device with camera functionality. In a preferred embodiment, the DUT can be a smart security camera unit with an internal memory card slot (e.g., a standard MicroSD card slot) for installing the DUT memory card. The programmable DC power supply is connected to the input terminal of the high-speed solid-state relay via a set of wires, and the output terminal of the high-speed solid-state relay is connected to the power input terminal of the DUT via another set of wires. The main control computer is connected to the control terminal of the high-speed solid-state relay via a digital I / O interface, with a response time of less than 10 microseconds. Simultaneously, communication links are established with the data acquisition module and the DUT via USB / network data interfaces. The data acquisition module is connected to the debug port or video stream output port of the DUT via a USB 3.0 or Ethernet interface for real-time capture of kernel logs, file system operation logs, and video frame metadata.

[0029] Optionally, when environmental stress testing is enabled, the system further includes: an environmental simulation chamber, wherein the device under test is fixed on a bracket provided inside the environmental simulation chamber, the environmental simulation chamber is a constant temperature and humidity chamber, and the chamber wall of the environmental simulation chamber is integrated with temperature and humidity sensors, and the signal output terminal of the temperature and humidity sensors is connected to the environmental monitoring unit of the main control computer through an analog input channel.

[0030] Continuing with the above embodiments of this application, the system further includes: a power-down control unit, such as... Figure 2 As shown, the power-down control unit consists of the programmable DC power supply, the high-speed solid-state relay, the power input terminal of the device under test, and the digital I / O interface of the main control computer; wherein, the positive output terminal of the programmable DC power supply is connected to the common terminal (COM) of the high-speed solid-state relay, the normally open terminal (NO) of the high-speed solid-state relay is connected to the positive terminal of the power input terminal of the device under test, and the negative output terminal of the programmable DC power supply is directly connected to the negative terminal of the power input terminal of the device under test, thus forming a complete power supply circuit for the device under test; The control signal terminal of the high-speed solid-state relay is connected to a GPIO pin in the digital I / O interface of the host computer via a shielded twisted-pair cable. This GPIO pin is configured in push-pull output mode and can output a 3.3V or 5V logic level to drive the internal optocoupler isolation circuit of the high-speed solid-state relay. The high-speed solid-state relay is selected with a response time of less than 10 microseconds, a conduction voltage drop of less than 0.1V, and a maximum load current of not less than 5A, to ensure that the power supply circuit of the device under test can be completely cut off within 1 millisecond after a power-down command is triggered.

[0031] Continuing with the above embodiments of this application, as Figure 3 As shown, the data acquisition module (corresponding to) Figure 3 The high-speed data acquisition and monitoring module establishes a bidirectional data channel with the device under test (DUT) via a USB / network data interface. Specifically, the data acquisition module has an embedded Linux system running a customized log acquisition service program. This program communicates with the DUT's UART debug port via a USB CDC-type virtual serial port protocol, receiving and caching kernel print information (such as dmesg logs) and file system operation logs (such as journal log entries in the ext4 file system) in real time. Simultaneously, the data acquisition module connects to the DUT's video stream server via the RTSP client protocol, subscribes to the main or sub-stream, and parses the timestamp (PTS / DTS), frame type (I / P / B frame), and sequence number fields in the H.264 / H.265 NAL unit header of each video frame to form a structured record of video stream metadata. All acquired file system operation logs and metadata are timestamped and stored on the data acquisition module's local SSD, and synchronized in real time to the host computer's database via TCP / IP protocol.

[0032] Continuing with the above embodiments of this application, as Figure 4 As shown, when simulating the impact of harsh environments such as high temperature and high humidity on the reliability of the memory card under test, the device under test is fixed on a non-metallic bracket inside the environmental simulation chamber to ensure unobstructed heat dissipation and easy replacement of the memory card slot. The environmental simulation chamber is a constant temperature and humidity test chamber conforming to IEC60068-2 standard, with an internal temperature control range of -10℃ to +70℃ and a humidity control range of 20%RH to 95%RH. The temperature and humidity sensor is a high-precision digital sensor installed inside the environmental simulation chamber near the device under test. The real-time measurement values ​​of the temperature and humidity sensor are transmitted to the environmental monitoring unit of the main control computer via an RS485 bus. The main control computer sends control commands to the controller of the environmental simulation chamber to adjust the temperature and humidity according to a preset environmental stress profile (such as 85℃ / 85%RH for 48 hours), thus achieving closed-loop control of the temperature and humidity within the environmental simulation chamber.

[0033] Continuing with the above embodiments of this application, the system further includes: the main control computer continuously parses the file system operation log returned by the data acquisition module; when it detects that the file system operation log contains an indication that the file system is performing a modification write storage operation or a log commit operation, it is determined to be a critical write node, and the main control computer is triggered to immediately output a high-level pulse signal to the programmable DC power supply through the digital I / O interface.

[0034] In practical embodiments, such as Figure 5 As shown, the entire testing process is driven by the main control computer executing a pre-loaded preset test strategy script. The specific steps are as follows: First, the main control computer sends a high-intensity recording command to the device under test via SSH or Telnet. This command carries recording parameters including: resolution 1920×1080, frame rate 25fps, bitrate 4Mbps, and loop overlay mode. Simultaneously, it starts the data acquisition module (corresponding to...). Figure 5 The log collection service program corresponding to the high-speed data acquisition module in the middle; Subsequently, the main control computer continuously decodes the file system operation logs returned by the data acquisition module. When keywords such as "ext4_sync_file" or "jbd2_commit_transaction" are detected in the system file operation logs, it indicates that the file system is performing fsync or log commit operations, which is identified as a critical write node. At this time, the main control computer immediately outputs a high-level pulse signal to the high-speed solid-state relay through the digital I / O interface, driving the high-speed solid-state relay to disconnect the power supply circuit within 1 millisecond, causing the device under test to lose power instantly. After the power-off state lasts for 5 seconds, the main control computer outputs a low-level signal again to close the high-speed solid-state relay, restoring power. After the device under test is powered on, it automatically executes the file system self-test program built into its firmware (such as e2fsck). The data acquisition module synchronously records the mount log during the mount process. This mount log includes bad block scan results, inode repair records, and video file index reconstruction logs, etc. After the device under test completes startup and re-enters the recording state, the main control computer obtains the complete logs and metadata before and after the power-off from the data acquisition module and performs automated data integrity verification. Specifically, the data integrity verification includes the following steps: Compare the timestamp of the last video frame before the power outage with the timestamp of the first video frame after the power outage, and calculate whether the time interval before and after the power outage exceeds a preset time threshold. If so, it is determined that there is a recording interruption. The preset time threshold can be any time value. In a preferred embodiment of this application, the preset time threshold can preferably be 2 seconds. Check if the CRC32 checksum of the last video file before the power outage is consistent with the actual checksum of the video file after the power outage. If not, mark it as corrupted data. Verify that there are any incomplete transaction rollback records in the file system operation log; To determine whether the total number of video files before and after the power outage resulted in the loss of some files, for example, by analyzing the change in the total number of video files before and after the power outage, if the total number of video files decreased, it indicates that some files were lost.

[0035] All verification results are quantified into a data integrity score, and stored in a structured test report database along with the context of the power outage event (such as write load at the time of power outage, ambient temperature and humidity, amount of data written to the memory card, etc.) and recovery time. This process is repeated to summarize the context information, recovery time and data integrity verification score of each power outage event to generate a structured test report, thus obtaining the structured test report corresponding to all power outage events.

[0036] Following the above embodiments of this application, in actual implementation, the main control computer operates based on a test control platform developed in Python. This test control platform integrates a log parsing engine, a power-down trigger decision-maker, a data verification module, and a report generator. The preset test strategy loaded by the main database computer includes the number of aging cycles, the duration of each recording round, the video encoding bitrate, the power-down trigger conditions, and environmental parameters. The preset test strategy can be configured as multiple aging and power-down cycles, for example, triggering a power-down every 100GB of writing, and executing 1000 cycles in total to simulate several years of usage scenarios.

[0037] The performance degradation of a memory card (such as a MicroSD card) throughout its entire lifecycle is quantified by sequential read / write speed tests (using the fio tool) after each cycle ends, and the number of bad blocks is tracked by reading the memory card's SMART information or the ECC error count in the kernel log.

[0038] The data acquisition module adopts an FPGA+ARM architecture to ensure that all metadata can be captured without packet loss even under high bitrate video streams.

[0039] The firmware of the device under test must have open debug ports and RTSP stream permissions, and support recording start and stop control via network commands. This is a prerequisite for implementing the test system in the embodiments of this application.

[0040] All hardware connections in this system use shielded cables and are properly grounded to avoid electromagnetic interference affecting the timing accuracy during power outages.

[0041] The main control computer, the data acquisition module, and the controller of the environmental simulation chamber in the system are all connected to the same local area network and time synchronization is achieved through the NTP protocol to ensure that the timestamps of all events have microsecond-level alignment accuracy.

[0042] Without the environmental simulation chamber, the system can be tested in a normal temperature and humidity laboratory environment, where the temperature and humidity sensors do not participate in the operation, but the rest of the process remains unchanged.

[0043] Continuing with the above embodiments of this application, the system further includes: The high-speed solid-state relay is replaced with an electronic switching circuit composed of an N-channel MOSFET. This electronic switching circuit is integrated inside the device under test (DUT) and remotely controlled by the host computer to achieve power-off, resulting in a faster response speed. The gate of the electronic switching circuit is connected to the digital I / O interface of the host computer via optocoupler isolation. The source of the electronic switching circuit is connected to the power input terminal of the DUT, and the drain of the electronic switching circuit is connected to the positive output terminal of the programmable DC power supply. The freewheeling diode of the electronic switching circuit is connected in parallel across the MOSFET to absorb the back electromotive force of the inductive load. This alternative solution also meets the sub-millisecond cutoff requirement.

[0044] During testing, if the device under test fails to properly mount a memory card (e.g., a MicroSD card) due to multiple power outages, the system automatically marks the memory card as faulty, terminates subsequent testing, and generates a final lifespan assessment report. All test data is encrypted and stored in a local database on the main control computer and can be exported to CSV or JSON format for further analysis.

[0045] In the embodiments of this application, in addition to monitoring logs through external interfaces, the data monitoring of collected logs and data can also be carried out by embedding lightweight probe code in the firmware of the device under test, which can directly report key file system operation log related events to the host computer over the network. This method provides more accurate data, but requires firmware modification.

[0046] During testing, accelerated aging can be achieved not only through high-intensity video recording, but also through low-level read and write cycles of the memory card using specialized Flash stress testing tools (such as f3write / f3read, etc.). This method of aging is more thorough, but it differs slightly from actual application scenarios.

[0047] In a preferred embodiment of this application, during the testing of a certain model of smart security camera's full lifecycle read / write performance and abnormal power-off recovery capability, the device under test is first installed on a non-metallic bracket inside an environmental simulation chamber, ensuring that its MicroSD card slot is oriented for easy replacement and good heat dissipation. The host computer establishes an SSH connection with the device under test via a USB / network data interface and communicates with the data acquisition module through the same interface. The positive output terminal of the programmable DC power supply is connected to the common terminal (COM) of the high-speed solid-state relay, and the normally open terminal (NO) of the high-speed solid-state relay is connected to the positive terminal of the power input terminal of the device under test via a wire, while the negative terminal is directly connected, forming a complete power supply circuit. The control terminal of the high-speed solid-state relay is connected to the GPIO pin in the digital I / O interface of the host computer via a shielded twisted pair cable. This GPIO pin is configured in push-pull output mode and is used to output logic levels to drive the internal optocoupler of the high-speed solid-state relay.

[0048] Before the test begins, the main control computer loads the preset test strategy: The system continuously records video at 1920×1080@25fps and 4Mbps bitrate. An abnormal power outage is triggered every 100GB of data written, and the cycle is repeated 1000 times. The environmental simulation chamber is set to a constant stress condition of 85℃ / 85%RH. Temperature and humidity sensors collect environmental parameters inside the chamber in real time and feed them back to the main control computer via RS485 bus. The computer then uses this data to adjust the controller of the environmental simulation chamber in a closed loop to maintain the set values.

[0049] Upon entering the testing phase, the host computer sends a command to the device under test (DUT) to start high-intensity recording, and simultaneously activates the log acquisition service program of the data acquisition module. This data acquisition module continuously receives kernel logs from the DUT's UART debug port via the USB CDC virtual serial port protocol, which includes journal transaction commit records for the ext4 file system. When the "jbd2_commit_transaction" log entry is parsed, it indicates that the device is currently in a critical window for writing file system metadata. The host computer immediately outputs a high-level pulse signal through the digital I / O interface, causing the high-speed solid-state relay to disconnect its normally open (NO) terminal within less than 1 millisecond, cutting off the power supply to the DUT. At this time, the DUT interrupts the ongoing file writing operation due to the sudden power loss, and incomplete page programming or block erasure operations may remain inside the MicroSD card.

[0050] After a 5-second power outage, the main control computer outputs a low-level signal, causing the high-speed solid-state relay to close again and restore power. After the device under test is powered on, its firmware automatically executes the file system self-test program: the e2fsck program performs a self-test on the MicroSD card, and the data acquisition module simultaneously captures the mount log during this process. This mount log includes bad block remapping records, inode table repair details, and video file index reconstruction logs. At the same time, the data acquisition module subscribes to the video stream of the device under test through the RTSP protocol, parses the PTS timestamp and frame sequence number in the H.264 NAL unit header, and forms a structured metadata stream.

[0051] After the device under test resumes normal recording, the main control computer obtains the complete dataset before and after the power outage from the data acquisition module and performs data integrity verification: First, compare the PTS of the last frame of video before the power outage with the PTS of the first frame of video after the power outage. If the time difference exceeds 2 seconds, it is determined that there is a recording interruption. Secondly, retrieve the CRC32 check value of the last video file before the power outage and compare it with the actual calculated value of the file after the power outage. If they do not match, the data is marked as corrupted. Next, check the file system log for rollback records such as "recovery required" or "orphan inode" to confirm whether there are any incomplete transactions. Finally, the total number of video files before and after the power outage was counted. If the number decreased, it indicates that some files were lost.

[0052] The above four indicators together constitute the data integrity score, which, along with contextual information such as the write load, ambient temperature and humidity, and total amount of data written at the time of the power outage, are stored in the structured database.

[0053] After each 100GB write operation, the host computer performs sequential read / write speed tests on the MicroSD card using the fio tool, and reads the ECC error count in its SMART attribute or the "uncorrectable error" entry in the kernel log to quantify performance degradation and bad block growth trends. If the MicroSD card cannot be mounted normally after three consecutive power outages, or if the data integrity score is lower than the threshold, the system determines that the card is faulty, terminates the test, and generates a lifespan assessment report. All test data is stored in the host computer's local database using AES-256 encryption and can be exported in JSON format for subsequent analysis.

[0054] In the above process, the main control computer, data acquisition module, and environmental simulation chamber controller are all connected to the same local area network and synchronize the system clock via the NTP protocol to ensure that the alignment accuracy of log timestamps, video PTS, and power-down trigger time reaches the microsecond level. The data acquisition module adopts an FPGA+ARM heterogeneous architecture, where the FPGA is responsible for high-speed parsing of the NAL unit header in the RTSP stream, and the ARM processor runs an embedded Linux system to handle log caching and network transmission, thus capturing all metadata without packet loss even at a high bit rate of 4Mbps. If an environmental simulation chamber is not available on site, the connection of temperature and humidity sensors can be omitted, and the rest of the process remains unchanged, with testing only performed under normal temperature and humidity conditions.

[0055] In summary, this application provides a testing system for the read / write performance and abnormal power-loss recovery capability of a memory card. The system includes: a device under test (DUT) and the DUT installed therein, a main control computer, a data acquisition module, a programmable DC power supply, and a high-speed solid-state relay. The main control computer controls the DUT to enter a high-intensity recording mode and simultaneously starts the log acquisition service program of the data acquisition module to record the timestamp sequence of all I / O events and return the file system operation log. When a power-loss trigger condition is met, the main control computer outputs a high-level pulse signal to the programmable DC power supply, driving the high-speed solid-state relay to cut off the power supply circuit of the DUT within 1 millisecond, causing the DUT to instantly lose power. After the power-loss state is maintained for a preset power-off duration, the main control computer sends a low-level pulse signal again. The signal causes the high-speed solid-state relay to close again, restoring power supply. After the device under test (DUT) is powered on, the firmware's built-in file system self-test program automatically performs a self-test on the DUT. The data acquisition module simultaneously records the mounting log during the restart and mounting process. After the DUT completes startup and re-enters recording mode, the main control computer obtains the complete logs and metadata before and after the power outage from the data acquisition module and performs data integrity verification, quantifying all verification results into a data integrity score. The context information, recovery time, and data integrity verification score of each power outage event are summarized to generate a structured test report, realizing automated, repeatable, and high-precision closed-loop verification of the long-term reliability, abnormal power outage response capability, and data integrity recovery capability of the memory card in the real-world usage scenario of the DUT.

[0056] It should be noted that this application can be implemented in software and / or a combination of software and hardware, for example, using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In one embodiment, the software program of this application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium, such as RAM memory, a magnetic or optical drive, a floppy disk, or similar devices. Furthermore, some steps or functions of this application can be implemented in hardware, for example, as circuitry that cooperates with a processor to perform the various steps or functions.

[0057] Furthermore, a portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. The program instructions invoking the methods of this application may be stored in a fixed or removable recording medium, and / or transmitted via data streams in broadcast or other signal carrying media, and / or stored in the working memory of a computer device operating according to the program instructions. Here, one embodiment of this application includes an apparatus comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein, when the computer program instructions are executed by the processor, the apparatus is triggered to operate the methods and / or technical solutions based on the foregoing embodiments of this application.

[0058] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within this application. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in the apparatus claims may also be implemented by a single unit or device in software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any particular order.

Claims

1. A system for testing the read / write performance and abnormal power-loss recovery capability of a memory card, wherein, The system includes: the device under test (DUT) and its installed memory card, a main control computer, a data acquisition module, a programmable DC power supply, and a high-speed solid-state relay. The main control computer controls the device under test to enter a high-intensity recording mode, and at the same time starts the log collection service program of the data acquisition module to record the timestamp sequence of all I / O events and return the file system operation log. When the power-down trigger condition is met, the main control computer outputs a high-level pulse signal to the programmable DC power supply, driving the high-speed solid-state relay to cut off the power supply circuit of the device under test within 1 millisecond, so that the device under test is instantly powered down. After the preset power outage duration is maintained in the power-off state, the main control computer sends a low-level signal again to cause the high-speed solid-state relay to close again and restore power supply; After the device under test is powered on, the firmware's built-in file system self-test program is automatically executed to perform a self-test on the storage card under test, and the data acquisition module synchronously records the mount log during the restart mount process; After the device under test completes startup and re-enters recording mode, the main control computer obtains complete logs and metadata before and after the power failure from the data acquisition module, performs data integrity verification, and quantifies all verification results into a data integrity score. A structured test report is generated by summarizing the context information, recovery time, and data integrity verification score for each power outage event.

2. The system according to claim 1, wherein, The device under test is an intelligent device with a camera function, and has a memory card slot inside for installing the memory card to be tested; The programmable DC power supply is connected to the input terminal of the high-speed solid-state relay via a set of wires, and the output terminal of the high-speed solid-state relay is connected to the power input terminal of the device under test via another set of wires. The main control computer is connected to the control terminal of the high-speed solid-state relay through a digital I / O interface, with a response time of less than 10 microseconds; at the same time, it establishes communication links with the data acquisition module and the device under test through USB / network data interfaces respectively. The data acquisition module is connected to the debug port or video stream output port of the device under test via a USB 3.0 or Ethernet interface, and is used to capture kernel logs, file system operation logs and video frame metadata in real time. The system also includes an environmental simulation chamber with an internal support frame for fixing the device under test. The environmental simulation chamber is a constant temperature and humidity chamber, and temperature and humidity sensors are integrated on the chamber walls. The signal output terminals of the temperature and humidity sensors are connected to the environmental monitoring unit of the main control computer through an analog input channel.

3. The system according to claim 1, wherein, The system also includes a power-down control unit, which is composed of the programmable DC power supply, the high-speed solid-state relay, the power input terminal of the device under test, and the digital I / O interface of the main control computer. The positive output terminal of the programmable DC power supply is connected to the common terminal COM of the high-speed solid-state relay, the normally open terminal NO of the high-speed solid-state relay is connected to the positive terminal of the power input terminal of the device under test, and the negative output terminal of the programmable DC power supply is directly connected to the negative terminal of the power input terminal of the device under test, thus forming a complete power supply circuit for the device under test. The control signal terminal of the high-speed solid-state relay is connected to a GPIO pin in the digital I / O interface of the host computer via a shielded twisted-pair cable. This GPIO pin is configured in push-pull output mode, outputting a 3.3V or 5V logic level to drive the internal optocoupler isolation circuit of the high-speed solid-state relay. The high-speed solid-state relay is selected with a response time of less than 10 microseconds, a conduction voltage drop of less than 0.1V, and a maximum load current of not less than 5A, ensuring that the power supply circuit of the device under test can be completely cut off within 1 millisecond after a power-down command is triggered.

4. The system according to claim 1, wherein, The main control computer continuously parses the file system operation logs returned by the data acquisition module. When it detects that the file system operation logs contain information indicating that the file system is performing a modification write storage operation or a log commit operation, it determines that it is a critical write node and triggers the main control computer to immediately output a high-level pulse signal to the programmable DC power supply through the digital I / O interface.

5. The system according to claim 1, wherein, The data acquisition module establishes a bidirectional data channel with the device under test via a USB / network data interface; The data acquisition module has an embedded Linux system running a log acquisition service program. This program communicates with the UART debug port of the device under test via a USB CDC virtual serial port protocol, receiving and caching kernel print information and file system operation logs in real time. Simultaneously, the data acquisition module connects to the video stream server of the device under test via an RTSP client protocol, subscribes to the main stream or sub-stream, and parses the timestamp, frame type, and sequence number fields in the H.264 / H.265 NAL unit header of each video frame to form a structured record of video stream metadata. All collected file system operation logs and metadata are stored in the local SSD of the data acquisition module after being aligned with timestamps, and are synchronized to the database of the main control computer in real time via TCP / IP protocol.

6. The system according to claim 2, wherein, When it is necessary to simulate the impact of high temperature and high humidity environment on the reliability of the memory card under test, the device under test is fixed on a non-metallic bracket inside the environment simulation chamber. The temperature control range inside the environmental simulation chamber is -10℃ to +70℃, and the humidity control range is 20%RH to 95%RH. The temperature and humidity sensor is installed inside the environmental simulation chamber near the device under test. The real-time measurement value of the temperature and humidity sensor is transmitted to the environmental monitoring unit of the main control computer via RS485 bus. The main control computer sends control commands to the controller of the environmental simulation chamber to adjust the temperature and humidity according to the preset environmental stress profile, thereby realizing closed-loop control of the temperature and humidity in the environmental simulation chamber.

7. The system according to any one of claims 1 to 6, wherein, The data integrity verification process includes the following steps: Compare the timestamp of the last video frame before the power outage with the timestamp of the first video frame after the power outage, and calculate whether the time interval before and after the power outage exceeds the preset time threshold. If so, it is determined that there is a recording interruption. Check if the CRC32 checksum of the last video file before the power outage is consistent with the actual checksum of the video file after the power outage. If not, mark it as corrupted data. Verify that there are any incomplete transaction rollback records in the file system operation log; The total number of video files before and after the power outage is counted to determine if some files were lost due to the power outage. If the total number of video files decreases, it indicates that some files were lost.

8. The system according to claim 1, wherein, The main control computer operates based on a test control platform developed in Python. This test control platform integrates a log parsing engine, a power failure trigger decision-maker, a data verification module, and a report generator. The preset test strategy loaded by the main computer includes the number of aging cycles, the duration of each recording round, the video encoding bitrate, the power failure trigger conditions, and environmental parameters. The preset test strategy is configured to have multiple aging and power failure cycles. The data acquisition module adopts an FPGA+ARM architecture; The firmware of the device under test needs to have open debug ports and RTSP stream permissions, and support recording start and stop control via network commands; All hardware connections in this system use shielded cables and are properly grounded to avoid electromagnetic interference affecting the accuracy of power-down timing. The main control computer, the data acquisition module, and the controller of the environmental simulation chamber in the system are all connected to the same local area network and time synchronization is achieved through the NTP protocol to ensure that the timestamps of all events have microsecond-level alignment accuracy.

9. The system according to claim 1, wherein, The system also includes: The high-speed solid-state relay is replaced with an electronic switching circuit composed of an N-channel MOSFET. The electronic switching circuit is integrated inside the device under test and is remotely controlled by the host computer to achieve power-off. The gate of the electronic switching circuit is connected to the digital I / O interface of the host computer after optocoupler isolation. The source of the electronic switching circuit is connected to the power input terminal of the device under test. The drain of the electronic switching circuit is connected to the positive output terminal of the programmable DC power supply. The freewheeling diode of the electronic switching circuit is connected in parallel across the MOSFET to absorb the back electromotive force of the inductive load.

10. The system according to claim 1, wherein, The recording parameters in the high-intensity recording mode include resolution, frame rate, bit rate, and loop overlay mode. The mount log includes bad block scan results and inode repair record set video file index reconstruction logs.

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