Automatic addressing circuit and method for a battery management system

Abstract

The application relates to the technical field of energy storage systems, and discloses an automatic addressing circuit and method of a battery management system. A host module sends an addressing start signal to each slave module through a controller area network and outputs a voltage signal to a first-level slave module through a control output circuit of the host module. A control output circuit of each slave module outputs a current signal to a signal acquisition circuit of a next-level slave module. The signal acquisition circuit of each slave module acquires the voltage or current signal output by the previous stage, converts the voltage or current signal into a voltage signal, and outputs the voltage signal to the control output circuit. The control output circuit compares the converted voltage signal with a preset value. If the voltage signal is within the preset value range, the control output circuit sets the address of the slave module accordingly. Each slave module returns its own address to the host module through the controller area network. The application can improve the efficiency and reliability of addressing, realize the combination of any battery pack, and has strong anti-interference performance.

Description

Technical Field

[0001] This application relates to the field of battery management systems for energy storage systems, and in particular to an automatic addressing circuit and method for a battery management system. Background Technology

[0002] With the rise of large-scale energy storage systems, the modularity of battery packs is becoming increasingly apparent. Combining battery packs of the same type into a single system is becoming more common; for example, a single 100V battery pack can be connected in series to form a 1500V battery system. In production and actual use, each battery pack has a Battery Management System (BMS). However, communication between BMSs requires different addresses. Traditional addressing methods include: Method 1 primarily involves addressing the BMS at the factory and then binding it to the battery pack. When assembling the battery system, assembly is based on the address. This method is not conducive to rapid assembly and scheduling during mass production, leading to additional production costs. Method 2 mainly involves placing "daisy-chain" signal lines in the battery pack system. The host then pulls the address identification lines sequentially via the Controller Area Network (CAN) and performs CAN communication to confirm and address each address. In practical applications, due to environmental interference (such as electromagnetic interference, ground offset, etc.) and frequent CAN message exchanges, unstable addressing signals and addressing timeouts often occur. Summary of the Invention

[0003] The purpose of this application is to provide an automatic addressing circuit and method for a battery management system, which can improve the efficiency and reliability of addressing, realize the combination of any battery pack, and at the same time have strong anti-interference ability.

[0004] In a first aspect, this application discloses an automatic addressing circuit for a battery management system, including a master module and several slave modules connected in sequence. The master module is communicatively connected to the several slave modules via a controller local area network. Each slave module includes a signal acquisition circuit and a control output circuit connected to each other. The master module includes the control output circuit. The control output circuit of the master module is connected to the signal acquisition circuit of the first-level slave module. The control output circuit of each slave module is connected to the signal acquisition circuit of the next-level slave module. The host module sends an addressing start signal to each slave module through the controller local area network and outputs a voltage signal to the first-level slave module through the control output circuit. The control output circuit of each slave module outputs a current signal to the signal acquisition circuit of the next-level slave module. The signal acquisition circuit of each slave module acquires the voltage or current signal output by the previous-level control output circuit, converts it into a voltage signal, and outputs it to the corresponding control output circuit. The control output circuit compares the converted voltage signal with a corresponding preset value. If the converted voltage signal is within the range of the preset value, the control output circuit sets the address of the slave module accordingly. Each slave module returns its own address to the master module via the controller LAN.

[0005] In a preferred embodiment, the signal acquisition circuit includes: The acquisition unit of the first-level slave module converts the current formed by the voltage signal output by the master module into a voltage signal. The acquisition units of the second to last-level slave modules convert the current signal output by the previous-level slave module into a voltage signal. The signal acquisition unit receives the converted voltage signal and outputs the converted voltage signal to the control output circuit through a serial peripheral interface.

[0006] In a preferred embodiment, the signal acquisition unit also provides a reference voltage to the control output circuit.

[0007] In a preferred embodiment, the signal acquisition circuit further includes: A power supply unit is used to provide DC power to the acquisition unit and the signal acquisition unit; A current protection unit is connected between the power supply unit and the acquisition unit.

[0008] In a preferred embodiment, the signal acquisition circuit further includes: A power supply unit is used to provide DC power to the acquisition unit and the signal acquisition unit; A first filtering unit is connected between the power supply unit and the signal acquisition unit.

[0009] In a preferred embodiment, the signal acquisition circuit further includes a second filtering unit, which is connected between the acquisition unit and the signal acquisition unit.

[0010] In a preferred embodiment, the signal acquisition circuit further includes a voltage regulator unit connected between the acquisition unit and ground.

[0011] In a preferred embodiment, the signal acquisition circuit further includes a first anti-reverse unit, one end of which is connected to the acquisition unit, and the other end of which receives the current signal.

[0012] In a preferred embodiment, the signal acquisition circuit further includes a port signal monitoring unit connected between the voltage or current signal and the signal acquisition unit.

[0013] In a preferred embodiment, the acquisition unit includes a first resistor, the first filtering unit includes a second resistor and a first capacitor, the second filtering unit includes a third resistor, a fourth resistor, a second capacitor, and a third capacitor, the current protection unit includes a fuse and a Zener diode, the voltage regulation unit includes a fourth capacitor, the first reverse protection unit includes a first diode, and the port signal monitoring unit includes a fifth resistor, a sixth resistor, and a fifth capacitor; wherein, one end of the fuse is connected to the power supply unit and one end of the second resistor, the other end of the fuse is connected to one end of the first resistor, one end of the second capacitor, one end of the Zener diode, one end of the third resistor, and one end of the fourth capacitor, the other end of the fourth capacitor is connected to the ground terminal, and the second resistor... The other end is connected to one end of the first capacitor and the signal acquisition unit. The other end of the first capacitor is grounded. The other end of the Zener diode, the other end of the first resistor, the other end of the second capacitor, and the other end of the fourth resistor are connected to the positive terminal of the first diode. One end of the third capacitor is connected to the other end of the third resistor and the signal acquisition unit. The other end of the third capacitor is connected to the other end of the fourth resistor and the signal acquisition unit. The negative terminal of the first diode is connected to one end of the fifth resistor and receives the current signal. The other end of the fifth resistor is connected to one end of the sixth resistor, one end of the fifth capacitor, and the signal acquisition unit. The other end of the sixth resistor is connected to the other end of the fifth capacitor and the signal acquisition unit.

[0014] In a preferred embodiment, the control output circuit includes: A signal output unit, comprising a digital-to-analog converter and a comparator, wherein the output of the digital-to-analog converter is connected to the positive input terminal of the comparator; A driving unit, the control terminal of which is connected to the output terminal of the signal output unit, and the first terminal outputs the current signal.

[0015] In a preferred embodiment, the control output circuit includes: A feedback unit is connected between the third terminal of the drive unit and the ground terminal; The third filtering unit is connected between the third terminal of the driving unit and the negative input terminal of the comparator.

[0016] In a preferred embodiment, the control output circuit further includes a second anti-reverse unit, which is connected to the first end of the drive unit.

[0017] In a preferred embodiment, the driving unit includes an NPN transistor, the feedback unit includes a seventh resistor, the third filtering unit includes an eighth resistor, a sixth capacitor, and a seventh capacitor, and the second anti-reverse unit includes a second diode; wherein, the base of the NPN transistor is connected to the output terminal of the comparator, the collector of the NPN transistor is connected to one end of the seventh resistor, one end of the eighth resistor, and one end of the seventh capacitor, the other end of the seventh resistor and one end of the sixth capacitor are connected to the negative input terminal of the comparator, and the other end of the seventh capacitor and the other end of the sixth capacitor are grounded.

[0018] In a preferred embodiment, the host module further includes the signal acquisition circuit, and the control output circuit of the last-stage slave module is connected to the signal acquisition circuit and outputs a corresponding current signal to the signal acquisition circuit of the host module; the host module sends an addressing end command to each slave module, and each slave module returns its own address to the host module through the controller local area network.

[0019] In a second aspect, this application discloses an automatic addressing method for a battery management system, comprising: The master module sends an addressing start signal to each slave module through the controller local area network and outputs a current signal to the first-level slave module through its control output circuit; The signal acquisition circuit of the first-level slave module converts the voltage signal into a current signal and compares it with a corresponding preset value. If the converted voltage signal is within the range of the corresponding preset value, the control output circuit sets the address of the slave module accordingly. The control output circuit of the second-level to last-level slave module outputs a current signal to the next-level slave module. The signal acquisition circuit of the second-level to last-level slave module acquires the current signal output by the previous-level control output circuit, converts it into a voltage signal, and outputs it to the control output circuit of the slave module. The control output circuit compares the converted voltage signal with a preset value. If the converted voltage signal is within the range of the corresponding preset value, the control output circuit sets the address of the slave module accordingly and outputs a current signal to the next-level slave module. Each slave module returns its own address to the master module via the controller LAN.

[0020] In a preferred embodiment, the range of preset values ​​for each slave module increases progressively.

[0021] The embodiments of this application have at least the following advantages over the prior art: 1. The addressing speed is improved. Addressing 8 slave modules simultaneously takes no more than 500ms, while CAN addressing of the same level takes about 2 seconds. 2. Improved addressing reliability: each module has a unique current address, resulting in strong anti-interference capability; 3. By combining the DAC and comparator inside the MCU with external circuitry for addressing, current source signal output can be achieved at a relatively low cost; 4. The idle acquisition channel of the AFE signal acquisition chip used for communication is utilized. The AFE high-series acquisition channel is cleverly used to complete the current acquisition under higher input voltage, thus avoiding the use of operational amplifiers. 5. The addressing process has a complete physical chain that allows for count feedback and confirmation; 6. The high-precision reference of the AFE is used as the DAC output reference voltage to replace the original external reference circuit, thereby improving accuracy; 7. The number of slave modules to be addressed can be arbitrarily changed, with a maximum support of 16.

[0022] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded. Attached Figure Description

[0023] Figure 1 This is a block diagram of an automatic addressing circuit for a battery management system according to one embodiment of this application.

[0024] Figure 2 This is a block diagram of a slave module according to one embodiment of this application.

[0025] Figure 3 This is a circuit diagram of the slave module according to one embodiment of this application.

[0026] Figure 4 This is a flowchart illustrating an automatic addressing method for a battery management system according to one embodiment of this application. Detailed Implementation

[0027] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0029] The first embodiment of this application relates to an automatic addressing circuit for a battery management system, the structure of which is as follows: Figure 1As shown, the automatic addressing circuit includes a master module and several sequentially connected slave modules (e.g., slave module 1, slave module 2, ..., slave module n). The master module communicates with each slave module via a Controller Area Network (CAN), and the slave modules are connected sequentially. Each slave module includes interconnected signal acquisition circuits and control output circuits, while the master module includes a control output circuit. The signal acquisition circuits and control output circuits of each level of the module are identical, as detailed below. The control output circuit of the master module is connected to the signal acquisition circuit of the first-level slave module, and the control output circuit of each slave module is connected to the signal acquisition circuit of the next-level slave module. The master module sends an addressing start signal to each slave module via CAN to begin addressing. It also outputs a voltage signal Adr_IN to the first-level slave module through its control output circuit. The first-level slave module uses the voltage signal converted from the current generated on its signal acquisition circuit based on the Adr_IN signal for addressing. Then, its control output circuit generates a current signal for the next-level slave module. Therefore, the control output circuit of each slave module outputs a current signal to the signal acquisition circuit of the next-level slave module. That is, the signal received at the Adr_IN port of the first-level slave module is a voltage signal, while the signals received at the Adr_IN port of the second to last-level slave modules are current signals. Each slave module's signal acquisition circuit receives the voltage or current signal Adr_IN output from the previous-level control output circuit, acquires it, converts it into a voltage signal, and outputs it to the corresponding control output circuit. The control output circuit compares the voltage signal with a corresponding preset value. If the voltage signal is within the preset value range, the control output circuit sets the address of the slave module accordingly. Furthermore, the control output circuit generates a current signal Adr_OUT based on the corresponding voltage signal and outputs it to the signal acquisition circuit of the next-level slave module for addressing.

[0030] As used in this article, the port Adr_IN, Adr_IN signal, voltage signal Adr_IN, and current signal Adr_IN have the same meaning, namely, the voltage or current signal on the port Adr_IN. Similarly, the port Adr_OUT, Adr_OUT signal, and current signal Adr_OUT have the same meaning, namely, the current signal on the port Adr_OUT.

[0031] After a preset time (e.g., 500ms), each slave module can return its address to the master module via CAN. The master module then acknowledges the addresses returned by each slave module. The specific preset time can be set according to the actual scenario, and this invention does not limit it.

[0032] Reference circuit block diagram of slave module Figure 2 As shown, each slave module includes a signal acquisition circuit and a control output circuit. The signal acquisition circuit includes a power supply unit, a current protection unit, an acquisition unit, a signal acquisition unit, a first filtering unit (e.g., filter unit 1), a second filtering unit (e.g., filter unit 2), a voltage regulation unit, a first reverse protection unit (e.g., reverse protection unit 1), and a port signal monitoring unit. The control output circuit includes a signal output unit, a drive unit, a feedback unit, a third filtering unit (e.g., filter unit 3), and a second reverse protection unit (e.g., reverse protection unit 2).

[0033] The power supply unit provides direct current (DC) to the acquisition unit and the signal acquisition unit. A current protection unit is connected between the power supply unit and the acquisition unit. Filter unit 1 is connected between the power supply unit and the signal acquisition unit. Filter unit 2 is connected between the acquisition unit and the signal acquisition unit. A voltage regulator unit connects the acquisition unit to ground. One end of the reverse protection unit 1 is connected to the acquisition unit, and the other end is connected to the voltage or current signal Adr_IN. A port signal monitoring unit is connected between the voltage or current signal Adr_IN and the signal acquisition unit. The acquisition unit converts the voltage or current signal Adr_IN into a voltage signal. The signal acquisition unit receives the voltage signal and outputs it to the control output circuit via a Serial Peripheral Interface (SPI). Specifically, the acquisition unit of the first-level slave module converts the current formed on the acquisition unit by the voltage signal Adr_IN output from the master module into a voltage signal. The acquisition units of the second to last-level slave modules convert the current signal Adr_IN output from the previous-level slave module into a voltage signal. The signal output unit includes a digital-to-analog converter (DAC) and a comparator. The output of the DAC is connected to the positive input of the comparator. The control terminal of the drive unit is connected to the output of the signal output unit, and the first terminal outputs the current signal Adr_OUT. The feedback unit is connected between the third terminal of the drive unit and ground. The filter unit 3 is connected between the third terminal of the drive unit and the negative input of the comparator. The anti-reverse unit 2 is connected to the first terminal of the drive unit. The drive unit generates the current signal Adr_OUT based on the received voltage signal, which serves as the current signal Adr_IN for the next stage input.

[0034] In this application, the current corresponding to each slave module address is unique, which has strong anti-interference ability. The slave modules do not need to be programmed one by one via CAN, and the addressing rate is improved. At the same time, the addressing of 8 slave modules takes no more than 500ms, while the CAN addressing of the same level takes about 2 seconds.

[0035] In addition, the signal acquisition unit also provides a reference voltage (VREF) to the control output circuit, eliminating the need for an external reference circuit to provide a reference voltage.

[0036] For details on the slave module's circuit structure, please refer to... Figure 3As shown, the acquisition unit includes a first resistor R24, the filtering unit includes a second resistor R30 and a first capacitor C10, the filtering unit 2 includes a third resistor R25, a fourth resistor R26, a second capacitor C9, and a third capacitor C7, the current protection unit includes a fuse F1 and a Zener diode Z1, the voltage regulation unit includes a fourth capacitor C12, the reverse protection unit 1 includes a first diode D12, and the port signal monitoring unit includes a fifth resistor R27, a sixth resistor R28, and a fifth capacitor C8. One end of the fuse F1 is connected to the power supply unit and one end of the second resistor R30, and the other end of the fuse F1 is connected to one end of the first resistor R24, one end of the second capacitor C9, one end of the Zener diode Z1, one end of the third resistor R25, and one end of the fourth capacitor C12. The other end of the fourth capacitor C12 is connected to ground. The other end of the second resistor R30 is connected to one end of the first capacitor C10 and the signal acquisition unit, and the other end of the first capacitor C10 is grounded. The other ends of the Zener diode Z1, the first resistor R24, the second capacitor C9, and the fourth capacitor C8 are also connected to the signal acquisition unit. The other end of resistor R26 is connected to the positive terminal of the first diode D12. One end of the third capacitor C7 is connected to the other end of the third resistor R25 and the signal acquisition unit. The other end of the third capacitor C7 is connected to the other end of the fourth resistor R26 and the signal acquisition unit. The negative terminal of the first diode D12 is connected to one end of the fifth resistor R27 and receives the current signal. The other end of the fifth resistor R27 is connected to one end of the sixth resistor R28, one end of the fifth capacitor C8 and the signal acquisition unit. The other end of the sixth resistor R28 is connected to the other end of the fifth capacitor C8 and the signal acquisition unit.

[0037] Continue to refer to Figure 3 As shown, the driving unit includes an NPN transistor Q1, the feedback unit includes a seventh resistor R23, the filter unit 3 includes an eighth resistor R31, a sixth capacitor C11, and a seventh capacitor C6, and the anti-reverse unit 2 includes a second diode D10. The base of the NPN transistor Q1 is connected to the output of the comparator (OPA in the figure), and the collector of the NPN transistor Q1 is connected to one end of the seventh resistor R23, one end of the eighth resistor R31, and one end of the seventh capacitor C6. The other end of the seventh resistor R23 and one end of the sixth capacitor C11 are connected to the negative input of the comparator, and the other ends of the seventh capacitor C6 and the sixth capacitor C11 are grounded.

[0038] Continue to refer to Figure 1As shown, the master module also includes the aforementioned signal acquisition circuit. The control output circuit of the last-stage slave module is connected to the signal acquisition circuit, ensuring a complete physical loop in the addressing process. After addressing is complete, the last-stage slave module outputs a current signal to the master module's signal acquisition circuit. The master module uses the current signal from the last-stage slave module to confirm the total number of addresses, thus verifying the correctness of the addressing process. Furthermore, upon receiving the current signal from the last-stage slave module, the master module sends an addressing completion command to each slave module. Each slave module then returns its address to the master module via the controller local area network to confirm addressing completion, without needing to wait a preset time before sending.

[0039] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0040] This invention employs a design approach combining MCU, current path, and AFE, enabling arbitrary battery pack combinations while exhibiting strong anti-interference capabilities, reducing the need for active command transmission by the CAN host, enabling one-click addressing, accelerating addressing efficiency, and maintaining compatibility with traditional addressing host modules. A system reference for this design is provided. Figure 1 As shown.

[0041] Master module: Responsible for slave addressing startup. It sends an addressing start message to each slave module via the CAN network, and then pulls the port DO high to start formal addressing. The port Adr_IN interface harness of the master module can be connected to or not connected to the port Adr_OUT of the last slave module. If connected, it can confirm the final physical addressing.

[0042] Slave module 1: Port Adr_IN receives the signal from port DO of the master module. After detecting the DO signal (i.e., the high-level signal from port DO), it sets its own address and then enables port Adr_OUT to output the current at address number 2.

[0043] Slave module n: Port Adr_IN receives the port Adr_OUT signal from the previous stage module, detects the current and identifies it as the corresponding address, and then outputs the current with address number n+1 from port Adr_OUT.

[0044] Internal design circuit reference for this design implementation Figure 2 and Figure 3 As shown.

[0045] Signal output unit: Integrated within the MCU used in this hardware design, it can output to the positive terminal of a comparator via a DAC. The output terminal of the comparator is connected to driver unit 1, and the negative terminal of the comparator is connected to filter unit 3. The signal output unit's C0 port is used to monitor the acquisition port signal, providing higher accuracy in identification and judgment.

[0046] Drive unit: An NPN transistor (Q1) is used as the input control for the low-side current signal. On the one hand, it works with the signal output unit, feedback unit and filter unit 3 to generate the current signal and generate a precise current signal Adr_OUT. On the other hand, it is used to bear the power loss of port Adr_IN when the voltage input is large.

[0047] Feedback Unit: This is the current sensing resistor (R23), which inputs the adjusted voltage to the signal output unit through filter unit 3 to complete precise feedback regulation. The source current generated by the drive unit is determined by R23, I=Vdac / R23, where Vdac is the output voltage of the digital-to-analog converter.

[0048] Filtering Unit 3: A filtering network formed by CRC filters out noise signals from external inputs, achieving good signal sampling and stabilizing the feedback loop. Specifically, C6 acts as an energy storage capacitor to stabilize the output waveform, while R31 and C11 perform internal and external coupling filtering when the current is turned on, and input feedback comparator.

[0049] Anti-reverse unit 2: This is implemented by unidirectional diode D10, which is used to protect the address addressing signal from reverse or negative pulses, and can avoid damage to the current generator caused by reverse circuit connection.

[0050] Power Supply Unit: The power source for the receiver to identify current signals. It comes from the clamped voltage of the module input and can vary arbitrarily within the supply voltage range (9~36V). It is connected to Filter Unit 1 and Current Protection Unit 1. The voltage signal provided by the power supply unit comes from the system voltage after voltage regulation and clamping, and no additional protection is required.

[0051] Filtering Unit 1: R25, R26, and C7 together form the RC filter for C18 and C17 of the CELL18 acquisition channel, filtering the signal from the power supply unit before inputting it to the signal acquisition unit. C9 acts as an energy storage capacitor to stabilize the detected waveform. Filtering Unit 1 and the signal acquisition unit together ensure the power supply stability of the addressing circuit, guaranteeing circuit stability.

[0052] Signal Acquisition Unit: Primarily designed by the AFE, it provides a high-precision reference signal VREF to the signal output unit for accurate current source signal generation. It receives and communicates with the signal output unit via SPI for control. It is also responsible for power signal acquisition, current signal acquisition, and voltage signal acquisition from the address identification port. The V+ power supply port of the signal acquisition unit provides basic power and power signal acquisition without the need for additional voltage divider acquisition. The highest serial acquisition channels C18 and C17 of the signal acquisition unit acquire the voltage across R24 to identify and acquire the current addressing signal. The signal originates from filter unit 2 and cannot be replaced by an additional differential operational amplifier. R30 and C10 are used for addressing power supply detection, which pauses the addressing detection function and reports a fault under abnormal voltage conditions.

[0053] Current protection unit: Primarily implemented using PPTC, it works in conjunction with the sampling and voltage regulation units to protect signals and devices in the event of a short circuit at the port, ensuring no damage to the circuit. If the Adr_OUT port signal is shorted to ground, it provides fuse protection; its impedance recovers upon short circuit restoration. F1 and Z1 together provide short-circuit protection. When the Adr_IN port signal is shorted to GND, the current through R24 increases, the voltage increases, Z1 reaches its threshold, and voltage clamping is activated. As the current continues to increase, F1 will blow for protection.

[0054] Sampling unit: It is mainly used to receive current signals, convert current signals into electrical signals, and provide filtering unit 2 for filtering before giving the signal to the signal acquisition unit for signal acquisition. Here, filtering unit 2 adopts a filtering method combining CRC and ground C, which can suppress interference pulses and achieve good signal sampling.

[0055] Voltage regulator unit: Its main function is to protect the signal acquisition channel from overvoltage. Specifically, the voltage regulator capacitor C12 is the same as C18's capacitance to ground, stabilizing the acquired signal and improving acquisition accuracy. When a short circuit to ground occurs at the port, the overvoltage of the sampling unit triggers the voltage regulator unit to clamp the sampling voltage and work with the current protection unit to complete the protection of the entire circuit.

[0056] Anti-reverse unit 1: Implemented using a unidirectional diode D12 to prevent damage to the signal acquisition port due to short circuit to the power supply or higher voltage.

[0057] Port signal monitoring unit: Composed of a voltage divider network and a filter network, it mainly acquires the voltage of the addressing input port to identify the host addressing signal and the actual condition of the port circuit. The port signal monitoring unit, together with the signals from filter unit 1 and filter unit 2, determines whether the port is short-circuited to power or ground. The input detection voltage is obtained by voltage division by R27 and R28, filtered by C8, and then acquired by the signal acquisition unit GPIO1. The port voltage can be calculated. When the port DO output is compatible, the voltage can be used to determine whether addressing is enabled.

[0058] The specific implementation of the addressing process is shown in the following example.

[0059] 1. When the host needs to perform addressing, it pulls the DO signal high and sends a CAN addressing message at the same time.

[0060] 2. When slave module 1 receives the addressing message, it detects that the Adr_IN signal is the output voltage of the master DO port, sets the address to slave module 1, and at the same time, the drive unit, through the combined action of the feedback unit and the filter unit, sets the port Adr_OUT to output the current of slave addressing 2.

[0061] 3. Slave module 2 detects the addressing current output by slave module 1, and at the same time confirms that the input signal circuit is connected normally. It sets the address to slave module 2, and at the same time, the drive unit, through the combined action of the feedback unit and the filter unit, sets the port Adr_OUT to output the current of slave address 3.

[0062] 4. Slave module n detects the addressing current output by slave module n-1, and at the same time confirms that the input signal circuit connection is normal. It sets the address to slave module n, and at the same time, the drive unit, through the combined action of the feedback unit and the filter unit, sets the port Adr_OUT to output the current of slave addressing n+1.

[0063] 5. The last slave module's port Adr_OUT is connected to the master's port Adr_IN. The master confirms that the slave module to be addressed is consistent with the design by the output current of the last slave module, and then the addressing is completed.

[0064] This embodiment completes addressing through current-type threshold changes, without limiting the number of battery packs, and can adapt to combinations of at least 16 packs, covering the maximum address allocation of energy storage systems.

[0065] Specifically, when the Adr_OUT signal experiences a short circuit, the drive unit will absorb the high power generated by the excessive voltage to protect the feedback circuit.

[0066] Specifically, when the Adr_OUT signal has a negative voltage, the anti-reverse unit 2 will prevent the negative voltage from damaging the current generation circuit.

[0067] In particular, when the Adr_OUT signal is superimposed with strong external interference, the unique structure of the filter unit 3 will maintain the stability of the current signal output.

[0068] Specifically, when the Adr_IN signal is short-circuited to ground, the sampling unit generates an overvoltage, which causes the voltage regulator unit to clamp and generate a large current signal that triggers the instantaneous fuse of the current protection unit, thus protecting the circuit.

[0069] Specifically, when the Adr_IN signal is short-circuited to ground, the short circuit will be identified by the port signal monitoring unit and the sampling unit.

[0070] Specifically, when the Adr_IN signal is short-circuited or injected with a higher voltage, the anti-reverse unit 1 prevents damage to the detection circuit caused by excessive voltage.

[0071] Specifically, when a short circuit occurs in the Adr_IN signal, or a higher voltage is injected, the sampling unit and the port signal monitoring unit jointly identify the short circuit and high voltage.

[0072] Because the port signal monitoring unit has additional current loss, the voltage obtained by the sampling unit must be filtered out by the additional current of the port signal monitoring unit before the voltage threshold can be determined. The specific calculation formula is as follows. Wherein: Vadr (valid) is used as the basis for determining the final address; Vcell18 is the signal collected by the sampling unit; Vcell1 is the signal collected by the port signal monitoring unit; Rc1 is the sampling resistor of R28 in the port signal monitoring unit; and Rc18 is the sampling resistor of R24 in the sampling unit.

[0073] The second embodiment of this application relates to an automatic addressing circuit method for a battery management system, the process of which is as follows: Figure 4 As shown, the method includes the following steps (a) to (d).

[0074] In step (a), the host module sends an addressing start signal to each slave module through the controller local area network and outputs a voltage signal to the first-level slave module through its control output circuit.

[0075] In step (b), the signal acquisition circuit of the first-level slave module converts the voltage signal into a current signal and compares it with the corresponding preset value. If the voltage signal is within the range of the corresponding preset value, the control output circuit sets the address of the slave module accordingly.

[0076] In step (c), the control output circuit of the second-level to the last-level slave module outputs a current signal to the next-level slave module. The signal acquisition circuit of the second-level to the last-level slave module acquires the current signal output by the control output circuit of the previous level and converts it into a voltage signal before outputting it to the control output circuit of the slave module. The control output circuit compares the voltage signal with the corresponding preset value. If the voltage signal is within the range of the preset value, the control output circuit sets the address of the slave module accordingly and outputs a current signal to the next-level slave module.

[0077] In step (d), each slave module returns its own address to the master module via the controller LAN.

[0078] It should be noted that the range of preset values ​​for each slave module increases progressively, as shown in Table 1 below. Table 1 The voltage range acquired by the signal acquisition unit is, for example, 0~2.5V. For encoding 8 slave modules, the 0.3~2.1V range can be evenly distributed among 8 threshold values, as shown in Table 1 above. If encoding 16 slave modules, the 0.3~2.1V range can be evenly distributed among 16 threshold values. Furthermore, the power supply unit of slave module 1 and the power supply of the DO port of the master module are externally connected via a wiring harness. If the power supply of master module 1 is 12V, and its DO module outputs 12V, the power supply of slave module 1 is also 12V. In this case, the voltage at port Adr_IN of slave module 1 is equal to the output voltage of the DO module, i.e., 12V. This means that no current flows through R24, and the voltage drop across R24 should be 0. However, due to some deviations in the signal acquisition circuit, the recognition threshold for address 1 can be set to a range of 0~30mV.

[0079] The first embodiment is a method embodiment corresponding to this embodiment. The technical details in the first embodiment can be applied to this embodiment, and the technical details in this embodiment can also be applied to the first embodiment.

[0080] Accordingly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the various method embodiments of this application. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media do not include transient computer-readable media, such as modulated data signals and carrier waves.

[0081] Furthermore, embodiments of this application also provide an automatic addressing device for a battery management system, including a memory for storing computer-executable instructions and a processor; the processor is used to implement the steps in the above-described method embodiments when executing the computer-executable instructions in the memory. The processor may be a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Microcontroller Unit (MCU), Neural Processing Unit (NPU), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices. The aforementioned memory may be read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or solid-state drive, etc. The steps of the methods disclosed in the embodiments of this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0082] Furthermore, embodiments of this application also provide a computer program product, including computer-executable instructions that, when executed by a processor, implement the steps in the above-described method embodiments.

[0083] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0084] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

[0085] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. An automatic addressing circuit for a battery management system, characterized by, It includes a master module and several slave modules connected in sequence. The master module is communicatively connected to the several slave modules through a controller local area network. Each slave module includes a signal acquisition circuit and a control output circuit connected to each other. The master module includes the control output circuit. The control output circuit of the master module is connected to the signal acquisition circuit of the first-level slave module. The control output circuit of each slave module is connected to the signal acquisition circuit of the next-level slave module. The host module sends an addressing start signal to each slave module through the controller local area network and outputs a voltage signal to the first-level slave module through the control output circuit. The control output circuit of each slave module outputs a current signal to the signal acquisition circuit of the next-level slave module. The signal acquisition circuit of each slave module acquires the voltage or current signal output by the previous-level control output circuit, converts it into a voltage signal, and outputs it to the corresponding control output circuit. The control output circuit compares the converted voltage signal with a corresponding preset value. If the converted voltage signal is within the range of the preset value, the control output circuit sets the address of the slave module accordingly. Each slave module returns its own address to the master module via the controller LAN.

2. The automatic addressing circuit of claim 1, wherein, The signal acquisition circuit includes: The acquisition unit of the first-level slave module converts the current formed by the voltage signal output by the master module into a voltage signal. The acquisition units of the second to last-level slave modules convert the current signal output by the previous-level slave module into a voltage signal. The signal acquisition unit receives the converted voltage signal and outputs the converted voltage signal to the control output circuit through a serial peripheral interface. The signal acquisition unit also provides a reference voltage to the control output circuit.

3. The automatic addressing circuit of claim 2, wherein, The signal acquisition circuit also includes: A power supply unit is used to provide DC power to the acquisition unit and the signal acquisition unit; A current protection unit is connected between the power supply unit and the acquisition unit; A first filtering unit is connected between the power supply unit and the signal acquisition unit; A second filtering unit is connected between the acquisition unit and the signal acquisition unit; A voltage stabilizing unit is connected between the acquisition unit and the ground terminal; A first anti-reverse unit, one end of which is connected to the acquisition unit, and the other end of which receives the current signal; and A port signal monitoring unit is connected between the voltage or current signal and the signal acquisition unit.

4. The automatic addressing circuit of claim 3, wherein, The acquisition unit includes a first resistor (R24), the first filtering unit includes a second resistor (R30) and a first capacitor (C10), the second filtering unit includes a third resistor (R25), a fourth resistor (R26), a second capacitor (C9), and a third capacitor (C7), the current protection unit includes a fuse (F1) and a Zener diode (Z1), the voltage regulation unit includes a fourth capacitor (C12), the first reverse protection unit includes a first diode (D12), and the port signal monitoring unit includes a fifth resistor (R27), a sixth resistor (R28), and a fifth capacitor (C8); wherein, one end of the fuse (F1) is connected to the power supply unit and one end of the second resistor (R30), the other end of the fuse (F1) is connected to one end of the first resistor (R24), one end of the second capacitor (C9), one end of the Zener diode (Z1), one end of the third resistor (R25), and one end of the fourth capacitor (C12), and the other end of the fourth capacitor (C12) is connected to the ground terminal. The other end of the second resistor (R30) is connected to one end of the first capacitor (C10) and the signal acquisition unit. The other end of the first capacitor (C10) is grounded. The other end of the Zener diode (Z1), the other end of the first resistor (R24), the other end of the second capacitor (C9), and the other end of the fourth resistor (R26) are connected to the positive terminal of the first diode (D12). One end of the third capacitor (C7) is connected to the other end of the third resistor (R25) and the signal acquisition unit. The other end of the third capacitor (C7) is connected to the other end of the fourth resistor (R26) and the signal acquisition unit. The negative terminal of the first diode (D12) is connected to one end of the fifth resistor (R27) and receives the current signal. The other end of the fifth resistor (R27) is connected to one end of the sixth resistor (R28), one end of the fifth capacitor (C8), and the signal acquisition unit. The other end of the sixth resistor (R28) is connected to the other end of the fifth capacitor (C8) and the signal acquisition unit.

5. The automatic addressing circuit of claim 1, wherein, The control output circuit includes: A signal output unit, comprising a digital-to-analog converter and a comparator, wherein the output of the digital-to-analog converter is connected to the positive input terminal of the comparator; The drive unit has its control terminal connected to the output terminal of the signal output unit, and its first terminal outputs the current signal. A feedback unit, wherein the feedback unit is connected between the third terminal of the driving unit and the ground terminal; and The third filtering unit is connected between the third terminal of the driving unit and the negative input terminal of the comparator.

6. The automatic addressing circuit of claim 5, wherein, The control output circuit further includes a second anti-reverse unit, which is connected to the first end of the drive unit.

7. The automatic addressing circuit according to claim 6, characterized in that, The driving unit includes an NPN transistor (Q1), the feedback unit includes a seventh resistor (R23), the third filtering unit includes an eighth resistor (R31), a sixth capacitor (C11), and a seventh capacitor (C6), and the second anti-reverse unit includes a second diode (D10); wherein, the base of the NPN transistor (Q1) is connected to the output terminal of the comparator, the collector of the NPN transistor (Q1) is connected to one end of the seventh resistor (R23), one end of the eighth resistor (R31), and one end of the seventh capacitor (C6), the other end of the seventh resistor (R23) and one end of the sixth capacitor (C11) are connected to the negative input terminal of the comparator, and the other end of the seventh capacitor (C6) and the other end of the sixth capacitor (C11) are grounded.

8. The automatic addressing circuit according to claim 1, characterized in that, The host module also includes the signal acquisition circuit. The control output circuit of the last-stage slave module is connected to the signal acquisition circuit and outputs a corresponding current signal to the signal acquisition circuit of the host module. The host module sends an addressing end command to each slave module, and each slave module returns its own address to the host module through the controller local area network.

9. An automatic addressing method of a battery management system, characterized by, include: The master module sends an addressing start signal to each slave module through the controller local area network and outputs a voltage signal to the first-level slave module through its control output circuit; The signal acquisition circuit of the first-level slave module converts the voltage signal into a current signal and compares it with a corresponding preset value. If the converted voltage signal is within the range of the corresponding preset value, the control output circuit sets the address of the slave module accordingly. The control output circuit of the second-level to last-level slave module outputs a current signal to the next-level slave module. The signal acquisition circuit of the second-level to last-level slave module acquires the current signal output by the previous-level control output circuit, converts it into a voltage signal, and outputs it to the control output circuit of the slave module. The control output circuit compares the converted voltage signal with a corresponding preset value. If the converted voltage signal is within the range of the preset value, the control output circuit sets the address of the slave module accordingly and outputs a current signal to the next-level slave module. Each slave module returns its own address to the master module via the controller LAN.

10. The method of automatic addressing according to claim 9, characterized in that, The range of preset values ​​for each slave module increases progressively.

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