Intermittent charge-discharge method, intermittent discharge method, and electronic circuit employing intermittent charge-discharge

Abstract

This invention discloses an intermittent charging and discharging method, an electronic circuit employing intermittent charging and discharging, and an intermittent discharging method. The intermittent charging and discharging method of this invention includes the following steps: charging a power stage circuit multiple times during multiple operating periods of a continuous series of pulses of a charging control signal, thereby generating multiple charging steps representing the rising wave of the voltage signal of the power stage circuit; and stopping charging the power stage circuit during multiple non-operating periods of the continuous series of pulses of the charging control signal, causing the voltage signal to generate a stop charging horizontal line segment or a discharge step segment between each pair of the multiple charging steps. This invention employs intermittent control for both charging and discharging of the power stage circuit. Therefore, the intermittent charging and discharging method, the intermittent discharging method, and the electronic circuit employing intermittent charging and discharging of this invention significantly improve control accuracy.

Description

Technical Field

[0001] This invention relates to charging and discharging, and in particular to an intermittent charging and discharging method, an intermittent discharging method, and an electronic circuit employing intermittent charging and discharging. Background Technology

[0002] In recent years, due to technological advancements and rising environmental awareness, people have increasingly higher demands for efficiency and electromagnetic interference control. Whether in communication applications or energy conversion, switch control plays a crucial role. Meanwhile, rising material and labor costs have made reducing product design area and improving technical quality a constant goal for researchers. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides an intermittent charging and discharging method, comprising the following steps: during a first period, charging a power stage circuit multiple times during multiple working periods of a series of pulses of a charging control signal, thereby generating multiple first charging segments of rising voltage signals of the power stage circuit; and during the first period, stopping charging the power stage circuit during multiple non-working periods of a series of pulses of the charging control signal, thereby generating a first stop charging horizontal segment or a first discharge segment between two of the multiple charging segments.

[0004] The present invention also provides an intermittent discharge method, comprising the following steps: discharging a power stage circuit multiple times during multiple operating periods of a series of pulses of a discharge control signal, thereby generating multiple discharge tiers with falling waves in the voltage signal of the power stage circuit; and discharging the power stage circuit multiple times during multiple non-operating periods of the series of pulses of the discharge control signal, thereby generating a stop-discharge horizontal line segment or a charging tier segment between two of the multiple discharge tiers in the voltage signal.

[0005] The present invention also provides an electronic circuit employing intermittent charging and discharging. The intermittent charging and discharging electronic circuit includes a control circuit, a power stage circuit, and a charging circuit. The control circuit generates a charging control signal. The power stage circuit receives a voltage signal. The charging circuit is coupled to the power stage circuit and the control circuit, and is controlled by the control circuit according to the charging control signal. During a first period, the control circuit controls the charging circuit to charge the power stage circuit multiple times during multiple operating periods of a plurality of consecutive pulses of the charging control signal, respectively, to generate a plurality of first charging steps of the rising wave segment of the voltage signal. During the first period, the control circuit controls the charging circuit to stop charging the power stage circuit during multiple non-operating periods of the plurality of consecutive pulses of the charging control signal, causing the voltage signal to generate a stop charging horizontal line segment or a first discharge step segment between two of the plurality of first charging steps.

[0006] In some embodiments, the control circuit further generates a discharge control signal, and the electronic circuit employing intermittent charging and discharging further includes a discharge circuit. The discharge circuit is coupled to the power stage circuit and the control circuit, and is controlled by the control circuit according to the discharge control signal. During a second period following the first period, the control circuit controls the charging circuit to discharge the power stage circuit multiple times during multiple operating periods of a plurality of consecutive pulses of the discharge control signal, causing a plurality of second discharge escalators with falling peaks to be generated in the voltage signal. During the second period, the control circuit controls the discharge circuit to stop discharging the power stage circuit during multiple non-operating periods of the plurality of consecutive pulses of the discharge control signal, causing the voltage signal to generate a stop-discharge horizontal segment or a second charging escalator between each of the plurality of second discharge escalators.

[0007] In some embodiments, the power stage circuit includes a first capacitor and a power transistor. A first terminal of the first capacitor is coupled to the charging circuit and the discharging circuit at the input terminal of the power stage circuit, and a second terminal of the first capacitor is coupled to ground. A first terminal of the power transistor is coupled to a first power supply voltage, a second terminal of the power transistor is coupled to the ground terminal, and a control terminal of the power transistor is coupled to the input terminal. The voltage signal is generated at the input terminal.

[0008] In some embodiments, the control circuit includes a first comparator and an output circuit. A first input terminal of the first comparator receives a first reference voltage signal, and a second input terminal of the first comparator receives a status signal. The first comparator compares the first reference voltage signal with the status signal to generate a switching signal at its output terminal, wherein the status signal represents the changing state of the voltage difference between the control terminal and the second terminal of the power transistor. The output circuit receives the switching signal and outputs the switching signal as either the charging control signal or the discharging control signal.

[0009] In some embodiments, the control circuit further includes a sensing comparison circuit, a judgment circuit, and a signal generation circuit. The sensing comparison circuit receives a sensed voltage signal and is configured to compare the sensed voltage signal with a plurality of second reference voltages to output a plurality of comparison signals, wherein the sensed voltage signal represents the voltage difference of the power transistor. The judgment circuit receives the plurality of comparison signals and is configured to determine, based on the plurality of comparison signals, the time difference between the time when the sensed voltage signal reaches each of the second reference voltages and a time threshold value, thereby generating a trigger signal. The signal generation circuit receives the trigger signal and generates the status signal, configured to control the level of the status signal based on the trigger signal.

[0010] In some embodiments, the sensing comparator circuit includes a sensing circuit, a plurality of second comparators, and a plurality of reference resistors. The sensing circuit is configured to sense the voltage difference of the power transistors to output the sensed voltage signal. A first input terminal of each of the second comparators is coupled to the sensing circuit to receive the sensed voltage signal, second input terminals of the plurality of second comparators are respectively coupled to a plurality of second reference voltages, and a plurality of output terminals of the plurality of second comparators output a plurality of comparison signals. The plurality of reference resistors are connected in series between a second power supply voltage and the ground terminal. The second power supply voltage serves as one of the second reference voltages. The plurality of reference resistors include a first reference resistor and a second reference resistor, and the voltage at a common node between the first reference resistor and the second reference resistor serves as the other of the second reference voltages.

[0011] In some embodiments, the signal generation circuit includes a first switch, an input current source, an input capacitor, and a second switch. A first terminal of the first switch is coupled to a second input terminal of the first comparator at a first node, and a control terminal of the first switch receives the trigger signal. A first terminal of the input current source is coupled to a second terminal of the first switch, and the second terminal of the input current source is coupled to a ground terminal, wherein when the first switch is turned on according to the trigger signal, the input current source circuit provides current to the first node through the first switch. A first terminal of the input capacitor is coupled to the first node, and a second terminal of the input capacitor is coupled to the ground terminal, wherein the status signal is generated at the first node. A first terminal of the second switch is coupled to the first node, and a second terminal of the second switch is coupled to the ground terminal. The determination circuit generates a reset signal, and the control terminal of the second switch receives the reset signal. At intervals equal to the time threshold value, the determination circuit enables the reset signal to turn on the second switch.

[0012] In some embodiments, the on / off state of the power transistors in the power stage circuit is controlled by the voltage signal, an indication signal indicates the on / off state of the power transistors, and the control circuit further includes a transition detection circuit. The transition detection circuit receives the indication signal and is configured to detect the rising and falling edges of the indication signal to output a transition detection signal. Whenever the transition detection circuit detects the rising edge of the indication signal, it outputs the transition detection signal to control the output circuit to output the switching signal as the charging control signal. Whenever the transition detection circuit detects the falling edge of the indication signal, it outputs the transition detection signal to control the output circuit to output the switching signal as the discharging control signal. Attached Figure Description

[0013] Figure 1 This is a block diagram of an electronic circuit employing intermittent charging according to the first embodiment of the present invention.

[0014] Figure 2 This is a flowchart of the intermittent charging method according to the first embodiment of the present invention.

[0015] Figure 3 This is a block diagram illustrating the intermittent charging and discharging method used in the second embodiment of the present invention.

[0016] Figure 4 This is a flowchart illustrating the steps of the intermittent discharge method according to the second embodiment of the present invention.

[0017] Figure 5 This is a circuit diagram of an electronic circuit employing intermittent charging and discharging, according to a third embodiment of the present invention.

[0018] Figures 6 to 11 The waveform diagrams are of the main signals of the electronic circuits in the fourth to ninth embodiments of the present invention.

[0019] Figure 12 This is a circuit diagram of the control circuit of the electronic circuit employing intermittent charging and discharging, according to the tenth embodiment of the present invention.

[0020] Figure 13 The waveform diagram shows the charging control signal and other main signals of the electronic circuit according to the tenth embodiment of the present invention.

[0021] Figure 14 The waveform diagram shows the discharge control signal and other main signals of the electronic circuit in the tenth embodiment of the present invention.

[0022] Figure 15 This is a circuit diagram of an electronic circuit employing intermittent charging and discharging according to the eleventh embodiment of the present invention.

[0023] Figure 16 The waveform diagram of the main signals of the electronic circuit in the twelfth embodiment of the present invention is shown. Detailed Implementation

[0024] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention.

[0025] Figure 1 This is a block diagram of an electronic circuit employing intermittent charging according to the first embodiment of the present invention. Figure 2 This is a flowchart illustrating the steps of the intermittent charging method according to the first embodiment of the present invention. Please refer to [link / reference]. Figure 1 and Figure 2 The intermittent charging method of the present invention includes, as follows: Figure 2 The intermittent charging steps S11 to S15 shown can be implemented by the electronic circuit employing intermittent charging of the present invention (e.g., Figure 1 The electronic circuit 1) executes. For example... Figure 1 As shown, electronic circuit 1 includes control circuit 10, charging circuit 11, and power stage circuit 12. Control circuit 10 generates a charging control signal SCH. Charging circuit 11 is coupled to control circuit 10 to receive the charging control signal SCH. Furthermore, charging circuit 11 is also coupled to power stage circuit 12. Control circuit 10 operates during multiple switching periods to control power stage circuit 12 via the charging control signal SCH. The following will explain... Figure 1 and Figure 2 To illustrate the operation of electronic circuit 1 in this case during each switching period.

[0026] In step S11, electronic circuit 1 enters the first period of the switching period (e.g., Figure 6 During the charging period P10, steps S12 to S15 are executed during the first period. During the first period, the charging control signal SCH has multiple consecutive pulse waves (i.e., at least two pulse waves, for example...). Figure 6 The pulse waves P11 to P12), and each pulse wave includes a duty-on period (e.g., Figure 6 Working hours (DN11~DN12) and non-working hours (e.g.) Figure 6 During the non-operating period (DF11-DF12), in step S12, the control circuit 10 controls the charging circuit 11 to perform the first charge on the power stage circuit 12 via the charging control signal SCH. Specifically, in step S12, during the first operating period of the charging control signal SCH (e.g., ...), Figure 6 During the operation of pulse P11 (DN11), control circuit 10 controls charging circuit 11 to perform the first charge on power stage circuit 12 to generate a voltage signal (e.g., Figure 5 The first charging step of the rising wave of the gate capacitor voltage signal VCg (e.g., the first charging step of the rising wave of the gate capacitor voltage signal VCg). Figure 6 The charging stage SU11). In this embodiment, the voltage signal is received by the power stage circuit 12. In step S13, the control circuit 10 controls the charging circuit 11 to stop the first charging of the power stage circuit 12 via the charging control signal SCH. Specifically, in step S13, during the first non-operating period after the first operating period of the charging control signal SCH (e.g., ... Figure 6 During the non-operating period (DF11) of pulse P11, control circuit 10 controls charging circuit 11 to stop the first charging of power stage circuit 12, causing the voltage signal to generate the first stop charging horizontal segment (e.g., after the first charging step) Figure 6 (The horizontal line segment SH11 is the one where charging has stopped).

[0027] Next, in step S14, during the second operating period after the first non-operating period of the charging control signal SCH (e.g., Figure 6 During the operation of pulse P12 (DN12), control circuit 10 controls charging circuit 11 to perform a second charge on power stage circuit 12, thereby generating the second charging stage (e.g., the rising wave of the aforementioned voltage signal) of the second charging phase. Figure 6 The charging stage SU12). Then, in step S15, during the second non-operating period after the second operating period of the continuing charging control signal SCH (e.g., Figure 6During the non-operating period of pulse P12 (DF12), control circuit 10 controls charging circuit 11 to stop the second charging of power stage circuit 12, causing the voltage signal to generate a second stop charging horizontal segment (e.g., after the second charging step) after the second charging step. Figure 6 (The horizontal line segment SH12 that stops charging).

[0028] In the above embodiments, the intermittent charging method of the present invention is illustrated using the first and second operating periods and the first and second non-operating periods of the charging control signal SCH in the first period as examples (i.e., using the charging control signal SCH having two consecutive pulses as an example). When the charging control signal SCH in the first period includes three (e.g.) Figure 6 When there are pulses P11 to P13 or more than three consecutive pulses, the electronic circuit 1 may perform operations similar to steps S12 and S13 (and / or steps S14 and S15) after step S15 to continue charging the power stage circuit 12 at least once and stopping charging at least once. That is, in the intermittent charging method of the present invention, after charging the power stage circuit 12 for a period of time, charging the power stage circuit 12 is stopped during the rest period to achieve intermittent / multi-stage charging of the power stage circuit 12.

[0029] Traditional charging methods employ a single continuous charge to directly charge the voltage of the power stage circuit from a trough or initial low level to a peak or preset high level. However, this invention uses intermittent / multi-stage charging for the power stage circuit 12, charging the voltage signal to different voltage levels during multiple charges. This gradually increases the voltage signal until it reaches the peak or preset high level. Compared to traditional charging methods, the intermittent charging method of this invention allows for setting the charging time and rest time (i.e., the duration of charging pause) for each stage according to application requirements, significantly improving the accuracy of charging control and providing more flexible control over the charging state of the power stage circuit 12.

[0030] Figure 3 This is a block diagram of an electronic circuit employing intermittent charging and discharging according to a second embodiment of the present invention. Figure 4 This is a flowchart illustrating the steps of the intermittent discharge method according to the second embodiment of the present invention. Figure 4 As shown, the intermittent discharge method of the present invention includes steps S21 to S25. For example... Figure 3As shown, in the second embodiment, the electronic circuit 3 employing intermittent charging and discharging includes a control circuit 10, a charging circuit 11, and a power stage circuit 12, as well as a discharging circuit 13. Steps S21 to S25 can be executed by the control circuit 10, the power stage circuit 12, and the discharging circuit 13 of the electronic circuit 3. (See reference...) Figure 3 In addition to generating a charging control signal SCH, control circuit 10 also generates a discharging control signal SDG. Discharging circuit 13 is coupled to control circuit 10 to receive the discharging control signal SDG. Furthermore, discharging circuit 13 is also coupled to power stage circuit 12. Control circuit 10 controls power stage circuit 12 via the charging control signal SCH and the discharging control signal SDG during multiple switching periods. The following will explain... Figure 3 and Figure 4 To illustrate the operation of electronic circuit 3 during the switching process in this case.

[0031] In some embodiments, steps S21 to S25 are followed by Figure 2 The intermittent charging steps S11 to S15 (in Figure 4 Following the dashed box (represented in the image), steps S11-S15 and S21-S25 constitute the steps of the intermittent charge-discharge method of the present invention. The intermittent charge-discharge method of the present invention utilizes an electronic circuit employing intermittent charge-discharge (e.g., Figure 3 3. Electronic circuits Figure 5 5. Electronic circuits, or Figure 15 The electronic circuit 15) is executed.

[0032] See Figure 3 and Figure 4 In step S21, electronic circuit 3 enters the second period of the switching period (e.g., Figure 6 During the discharge period P30), steps S22 to S25 are executed during the second period. During the second period, the discharge control signal SDG has multiple consecutive pulses (i.e., at least two pulses, for example...). Figure 6 The pulse waves P21 to P22), and each pulse wave includes the working period (e.g., Figure 6 During working hours (DN21~DN22) and during non-working hours (e.g.) Figure 6 (The non-working periods DF21-DF22). In the embodiment where steps S21-S25 follow steps S11-S15, the aforementioned second period occurs after the first period on the timeline.

[0033] In step S22, the control circuit 10 controls the discharge circuit 13 to perform the first discharge on the power stage circuit 12 via the discharge control signal SDG. Specifically, in step S22, during the first operating period of the discharge control signal SDG (e.g., ...), Figure 6During the operation of pulse P21 (DN21), control circuit 10 controls discharge circuit 13 to perform the first discharge on power stage circuit 12 to generate the first discharge stage of the falling wave of the aforementioned voltage signal (e.g., Figure 6 The discharge stage SD21). In step S23, the control circuit 10 controls the discharge circuit 13 to stop the first discharge to the power stage circuit 12 via the discharge control signal SDG. Specifically, in step S23, during the first non-operation period after the first operating period of the discharge control signal SDG (e.g., Figure 6 During the non-operating period of pulse P21 (DF21), control circuit 10 controls discharge circuit 13 to stop the first discharge to power stage circuit 12, so that the voltage signal generates the first stop discharge horizontal segment (e.g., after the first discharge stage) Figure 6 (The horizontal line segment SH21 where the discharge stops).

[0034] Next, in step S24, during the second operating period after the first non-operating period of the discharge control signal SDG (e.g., Figure 6 During the operation of pulse P22 (DN22), control circuit 10 controls discharge circuit 13 to perform a second discharge on power stage circuit 12 to generate the second discharge stage of the falling wave of the aforementioned voltage signal (e.g., Figure 6 The elevator section SD22). Then, in step S25, during the second non-operating period after the second operating period of the continuing discharge control signal SDG (e.g., Figure 6 During the non-operation period of pulse P22 (DF22), control circuit 10 controls discharge circuit 13 to stop the second discharge to power stage circuit 12, so that the voltage signal generates a second stop discharge horizontal segment (e.g., after the second discharge segment) Figure 6 (The horizontal line segment SH22 where the discharge stops).

[0035] In the above embodiments, the intermittent discharge method of the present invention is illustrated using the first and second operating periods and the first and second non-operating periods of the discharge control signal SDG in the second period as examples (i.e., using the discharge control signal SDG having two consecutive pulses as an example). When the discharge control signal SDG in the second period includes three (e.g.) Figure 6When there are pulses (P21-P23) or more than three consecutive pulses, the electronic circuit 3 may perform operations similar to steps S22 and S23 (and / or steps S24 and S25) after step S25 to continue discharging the power stage circuit 12 at least once and stopping the discharge at least once. It is worth noting that in the intermittent discharge method of the present invention, after discharging the power stage circuit 12 for a period of time, discharging the power stage circuit 12 is stopped during the rest period to achieve intermittent / multi-stage discharge of the power stage circuit 12.

[0036] Traditional discharge methods employ a single continuous discharge to directly discharge the voltage of the power stage circuit from a peak level or initial high level to a trough level or a preset low level. In contrast, this invention uses intermittent / multi-stage discharge for the power stage circuit 12, discharging the voltage signal to different voltage levels during multiple discharges to gradually reduce the voltage until it finally reaches a trough level or a preset low level. Compared to traditional discharge methods, the intermittent discharge method of this invention allows for setting the discharge time and rest time (i.e., the duration of discharge cessation) for each stage according to application requirements, significantly improving the accuracy of discharge control and providing more flexible control over the discharge state of the power stage circuit 12.

[0037] Compared to traditional charging and discharging methods, in the intermittent charging and discharging method of the present invention, the control circuit 10 precisely controls the level of the voltage signal by intermittently controlling the enable time of the charging circuit 11 and / or the discharging circuit 13. For example, it precisely controls the speed at which the voltage signal rises from a trough level or an initial low level to a peak level or a preset high level (hereinafter referred to as the voltage signal rise rate), and / or precisely controls the speed at which the voltage signal falls from a peak level or an initial high level to a trough level or a preset low level (hereinafter referred to as the voltage signal fall rate), thereby controlling the switching speed of the power stage circuit 12 to different operating states. The control circuit 10 can select an appropriate intermittent switching strategy to control the rise and / or fall rate of the voltage signal based on the characteristics of the selected power stage circuit 12, such as its conduction curve and parasitic parameters.

[0038] If only a simple setting of the rise and / or fall rate of the aforementioned voltage signal is required, a relatively low-frequency fixed-frequency control can be selected. Fixed-frequency operation results in relatively low noise. Variable-frequency control, on the other hand, is suitable for applications requiring more precise control of the voltage level changes of the aforementioned voltage signal, providing an effective and real-time response through frequency conversion.

[0039] Figure 5 This is a circuit diagram of an electronic circuit employing intermittent charging and discharging according to a third embodiment of the present invention. Figure 5As shown, the electronic circuit 5 of the present invention, employing intermittent charging and discharging, includes a control circuit 10, a charging circuit 11A, a discharging circuit 13A, and a power stage circuit 12A. The control circuit 10 generates a charging control signal SCH and a discharging control signal SDG. Figure 5 In this diagram, the pulse patterns of the charging control signal SCH and the discharging control signal SDG are for illustrative purposes only and are not intended to limit the scope of the invention. (Comparison) Figure 5 and Figure 3 , Figure 5 The charging circuit 11A, discharging circuit 13A, and power stage circuit 12A are respectively Figure 3 The charging circuit 11, discharging circuit 13, and power stage circuit 12 are each implemented in one manner. The charging circuit 11A includes a charging-side current source circuit 110 (hereinafter referred to as "current source circuit 110") and a charging switch SW11. In this embodiment, the current source circuit 110 includes a charging-side current source CU1 (hereinafter referred to as "current source CU1"). The input terminal of the current source CU1 is coupled to the power supply voltage VCC, and its output terminal is coupled to the first terminal of the charging switch SW11. The second terminal of the charging switch SW11 is coupled to the input terminal of the power stage circuit 12A at node N10. The control terminal of the charging switch SW11 is coupled to the control circuit 10 to receive the charging control signal SCH.

[0040] The discharge circuit 13A includes a discharge-side current source circuit 130 (hereinafter referred to as "current source circuit 130") and a discharge switch SW13. In this embodiment, the current source circuit 130 includes a discharge-side current source CU2 (hereinafter referred to as "current source CU2"). The input terminal of the current source CU2 is coupled to the input terminal of the power stage circuit 12A at node N10, and its output terminal is coupled to the first terminal of the discharge switch SW13. The second terminal of the discharge switch SW13 is coupled to the ground terminal GND. The control terminal of the discharge switch SW13 is coupled to the control circuit 10 to receive the discharge control signal SDG.

[0041] See Figure 5The power stage circuit 12A mainly includes a capacitor Cg and a power transistor M1. Furthermore, depending on the system architecture in which the electronic circuit 5 is applied, the power stage circuit 12A may also include other circuit elements. For example, in the case of a Local Interconnect Network (LIN) system architecture, the power stage circuit 12A may also include an upper diode D1, a lower diode D2, resistors R1 and R2, and a capacitor C1. The first terminal of capacitor Cg and the control terminal of power transistor M1 are coupled to the input terminal of power stage circuit 12A at node N10, and through this input terminal of power stage circuit 12A, are coupled to the second terminal of charging switch SW11 and the first terminal of current source CU2. The second terminal of capacitor Cg is coupled to ground GND. The first terminal of power transistor M1 is coupled to the cathode of lower diode D2, and its second terminal is coupled to ground GND. The cathode of upper diode D1 is coupled to the anode of lower diode D2. The first terminals of resistors R2 and R1 are coupled to the power supply voltage VBAT. The second terminal of resistor R2 is coupled to the anode of the upper diode D1. The second terminal of resistor R1, the cathode of the upper diode D1, the anode of the lower diode D2, and the first terminal of capacitor C1 are coupled to the output terminal LIN of the power stage circuit 12A. The second terminal of capacitor C1 is coupled to the ground terminal GND. In this embodiment, power transistor M1 is implemented as an N-type field-effect transistor; therefore, the control terminal, the first terminal, and the second terminal of power transistor M1 are the gate, drain, and source of the N-type transistor, respectively.

[0042] When the charging switch SW11 is turned on according to the charging control signal SCH, the current source CU1 provides charging current flowing through the turned-on charging switch SW11 to the capacitor Cg, charging the capacitor Cg and causing the voltage level of the gate capacitor voltage signal VCg at the first terminal of the capacitor Cg (i.e., the input terminal of the power stage circuit 12A) to gradually increase. When the charging switch SW11 is turned off according to the charging control signal SCH, the current source circuit 110 stops providing the above-mentioned charging current to the capacitor Cg, causing the charging circuit 11A to stop charging the capacitor Cg and the voltage level of the gate capacitor voltage signal VCg to stop increasing. For example, the charging switch SW11 is turned on during the operation period of the charging control signal SCH and turned off during the non-operation period of the charging control signal SCH. The multiple operating periods of the multiple pulses of the charging control signal SCH can be determined according to the voltage difference between the control terminal and the second terminal of the power transistor M1, that is, according to the actual gate-source voltage (VGS) of the power transistor M1.

[0043] When discharge switch SW13 is turned on according to discharge control signal SDG, current source CU2 provides discharge current, flowing through the turned-on discharge switch SW13 to ground terminal GND, to discharge capacitor Cg of power stage circuit 12A, causing the voltage level of gate capacitor voltage signal VCg to gradually decrease. When discharge switch SW13 is turned off according to discharge control signal SDG, current source circuit 130 stops providing the above-mentioned discharge current to ground terminal GND, causing discharge circuit 13A to stop discharging capacitor Cg and the voltage level of gate capacitor voltage signal VCg to stop decreasing. For example, discharge switch SW13 is turned on during the operation period of discharge control signal SDG and turned off during the non-operation period of discharge control signal SDG. The multiple operating periods of multiple consecutive pulses of discharge control signal SDG can be determined according to the actual gate-source voltage (VGS) of power transistor M1.

[0044] Based on the above, the present invention intermittently controls the charging switch SW11 to be in the on state, so that the charging current output by the current source CU1 is gradually released to the capacitor Cg during discontinuous periods to increase the voltage at the control terminal of the power transistor M1 (i.e., the voltage level of the gate capacitor voltage signal VCg), thereby controlling the turn-on speed of the power transistor M1. Similarly, the present invention intermittently controls the discharging switch SW13 to be in the on state, so that the capacitor Cg is gradually discharged during discontinuous periods to decrease the voltage at the control terminal of the power transistor M1, thereby controlling the turn-off speed of the power transistor M1. The power transistor M1 operates according to the gate capacitor voltage signal VCg, thereby controlling the rate of change (rise or fall) of the output voltage level at the output terminal LIN of the power stage circuit 12A.

[0045] Figure 6 The waveform diagram of the main signals of the electronic circuit in the fourth embodiment of the present invention is shown. Figure 6 The multi-pulse pattern of the charging control signal SCH is as follows: Figure 1 , Figure 3 , Figure 5 and Figure 15 An example of each charging control signal SCH, and Figure 6 The multi-pulse pattern of the discharge control signal SDG is as follows: Figure 3 , Figure 5 and Figure 15 An example of the respective discharge control signal SDG.

[0046] like Figure 6As shown, the frequencies, operating periods, non-operating periods, or combinations thereof of the multiple pulses of the charging control signal SCH may differ from each other, and the frequencies, operating periods, non-operating periods, or combinations thereof of the multiple pulses of the discharging control signal SDG may also differ from each other. However, this is only an example and the invention is not limited thereto. The control circuit 10 controls the power stage circuit 12A through the charging control signal SCH and the discharging control signal SDG during multiple switching periods. See also... Figure 6 Electronic circuit 5 can operate during the switching periods P10, P20, P30, and P40. In the following text, it will be explained by... Figure 5 Electronic circuit 5 Figure 6 The present invention describes the charging and discharging operation of the power stage circuit during switching using the main signals. During the charging period P10 of the power stage circuit 12A, the charging control signal SCH has multiple continuous pulses P11 to P13, each pulse including an operating period and a non-operating period. Therefore, pulses P11 to P13 each include operating periods DN11 to DN13 and non-operating periods DF11 to DF13. Furthermore, during the charging period P10 and the subsequent sustaining period P20, the discharging control signal SDG is maintained at a low voltage level without any pulses.

[0047] See Figure 5 and Figure 6 During charging period P10, because the discharge control signal SDG is maintained at a low voltage level, the discharge switch SW13 is continuously turned off to cut off the discharge path between node N10 and ground GND. Furthermore, during charging period P10, the control circuit 10 turns on the charging switch SW11 during the operation period of the charging control signal SCH (DN11-DN13), causing the charging circuit 11A to supply a charging current with a charging current value i1 to the power stage circuit 12A through the current source circuit 110. In this way, during the operation period (DN11-DN13), the charging current from the current source circuit 110 is provided to the first terminal of capacitor Cg to charge capacitor Cg multiple times, resulting in multiple charging stages SU11-SU13 in the rising wave of the gate capacitor voltage signal VCg. (See also...) Figure 5 and Figure 6During the operating period DN11 to DN13, the gate current ICg of capacitor Cg has a charging current value i1, where the charging current value i1 is positive, indicating that the direction of the gate current ICg is towards capacitor Cg (i.e., charging capacitor Cg). During the charging period P10, during the multiple non-operating periods DF11 to DF13 of the charging control signal SCH, the control circuit 10 turns off the charging switch SW11, causing the charging circuit 11A to stop charging the power stage circuit 12A with the charging current. Therefore, during the non-operating periods DF11 to DF13, the gate capacitor voltage signal VCg stops rising, and multiple stop charging horizontal segments SH11 to SH13 are generated in the rising wave. After the charging period P10, the electronic circuit 5 enters the maintenance period P20 for operation.

[0048] During the sustain period P20, the control circuit 10 causes the charging control signal SCH to have a pulse P14. In this embodiment, the duration of the duty cycle (i.e., the pulse width of pulse P14) of pulse P14 is equal to the duration of the sustain period P20, and pulse P14 has no non-duty cycle. See also Figure 5 and Figure 6 During the maintenance period P20, the charging switch SW11 is turned on according to the pulse P14, and the charging circuit 11A supplies charging current to the first terminal of capacitor Cg through the current source circuit 110, causing capacitor Cg to be recharged and the gate capacitor voltage signal VCg to rise again. When the gate capacitor voltage signal VCg rises to the aforementioned peak level or the preset high level, the gate current ICg becomes zero, and the charging switch SW11 remains on according to the pulse P14 to maintain the gate capacitor voltage signal VCg at the aforementioned peak level or the preset high level. At the end of the maintenance period P20, the charging control signal SCH switches to a low voltage level (i.e., the pulse P14 ends). After the maintenance period P20, the electronic circuit 5 enters the discharge period P30 of the power stage circuit 12A for operation.

[0049] like Figure 6 As shown, during the discharge period P30, the discharge control signal SDG has multiple continuous pulses P21 to P23, and each pulse includes both an operating period and a non-operating period. Therefore, pulses P21 to P23 respectively include operating periods DN21 to DN23, and each includes non-operating periods DF21 to DF23.

[0050] See Figure 5 and Figure 6During the discharge period P30 and the subsequent sustaining period P40, the charging control signal SCH switches to a low voltage level and remains at that level. Therefore, the charging switch SW11 is continuously turned off to cut off the charging path between the power supply voltage VCC and node N10. Furthermore, during the discharge period P30, the control circuit 10 turns on the discharge switch SW13 during the operation of the discharge control signal SDG (DN21–DN23), allowing capacitor Cg to discharge through the current source CU2. Therefore, multiple discharge stages SD21–SD23 are generated during the gradually decreasing falling band of the gate capacitor voltage signal VCg. (See also...) Figure 5 and Figure 6 During the operating period DN21 to DN23, the gate current ICg of capacitor Cg has a discharge current value -i2, where the discharge current value -i2 is negative, indicating that the direction of the gate current ICg is outflow from capacitor Cg (i.e., capacitor Cg is discharging). During the discharge period P30, the control circuit 10 turns off the discharge switch SW13 during multiple non-operating periods DF21 to DF23 of the discharge control signal SDG, causing the discharge circuit 13A to stop discharging capacitor Cg. Therefore, during the non-operating periods DF2 to DF23, the gate capacitor voltage signal VCg stops decreasing, and multiple stop-discharge horizontal segments SH21 to SH23 are generated in the falling band. After the discharge period P30, the electronic circuit 5 enters the maintenance period P40 for operation.

[0051] During the sustain period P40, the control circuit 10 causes the electrical control signal SDG to have a pulse P24. In this embodiment, the duration of the duty cycle (i.e., the pulse width of pulse P24) of pulse P24 is equal to the duration of the sustain period P40. See also Figure 5 and Figure 6 During the maintenance period P40, the discharge switch SW13 is turned on according to pulse P24, and the discharge circuit 13A discharges capacitor Cg again through the discharge current provided by current source CU2, causing the gate capacitor voltage signal VCg to drop again. When the gate capacitor voltage signal VCg drops to the aforementioned trough level or a preset low level, the gate current ICg becomes zero, and the discharge switch SW13 remains on according to pulse P24 to maintain the gate capacitor voltage signal VCg at the aforementioned trough level or a preset low level. At the end of the maintenance period P40, the discharge control signal SDG switches to a low voltage level (i.e., pulse P24 ends). After the maintenance period P40, the electronic circuit 5 enters the charging period P10 of the next switching period for operation.

[0052] Figure 7 The waveform diagram of the main signals of the electronic circuit in the fifth embodiment of the present invention is shown. Figure 7 The multi-pulse pattern of the charging control signal SCH is as follows: Figure 1 , Figure 3 , Figure 5 and Figure 15 Another example of their respective charging control signals SCH, and Figure 7 The multi-pulse pattern of the discharge control signal SDG is as follows: Figure 3 , Figure 5 and Figure 15 Another example of their respective discharge control signals SDG.

[0053] Comparison Figure 6 and Figure 7 , Figure 7 Compared to Figure 6 The difference lies in that, during charging period P10, the discharge control signal SDG has the same pulse pattern as the charging control signal SCH. According to the operation of the charging circuit 11A and the discharging circuit 13A in the aforementioned embodiment, the charging switch SW11 is turned on during the operation of the charging control signal SCH, and the discharging switch SW13 is turned on during the operation of the discharging control signal SDG. Assume that the charging current value i1 is greater than the discharging current value i2. Figure 7 During the charging period P10, while the charging switch SW11 is turned on, the discharging switch SW13 is also turned on. This allows the current source circuit 110 to supply charging current to the first terminal of capacitor Cg, and simultaneously provides discharging current through current source CU2 to discharge capacitor Cg. For example... Figure 7 As shown, in the charging phase of the rising wave of the gate capacitor voltage signal VCg, capacitor Cg is charged according to the current difference between the charging current value i1 and the discharging current value i2 (i.e., the gate current ICg, ICg = i1 - i2 (positive value)). Compared to Figure 6 , Figure 7 The gate capacitor voltage signal VCg rises slowly from the trough level or initial low level to the peak level or preset high level during the rising phase. During the rising phase of the gate capacitor voltage signal VCg (i.e., during charging P10), appropriately using a gate current ICg with a charging current value i1 or a current difference (ICg = i1 - i2) to charge the capacitor Cg can improve the control accuracy of the conduction speed of the power stage circuit 12A.

[0054] Assume the discharge current i2 is greater than the charging current i1. According to other embodiments, during discharge P30, while charging switch SW11 is turned on, discharge switch SW13 is also turned on, so that current source circuit 110 supplies charging current to the first terminal of capacitor Cg, and simultaneously provides discharge current through current source CU2 to discharge capacitor Cg. In the charging phase of the falling band of the gate capacitor voltage signal VCg, capacitor Cg is discharged according to the current difference between charging current i1 and discharge current i2 (ICg = i1 - i2 (negative value)). Compared to Figure 6 In this embodiment, the gate capacitor voltage signal VCg discharges directly from the peak level or initial high level to the trough level or preset low level at a relatively slow speed during the falling band. During the falling band of the gate capacitor voltage signal VCg (i.e., during the discharge period P30), appropriately using a gate current ICg with a discharge current value i2 or a current difference (ICg = i1 - i2) to discharge the capacitor Cg can improve the control accuracy of the turn-off speed of the power stage circuit 12A.

[0055] Figures 8 to 11 The following are waveform diagrams of the signals of the electronic circuits in the sixth to ninth embodiments of the present invention. Figure 1 , Figure 3 , Figure 5 and Figure 15 The pulse pattern of the charging control signal SCH generated by the control circuit 10 and / or Figure 3 , Figure 5 and Figure 15 The pulse pattern of the discharge control signal SDG generated by the control circuit 10 can be the same as that of... Figure 8 The control signal SWA shown is as follows: Figure 9 The control signal SWb shown is as follows: Figure 10 The control signal SWc shown, or as... Figure 11 The pulse pattern of the control signal SWd is shown. (See also...) Figure 8 Multiple pulses of the control signal SWA have the same frequency, for example, all equal to a fixed frequency Fsw. (See also...) Figure 9 Multiple pulses of the control signal SWb have the same operating period, for example, all equal to the fixed on-time Ton. (See also...) Figure 10 Multiple pulses of the control signal SWc have the same non-operating period, for example, all equal to the fixed off time Toff. (See also...) Figure 11 The multiple pulses of the control signal SWd each have the same duty cycle D. The above pulse patterns are merely illustrative examples and are not intended to limit the scope of the invention.

[0056] Figure 12 This is a circuit diagram of the control circuit of the electronic circuit employing intermittent charging and discharging, according to the tenth embodiment of the present invention. Figure 13 The waveform diagram shows the charging control signal and other main signals of the electronic circuit during switching, as shown in the tenth embodiment of the present invention. Figure 14 The waveform diagram shows the discharge control signal and other main signals of the electronic circuit during switching, as shown in the tenth embodiment of the present invention. Figure 12 The control circuit 10A is Figure 1 , Figure 3 , Figure 5 and Figure 15This is one embodiment of the control circuit 10, but it is only illustrative and the invention is not limited thereto. Figure 12 As shown, the control circuit 10A includes a charge / discharge switching circuit 100, a comparator 101, a signal generation circuit 102, a judgment circuit 103, a sensing and comparison circuit 104, and a transition detection circuit 105. During multiple switching periods, the control circuit 10A controls the power stage circuit 12A through the charging control signal SCH and the discharging control signal SDG.

[0057] Sensing circuit 120 is coupled to the control terminal (gate) and the second terminal (source) of power transistor M1 to sense the actual voltage difference VGS between the control terminal and the second terminal, and outputs a sensed voltage signal S30. The voltage level of the sensed voltage signal S30 represents the actual voltage difference VGS. In one embodiment, the voltage level of the sensed voltage signal S30 is equal to the value of the actual voltage difference VGS. A plurality of comparators 121 to 123 (described in detail below) of sensing comparator circuit 104 receive the sensed voltage signal S30 from sensing circuit 120 and compare the sensed voltage signal S30 with a plurality of reference voltages V31 to V33 respectively, and output a plurality of comparison signals S31 to S33 respectively.

[0058] The judgment circuit 103 is coupled to the sensing comparison circuit 104 to receive comparison signals S31 to S33, and determines the time difference between the time taken for the sensed voltage signal S30 to reach each reference voltage V31 to V33 and the time threshold value based on the comparison signals S31 to S33, and generates a trigger signal S34 based on the judgment result. The signal generation circuit 102 is coupled to the first output terminal of the judgment circuit 103 to receive the trigger signal S34, and generates a state signal Vstate based on the trigger signal S34. In this embodiment, the signal generation circuit 102 controls the voltage level of the state signal Vstate based on the trigger signal S34. As described above, the trigger signal S34 is generated based on the level change of the sensed voltage signal S30 (representing the actual voltage difference VGS of the power transistor M1), and the signal generation circuit 102 generates the state signal Vstate under the control of the trigger signal S34. Therefore, the state signal Vstate depends on the change state of the actual voltage difference VGS.

[0059] The first input terminal of comparator 101 (e.g., the inverting input terminal (-)) receives a reference voltage signal Vsaw, and its second input terminal (e.g., the non-inverting input terminal (+)) is coupled to signal generation circuit 102 to receive a status signal Vstate. Comparator 101 compares the status signal Vstate with the reference voltage signal Vsaw to generate a switching signal S37 at the output terminal of comparator 101. When the voltage level of the status signal Vstate is higher than the voltage level of the reference voltage signal Vsaw, the switching signal S37 is at a high voltage level (corresponding to the operating period); when the voltage level of the status signal Vstate is lower than the voltage level of the reference voltage signal Vsaw, the switching signal S37 is at a low voltage level (corresponding to the non-operating period). The input terminal of charge / discharge switching circuit 100 is coupled to the output terminal of comparator 101 to receive the switching signal S37. The first output terminal of charge / discharge switching circuit 100 serves as the first output terminal of control circuit 10A, and is coupled to... Figure 1 or Figure 3 The input terminal of the charging circuit 11 shown, or coupled to, is as follows Figure 5 The charging circuit 11A shown, or coupled to, as Figure 15 The charging circuit 11B shown includes the control terminal of the charging switch SW11. The second output terminal of the charge / discharge switching circuit 100, serving as the second output terminal of the control circuit 10A, is coupled to... Figure 3 The input terminal of the discharge circuit 13 shown, or coupled to, is as follows Figure 5 The discharge circuit 13A shown, or coupled to, as Figure 15 The control terminal of the discharge switch SW13 included in the discharge circuit 13B shown.

[0060] See Figure 12 The sensing comparator circuit 104 may include a sensing circuit 120, a plurality of comparators 121-123, and a plurality of reference resistors R31-R33. In other embodiments, the sensing circuit 120 may be disposed outside the sensing comparator circuit 104. The first input terminal (e.g., the non-inverting input (+)) of each of the comparators 121-123 is coupled to the output terminal of the sensing circuit 120 to receive the sensed voltage signal S30. The reference resistors R31-R33 are sequentially connected in series between the power supply voltage VDD and the ground terminal GND. Specifically, the first terminal of the reference resistor R31 is coupled to the power supply voltage VDD, the second terminal of the reference resistor R31 is coupled to the first terminal of the reference resistor R32, the second terminal of the reference resistor R32 is coupled to the first terminal of the reference resistor R33, and the second terminal of the reference resistor R33 is coupled to the ground terminal GND. The reference resistors R31-R33 perform a voltage divider operation on the voltage difference between the power supply voltage VDD and the ground terminal GND to generate reference voltages V31, V32, and V33.

[0061] The second input terminal of comparator 121 (e.g., the inverting input (-)) is coupled to the first terminal of reference resistor R31 to receive the power supply voltage VDD as the reference voltage V31. Comparator 121 compares the voltage of the sensed voltage signal S30 with the reference voltage V31 to generate a comparison signal S31 at the output terminal of comparator 121. The second input terminal of comparator 122 (e.g., the non-inverting input) is coupled to the common node between reference resistors R31 and R32 to receive the reference voltage V32 from this common node. Comparator 122 compares the voltage of the sensed voltage signal S30 with the reference voltage V32 to generate a comparison signal S32 at the output terminal of comparator 122. The second input terminal of comparator 123 (e.g., the non-inverting input) is coupled to the common node between reference resistors R32 and R33 to receive the reference voltage V33 from this common node. Comparator 123 compares the voltage of the sensed voltage signal S30 with the reference voltage V33 to generate a comparison signal S33 at the output of comparator 123. The comparison signals S31 to S33 are then provided to the judgment circuit 103.

[0062] See Figure 12 The signal generation circuit 102 may include switches SW1 and SW2, an input current source CUin, and an input capacitor Cin. The first terminal of switch SW1 is coupled to the second input terminal of comparator 101 at node N11. The first terminal of the input current source CUin is coupled to the second terminal of switch SW1, and its second terminal is coupled to ground GND. The control terminal of switch SW1 is coupled to the first output terminal of judgment circuit 103 to receive a trigger signal S34. The first terminal of input capacitor Cin and the first terminal of switch SW2 are coupled to node N11. The second terminals of input capacitor Cin and the second terminal of switch SW2 are coupled to ground GND. Judgment circuit 103 also generates a reset signal S35. The control terminal of switch SW2 is coupled to the second output terminal of judgment circuit 103 to receive the reset signal S35.

[0063] When switch SW1 is turned on according to trigger signal S34, the input current provided by input current source CUin flows through switch SW1 to node N11 to charge input capacitor Cin, increasing the voltage at the first terminal of input capacitor Cin (i.e., the voltage at node N11). The voltage signal at the first terminal of input capacitor Cin serves as the state signal Vstate. The judgment circuit 103 then determines the state signal Vstate at intervals equal to a time threshold value (e.g., ...). Figure 13 The ideal interval time t0) enables the reset signal S35 (for example, to make the reset signal S35 have a pulse to turn on the switch SW2 to discharge the input capacitor Cin, thereby resetting the voltage of the second input terminal of the comparator 101 to zero).

[0064] The charge / discharge switching circuit 100 uses the switching signal S37 received from the output of the comparator 101 as the charging control signal SCH and / or the discharging control signal SDG. For example, the charge / discharge switching circuit 100 can determine whether to output the switching signal S37 as the charging control signal SCH and / or the discharging control signal SDG based on the state change detection signal S38 received from the state change detection circuit 105, as detailed below.

[0065] The transition detection circuit 105 receives an indication signal S39 (from an external circuit). According to one embodiment of the invention, the rising edge of the indication signal S39 indicates that the gate capacitor voltage signal VCg has entered the rising band, and the falling edge of the indication signal S39 indicates that the gate capacitor voltage signal VCg has entered the falling band. The transition detection circuit 105 detects the rising and falling edges of this indication signal S39 to output a transition detection signal S38. According to one embodiment of the invention, during switching, whenever the transition detection circuit 105 detects such... Figure 13 When the rising edge of the indicated signal S39 is reached, the transition detection circuit 105 outputs a transition detection signal S38 with charging indication information to the charge / discharge switching circuit 100, so as to instruct the charge / discharge switching circuit 100 to use the switching signal S37 as the charging control signal SCH, thereby charging the capacitor Cg of the power stage circuit 12A and causing the power transistor M1 to enter the conduction state.

[0066] According to an embodiment of the present invention, during the switching period, whenever the switching detection circuit 105 detects such as Figure 14 When the falling edge of the indicated signal S39 is reached, the transition detection circuit 105 outputs a transition detection signal S38 with discharge indication information to the charge / discharge switching circuit 100, instructing the charge / discharge switching circuit 100 to use the switching signal S37 as the discharge control signal SDG, thereby discharging the capacitor Cg of the power stage circuit 12A and causing the power transistor M1 to enter the off state. As described above, the indicated signal S39 can represent the on and off states of the power transistor M1 during each switching period. In some embodiments, the transition detection circuit 105 may be located within the judgment circuit 103, and the judgment circuit 103 generates and outputs the transition detection signal S38. In other embodiments, the transition detection circuit 105 may be omitted, and the judgment circuit 103 detects the rising and falling edges of this indicated signal S39 and generates and outputs the transition detection signal S38.

[0067] like Figure 13 , Figure 14 As shown, during the switching period, the curve of the actual voltage difference VGS of power transistor M1 changing with time may deviate from the curve of the ideal voltage difference VGSTG changing with time. See [reference needed]. Figure 13Starting from the rising edge of indicator signal S39, the ideal voltage difference VGSTG takes ideal time (Tideal) to rise from 0 volts to the supply voltage VDD; see also Figure 14 Starting from the falling edge of the indicator signal S39, the ideal voltage difference VGSTG takes an ideal time, Tideal, to drop from the power supply voltage VDD to 0 volts. According to this embodiment of the invention, the power supply voltage VDD is divided into m voltage segments on average. For example, the power supply voltage VDD is divided into 3 (m = 3) voltage segments on average. Ideally, the actual voltage difference VGS of the power transistor M1 increases from 0 volts to 1 / 3 of the default power supply voltage VDD (first target voltage) after an ideal interval time t0, then increases from 1 / 3 to 2 / 3 (second target voltage) after another ideal interval time t0, and then increases from 2 / 3 to VDD (third target voltage) after yet another ideal interval time t0. Therefore, the ideal time Tideal is divided into 3 ideal interval times t0, i.e., t0 = Tideal / m, where m = 3. Similarly, ideally, the actual voltage difference VGS decreases from the power supply voltage VDD to 2 / 3 of the power supply voltage VDD, from 2 / 3 of the power supply voltage VDD to 1 / 3, and from 1 / 3 of the power supply voltage VDD to 0 volts in three ideal time intervals t0.

[0068] As described above, whenever the judgment circuit 103 enables the reset signal S35, the switch SW2 is turned on according to the enabled reset signal S35 (i.e., according to the pulse of the reset signal S35), causing the voltage of the input capacitor Cin to discharge and reset to zero. Ideally, whenever the judgment circuit 103 enables the reset signal S35, the judgment circuit 103 causes the trigger signal S34 to have an initial pulse P31, and the initial pulse P31 has a preset operating period DN31. In this embodiment, the preset operating period DN31 is equal to the ideal interval time t0 divided by a constant k (DN31 = t0 / k). In one embodiment, the constant k is preset according to system requirements. At each ideal time Tideal, the trigger signal S34 has three initial pulses P31, corresponding to three ideal interval times t0 respectively. Figure 13 , Figure 14 In the diagram, the initial pulse P31 is represented by a dashed line. Because some initial pulses P31 completely or partially overlap with modulated pulses represented by solid lines (e.g., modulated pulses P41–P43, modulated pulses P81–P83, described later), therefore… Figure 13 , Figure 14 The dashed line in the initial pulse P31 that overlaps with the modulated pulse is not shown.

[0069] However, in reality, during the switching period, the actual voltage difference VGS of the power transistor M1 may reach at least one target voltage on time, early, or late. Therefore, the control circuit 10A of this embodiment adjusts the operating period of multiple pulses of at least one of the charging control signal SCH and the discharging control signal SDG according to the actual voltage difference VGS of the power transistor M1, so that the actual voltage difference VGS can gradually approach the ideal voltage difference VGSTG.

[0070] See Figure 12 The judgment circuit 103 also receives the indication signal S39. For example... Figure 13 As shown, based on the rising edge of the indicator signal S39, the electronic circuit enters the current switching period. The charge / discharge switching circuit 100 uses the switching signal S37 as the charging control signal SCH according to the state detection signal S38, and the gate capacitor voltage signal VCg enters the rising band (i.e., enters the charging period of the power stage circuit 12A), causing the actual voltage difference VGS of the power transistor M1 to gradually increase with the gate capacitor voltage signal VCg. In detail, at the rising edge of the indicator signal S39 (i.e., the start time of the first ideal interval time t0 during the charging period) and the start time of the second and third ideal interval times t0 respectively, the determination circuit 103 causes the reset signal S35 to have pulses to turn on the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero. In this embodiment, assuming that at the start time of each of the first to third ideal interval times t0, the determination circuit 103 causes the trigger signal S34 to have an initial pulse P31. In other words, during the current switching period, the initial pulse P31 serves as the modulated pulses P41 to P43 of the trigger signal S34, and the actual working period Tvty(t) of the modulated pulses P41 to P43 is equal to DN31 (=t0 / k) (y is 41, 42, or 43), so that the switch SW1 is turned on, causing the input capacitor Cin to be charged, and the voltage level of the state signal Vstate begins to increase, such as... Figure 13 The state signal Vstate is represented by a dashed line. Based on the state signal Vstate during the current switching period, the charging control signal SCH has three initial pulses P60 during the first to third ideal interval times t0, respectively, through the operation of comparator 101 and the charging / discharging switching circuit 100. Assuming that during the charging period of the current switching period, based on these three initial pulses P60, as follows... Figure 13 As shown, the curve of the actual voltage difference VGS changing with time deviates from the curve of the ideal voltage difference VGSTG changing with time. Based on the above, it can be seen that these three initial pulses P60 correspond to the three initial pulses P31 of the trigger signal S34. The initial pulse P60 is represented by a dashed line, while the modulation pulses P61 to P63 (described later) are represented by solid lines. Figure 13There should be three initial pulse waves P60, but since the first initial pulse wave P60 completely overlaps with the modulated pulse wave P61, therefore... Figure 13 The first initial pulse P60 is not shown in the image.

[0071] See Figure 13 During this current switching period, starting from the beginning of the first ideal interval time t0, the actual voltage difference VGS of the power transistor M1 takes equal to the actual interval time t11 of the ideal interval time t0 to reach 1 / 3 of the power supply voltage VDD from 0 volts, i.e., t11 = t0. Therefore, the actual interval time t11 minus the ideal interval time t0 yields the time difference Δt11 (Δt11 = t11 - t0 = 0, i.e., there is no error between the actual interval time t11 and the ideal interval time t0). In an embodiment of the present invention, once the actual voltage difference VGS increases from 0 volts and reaches 1 / 3 of the power supply voltage VDD, the voltage level of the sensed voltage signal S30 is equal to the reference voltage V33. At this time, the comparison signal S33 output by the comparator 123 switches to a high voltage level. The determination circuit 103 obtains the actual interval time t11 based on the rising edge of the indication signal S39 and the time when the comparison signal S33 switches to a high voltage level. The judgment circuit 103 determines that the actual interval time t11 is equal to the ideal interval time t0 (t11=t0), and calculates that the time difference Δt11 is equal to zero (Δt11=0).

[0072] According to Equation 1, the judgment circuit 103 determines the actual operating period of one of the multiple modulated pulses of the trigger signal S34 during the next switching period:

[0073] Tvty(t+1)=Tvty(t)+c*Δtx (Formula 1)

[0074] Where Tvty(t) represents the actual operating period of a modulated pulse of the trigger signal S34 during the current switching period, Tvty(t+1) represents the actual operating period of a modulated pulse of the trigger signal S34 during the next switching period, c is a predetermined error compensation coefficient, x is 11, 12, 13, 21, 22, or 23, and y is 41, 42, 43, 81, 82, or 83.

[0075] As described above, during the current switching period, the actual operating period Tvt41(t) of the modulated pulse P41 of the trigger signal S34 is equal to DN31 (=t0 / k), and Δt11=0. Therefore, according to Equation 1, the judgment circuit 103 determines that the actual operating period Tvt41(t+1) of the modulated pulse P41 of the trigger signal S34 in the next switching period is equal to t0 / k, that is, equal to the preset operating period DN31 (Tvt41(t+1)=t0 / k+c*0=t0 / k=DN31). In this embodiment, the multiple modulated pulses of the trigger signal S34 are represented by solid lines. Therefore, the modulated pulse P41 of the solid line overlaps with the initial pulse P31 of the corresponding dashed line. Figure 13 Only the modulated pulse P41 is presented in the middle.

[0076] As described above, the actual operating period Tvt41 of the modulated pulse P41 is equal to the preset operating period DN31 of the initial pulse P31. During the next switching period, switch SW1 is turned on within the preset operating period DN31 according to the modulated pulse P41, and the input current provided by the input current source Cuin charges the input capacitor Cin via switch SW1 for the duration of the preset operating period DN31. Figure 13 As shown, the duration during which the actual voltage level of the state signal Vstate (indicated by the solid line) is higher than the voltage level of the reference voltage signal Vsaw is equal to the ideal operating period (i.e., the operating period of the initial pulse P60). Thus, the duration for which the switching signal S37 is at a high voltage level is equal to the aforementioned ideal operating period. In the next switching period, when the charge / discharge switching circuit 100 outputs the switching signal S37 as the charging control signal SCH based on the rising edge of the indicator signal S39 via the state detection signal S38, the charge / discharge switching circuit 100 controls the first pulse of the charging control signal SCH to have an operating period equal to the aforementioned ideal operating period (i.e., the modulated pulse P61, whose operating period is equal to the aforementioned ideal operating period), making the conduction period of the power transistor M1 equal to the aforementioned ideal operating period.

[0077] See Figure 13During this current switching period, starting from the beginning of the second ideal interval time t0, the actual voltage difference VGS of the power transistor M1 takes an actual interval time t12 to reach 2 / 3 of the power supply voltage VDD, which is delayed from 1 / 3 of the power supply voltage VDD. Since the actual interval time t12 is greater than the ideal interval time t0 (i.e., t12 > t0), the actual interval time t12 minus the ideal interval time t0 yields the time difference Δt12 (Δt12 = t12 - t0 > 0, meaning there is an error between the actual interval time t12 and the ideal interval time t0). In an embodiment of the invention, once the actual voltage difference VGS increases from 1 / 3 of the power supply voltage VDD and reaches 2 / 3 of the power supply voltage VDD, the voltage level of the sensed voltage signal S30 equals the reference voltage V32. At this time, the comparison signal S32 output by comparator 122 switches to a high voltage level. The determination circuit 103 obtains the actual interval time t12 based on the beginning of the second ideal interval time t0 and the time when the comparison signal S32 switches to a high voltage level. The judgment circuit 103 determines that the actual interval time t12 is greater than the ideal interval time t0 (t12>t0), and calculates that the time difference Δt12 is greater than zero (Δt12>0). As mentioned above, during the current switching period, the actual working period Tvt42(t) of the modulated pulse P42 of the trigger signal S34 is equal to DN31 (=t0 / k). According to Equation 1, the judgment circuit 103 determines that during the next switching period, the actual working period Tvt42(t+1) of the modulated pulse P42 of the trigger signal S34 is equal to t0 / k+c*Δt12, which is greater than the preset working period DN31 (Tvt42(t+1)=t0 / k+c*Δt12>DN31).

[0078] As described above, the actual operating period Tvt42 of the modulated pulse P42 is greater than the preset operating period DN31 of the initial pulse P31. Therefore, during the next switching period, switch SW1 is turned on for the longer actual operating period Tvt42 according to the modulated pulse P42, and the time for the input current provided by the input current source Cuin to charge the input capacitor Cin via switch SW1 becomes longer (longer than the preset operating period DN31), as... Figure 13As shown, the duration during which the actual voltage level of the status signal Vstate marked by a solid line is higher than the voltage level of the reference voltage signal Vsaw becomes longer (longer than the above-mentioned ideal operating period). In this way, the duration during which the switching signal S37 is at a high voltage level becomes longer. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the charge control signal SCH based on the rising edge of the indication signal S39, the charge-discharge switching circuit 100 controls the duty cycle of the second pulse of the charge control signal SCH to be longer than the above-mentioned ideal operating period (that is, modulates the pulse P62, whose duty cycle is longer than the above-mentioned ideal operating period), making the conduction period of the power transistor M1 longer. Since the second initial pulse P60 partially overlaps with the modulated pulse P62 presented by a solid line, Figure 13 the dotted line indicating the overlapping part of the second initial pulse P60 and the modulated pulse P62 in Figure 13 is not shown.

[0079] Refer to Figure 13 , in this current switching period, starting from the starting point of the third ideal interval time t0, the actual voltage difference VGS of the power transistor M1 reaches the power supply voltage VDD from 2 / 3 of the power supply voltage VDD in the actual interval time t13, and the actual interval time t13 is less than the ideal interval time t0, that is, t13 < t0. Therefore, the time difference Δt13 is obtained by subtracting the ideal interval time t0 from the actual interval time t13 (Δt13 = t13 - t0 < 0). In an embodiment of the present invention, once the actual voltage difference VGS increases from 2 / 3 of the power supply voltage VDD and reaches the power supply voltage VDD, the voltage level of the sense voltage signal S30 is equal to the reference voltage V33. At this time, the comparison signal S31 output by the comparator 121 switches to a high voltage level. The determination circuit 103 obtains the actual interval time t13 based on the starting point of the third ideal interval time t0 and the point when the comparison signal S31 switches to a high voltage level. The determination circuit 103 determines that the actual interval time t13 is less than the ideal interval time t0 (t13 < t0), and calculates that the time difference Δt13 is less than zero (Δt13 < 0, that is, there is an error between the actual interval time t13 and the ideal interval time t0). As described above, in the current switching period, the actual operating period Tvt43(t) of the modulated pulse P43 of the trigger signal S34 is equal to DN31 (= t0 / k). According to Equation 1, the determination circuit 103 determines that the actual operating period Tvt43(t + 1) of the modulated pulse P43 of the trigger signal S34 in the next switching period is equal to t0 / k + c * Δt13, that is, less than the preset operating period DN31 (Tvt43(t + 1) = t0 / k + c * Δt13 < DN31).

[0080] As described above, the actual operating period Tvt43 of the modulated pulse P43 is less than the preset operating period DN31 of the initial pulse P31. Therefore, in the next switching period, switch SW1 is turned on during the shorter actual operating period Tvt43 according to the modulated pulse P43, and the time for the input current provided by the input current source Cuin to charge the input capacitor Cin via switch SW1 is shortened (shorter than the preset operating period DN31). Figure 13 As shown, this shortens the duration for which the actual voltage level of the state signal Vstate (indicated by the solid line) is higher than the voltage level of the reference voltage signal Vsaw (shorter than the ideal operating period). Consequently, the duration for which the switching signal S37 is at a high voltage level is shortened. During the next switching period, when the charge / discharge switching circuit 100 outputs the switching signal S37 as the charging control signal SCH based on the rising edge of the indicator signal S39, the operating period of the third pulse of the charging control signal SCH controlled by the charge / discharge switching circuit 100 is shorter than the ideal operating period (i.e., the modulated pulse P63 has a shorter operating period than the ideal operating period), thus shortening the on-time of the power transistor M1. Since the third initial pulse P60 partially overlaps with the modulated pulse P63 (indicated by the solid line), therefore... Figure 13 The dashed line at the point where the third initial pulse P60 overlaps with the modulated pulse P63 is not shown in the image.

[0081] During each switching period, at the end of the third ideal interval time t0 during the charging period, the determination circuit 103 pulses the reset signal S35 again to turn on the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero. Simultaneously, at the end of the third ideal interval time t0, the charge / discharge switching circuit 100 pulses the charging control signal SCH with a pulse P64, and the pulse width of P64 ends at the falling edge of the indicator signal S39. During the pulse width of P64 (i.e., during the maintenance period of the power stage circuit 12A), the charging switch SW11 remains on according to P64, and the gate capacitor voltage signal VCg rises and remains at the peak level or a preset high level, causing the actual voltage difference VGS of the power transistor M1 to rise and remain at a specific level (this specific level is higher than the power supply voltage VDD level).

[0082] In one embodiment, during each switching period, based on the rising edge of the indication signal S39, the determination circuit 103 starts counting the number of pulses of the reset signal S35. When the cumulative number of pulses of the reset signal S35 starting from the rising edge of the indication signal S39 reaches a pulse count threshold (e.g., ...), the count continues. Figure 13 When there are four (=m+1=3+1) as shown, the judgment circuit 103 outputs a control signal S40 to control the charge-discharge switching circuit 100, so that its output charging control signal SCH has a pulse P64.

[0083] As described above, based on the rising edge of the indicator signal S39, the gate capacitor voltage signal VCg enters the rising band. During the rising band of the gate capacitor voltage signal VCg, the intermittent charging and discharging method of the present invention adjusts the operating period of multiple pulses of the charging control signal SCH (i.e., the on-time of the charging switch SW11) according to the actual voltage difference VGS of the power transistor M1. In this way, the change in the actual voltage difference VGS of the power transistor M1 can gradually approach the ideal voltage difference VGSTG.

[0084] During each switching period, during the charging and sustaining periods of the power stage circuit 12A, the charge / discharge switching circuit 100 controls the discharge control signal SDG to remain at a low voltage level to turn off the discharge switch SW13, thereby cutting off the discharge path between node N10 and ground terminal GND until the falling edge of the indicator signal S39.

[0085] like Figure 14 As shown, during the current switching period, based on the falling edge of the indication signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as the discharge control signal SDG according to the state detection signal S38, and the gate capacitor voltage signal VCg enters the falling band (i.e., the discharge period of the power stage circuit 12A), causing the actual voltage difference VGS of the power transistor M1 to gradually decrease along with the gate capacitor voltage signal VCg. During the discharge period, the charge / discharge switching circuit 100 first controls the discharge control signal SDG to have a pulse P80, so that the discharge switch SW13 is turned on during the operation of the pulse P80, causing the actual voltage difference VGS of the power transistor M1 to start decreasing from a specific level higher than the power supply voltage VDD. The operation period of the pulse P80 is preset, starting at the point when the actual voltage difference VGS begins to decrease from the specific level, and ending at the point when the reset signal S35 makes its first pulse during the discharge period.

[0086] Furthermore, based on the falling edge of the indicator signal S39, the charge / discharge switching circuit 100 controls the charging control signal SCH to switch to a low voltage level and maintains it at the low voltage level until the rising edge of the indicator signal S39 during the next switching period.

[0087] Next, during the current switching period, at the start of each of the first to third ideal intervals t0 during the discharge period, the determination circuit 103 causes the reset signal S35 to have a pulse to turn on the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero. In this embodiment, it is assumed that at the start of each of the first to third ideal intervals t0 during the discharge period, the determination circuit 103 causes the trigger signal S34 to have an initial pulse P31. In other words, during the current switching period, the initial pulse P31 serves as the modulated pulses P81 to P83 of the trigger signal S34, and the actual operating period Tvty(t) of the modulated pulses P81 to P83 is equal to DN31 (=t0 / k) (y is 81, 82, or 83). Furthermore, at the start of each of the first to third ideal intervals t0 during the discharge period, the determination circuit 103 causes the trigger signal S34 to have an initial pulse P31 to turn on the switch SW1, causing the input capacitor Cin to be charged, and the voltage level of the state signal Vstate begins to increase, such as Figure 14 The state signal Vstate is represented by a dashed line. Based on the state signal Vstate during the current switching period, the charging control signal SCH has three initial pulses P60 during the first to third ideal interval times t0, respectively, through the operation of comparator 101 and the charge / discharge switching circuit 100. During the discharge period of the current switching period, based on these three initial pulses P60, as follows... Figure 14 As shown, the curve of the actual voltage difference VGS changing with time deviates from the curve of the ideal voltage difference VGSTG changing with time. As can be seen from the above, the three initial pulses P60 during the discharge period correspond to the three initial pulses P31 of the trigger signal S34. The initial pulses P60 are represented by dashed lines, while the modulated pulses P91 to P93 (described later) are represented by solid lines.

[0088] See Figure 14, during this current switching period, starting from the starting point of the first ideal interval time t0, the actual voltage difference VGS reaches 2 / 3 of the power supply voltage VDD in an actual interval time t23 shorter than the ideal interval time t0, that is, t23 < t0. According to the above description and the analogous operation during the charging period, the judgment circuit 103 calculates that the time difference Δt23 is less than zero (Δt23 = t23 - t0 < 0, that is, there is an error between the actual interval time t23 and the ideal interval time t0). As described above, during the current switching period, the actual working period Tvt81(t) of the modulation pulse P81 of the trigger signal S34 is equal to DN31 (= t0 / k). According to Equation 1, the judgment circuit 103 determines that the actual working period Tvt81(t + 1) of the modulation pulse P81 of the trigger signal S34 in the next switching period is equal to t0 / k + c * Δt23, that is, less than the preset working period DN31 (Tvt81(t + 1) = t0 / k + c * Δt23 < DN31). The switch SW1 conducts in a shorter actual working period Tvt81, and the charging time of the input capacitor Cin becomes shorter (shorter than the time length of the preset working period DN31), as Figure 14 shown, so that the duration during which the actual voltage level of the status signal Vstate is higher than the voltage level of the reference voltage signal Vsaw becomes shorter (shorter than the above ideal working period). In this way, the duration during which the switching signal S37 is at a high voltage level becomes shorter. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the discharge control signal SDG based on the falling edge of the indication signal S39, the charge-discharge switching circuit 100 controls the working period of the first pulse of the discharge control signal SDG to be shorter than the above ideal working period (that is, the modulation pulse P91, whose working cycle is shorter than the above ideal working period), making the conduction time of the power transistor M1 shorter. Since the first initial pulse P60 and the modulation pulse P91 partially overlap, Figure 14 the dotted line indicating the overlapping part of the first initial pulse P60 and the modulation pulse P91 in

[0089] is not shown. Figure 14 , the starting point of the working period of the modulation pulse P91 overlaps with the ending point of the working period of the pulse P80, so Figure 14 the rising edge of the modulation pulse P91 is not presented in

[0090] Refer to Figure 14During this current switching period, starting from the beginning of the second ideal interval time t0, the actual voltage difference VGS takes a longer time than the ideal interval time t0, from 2 / 3 of the power supply voltage VDD to 1 / 3 of the power supply voltage VDD, i.e., t22>t0. Based on the above description and the analogy during charging, the judgment circuit 103 calculates that the time difference Δt22 is greater than zero (Δt22=t22-t0>0, i.e., there is an error between the actual interval time t22 and the ideal interval time t0). As mentioned above, during the current switching period, the actual operating period Tvt82(t) of the modulation pulse P82 of the trigger signal S34 is equal to DN31(=t0 / k). According to Equation 1, the judgment circuit 103 determines that the actual working period Tvt82(t+1) of the modulated pulse P82 of the trigger signal S34 in the next switching period is equal to t0 / k+c*Δt22, which is greater than the preset working period DN31 (Tvt82(t+1)=t0 / k+c*Δt22>DN31). Switch SW1 is turned on during the longer actual working period Tvt82, and the charging time of the input capacitor Cin becomes longer (longer than the preset working period DN31), such as... Figure 14 As shown, this makes the duration for which the actual voltage level of the state signal Vstate is higher than the voltage level of the reference voltage signal Vsaw longer (longer than the ideal operating period). Consequently, the duration for which the switching signal S37 is at a high voltage level is longer. During the next switching period, when the charge / discharge switching circuit 100 outputs the switching signal S37 as the discharge control signal SDG based on the falling edge of the indicator signal S39, the second pulse of the discharge control signal SDG controlled by the charge / discharge switching circuit 100 operates for a period longer than the ideal operating period (i.e., the modulated pulse P92 has a longer operating period than the ideal operating period), thus increasing the on-time of the power transistor M1. Since the second initial pulse P60 partially overlaps with the modulated pulse P92, therefore... Figure 14 The dashed line at the point where the second initial pulse P60 overlaps with the modulated pulse P92 is not shown in the image.

[0091] See Figure 14, during this current switching period, starting from the start point of the third ideal interval time t0, the actual voltage difference VGS reaches 0 volts earlier than the ideal interval time t0 by 1 / 3 of the power supply voltage VDD within the actual interval time t21, that is, t21 < t0. According to the above description and the analogous operation during the charging period, the determination circuit 103 calculates that the time difference Δt21 is less than zero (Δt21 = t21 - t0 < 0, that is, there is an error between the actual interval time t21 and the ideal interval time t0). As described above, during the current switching period, the actual working period Tvt83(t) of the modulation pulse P83 of the trigger signal S34 is equal to DN31 ( = t0 / k). According to Equation 1, the determination circuit 103 determines that in the next switching period, the actual working period Tvt83(t + 1) of the modulation pulse P83 of the trigger signal S34 is equal to t0 / k + c*Δt21, that is, less than the preset working period DN31 (Tvt83 = t0 / k + c*Δt21 < DN31). The switch SW1 conducts during the shorter actual working period Tvt83, and the charging time of the input capacitor Cin becomes shorter (shorter than the time length of the preset working period DN31), as Figure 14 shown, making the duration during which the actual voltage level of the status signal Vstate is higher than the voltage level of the reference voltage signal Vsaw shorter (shorter than the above ideal working period). In this way, the duration during which the switching signal S37 is at the high voltage level becomes shorter. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the discharge control signal SDG based on the falling edge of the indication signal S39, the charge-discharge switching circuit 100 controls the working period of the third pulse of the discharge control signal SDG to be shorter than the above ideal working period (that is, the modulation pulse P93, whose working cycle is shorter than the above ideal working period), making the conduction time of the power transistor M1 shorter. Since the third initial pulse P60 and the modulation pulse P93 partially overlap, Figure 14 the dotted line indicating the overlapping part of the third initial pulse P60 and the modulation pulse P93 is not shown in

[0092] In each switching period, at the end point of the third ideal interval time t0 during the discharge period, the determination circuit 103 makes the reset signal S35 have a pulse again to conduct the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero again. At the same time, at the end point of the third ideal interval time t0, the charge-discharge switching circuit 100 makes the discharge control signal SDG have a pulse P94, and the pulse width period of the pulse P94 ends at the rising edge of the indication signal S39. During the pulse width period of the pulse P94 (that is, during the maintenance period of the power stage circuit 12A), the discharge switch SW13 continuously conducts according to the pulse P94, and the gate capacitor voltage signal VCg is maintained at the valley level or a preset low level, making the actual voltage difference VGS of the power transistor M1 maintained at 0 volts.

[0093] According to one embodiment, during each switching period, based on the falling edge of the indicator signal S39, the determination circuit 103 starts counting the number of pulses of the reset signal S35. When the cumulative number of pulses of the reset signal S35 starting from the falling edge of the indicator signal S39 reaches a pulse count threshold (e.g., ...), the count continues. Figure 14 When there are four (=m+1=3+1) as shown, the judgment circuit 103 outputs a control signal S40 to control the charge-discharge switching circuit 100, so that its output discharge control signal SDG has a pulse P94.

[0094] As described above, based on the falling edge of the indicator signal S39, the gate capacitor voltage signal VCg enters the falling band. During the falling band of the gate capacitor voltage signal VCg, the intermittent charging and discharging method of the present invention adjusts the operating period of multiple pulses of the discharge control signal SDG (i.e., the on-time of the discharge switch SW13) according to the actual voltage difference VGS of the power transistor M1, so that the change of the actual voltage difference VGS of the power transistor M1 can be closer to the ideal voltage difference VGSTG.

[0095] Based on the above, during the current switching period, the control circuit 10A determines the pulse patterns of the charging control signal SCH and the discharging control signal SDG during the next switching period based on the actual voltage difference VGS. This achieves the intermittent charging and discharging method of the present invention, thereby improving the accuracy of charging and discharging control and flexibly controlling the charging and discharging states of the power stage circuit 12A. Through the charging and discharging control of this invention, the curve of the actual voltage difference VGS of the power transistor M1 changing with time can be changed, gradually conforming to the curve of the ideal voltage difference VGSTG changing with time, thereby enabling the output voltage level change rate of the power stage circuit 12A at the output terminal LIN to reach the desired value.

[0096] In the above embodiments, the pulse pattern of the charging control signal SCH and / or discharging control signal SDG is determined based on the actual gate-source voltage (VGS) of the power transistor M1. In other embodiments, the pulse pattern of the charging control signal SCH and / or discharging control signal SDG can be determined based on the drain-source voltage (VDS) of the power transistor M1. Specifically, the control circuit 10A can perform the pulse pattern based on the drain-source voltage of the power transistor M1 dropping from the supply voltage VDD to 0 volts in an ideal time, Tideal. Figures 12 to 14 Similar operations are performed to determine the pulse pattern of the charging control signal SCH and / or the discharging control signal SDG. Please refer to the relevant description. Figures 12 to 14 The explanation is omitted here.

[0097] Please see Figure 15This is a circuit diagram of the electronic circuit 15 employing intermittent charging and discharging according to the eleventh embodiment of the present invention. Figure 5 In the circuit, charging circuit 11A includes current source CU1, and discharging circuit 13A includes current source CU2. Figure 15 In the embodiment, the charging circuit 11B includes a charging-side resistor R15, replacing... Figure 5 The charging circuit 11A; the discharging circuit 13B includes a discharging-side resistor R16, replacing... Figure 5 The discharge circuit is 13A.

[0098] When the charging switch SW11 is turned on according to the charging control signal SCH, the charging current flows from the power supply voltage VCC through the charging-side resistor R15 and the turned-on charging switch SW11 to the capacitor Cg, charging the capacitor Cg and gradually increasing the voltage level of the gate capacitor voltage signal VCg at the first terminal of the capacitor Cg. When the discharging switch SW13 is turned on according to the discharging control signal SDG, the discharging current flows from the first terminal of the capacitor Cg through the discharging-side resistor R16 and the turned-on discharging switch SW13 to the ground terminal GND, discharging the capacitor Cg and gradually decreasing the voltage level of the gate capacitor voltage signal VCg.

[0099] In the above embodiments, based on the rising edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as only the charging control signal SCH according to the transition detection signal S38; based on the falling edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as only the discharging control signal SDG according to the transition detection signal S38. In some embodiments, based on the rising edge and / or falling edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as both the charging control signal SCH and the discharging control signal SDG according to the transition detection signal S38. For example, during charging, based on the rising edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as both the charging control signal SCH and the discharging control signal SDG, such that the charging control signal SCH and the discharging control signal SDG have the same pulse pattern, such as... Figure 7 As shown.

[0100] As described above, during the current switching period, the control circuit 10A controls the charging circuit 11A and the discharging circuit 13A based on the switching signal S37 determined in the previous switching period, thereby controlling the charging and discharging of the power stage circuit 12A, and further controlling the turn-on and turn-off speed of the power transistor M1. According to another embodiment of the invention, during the charging period of this current switching period, while the power stage circuit 12A is charging based on the switching signal S37 determined in the previous switching cycle, the control circuit 10A determines whether to additionally enable the discharge control signal SDG (i.e., additionally control the discharge control signal SDG to be at a high voltage level) based on the actual voltage difference VGS. For details, see [link to documentation]. Figure 12 and Figure 13 During the charging period of the current switching period, if the judgment circuit 103 determines that any of the comparison signals S31 to S33 switches to a high voltage level within the first ideal interval time t0, or determines that comparison signals S31 or S32 switches to a high voltage level within the second ideal interval time t0, or determines that comparison signal S31 switches to a high voltage level within the first half (first half) of the third ideal interval time t0, it indicates that the power stage circuit 12A has been overcharged. At this time, the judgment circuit 103 controls the charge / discharge switching circuit 100 to additionally enable the discharge control signal SDG through the judgment signal S36, so as to reduce the voltage level of the gate capacitor voltage signal VCg. For example, see Figure 16 During period P15 of the charging process, the discharge control signal SDG did not... Figure 7 Instead of switching to a low voltage level, it remains at a high voltage level (i.e., compared to the previous level). Figure 7 The corresponding pulse of the discharge control signal SDG is additionally enabled, thereby extending the operating period of the corresponding pulse of the discharge control signal SDG to turn on the discharge switch SW13. Therefore, the gate capacitor voltage signal VCg decreases during period P15, resulting in a discharge stage SD11 in the rising phase of the gate capacitor voltage signal VCg, thereby compensating for the excessively rapid rise in the level of the gate capacitor voltage signal VCg due to overcharging. Figure 16 As shown, elevator segment SD11 is located between two charging segments.

[0101] Similarly, during the discharge period of this current switching period, while the power stage circuit 12A discharges based on the switching signal S37 determined in the previous switching cycle, the control circuit 10A determines whether to additionally enable the charging control signal SCH (i.e., to keep the additional charging control signal SCH at a high voltage level) based on the actual voltage difference VGS. For details, see [link to relevant documentation]. Figure 12 and Figure 14During the discharge period of the current switching period, if the judgment circuit 103 determines that the comparison signal S32 or S33 switches to a low voltage level within the first ideal interval time t0, or determines that the comparison signal S33 switches to a low voltage level within the second ideal interval time t0, or determines that the comparison signal S33 switches to a low voltage level within the first half (first half) of the third ideal interval time t0, it indicates that the power stage circuit 12A has over-discharged. At this time, the judgment circuit 103 controls the charge / discharge switching circuit 100 to additionally enable the charging control signal SCH through the judgment signal S36, so as to increase the voltage level of the gate capacitor voltage signal VCg. For example, see Figure 16 During period P16 of the charging process, the charging control signal SCH was not as expected. Figure 7 Instead of maintaining a low voltage level, it switches to a high voltage level (i.e., compared to the previous level). Figure 7 An additional enable charging control signal (SCH) is used to turn on the charging switch SW11. Therefore, the gate capacitor voltage signal VCg rises during period P16, creating a charging step SU21 in the falling band of the gate capacitor voltage signal VCg, thereby compensating for the excessively rapid level drop of the gate capacitor voltage signal VCg due to over-discharge. Figure 16 As shown, the charging elevator segment SU21 is located between the two discharging elevator segments. In this embodiment, the lengths of P15 and P16 are equal.

[0102] pass Figure 16 In one embodiment, during the current switching period, when the power stage circuit 12A overcharges or overdischarges based on the switching signal S37 determined in the previous switching period, the control circuit 10A can fine-tune the pulse pattern of the charging control signal SCH and / or the discharging control signal SDG in real time, thereby correcting the level change of the gate capacitor voltage signal VCg, so as to accelerate the curve of the actual voltage difference VGS of the power transistor M1 changing with time to match the curve of the ideal voltage difference VGSTG changing with time.

[0103] In other embodiments, the control circuit 10A or the charge / discharge switching circuit 100 may further include a compensation circuit that receives a judgment signal S36 and generates a pulse corresponding to the discharge segment SD11 and / or a pulse corresponding to the charging segment SU21 based on the judgment signal S36. When the charge / discharge switching circuit 100 receives this pulse during charging, it controls the discharge control signal SDG to have this pulse (e.g., Figure 16 In the context of the discharge control signal SDG, the pulse corresponding to period P15 is used; when the charge / discharge switching circuit 100 receives this pulse during the discharge period, it controls the charge control signal SCH to have this pulse (e.g., the pulse during period P15). Figure 16In the context of the charging control signal SCH, this corresponds to the pulse during period P16. This invention does not limit the specific architecture of the compensation circuit; any circuit capable of generating pulses with a fixed width based on the judgment signal S36 can serve as the aforementioned compensation circuit.

[0104] It is worth noting that the intermittent charge-discharge method of the present invention, replacing the existing technology which involves continuous charging during charging and continuous discharging during discharging, enables more precise control. The charging circuit, discharging circuit, and multiple circuit elements included in the power stage circuit of the electronic circuit employing intermittent charge-discharge of the present invention are merely illustrative examples and are not intended to limit the invention.

[0105] In summary, this invention provides an intermittent charging and discharging method, an intermittent discharging method, and an electronic circuit employing intermittent charging and discharging. The intermittent charging and discharging method and the electronic circuit employing intermittent charging and discharging employ intermittent control of the on / off states of both the charging circuit (including the charging switch) and the discharging circuit (including the discharging switch). The intermittent discharging method employs intermittent control of the on / off states of the discharging circuit (including the discharging switch). Therefore, compared to the prior art, the intermittent charging and discharging method, the intermittent discharging method, and the electronic circuit employing intermittent charging and discharging significantly improve control accuracy. Furthermore, compared to the prior art, the electronic circuit employing intermittent charging and discharging reduces the required control hardware circuitry, thereby reducing design area and power consumption, and saving costs.

[0106] The above-disclosed content is only a preferred and feasible embodiment of the present invention and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included in the claims of the present invention.

[0107] [Symbol Explanation]

[0108] 1, 3, 5, 15: Electronic Circuits

[0109] 10, 10A: Control circuit

[0110] 11, 11A, 11B: Charging circuit

[0111] 12, 12A: Power stage circuit

[0112] 13, 13A, 13B: Discharge circuit

[0113] 100: Charge / discharge switching circuit

[0114] 102: Signal generation circuit

[0115] 103: Judgment Circuit

[0116] 104: Sensing Comparison Circuit

[0117] 105: Transition Detection Circuit

[0118] 101: Comparator

[0119] 110: Charging-side current source circuit

[0120] 120: Sensing Circuit

[0121] 121-123: Comparator

[0122] 130: Discharge-side current source circuit

[0123] C1, Cg: Capacitors

[0124] Cin: Input capacitance

[0125] CU1: Charging-side current source

[0126] CU2: Discharge-side current source

[0127] CUin: Input current source

[0128] D: Duty Cycle

[0129] D1: Upper diode

[0130] D2: Lower diode

[0131] DN11~DN13, DN21~DN23, DN31: During working period

[0132] DF11~DF13, DF21~DF23: Non-working period

[0133] Fsw: Fixed Frequency

[0134] GND: Ground terminal

[0135] i1: Charging current value

[0136] i2: Discharge current value

[0137] ICg: Gate current

[0138] LIN: Output terminal

[0139] M1: Power transistor

[0140] N10, N11: Nodes

[0141] P10: During charging

[0142] P11~P14: Pulse Wave

[0143] P15, P16: Period

[0144] P20, P40: Maintenance period

[0145] P21~P24: Pulse Wave

[0146] P30: During discharge

[0147] P31: Initial Pulse

[0148] P41~P43: Modulated Pulse Waves

[0149] P60: Initial Pulse Wave

[0150] P61~P63: Modulated Pulse Waves

[0151] P64: Pulse Wave

[0152] P80: Pulse Wave

[0153] P81~P83: Modulated Pulse Waves

[0154] P91~P93: Modulated Pulse Waves

[0155] P94: Pulse Wave

[0156] R1, R2: Resistors

[0157] R15: Charging-side resistor

[0158] R16: Discharge side resistance

[0159] R31~R33: Reference resistors

[0160] S11~S15, S21~S25: Steps

[0161] S30: Sensing voltage signal

[0162] S31~S33: Comparison signals

[0163] S34: Trigger signal

[0164] S35: Reset signal

[0165] S36: Determine the signal

[0166] S37: Switching signal

[0167] S38: Transition Detection Signal

[0168] S39: Indicating signal

[0169] S40: Control signal

[0170] SCH: Charging control signal

[0171] SD11, SD21~SD23: Elevator section

[0172] SDG: Discharge control signal

[0173] SH11~SH13: Horizontal line segment indicating charging stop

[0174] SH21~SH23: Horizontal segment where discharge has stopped

[0175] SU11~SU13、SU21: Charging elevator section

[0176] SW1, SW2: Switches

[0177] SW11: Charging switch

[0178] SW13: Discharge switch

[0179] SWa, SWb, SWc, SWd: Control signals

[0180] t0: Ideal interval time

[0181] t11, t12, t13, t21, t22, t23: Actual interval time

[0182] Tideal: Ideal Time

[0183] Toff: Fixed off time

[0184] Ton: Fixed conduction time

[0185] V31~V33: Reference voltage

[0186] VCg: Gate capacitance voltage signal

[0187] VCC, VBAT, VDD: Power supply voltage

[0188] VGS: Actual gate-source voltage / Actual voltage difference

[0189] VGSTG: Ideal Voltage Difference

[0190] Vsaw: Reference voltage signal

[0191] Vstate: State signal

[0192] Δt11~Δt13: Time difference

[0193] Δt21~Δt23: Time difference.

Claims

1. An intermittent charge-discharge method, characterized in that, Includes the following steps: During the first period, the power stage circuit is charged multiple times during multiple working periods of multiple consecutive pulses of the charging control signal, so as to generate multiple first charging steps of the rising wave of the voltage signal of the power stage circuit. as well as During the first period, during multiple non-operating periods of a plurality of consecutive pulses of the charging control signal, charging of the power stage circuit is stopped, causing the voltage signal to generate a stop charging horizontal segment or a first release segment between two of the plurality of first charging segments.

2. An intermittent discharge method, characterized in that, Includes the following steps: During multiple working periods of multiple consecutive pulses of the discharge control signal, the power stage circuit is discharged multiple times, so that multiple discharge stages with falling waves are generated in the voltage signal of the power stage circuit. as well as During multiple non-operating periods of multiple consecutive pulses of the discharge control signal, the power stage circuit is discharged multiple times, causing the voltage signal to generate a stop-discharge horizontal line segment or a charging line segment between two of the multiple discharge elevator segments.

3. An electronic circuit employing intermittent charging and discharging, characterized in that, Include: The control circuit generates a charging control signal. The power stage circuit receives voltage signals; and A charging circuit is coupled to the power stage circuit and the control circuit, and is controlled by the control circuit according to the charging control signal; During the first period, the control circuit controls the charging circuit to charge the power stage circuit multiple times during multiple working periods of multiple consecutive pulses of the charging control signal, so as to generate multiple first charging steps of the rising wave of the voltage signal. During the first period, the control circuit controls the charging circuit to stop charging the power stage circuit during multiple non-working periods of multiple consecutive pulses of the charging control signal, so that the voltage signal generates a stop charging horizontal line segment or a first release elevator segment between two of the multiple first charging elevator segments.

4. The electronic circuit employing intermittent charging and discharging according to claim 3, characterized in that, The control circuit also generates a discharge control signal, and the electronic circuit employing intermittent charging and discharging further includes: The discharge circuit is coupled to the power stage circuit and the control circuit, and is controlled by the control circuit according to the discharge control signal; During the second period following the first period, the control circuit controls the charging circuit to discharge the power stage circuit multiple times during multiple working periods of multiple consecutive pulses of the discharge control signal, so that multiple second discharge stages with falling wave bands are generated in the voltage signal respectively. During the second period, the control circuit controls the discharge circuit to stop discharging the power stage circuit during multiple non-operating periods of the multiple pulses of the discharge control signal, so that the voltage signal generates a stop discharge horizontal line segment or a second charging line segment between each two of the multiple second discharge elevator segments.

5. The electronic circuit employing intermittent charging and discharging according to claim 4, characterized in that, The power stage circuit includes: A first capacitor, the first terminal of which is coupled to the charging circuit and the discharging circuit at the input terminal of the power stage circuit, and the second terminal of which is coupled to ground; and A power transistor, wherein a first terminal of the power transistor is coupled to a first power supply voltage, a second terminal of the power transistor is coupled to the ground terminal, and a control terminal of the power transistor is coupled to the input terminal; The voltage signal is generated at the input terminal.

6. The electronic circuit employing intermittent charging and discharging according to claim 5, characterized in that, The control circuit includes: A first comparator receives a first reference voltage signal at its first input terminal and a status signal at its second input terminal. The first comparator compares the first reference voltage signal with the status signal to generate a switching signal at its output terminal, wherein the status signal indicates the changing state of the voltage difference between the control terminal and the second terminal of the power transistor. as well as The output circuit receives the switching signal and outputs the switching signal as the charging control signal or the discharging control signal.

7. The electronic circuit employing intermittent charging and discharging according to claim 6, characterized in that, The control circuit also includes: A sensing comparison circuit receives a sensed voltage signal and is configured to compare the sensed voltage signal with a plurality of second reference voltages to output a plurality of comparison signals, wherein the sensed voltage signal represents the voltage difference of the power transistor; The judgment circuit receives multiple comparison signals, configures itself to determine the time difference between the time when the sensed voltage signal reaches each of the second reference voltages and the time threshold value based on the multiple comparison signals, and generates a trigger signal accordingly. as well as A signal generation circuit receives the trigger signal and generates the status signal, configured to control the level of the status signal based on the trigger signal.

8. The electronic circuit employing intermittent charging and discharging according to claim 7, characterized in that, The sensing comparison circuit includes: A sensing circuit configured to sense the voltage difference of the power transistors to output the sensed voltage signal; A plurality of second comparators are provided, with the first input terminal of each second comparator coupled to the sensing circuit to receive the sensing voltage signal, the second input terminals of the plurality of second comparators being respectively coupled to a plurality of second reference voltages, and the plurality of output terminals of the plurality of second comparators outputting a plurality of comparison signals. as well as Multiple reference resistors are connected in series between the second power supply voltage and the ground terminal; The second power supply voltage is one of the second reference voltages; The plurality of reference resistors include a first reference resistor and a second reference resistor, and the voltage at a common node between the first reference resistor and the second reference resistor is another of the second reference voltages.

9. The electronic circuit employing intermittent charging and discharging according to claim 7, characterized in that, The signal generation circuit includes: A first switch, the first end of the first switch being coupled to the second input of the first comparator at the first node, and the control end of the first switch receiving the trigger signal; An input current source is provided, wherein a first terminal of the input current source is coupled to a second terminal of the first switch, and the second terminal of the input current source is coupled to the ground terminal, wherein when the first switch is turned on according to the trigger signal, the input current source circuit provides current to the first node through the first switch; An input capacitor, wherein a first end of the input capacitor is coupled to the first node, and a second end of the input capacitor is coupled to the ground terminal, wherein the status signal is generated at the first node; as well as A second switch, the first end of which is coupled to the first node, and the second end of which is coupled to the grounding terminal; The determination circuit generates a reset signal, and the control terminal of the second switch receives the reset signal. At intervals equal to the time threshold value, the determination circuit enables the reset signal to turn on the second switch.

10. The electronic circuit employing intermittent charging and discharging according to claim 6, characterized in that, The on / off state of the power transistor in the power stage circuit is controlled by the voltage signal, the indication signal indicates the on / off state of the power transistor, and the control circuit further includes: A transition detection circuit receives the indication signal and is configured to detect the rising edge and falling edge of the indication signal to output a transition detection signal. Whenever the state transition detection circuit detects the rising edge of the indication signal, the state transition detection circuit outputs the state transition detection signal to control the output circuit to output the switching signal as the charging control signal; Whenever the state transition detection circuit detects the falling edge of the indicator signal, the state transition detection circuit outputs the state transition detection signal to control the output circuit to output the switching signal as the discharge control signal.

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