Trigger for reducing setup time

Abstract

A trigger includes: a clock buffer that outputs an inverted clock signal of a clock signal based on a clock signal and a buffer clock signal obtained by delaying the phase of the clock signal; a master latch that includes a scan path and a data path, the data path receiving a data signal independently of the scan path; a slave latch that generates a first drive signal based on a first latch signal from the master latch and outputs an inverted output signal based on the first latch signal, the buffer clock signal, and the first drive signal; and an output driver that outputs the output signal based on the inverted output signal.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2025-0000475, filed on January 2, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments relate to an electronic device, and more specifically, to a flip-flop for setting a negative setup time by reducing setup time. Background Technology

[0004] Flip-flops are general-purpose data storage elements used in digital electronic circuits. They are timing storage elements that enable sequential and stable logic designs, and can store logic states, parameters, or digital control signals.

[0005] Microprocessors comprise a large number of flip-flops, and to perform high-performance microprocessor operations, it is advantageous to reduce the setup time, hold time, and / or clock-to-output time (or CQ time) for the flip-flops. Generally, setup time is the time during which the logic level of the data should be maintained at a specific value before the rising edge of the clock.

[0006] Although flip-flops incorporating multiplexers have been proposed to internalize the scan function, a drawback is the relatively long path for sampling (or latching) the data signal in the flip-flop's main latch. This increases setup time and thus reduces the overall operating speed of the flip-flop. Alternatively, while flip-flops incorporating main latches that directly sample the data signal have been proposed to reduce setup time, there are limitations to this reduction. Summary of the Invention

[0007] One aspect is to provide a trigger that reduces setup time and allows for easy and flexible circuit design.

[0008] According to one or more embodiments, a trigger is provided, comprising: a clock buffer configured to output an inverted clock signal of the clock signal based on a clock signal and a buffer clock signal obtained by delaying the phase of the clock signal; a master latch including a scan path and a data path, the data path being configured to receive a data signal independently of the scan path; a slave latch configured to generate a first drive signal based on a first latch signal from the master latch, the slave latch being configured to output an inverted output signal based on the first latch signal, the buffer clock signal, and the first drive signal; and an output driver configured to output the output signal based on the inverted output signal.

[0009] According to another aspect of one or more embodiments, a trigger is provided, comprising: a clock buffer configured to output an inverted clock signal of the clock signal based on a clock signal and a buffer clock signal obtained by delaying the phase of the clock signal; a master latch including a scan path and a data path independent of each other, the master latch being configured to output a first latch signal having a second logic level, the second logic level being lower than a first logic level of a data signal having a first logic level; a slave latch configured to generate a first drive signal having a first logic level based on the first latch signal, the slave latch being configured to output an inverted output signal having a second logic level in response to the first logic level of the first drive signal and a rising edge of the buffer clock signal; and an output driver configured to output an output signal having a first logic level based on the inverted output signal.

[0010] According to another aspect of one or more embodiments, a trigger is provided, comprising: a clock buffer configured to output an inverted clock signal of the clock signal based on a clock signal and a buffer clock signal obtained by delaying the phase of the clock signal; a master latch including a scan path and a data path, the scan path being configured to receive a scan enable signal and a scan input signal, and the data path being configured to receive a data signal independently of the scan path; a slave latch including a pull-up driver and a pull-down driver, the pull-up driver being configured to pull up the inverted output signal based on a first latch signal of the master latch and the buffer clock signal, and the pull-down driver being configured to pull down the inverted output signal based on the first latch signal and the inverted clock signal; and an output driver configured to output an output signal based on the inverted output signal. Attached Figure Description

[0011] Various embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a trigger according to an embodiment;

[0013] Figure 2 The embodiments are shown in more detail below. Figure 1 The circuit diagram of the trigger;

[0014] Figure 3 The embodiments shown include Figure 2 The circuit diagram of the flip-flop shown is an example of a flip-flop from a latch.

[0015] Figure 4 , Figure 5 and Figure 6 This is a diagram illustrating the operation of the trigger according to an embodiment;

[0016] Figure 7 This is a timing diagram of some signals according to an embodiment;

[0017] Figure 8 This is a diagram illustrating the operation of the trigger according to an embodiment;

[0018] Figure 9 This is a circuit diagram illustrating the main latch according to an embodiment;

[0019] Figure 10 , Figure 11 and Figure 12 This is a circuit diagram illustrating a trigger according to some embodiments;

[0020] Figure 13 This is a block diagram illustrating the trigger according to an embodiment; and

[0021] Figure 14 A more detailed description of the embodiments is provided below. Figure 13 The circuit diagram of the trigger. Detailed Implementation

[0022] Various embodiments will be described in detail with reference to the accompanying drawings.

[0023] As used herein, the terms “first” and “second” may modify various components regardless of their order and / or importance, and do not limit the components. These terms are used only to distinguish one component from another. For example, “first” user equipment and “second” user equipment may refer to user equipment that is different from each other, regardless of the order or importance of the equipment. For example, without departing from the scope of this disclosure, a “first” component may be referred to as a “second” component, and similarly, a “second” component may be referred to as a “first” component.

[0024] In this specification, a "common node" refers to a point where the terminals of at least two transistors are connected to each other. For example, a common node between a first transistor and a second transistor may refer to a point where the source of the first transistor and the drain of the second transistor are connected to each other, or where the drain of the first transistor and the source of the second transistor are connected to each other.

[0025] In this specification, when a transistor is turned on, the conducting transistor electrically connects the points connected to its two terminals to each other. When a transistor is turned off, the points connected to its two terminals can be electrically disconnected from each other.

[0026] Figure 1 This is a block diagram illustrating trigger 100 according to an embodiment.

[0027] refer to Figure 1The trigger 100 may include a clock buffer 110, a master latch 120, a slave latch 130, and an output driver 140.

[0028] Clock buffer 110 can receive a clock signal CK. The clock signal CK can be generated by an external device outside of flip-flop 100 (e.g., a clock generator or clock management unit (CMU)). Clock buffer 110 can generate an inverted clock signal nclk and a buffer clock signal bclk based on the clock signal CK. The inverted clock signal nclk can be a signal with a phase opposite to that of the clock signal CK, i.e., a signal obtained by inverting the phase of the clock signal CK. The buffer clock signal bclk can be a signal obtained by delaying the phase of the clock signal CK. The buffer clock signal bclk can also be a signal obtained by inverting the phase of the inverted clock signal nclk. In some embodiments, the inverted clock signal nclk can be output to master latch 120. In some embodiments, the inverted clock signal nclk can be provided to slave latch 130. The buffer clock signal bclk can be output to each of master latch 120 and slave latch 130.

[0029] The master latch 120 can receive a data signal D, a scan enable signal SE, and a scan input signal SI. The scan enable signal SE can be a signal used to enable (or activate) or disable (or deactivate) a scan operation on a semiconductor circuit (not shown). For example, a scan operation can be enabled when the scan enable signal SE has a first logic level (e.g., logic high or logic high). A scan operation can be disabled when the scan enable signal SE has a second logic level opposite to the first logic level (e.g., logic low or logic low). The scan input signal SI can be a signal used to perform a scan operation. Although the first and second logic levels are examples, for ease of explanation, the following description will assume that the first logic level is logic high and the second logic level is logic low.

[0030] The main latch 120 can latch the data signal D or the scan input signal SI based on the inverted clock signal nclk and the buffer clock signal bclk, and can output the first latch signal M3 indicating the latch signal.

[0031] In an embodiment, the master latch 120 may include a scan path 121 and a data path 122 that are independent of each other. The master latch 120 according to the embodiment may also include a feedback path 123. When the scan path 121 and the data path 122 are independent of each other, the term "independent" may mean that the data signal D is input to the data path 122 independently of the scan path 121.

[0032] Scan path 121 can receive scan enable signal SE and scan input signal SI, and can output scan path signal to data path 122. When the logic level of scan enable signal SE is the first logic level, scan path 121 can invert scan input signal SI. In an embodiment, scan path 121 may include a scan multiplexer. In this case, master latch 120 may be referred to as master latch containing scan multiplexer. Data path 122 can receive scan path signal, scan enable signal SE and data signal D, can perform logical operations on data signal D and scan path signal based on inverted clock signal nclk and buffer clock signal bclk, and can output first latch signal M3. Feedback path 123 can feed back the first latch signal M3 of the previous stage to master latch 120 based on inverted clock signal nclk and buffer clock signal bclk, and can hold the first latch signal M3 generated in the previous stage.

[0033] Latch 130 can latch the first latch signal M3 based on the buffer clock signal bclk, and can output an inverted output signal QN indicating the latched signal. The inverted output signal QN can be a signal with a phase opposite to that of the output signal Q, that is, a signal obtained by inverting the phase of the output signal Q.

[0034] In an embodiment, the slave latch 130 may include a first driver 131 and a second driver 132. The slave latch 130 may also include a feedback path 133. The first driver 131 may generate a first drive signal based on a first latch signal M3 and may output the first drive signal to the second driver 132. The first drive signal may be a signal used to drive the inverted output signal QN. The second driver 132 may output the inverted output signal QN based on the first drive signal, the first latch signal M3, and the buffer clock signal bclk. The feedback path 133 may feed back the second latch signal from the previous stage to the slave latch 130 based on the buffer clock signal bclk and may retain the second latch signal generated in the previous stage. The second latch signal may be a signal obtained by latching the inverted output signal QN based on the buffer clock signal bclk. In an embodiment, the feedback path 133 may perform a feedback operation based on the inverted clock signal nclk and the buffer clock signal bclk.

[0035] The output driver 140 can output the output signal Q based on the inverted output signal QN.

[0036] Based on the above description, the operation of latching data signal D can be executed at high speed, which can reduce setup time and power consumption.

[0037] Figure 2 The embodiments are shown in more detail below. Figure 1 The circuit diagram of flip-flop 100. In Figure 2 For the sake of brevity, references and other information will be omitted. Figure 1 The description is the same as the description given.

[0038] refer to Figure 1 and Figure 2 In an embodiment, clock buffer 110 may include multiple inverters I0 and I1. Inverter I0 can invert the clock signal CK and output an inverted clock signal nclk. In an embodiment, the transition time of the inverted clock signal nclk and / or the occurrence time of its edge may be the same as the transition time of the clock signal CK and / or the occurrence time of its edge. In some embodiments, the transition time of the inverted clock signal nclk (and / or the occurrence time of its edge) may be delayed compared to the transition time of the clock signal CK (and / or the occurrence time of its edge). Inverter I1 can invert the inverted clock signal nclk and output a buffer clock signal bclk. In an embodiment, the transition time of the buffer clock signal bclk may be delayed compared to the transition time of the clock signal CK.

[0039] In this embodiment, the scan path 121 of the main latch 120 may include a NAND arithmetic unit I2 and a tri-state inverter TSI0. The NAND arithmetic unit I2 can perform NAND operations on the scan enable signal SE and the scan input signal SI, and can output a scan signal nsi. The scan signal nsi may include the result of the NAND operation. The tri-state inverter TSI0 can receive the scan signal nsi, the inverted clock signal nclk, and the buffer clock signal bclk. The tri-state inverter TSI0 can output the scan signal nsi as the scan path signal M2 based on the logic level of each of the inverted clock signal nclk and the buffer clock signal bclk.

[0040] The data path 122 of the master latch 120 may include multiple AND-OR-inverter (AOI) circuits. In an embodiment, an AOI circuit may include an AND operator, an OR operator, and an inverter. In some embodiments, an AOI circuit may include an AND operator and a NOR operator. (See reference...) Figure 2 For example, the first AOI circuit may include an AND operator I3 and a NOR operator I4, and the second AOI circuit may include an AND operator I5 and a NOR operator I6.

[0041] The first AOI circuit can output an internal clock signal M3CK based on the scan enable signal SE, the first latch signal M3, and the buffer clock signal bclk. In this case, the first latch signal M3 input to the first AOI circuit can be a signal whose operation has been completed in the previous stage. The AND operator I3 of the first AOI circuit can perform a first AND operation on the first latch signal M3 and the buffer clock signal bclk. The NOR operator I4 of the first AOI circuit can perform a first NOR operation on the output signal of the AND operator I3, which indicates the result of the first AND operation, and the scan enable signal SE. The NOR operator I4 can output an internal clock signal M3CK indicating the result of the first NOR operation.

[0042] The second AOI circuit can output a first latch signal M3 based on the scan path signal M2, the data signal D, and the internal clock signal M3CK. The AND operator I5 of the second AOI circuit can perform a second AND operation on the internal clock signal M3CK and the data signal D. The NOR operator I6 of the second AOI circuit can perform a second NOR operation on the output signal of the AND operator I5 (indicating the result of the second AND operation) and the scan path signal M2. The NOR operator I6 can output the result of the second NOR operation as the first latch signal M3 of the current stage.

[0043] The feedback path 123 of the main latch 120 may include a tri-state inverter TSI1. The tri-state inverter TSI1 can receive the first latch signal M3, the inverted clock signal nclk, and the buffer clock signal bclk. The tri-state inverter TSI1 can feed back the first latch signal M3 of the previous stage to the output terminal of the tri-state inverter TSI0 (and / or the input terminal of the NOR operator I6) according to the logic level of each of the inverted clock signal nclk and the buffer clock signal bclk.

[0044] The logic level of the current stage's first latch signal M3 can be determined based on the logic level of each of the previous stage's first latch signal M3, the scan enable signal SE, the buffer clock signal bclk based on the clock signal CK, and the internal clock signal M3CK. For example, when the logic level of the scan enable signal SE is logic low, data path 122 can be activated, and the logic level of the scan path signal M2 can be logic low. When the logic levels of the previous stage's first latch signal M3, the scan enable signal SE, and the buffer clock signal bclk based on the clock signal CK are all logic low, the logic level of the internal clock signal M3CK can be logic high, and the inverted data signal DN can be output as the current stage's first latch signal M3. In the following text, the logic levels of the previous stage's first latch signal M3, the scan enable signal SE, and the buffer clock signal bclk based on the clock signal CK are respectively represented as "[M3,SE,bclk,M3CK]=(0 / 1,0 / 1,0 / 1,0 / 1)". In this configuration, when [M3,SE,bclk,M3CK] = (0,0,0,1) or (1,0,0,1), the inverted data signal DN can be output as the first latch signal M3 of the current stage. When [M3,SE,bclk,M3CK] = (0,0,1,1) or (1,0,1,0), the first latch signal M3 of the previous stage can be output. When the scan enable signal SE is at a logic high level, data path 122 can be deactivated, and the scan input signal SI can be output as the output signal of the master latch 120. That is, [M3,SE,CK,M3CK] = (0,1,0,1), (0,1,1,0), (1,1,0,0), or (1,1,1,0).

[0045] As described above, since the scan path 121 and the data path 122 are independently separated by using the scan enable signal SE and the scan input signal SI for testing and debugging, unlike the data signal D, the operation of latching the data signal D can be performed at high speed.

[0046] The performance of flip-flop 100 can be further improved by using a buffer clock signal bclk that is delayed more than the inverted clock signal nclk to set a setup time of 0 or less.

[0047] In an embodiment, latch 130 can be configured to generate a first drive signal DT based on a first latch signal M3. For example, a first driver 131 of latch 130 can receive the first latch signal M3 and output the first drive signal DT to a second driver 132 of latch 130.

[0048] In an embodiment, latch 130 can be configured to output an inverted output signal QN based on a first latch signal M3, a buffer clock signal bclk, and a first drive signal DT. For example, a second driver 132 can be configured to perform an operation on the first latch signal M3 and the buffer clock signal bclk. The second driver 132 can be configured to output the inverted output signal QN based on a second drive signal CKB, the buffer clock signal bclk, and the first drive signal DT corresponding to the result of the operation. According to an embodiment, the second driver 132 may include a NAND arithmetic unit I7 and a clocked latch CLAT. The NAND arithmetic unit I7 can perform NAND operations on the first latch signal M3 and the buffer clock signal bclk, and can output the second drive signal CKB to the clocked latch CLAT. The clocked latch CLAT can receive the first drive signal DT, the second drive signal CKB, and the buffer clock signal bclk, and can output the inverted output signal QN. For example, the clock control latch CLAT can be configured to output an inverted output signal QN with a first logic level in response to the falling edge of the second drive signal CKB. The clock control latch CLAT can also be configured to output an inverted output signal QN with a second logic level in response to the rising edge of the first drive signal DT and the rising edge of the buffer clock signal bclk. The second logic level can be lower than the first logic level.

[0049] In an embodiment, the feedback path 133 from latch 130 can be configured to perform a feedback operation based on the inverted output signal QN, the second drive signal CKB, and the buffer clock signal bclk. Feedback path 133 may include an inverter I8 and a tri-state inverter TSI2. Inverter I8 can invert the inverted output signal QN and output the second latch signal QI. Tri-state inverter TSI2 can receive the second latch signal QI, the second drive signal CKB, and the buffer clock signal bclk. Tri-state inverter TSI2 can feed back the second latch signal QI to the output terminal of the clock-controlled latch CLAT (and / or the input terminal of inverter I8) according to the logic level of each of the second drive signal CKB and the buffer clock signal bclk.

[0050] In one embodiment, the output driver 140 may include an inverter 19. The inverter 19 can invert the inverted output signal QN and output the output signal Q to an external source.

[0051] Figure 3 The embodiments shown include Figure 2 The circuit diagram of the flip-flop 100 is an example of the latch 130. Figure 3 For the sake of brevity, references and other information will be omitted. Figure 2 The description is the same as the description given.

[0052] refer to Figure 2 and Figure 3 Clock buffer 110 and master latch 120 are connected to reference Figure 2 The description is the same. In an embodiment, the first driver 131 may include an inverter I10, which includes an input terminal for receiving a first latch signal M3 and an output terminal for outputting a first drive signal DT. The inverter I10 can invert the first latch signal M3 and output the first drive signal DT. That is, the first drive signal DT according to the embodiment may be a signal obtained by inverting the phase of the first latch signal M3.

[0053] In an embodiment, the NAND arithmetic unit I7 of the second driver 132 may include a plurality of P-type metal-oxide-semiconductor (PMOS) transistors M19 and M22 and a plurality of N-type metal-oxide-semiconductor (NMOS) transistors M20 and M21. The plurality of PMOS transistors M19 and M22 may be connected in parallel between a first power supply line to which a first power supply voltage VDD is applied and the output terminal of the NAND arithmetic unit I7. The PMOS transistor M19 and the plurality of NMOS transistors M20 and M21 may be connected in series between the first power supply line and a second power supply line with a second power supply voltage (e.g., ground voltage). A first latch signal M3 may be provided to the gate of each of the PMOS transistors M19 and M20. A buffer clock signal bclk may be provided to the gate of each of the NMOS transistors M21 and M22.

[0054] In an embodiment, the clock-controlled latch CLAT of the second driver 132 may include a clock-controlled complementary metal-oxide-semiconductor (CMOS) (C) 2 MOS). C 2The MOS transistor may include a PMOS transistor M23 and multiple NMOS transistors M24 and M25. Transistors M23, M24, and M25 can be connected in series between a first power line and a second power line. PMOS transistor M23 can be connected between the first power line and a first common node, and a second drive signal CKB can be provided to the gate of PMOS transistor M23. When the logic level of the buffer clock signal bclk is logic low (L), the second drive signal CKB can be pre-charged to logic high (H). NMOS transistor M24 can be connected between the first and second common nodes, and a first drive signal DT can be provided to the gate of NMOS transistor M24. NMOS transistor M25 can be connected between the second power line and the second common node, and the buffer clock signal bclk can be provided to the gate of NMOS transistor M25.

[0055] In some embodiments, the clock control latch CLAT of the second driver 132 can be implemented as a tri-state inverter.

[0056] In an embodiment, the tri-state inverter TSI2 of the feedback path 133 may include a plurality of PMOS transistors M26 and M27 and a plurality of NMOS transistors M28 and M29 connected in series between the first power line and the second power line.

[0057] In this embodiment, the gate of each of the PMOS transistors M26 and M29 can be connected to the output terminal of the inverter I8, the buffer clock signal bclk can be provided to the gate of the PMOS transistor M27, the second drive signal CKB can be provided to the gate of the NMOS transistor M28, and one electrode of each of the PMOS transistors M27 and M28 can be connected to the output terminal of the clock control latch CLAT and the input terminal of the inverter I8. However, the embodiment is not limited to this, and in some embodiments, the arrangement and position of the PMOS transistors M26 and M27 can be interchanged, and the arrangement and position of the NMOS transistors M28 and M29 can be interchanged.

[0058] Based on the above description, because C 2 MOS is used to separate the clock-to-output path (or CQ path) into a PMOS transistor M23 and multiple NMOS transistors M24 and M25, thus facilitating the design of flip-flop 100.

[0059] Figure 4 , Figure 5 and Figure 6 This is a diagram illustrating the operation of trigger 100 according to an embodiment. In detail, Figure 4 , Figure 5 and Figure 6 This is a diagram used to describe the operation of latching the data signal D from logic low level L to logic high level H.

[0060] refer to Figure 4 , Figure 5 and Figure 6 The scan enable signal SE can have a logic low level L. In this case, the logic level of the scan signal nsi can be a logic high level H, and the logic level of the scan path signal M2 can be a logic low level L. In an embodiment, the master latch 120 can be configured to output a first latch signal M3 with a logic low level L in response to a data signal D with a logic high level H. The slave latch 130 can be configured to generate a first drive signal DT with a logic high level H based on the first latch signal M3, and can output an inverted output signal QN with a logic low level L in response to the rising edge of the buffer clock signal bclk and the first drive signal DT.

[0061] refer to Figure 4 Because the internal clock signal M3CK has a logic high level (H) when the clock signal CK has a logic low level (L), the inverted data signal DN can be output as the first latch signal M3. The logic level of the first latch signal M3 can be a logic high level (H). In this case, PMOS transistor M19 can be turned off, and NMOS transistor M20 can be turned on. The buffer clock signal bclk can have a logic low level (L), NMOS transistors M21 and M25 can be turned off, and PMOS transistor M22 can be turned on. When PMOS transistor M22 is turned on, the logic level of the second drive signal CKB can be a logic high level (H). In this case, PMOS transistor M23 can be turned off. The logic level of the first drive signal DT can be a logic low level (L). In this case, NMOS transistor M24 can be turned on. PMOS transistor M26 or NMOS transistor M29 can be turned on according to the logic level of the second latch signal Qi.

[0062] refer to Figure 5The logic level of the clock signal CK can transition from logic low (L) to logic high (H). That is, a rising edge of the clock signal CK is possible. With the rising edge of the clock signal CK, the logic level of the inverted clock signal nclk can transition from logic high (H) to logic low (L). The logic level of the data signal D can transition from logic low (L) to logic high (H). In this case, the logic level of the first latch signal M3 can transition from logic high (H) to logic low (L). Therefore, PMOS transistor M19 can be turned on, and NMOS transistor M20 can be turned off. The logic level of the second drive signal CKB can be logic high (H). The logic level of the first drive signal DT can transition from logic low (L) to logic high (H). In this case, NMOS transistor M24 can be turned on.

[0063] refer to Figure 6 The logic level of the buffer clock signal bclk can transition from logic low (L) to logic high (H). In this case, NMOS transistors M21 and M25 can be turned on, and PMOS transistor M22 can be turned off. Due to the turned-on NMOS transistors M24 and M25, the second power supply voltage (e.g., the voltage to ground) of the second power supply line can be applied to the common node (e.g., C) of PMOS transistor M23 and NMOS transistor M24. 2 (The output terminal of the MOS). In this case, the inverted output signal QN can have a logic low level L. That is, the inverted output signal QN can be driven by the first drive signal DT and the buffer clock signal bclk. The second latch signal QI and the output signal Q can have a logic high level H, the PMOS transistors M26 and M27 can be turned off, and the NMOS transistors M28 and M29 can be turned on.

[0064] Figure 7 The diagram illustrates timing diagrams for signals CK, nclk, bclk, D, M3, DT, CKB, and QN according to an embodiment. In detail, Figure 7 It is a timing diagram used to latch the data signal D as it transitions from logic low level L to logic high level H.

[0065] refer to Figure 7When the rising edge of the clock signal CK occurs at time t0, the falling edge of the inverted clock signal nclk can occur at time t1. At time t2, after time t0, the data signal D can transition from logic low L to logic high H. At time t3, the first latch signal M3 can transition from logic high H to logic low L, and at time t4, the first drive signal DT can transition from logic low L to logic high H. When the rising edge of the buffer clock signal bclk occurs and the buffer clock signal bclk has a logic high level H at time t3, after time t0, the inverted output signal QN can transition from logic high H to logic low L at time t5. The logic level of the second drive signal CKB can typically be maintained at logic high H.

[0066] A setup time of 0 or greater refers to the time during which the value (or logic level) of the data signal D should be maintained before the rising edge of the clock signal CK occurs. When a setup time of 0 or greater (hereinafter, positive setup time) is set, the data signal D should maintain the transition logic level for a positive setup time or longer before the rising edge of the clock signal CK occurs. Therefore, for high-speed operation, the performance of the flip-flop can increase as the setup time decreases. A setup time less than 0, i.e., a negative setup time tnsu, can mean that the data signal D can be stably latched even if the value of the data signal D changes after the rising edge of the clock signal CK. The first drive signal DT can have a logic high level H before the buffer clock signal bclk is fully pulled up (or before the transition of the buffer clock signal bclk to logic high level H is complete). Therefore, flip-flops 100, 101, 102, 103, and 200 in various embodiments can accurately latch the data signal D even when the transition point of the data signal D occurs after the rising edge of the clock signal CK. That is, because the inverted output signal QN is driven by using the first drive signal DT, the second drive signal CKB, and the buffer clock signal bclk, the negative setup time tnsu can be set to the flip-flops 100, 101, 102, 103, and 200 in the various embodiments. Therefore, high-speed operation of the flip-flops 100, 101, 102, 103, and 200 is possible, and the performance of the flip-flops 100, 101, 102, 103, and 200 can be improved.

[0067] Figure 8 This is a diagram illustrating the operation of trigger 100 according to an embodiment. Figure 8 For the sake of brevity, references and other information will be omitted. Figure 4 , Figure 5 and Figure 6 The description is the same as the description given.

[0068] refer to Figure 8In this embodiment, the master latch 120 can be configured to output a first latch signal M3 with a logic high level H in response to a data signal D with a logic low level L. The slave latch 130 can output an inverted output signal QN with a logic high level H in response to the rising edge of the first latch signal M3 with a logic high level H, a first drive signal DT with a logic low level L, and a buffer clock signal bclk.

[0069] For example, the scan enable signal SE can have a logic level of logic low L. When the data signal D transitions from logic high H to logic low L, the first latch signal M3 can transition from logic low L to logic high H, and the first drive signal DT can transition from logic high H to logic low L. In this case, PMOS transistor M19 and NMOS transistor M24 can be turned off, and NMOS transistor M20 can be turned on. As the rising edge of the clock signal CK occurs, the logic level of the buffer clock signal bclk can transition from logic low L to logic high H. Therefore, PMOS transistor M27 can be turned off, and NMOS transistors M21 and M25 can be turned on. Since NMOS transistors M20 and M21 are turned on, the second drive signal CKB can have a logic low L, PMOS transistor M23 can be turned on, and NMOS transistor M28 can be turned off. Due to the turned-on PMOS transistor M23, the inverted output signal QN can transition from logic low L to logic high H. That is, the inverted output signal QN can be driven by the first drive signal DT and the buffer clock signal bclk. The output signal Q and the second latch signal QI can be transitioned from logic high level H to logic low level L.

[0070] Figure 9 This is a circuit diagram illustrating the main latch 120 according to an embodiment. Figure 9 For the sake of brevity, references and other information will be omitted. Figure 2 and Figure 3 The description is the same as the description given.

[0071] refer to Figure 9 NAND arithmetic unit I2 and reference Figure 2The description is identical. The tri-state inverter TSI0 may include multiple PMOS transistors MP0 and MP1 and multiple NMOS transistors MN0 and MN1 connected in series between a first power line and a second power line. In an embodiment, the gate of each of the PMOS transistors MP0 and MN1 may be connected to the output terminal of the NAND arithmetic unit I2. A buffer clock signal bclk may be provided to the gate of the PMOS transistor MP1, an inverted clock signal nclk may be provided to the gate of the NMOS transistor MN0, and a common node between the PMOS transistors MP1 and MN0 may be connected to the input terminal of the second AOI circuit AOI2. However, the embodiment is not limited thereto, and in some embodiments, the positions of transistors MP0, MP1, MN0, and MN1 may be changed.

[0072] The first AOI circuit AOI1 may include an AND operator I3 and a NOR operator I4. The second AOI circuit AOI2 may include multiple PMOS transistors M4, M5, M11, and M12, and multiple NMOS transistors M6, M7, M13, and M14. Transistors M4, M5, M6, and M7, and transistors M11, M12, M13, and M14 may be connected in series between the first and second power lines. Transistors M8, M9, and M10 may be connected in series between the common node between PMOS transistors M4 and M5 and the second power line. A scan path signal M2 may be provided to the gates of transistors M4, M6, M7, and M11. An internal clock signal M3CK may be provided to the gates of transistors M5, M10, and M14. A data signal D may be provided to the gates of transistors M8, M9, M12, and M13. The scan path signal M2 can be input to the common terminal of transistors M5, M6, M8, M9, M12 and M13, and the first latch signal M3 can be output from the common terminal of transistors M5, M6, M8, M9, M12 and M13.

[0073] The tri-state inverter TSI1 may include multiple PMOS transistors M15 and M16 and multiple NMOS transistors M17 and M18 connected in series between a first power line and a second power line. In an embodiment, transistors M15, M16, M17, and M18 may be connected in series between the first and second power lines. The gates of transistors M15 and M18 may be connected to the output terminal of the main latch 120, and the common node between transistors M16 and M17 may be connected to the output terminal of the tri-state inverter TSI0 and the input terminal of the second AOI circuit AOI2. The inverted clock signal nclk may be provided to the gate of the PMOS transistor M16, and the buffer clock signal bclk may be provided to the gate of the NMOS transistor M17.

[0074] Figure 10 , Figure 11 and Figure 12 This is a circuit diagram illustrating flip-flops 101, 102, and 103 according to some embodiments. Figure 10 , Figure 11 and Figure 12 For the sake of brevity, references and other information will be omitted. Figure 2 , Figure 3 and Figure 9 The description is the same as the description given.

[0075] refer to Figure 10 In an embodiment, the slave latch of trigger 101 can be configured to perform a feedback operation based on the inverted output signal QN, the inverted clock signal nclk, and the buffer clock signal bclk. For example, with Figure 3 Similarly, the three-state inverter TSI2, Figure 10 The tri-state inverter TSI2 can have multiple PMOS transistors M26 and M27 and multiple NMOS transistors M28 and M29 connected in series between the second power lines. However, compared with... Figure 3 Unlike the tri-state inverter TSI2, the inverting clock signal nclk, instead of the second drive signal CKB, can be provided to the gate of the NMOS transistor M28.

[0076] According to the above embodiments, the operating speed of the trigger 101 can be further improved.

[0077] refer to Figure 11 In this embodiment, the trigger 102 can receive a reset signal R and can perform a reset operation based on the reset signal R. For example, the tri-state inverter TSI0 may also include a PMOS transistor MP30 connected in series with the PMOS transistor MP0. For example, it may include an NMOS transistor MN31 connected between the second power line and the common node between the PMOS transistor MP1 and the NMOS transistor MN0 of the tri-state inverter TSI0. For example, the tri-state inverter TSI1 may also include a PMOS transistor MP32 connected in series with the PMOS transistor M15. A reset signal can be provided to the gates of the PMOS transistors MP30 and MP32, and the NMOS transistor MN31. Figure 10 Similarly, the NOR operator I4, Figure 11 The NOR operator I4 may include input terminals for receiving the output signal of the AND operator I3 and the scan enable signal SE. Figure 10 Unlike the I4 NOR operator, Figure 11 The NOR arithmetic unit I4 may also include an input terminal for receiving a reset signal R. The NOR arithmetic unit I11, instead of... Figure 2The inverter I8 can be included in the flip-flop 102. The NOR operator I11 can perform a NOR operation on the inverted output signal QN and the reset signal R, and can output a second latch signal QI corresponding to the result of the NOR operation. For example, when the logic level of the reset signal R is the second logic level (e.g., logic low level L), the logic level of the output signal Q can always be the second logic level.

[0078] refer to Figure 12 In an embodiment, the trigger 103 can receive the inverted set signal SN of the set signal and can perform a set operation based on the inverted set signal SN.

[0079] For example, the tri-state inverter TSI0 may also include an NMOS transistor MN30 connected in series with the NMOS transistor MN1. For example, it may include a PMOS transistor MP31 connected between the first power line and the common node between the PMOS transistor MP1 and the NMOS transistor MN0. For example, the tri-state inverter TSI1 may also include an NMOS transistor MN32 connected in series with the NMOS transistor M18. An inverted set signal SN may be provided to the gates of transistors MN30, MP31, and MN32. The flip-flop 103 may include a NAND arithmetic unit I12 instead of... Figure 2 The inverter I8. The NAND arithmetic unit I12 can perform NAND operations on the inverted output signal QN and the inverted set signal SN, and can output a second latch signal QI corresponding to the result of the NAND operation. For example, when the logic level of the set signal is logic high H and the logic level of the inverted set signal SN is logic low L, the logic level of the output signal Q can always be logic high H.

[0080] Figure 13 This is a block diagram illustrating trigger 200 according to an embodiment. Figure 13 For the sake of brevity, references and other information will be omitted. Figure 1 The description is the same as the description given.

[0081] refer to Figure 13 The trigger 200 may include a clock buffer 210, a master latch 220, a slave latch 230, and an output driver 240. The clock buffer 210, master latch 220, and output driver 240 can be respectively connected to... Figure 1 The clock buffer 110, master latch 120 and output driver 140 are the same.

[0082] In an embodiment, latch 230 may include a pull-up driver 231 and a pull-down driver 232. Pull-up driver 231 may be configured to pull up the inverted output signal QN based on a first latch signal M3 and a buffer clock signal bclk. Pull-down driver 232 is configured to pull down the inverted output signal QN based on the first latch signal M3 and the inverted clock signal nclk.

[0083] The latch 230 may also include a feedback path 233. In some embodiments, the feedback path 233 may be configured to perform a feedback operation based on the inverted output signal QN, the inverted clock signal nclk, and the buffer clock signal bclk. In some embodiments, the feedback path 233 may be configured to perform a feedback operation based on the inverted output signal QN, the second drive signal CKB, and the buffer clock signal bclk.

[0084] Based on the above description, the operation of latching data signal D can be executed at high speed, and the setup time can be reduced.

[0085] Figure 14 A more detailed description of the embodiments is provided below. Figure 13 The circuit diagram of the flip-flop 200. In Figure 14 For the sake of brevity, references and other information will be omitted. Figure 2 , Figure 3 , Figure 9 and Figure 10 The description is the same as the description given.

[0086] refer to Figure 14 , Figure 13 The scan path 221, data path 222, and feedback path 223 may include, as referenced Figure 9 The aforementioned components.

[0087] Figure 13 The pull-up driver 231 may include a NAND arithmetic unit I13 and a PMOS transistor M23. The NAND arithmetic unit I13 can perform NAND operations on a first latch signal M3 and a buffer clock signal bclk. The PMOS transistor M23 may be connected between a first power line and a common node, and may include a gate electrode connected to the output terminal of the NAND arithmetic unit I13. According to an embodiment... Figure 13 The pull-up driver 231 may include PMOS transistors M19 and M22, NMOS transistors M20 and M21, and PMOS transistor M23 configured to pull up the inverted output signal QN.

[0088] Figure 13The pull-down driver 232 may include a NOR operator I14 and an NMOS transistor M24. The NOR operator I14 can perform a NOR operation on a first latch signal M3 and an inverted clock signal nclk. The NMOS transistor M24 may be connected between a second power supply line and a common node of the PMOS transistor M23, and may include a gate electrode connected to the output terminal of the NOR operator I14. According to an embodiment... Figure 13 The pull-down driver 232 includes a stack of NMOS transistors M24 instead of NMOS transistors M24 and M25 configured to pull down the inverted output signal QN, and includes a NOR arithmetic unit I14 instead of an inverter I10 for receiving the first latch signal M3 and the inverted clock signal nclk.

[0089] While various embodiments have been described using specific terminology, these terms are for the purpose of explaining the technical concept of this disclosure only and are not intended to limit the meaning and scope of the appended claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be made therein. Accordingly, the technical scope of this disclosure should be defined by the following claims.

[0090] Although various embodiments have been specifically shown and described with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A trigger, the trigger comprising: A clock buffer, configured to output an inverted clock signal of a clock signal and a buffer clock signal obtained by delaying the phase of the clock signal; A master latch, comprising a scan path and a data path, wherein the data path is configured to receive data signals independently of the scan path; The slave latch is configured to generate a first drive signal based on a first latch signal from the master latch, and the slave latch is configured to output an inverted output signal based on the first latch signal, the buffer clock signal, and the first drive signal. as well as An output driver is configured to output an output signal based on the inverted output signal.

2. The trigger according to claim 1, wherein, The slave latch includes: A first driver, configured to invert the first latch signal, and configured to output the inverted first latch signal as the first drive signal; and A second driver is configured to perform an operation on the first latch signal and the buffer clock signal, and the second driver is configured to output the inverted output signal based on the buffer clock signal, the first drive signal and a second drive signal corresponding to the result of the operation.

3. The trigger according to claim 2, wherein, The first driver includes an inverter, which has an input terminal for receiving the first latch signal and an output terminal for outputting the first drive signal.

4. The trigger according to claim 2, wherein, The second driver includes: A NAND arithmetic unit configured to perform NAND operations on the first latch signal and the buffer clock signal, the NAND arithmetic unit being configured to output the second drive signal; and A clock-controlled latch is configured to output the inverted output signal having a first logic level in response to the falling edge of the second drive signal, and the clock-controlled latch is configured to output the inverted output signal having a second logic level lower than the first logic level in response to the rising edge of the first drive signal and the rising edge of the buffer clock signal.

5. The trigger according to claim 4, wherein, The clock-controlled latch includes: A first transistor is connected between a first power line to which a first power supply voltage is applied and a first common node, the first transistor including a gate for receiving the second drive signal; A second transistor, connected between the first common node and the second common node, includes a gate for receiving the first drive signal; and A third transistor is connected between a second power supply line to which a second power supply voltage is applied and the second common node, the third transistor including a gate that receives the buffer clock signal.

6. The trigger according to claim 2, wherein, The slave latch also includes a feedback path configured to perform a feedback operation based on the inverted output signal, the second drive signal, and the buffer clock signal.

7. The trigger according to claim 1, wherein, The slave latch also includes a feedback path configured to perform a feedback operation based on the inverted output signal, the inverted clock signal, and the buffer clock signal.

8. The trigger according to claim 7, wherein, The scan path and the data path are configured to receive a reset signal. The feedback path includes: A NOR operator configured to perform a NOR operation on the inverted output signal and the reset signal, the NOR operator being configured to output a second latch signal corresponding to the result of the NOR operation; and A tri-state inverter is configured to feed back the second latch signal of the previous stage to the input terminal of the NOR arithmetic unit according to the logic level of each of the inverted clock signal and the buffer clock signal.

9. The trigger according to claim 7, wherein, The scan path and the data path are configured to receive the inverted set signal of the set signal. The feedback path includes: A NAND arithmetic unit configured to perform a NAND operation on the inverted output signal and the inverted set signal, the NAND arithmetic unit being configured to output a second latch signal corresponding to the result of the NAND operation; and A tri-state inverter is configured to feed back the second latch signal of the previous stage to the input terminal of the NAND arithmetic unit according to the logic level of each of the inverted clock signal and the buffer clock signal.

10. A trigger, the trigger comprising: A clock buffer, configured to output an inverted clock signal of a clock signal and a buffer clock signal obtained by delaying the phase of the clock signal; A master latch, comprising a scan path and a data path that are independent of each other, is configured to output a first latch signal having a second logic level, the second logic level being lower than the first logic level of a data signal having a first logic level; A slave latch is configured to generate a first drive signal having the first logic level based on the first latch signal, and the slave latch is configured to output an inverted output signal having the second logic level in response to the first logic level of the first drive signal and the rising edge of the buffer clock signal. as well as An output driver is configured to output an output signal having the first logic level based on the inverted output signal.

11. The trigger of claim 10, wherein, The slave latch includes: A NAND arithmetic unit is configured to perform NAND operations on the first latch signal and the buffer clock signal, and the NAND arithmetic unit is configured to output a second drive signal having the first logic level; A clock-controlled latch is configured to output the inverted output signal having the second logic level in response to the first logic level of the first drive signal, the first logic level of the second drive signal, and the rising edge of the buffer clock signal. An inverter configured to invert the inverted output signal; and A three-state inverter is configured to feed back the second latch signal of the inverter to the output terminal of the clock-controlled latch based on the buffer clock signal and the second drive signal.

12. The trigger according to claim 10, wherein, The slave latch includes: A NAND arithmetic unit is configured to perform NAND operations on the first latch signal and the buffer clock signal, and the NAND arithmetic unit is configured to output a second drive signal having the first logic level; A clock-controlled latch is configured to output the inverted output signal having the second logic level in response to the first logic level of the first drive signal, the first logic level of the second drive signal, and the rising edge of the buffer clock signal. An inverter configured to invert the inverted output signal; and A three-state inverter is configured to feed back the second latch signal of the inverter to the output terminal of the clock control latch based on the inverted clock signal and the second drive signal.

13. The trigger according to claim 12, wherein, The clock-controlled latch includes: A first transistor is connected between a first power line to which a first power supply voltage is applied and a first common node, the first transistor including a gate for receiving the second drive signal; A second transistor, connected between the first common node and the second common node, includes a gate for receiving the first drive signal; and A third transistor is connected between a second power supply line to which a second power supply voltage is applied and the second common node, the third transistor including a gate that receives the buffer clock signal.

14. The trigger of claim 10, wherein, The scan path and the data path are configured to receive a reset signal, and The latch also includes a feedback path. The feedback path includes: A NOR operator configured to perform a NOR operation on the inverted output signal and the reset signal, the NOR operator being configured to output a second latch signal corresponding to the result of the NOR operation; and A tri-state inverter is configured to feed back the second latch signal of the previous stage to the input terminal of the NOR arithmetic unit according to the logic level of each of the inverted clock signal and the buffer clock signal.

15. The trigger according to claim 10, wherein, The scan path and the data path are configured to receive an inverted set signal of the set signal, and The latch also includes a feedback path. The feedback path includes: A NAND arithmetic unit configured to perform a NAND operation on the inverted output signal and the inverted set signal, the NAND arithmetic unit being configured to output a second latch signal corresponding to the result of the NAND operation; and A tri-state inverter is configured to feed back the second latch signal of the previous stage to the input terminal of the NAND arithmetic unit according to the logic level of each of the inverted clock signal and the buffer clock signal.

16. A trigger, the trigger comprising: A clock buffer, configured to output an inverted clock signal of a clock signal and a buffer clock signal obtained by delaying the phase of the clock signal; A master latch includes a scan path and a data path, the scan path being configured to receive a scan enable signal and a scan input signal, and the data path being configured to receive a data signal independently of the scan path; The latch includes a pull-up driver and a pull-down driver, the pull-up driver being configured to pull up the inverted output signal based on a first latch signal of the master latch and a buffer clock signal, and the pull-down driver being configured to pull down the inverted output signal based on the first latch signal and the inverted clock signal. as well as An output driver is configured to output an output signal based on the inverted output signal.

17. The trigger of claim 16, wherein, The pull-up driver includes: A NAND arithmetic unit configured to perform NAND operations on the first latch signal and the buffer clock signal; and A PMOS transistor is connected between a first power line to which a first power supply voltage is applied and a common node of the pull-down driver, the PMOS transistor including a gate electrode connected to the output terminal of the NAND arithmetic unit.

18. The trigger of claim 16, wherein, The pull-down driver includes: A NOR operator configured to perform a NOR operation on the first latch signal and the inverted clock signal; and An NMOS transistor is connected between a second power supply line to which a second power supply voltage is applied and a common node of the pull-up driver. The NMOS transistor includes a gate electrode connected to the output terminal of the NOR arithmetic unit.

19. The trigger of claim 16, wherein the slave latch further includes a feedback path configured to perform a feedback operation based on the inverted output signal, the inverted clock signal, and the buffer clock signal.

20. The trigger of claim 16, wherein, The scanning path includes: A NAND arithmetic unit configured to perform a NAND operation on the scan enable signal and the scan input signal, the NAND arithmetic unit being configured to output a scan signal corresponding to the result of the NAND operation; and A three-state inverter, configured to output a scan path signal based on the scan signal, the inverted clock signal, and the buffer clock signal, and The data path includes: The first AND-OR inverter (AOI) circuit is configured as follows: Perform a first AND operation on the first latch signal and the buffer clock signal. Perform a first NOR operation on the result of the first AND operation and the scan enable signal, and Output an internal clock signal corresponding to the result of the first NOR operation; and The second AOI circuit is configured as follows: Perform a second AND operation on the internal clock signal and the data signal. Perform a second NOR operation on the result of the second AND operation and the scan signal, and The result of the second NOR operation is output as the second latch signal.

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